88332a002d9653365b753681b841b32423001e03
[linux-3.10.git] / arch / arm / mach-tegra / pm.h
1 /*
2  * arch/arm/mach-tegra/include/mach/pm.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  *      Colin Cross <ccross@google.com>
8  *
9  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms and conditions of the GNU General Public License,
13  * version 2, as published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18  * more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
22  */
23
24
25 #ifndef _MACH_TEGRA_PM_H_
26 #define _MACH_TEGRA_PM_H_
27
28 #include <linux/mutex.h>
29 #include <linux/init.h>
30 #include <linux/errno.h>
31 #include <linux/clkdev.h>
32
33 #include "iomap.h"
34
35 #define PMC_SCRATCH0            0x50
36 #define PMC_SCRATCH1            0x54
37 #define PMC_SCRATCH4            0x60
38
39 enum tegra_suspend_mode {
40         TEGRA_SUSPEND_NONE = 0,
41         TEGRA_SUSPEND_LP2,      /* CPU voltage off */
42         TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
43         TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
44         TEGRA_MAX_SUSPEND_MODE,
45 };
46
47 enum suspend_stage {
48         TEGRA_SUSPEND_BEFORE_PERIPHERAL,
49         TEGRA_SUSPEND_BEFORE_CPU,
50 };
51
52 enum resume_stage {
53         TEGRA_RESUME_AFTER_PERIPHERAL,
54         TEGRA_RESUME_AFTER_CPU,
55 };
56
57 struct tegra_suspend_platform_data {
58         unsigned long cpu_timer;   /* CPU power good time in us,  LP2/LP1 */
59         unsigned long cpu_off_timer;    /* CPU power off time us, LP2/LP1 */
60         unsigned long core_timer;  /* core power good time in ticks,  LP0 */
61         unsigned long core_off_timer;   /* core power off time ticks, LP0 */
62         bool corereq_high;         /* Core power request active-high */
63         bool sysclkreq_high;       /* System clock request is active-high */
64         bool sysclkreq_gpio;       /* if System clock request is set to gpio */
65         bool combined_req;         /* if core & CPU power requests are combined */
66         enum tegra_suspend_mode suspend_mode;
67         unsigned long cpu_lp2_min_residency; /* Min LP2 state residency in us */
68         void (*board_suspend)(int lp_state, enum suspend_stage stg);
69         /* lp_state = 0 for LP0 state, 1 for LP1 state, 2 for LP2 state */
70         void (*board_resume)(int lp_state, enum resume_stage stg);
71         unsigned int cpu_resume_boost;  /* CPU frequency resume boost in kHz */
72 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
73         bool lp1_lowvolt_support;
74         unsigned int i2c_base_addr;
75         unsigned int pmuslave_addr;
76         unsigned int core_reg_addr;
77         unsigned int lp1_core_volt_low_cold;
78         unsigned int lp1_core_volt_low;
79         unsigned int lp1_core_volt_high;
80 #endif
81         unsigned int lp1bb_core_volt_min;
82         unsigned long lp1bb_emc_rate_min;
83         unsigned long lp1bb_emc_rate_max;
84 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
85         unsigned long min_residency_vmin_fmin;
86         unsigned long min_residency_ncpu_slow;
87         unsigned long min_residency_ncpu_fast;
88         unsigned long min_residency_crail;
89         bool crail_up_early;
90 #endif
91         unsigned long min_residency_mc_clk;
92         bool usb_vbus_internal_wake; /* support for internal vbus wake */
93         bool usb_id_internal_wake; /* support for internal id wake */
94
95         void (*suspend_dfll_bypass)(void);
96         void (*resume_dfll_bypass)(void);
97 };
98
99 /* clears io dpd settings before kernel code */
100 void tegra_bl_io_dpd_cleanup(void);
101
102 unsigned long tegra_cpu_power_good_time(void);
103 unsigned long tegra_cpu_power_off_time(void);
104 unsigned long tegra_cpu_lp2_min_residency(void);
105 unsigned long tegra_mc_clk_stop_min_residency(void);
106 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
107 unsigned long tegra_min_residency_vmin_fmin(void);
108 unsigned long tegra_min_residency_ncpu(void);
109 unsigned long tegra_min_residency_crail(void);
110 bool tegra_crail_can_start_early(void);
111 #else
112 static inline bool tegra_crail_can_start_early(void)
113 { return false; }
114 #endif
115 void tegra_limit_cpu_power_timers(unsigned long us_on, unsigned long us_off);
116 void tegra_clear_cpu_in_pd(int cpu);
117 bool tegra_set_cpu_in_pd(int cpu);
118
119 void tegra_mc_clk_prepare(void);
120 void tegra_mc_clk_finish(void);
121 int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags);
122 #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE
123 int tegra_is_lp1_suspend_mode(void);
124 #endif
125 void tegra_lp1bb_suspend_emc_rate(unsigned long emc_min, unsigned long emc_max);
126 void tegra_lp1bb_suspend_mv_set(int mv);
127 unsigned long tegra_lp1bb_emc_min_rate_get(void);
128
129 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
130 #define FLOW_CTRL_CLUSTER_CONTROL \
131         (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c)
132 #endif
133
134 #define FLOW_CTRL_CPU_PWR_CSR \
135         (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x38)
136 #define FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE       1
137
138 #define FLOW_CTRL_MPID \
139         (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x3c)
140
141 #define FLOW_CTRL_RAM_REPAIR \
142         (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x40)
143 #define FLOW_CTRL_RAM_REPAIR_BYPASS_EN  (1<<2)
144 #define FLOW_CTRL_RAM_REPAIR_STS        (1<<1)
145 #define FLOW_CTRL_RAM_REPAIR_REQ        (1<<0)
146
147 #define FUSE_SKU_DIRECT_CONFIG \
148         (IO_ADDRESS(TEGRA_FUSE_BASE) + 0x1F4)
149 #define FUSE_SKU_DISABLE_ALL_CPUS       (1<<5)
150 #define FUSE_SKU_NUM_DISABLED_CPUS(x)   (((x) >> 3) & 3)
151
152 void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat);
153
154 u64 tegra_rtc_read_ms(void);
155
156 /*
157  * Callbacks for platform drivers to implement.
158  */
159 extern void (*tegra_deep_sleep)(int);
160
161 unsigned int tegra_idle_power_down_last(unsigned int us, unsigned int flags);
162
163 #if defined(CONFIG_PM_SLEEP) && !defined(CONFIG_ARCH_TEGRA_2x_SOC)
164 void tegra_lp0_suspend_mc(void);
165 void tegra_lp0_resume_mc(void);
166 void tegra_lp0_cpu_mode(bool enter);
167 #else
168 static inline void tegra_lp0_suspend_mc(void) {}
169 static inline void tegra_lp0_resume_mc(void) {}
170 static inline void tegra_lp0_cpu_mode(bool enter) {}
171 #endif
172
173 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
174 #define INSTRUMENT_CLUSTER_SWITCH 0     /* Should be zero for shipping code */
175 #define DEBUG_CLUSTER_SWITCH 0          /* Should be zero for shipping code */
176 #define PARAMETERIZE_CLUSTER_SWITCH 1   /* Should be zero for shipping code */
177
178 #define CLUSTER_SWITCH_TIME_AVG_SHIFT   4
179 #define CLUSTER_SWITCH_AVG_SAMPLES      (0x1U << CLUSTER_SWITCH_TIME_AVG_SHIFT)
180
181 enum tegra_cluster_switch_time_id {
182         tegra_cluster_switch_time_id_start = 0,
183         tegra_cluster_switch_time_id_prolog,
184         tegra_cluster_switch_time_id_switch,
185         tegra_cluster_switch_time_id_epilog,
186         tegra_cluster_switch_time_id_end,
187         tegra_cluster_switch_time_id_max
188 };
189
190 static inline bool is_g_cluster_present(void)
191 {
192         u32 fuse_sku = readl(FUSE_SKU_DIRECT_CONFIG);
193         if (fuse_sku & FUSE_SKU_DISABLE_ALL_CPUS)
194                 return false;
195         return true;
196 }
197 static inline unsigned int is_lp_cluster(void)
198 {
199         unsigned int reg;
200 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
201         reg = readl(FLOW_CTRL_CLUSTER_CONTROL);
202         return reg & 1; /* 0 == G, 1 == LP*/
203 #else
204         asm("mrc        p15, 0, %0, c0, c0, 5\n"
205             "ubfx       %0, %0, #8, #4"
206             : "=r" (reg)
207             :
208             : "cc","memory");
209         return reg ; /* 0 == G, 1 == LP*/
210 #endif
211 }
212 int tegra_cluster_control(unsigned int us, unsigned int flags);
213 void tegra_cluster_switch_prolog(unsigned int flags);
214 void tegra_cluster_switch_epilog(unsigned int flags);
215 int tegra_switch_to_g_cluster(void);
216 int tegra_switch_to_lp_cluster(void);
217 int tegra_cluster_switch(struct clk *cpu_clk, struct clk *new_cluster_clk);
218 #else
219 #define INSTRUMENT_CLUSTER_SWITCH 0     /* Must be zero for ARCH_TEGRA_2x_SOC */
220 #define DEBUG_CLUSTER_SWITCH 0          /* Must be zero for ARCH_TEGRA_2x_SOC */
221 #define PARAMETERIZE_CLUSTER_SWITCH 0   /* Must be zero for ARCH_TEGRA_2x_SOC */
222
223 static inline bool is_g_cluster_present(void)   { return true; }
224 static inline unsigned int is_lp_cluster(void)  { return 0; }
225 static inline int tegra_cluster_control(unsigned int us, unsigned int flags)
226 {
227         return -EPERM;
228 }
229 static inline void tegra_cluster_switch_prolog(unsigned int flags) {}
230 static inline void tegra_cluster_switch_epilog(unsigned int flags) {}
231 static inline int tegra_switch_to_g_cluster(void)
232 {
233         return -EPERM;
234 }
235 static inline int tegra_switch_to_lp_cluster(void)
236 {
237         return -EPERM;
238 }
239 static inline int tegra_cluster_switch(struct clk *cpu_clk,
240                                        struct clk *new_cluster_clk)
241 {
242         return -EPERM;
243 }
244 #endif
245
246 #if INSTRUMENT_CLUSTER_SWITCH
247 void tegra_cluster_switch_time(unsigned int flags, int id);
248 #else
249 static inline void tegra_cluster_switch_time(unsigned int flags, int id) { }
250 #endif
251
252 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
253 void tegra2_lp0_suspend_init(void);
254 void tegra2_lp2_set_trigger(unsigned long cycles);
255 unsigned long tegra2_lp2_timer_remain(void);
256 #else
257 void tegra3_lp2_set_trigger(unsigned long cycles);
258 unsigned long tegra3_lp2_timer_remain(void);
259 int tegra3_is_cpu_wake_timer_ready(unsigned int cpu);
260 void tegra3_lp2_timer_cancel_secondary(void);
261 #endif
262
263 static inline void tegra_lp0_suspend_init(void)
264 {
265 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
266         tegra2_lp0_suspend_init();
267 #endif
268 }
269
270 static inline void tegra_pd_set_trigger(unsigned long cycles)
271 {
272 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
273         tegra2_lp2_set_trigger(cycles);
274 #else
275         tegra3_lp2_set_trigger(cycles);
276 #endif
277 }
278
279 static inline unsigned long tegra_pd_timer_remain(void)
280 {
281 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
282         return tegra2_lp2_timer_remain();
283 #else
284         return tegra3_lp2_timer_remain();
285 #endif
286 }
287
288 static inline int tegra_is_cpu_wake_timer_ready(unsigned int cpu)
289 {
290 #if defined(CONFIG_TEGRA_LP2_CPU_TIMER) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
291         return 1;
292 #else
293         return tegra3_is_cpu_wake_timer_ready(cpu);
294 #endif
295 }
296
297 static inline void tegra_pd_timer_cancel_secondary(void)
298 {
299 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
300         tegra3_lp2_timer_cancel_secondary();
301 #endif
302 }
303
304 #if DEBUG_CLUSTER_SWITCH && 0 /* !!!FIXME!!! THIS IS BROKEN */
305 extern unsigned int tegra_cluster_debug;
306 #define DEBUG_CLUSTER(x) do { if (tegra_cluster_debug) printk x; } while (0)
307 #else
308 #define DEBUG_CLUSTER(x) do { } while (0)
309 #endif
310 #if PARAMETERIZE_CLUSTER_SWITCH
311 void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags);
312 #else
313 static inline void tegra_cluster_switch_set_parameters(
314         unsigned int us, unsigned int flags)
315 { }
316 #endif
317
318 #ifdef CONFIG_SMP
319 extern bool tegra_all_cpus_booted __read_mostly;
320 #else
321 #define tegra_all_cpus_booted (true)
322 #endif
323
324 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC) \
325         && defined(CONFIG_SMP)
326 void tegra_smp_clear_power_mask(void);
327 #else
328 static inline void tegra_smp_clear_power_mask(void){}
329 #endif
330
331 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
332 void tegra_smp_save_power_mask(void);
333 void tegra_smp_restore_power_mask(void);
334 #endif
335
336 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
337 void tegra_generic_smc(u32 type, u32 subtype, u32 arg);
338 #endif
339
340 /* The debug channel uart base physical address */
341 extern unsigned long  debug_uart_port_base;
342
343 extern struct clk *debug_uart_clk;
344 void tegra_console_uart_suspend(void);
345 void tegra_console_uart_resume(void);
346
347
348 #endif /* _MACH_TEGRA_PM_H_ */