secureos: Remove useless smc for t114
[linux-3.10.git] / arch / arm / mach-tegra / pm.c
1 /*
2  * arch/arm/mach-tegra/pm.c
3  *
4  * CPU complex suspend & resume functions for Tegra SoCs
5  *
6  * Copyright (c) 2009-2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/ctype.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/sched.h>
28 #include <linux/smp.h>
29 #include <linux/irq.h>
30 #include <linux/interrupt.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/debugfs.h>
34 #include <linux/delay.h>
35 #include <linux/suspend.h>
36 #include <linux/slab.h>
37 #include <linux/serial_reg.h>
38 #include <linux/seq_file.h>
39 #include <linux/uaccess.h>
40 #include <linux/syscore_ops.h>
41 #include <linux/cpu_pm.h>
42 #include <linux/clk/tegra.h>
43 #include <linux/export.h>
44 #include <linux/vmalloc.h>
45 #include <linux/memblock.h>
46 #include <linux/console.h>
47 #include <linux/tegra_audio.h>
48
49 #include <trace/events/power.h>
50 #include <trace/events/nvsecurity.h>
51
52 #include <asm/cacheflush.h>
53 #include <asm/idmap.h>
54 #include <asm/localtimer.h>
55 #include <asm/pgalloc.h>
56 #include <asm/pgtable.h>
57 #include <asm/tlbflush.h>
58 #include <asm/suspend.h>
59 #include <asm/smp_plat.h>
60
61 #include <mach/irqs.h>
62 #include <mach/powergate.h>
63 #include <mach/hardware.h>
64
65 #include "board.h"
66 #include "clock.h"
67 #include "common.h"
68 #include "cpuidle.h"
69 #include "fuse.h"
70 #include "gic.h"
71 #include "iomap.h"
72 #include "pm.h"
73 #include "pm-irq.h"
74 #include "reset.h"
75 #include "sleep.h"
76 #include "timer.h"
77 #include "dvfs.h"
78 #include "cpu-tegra.h"
79
80 #define CREATE_TRACE_POINTS
81 #include <trace/events/nvpower.h>
82
83 struct suspend_context {
84         /*
85          * The next 7 values are referenced by offset in __restart_plls
86          * in headsmp-t2.S, and should not be moved
87          */
88         u32 pllx_misc;
89         u32 pllx_base;
90         u32 pllp_misc;
91         u32 pllp_base;
92         u32 pllp_outa;
93         u32 pllp_outb;
94         u32 pll_timeout;
95
96         u32 cpu_burst;
97         u32 clk_csite_src;
98         u32 cclk_divider;
99
100         u32 mc[3];
101         u8 uart[5];
102
103         struct tegra_twd_context twd;
104 #ifdef CONFIG_ARM_ARCH_TIMER
105         struct arch_timer_context arch_timer;
106 #endif
107 };
108
109 #ifdef CONFIG_PM_SLEEP
110 phys_addr_t tegra_pgd_phys;     /* pgd used by hotplug & LP2 bootup */
111 static pgd_t *tegra_pgd;
112 static DEFINE_SPINLOCK(tegra_lp2_lock);
113 static cpumask_t tegra_in_lp2;
114 static cpumask_t *iram_cpu_lp2_mask;
115 static unsigned long *iram_cpu_lp1_mask;
116 static u8 *iram_save;
117 static unsigned long iram_save_size;
118 static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA);
119 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
120 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
121 static int tegra_last_pclk;
122 #endif
123
124 struct suspend_context tegra_sctx;
125
126 #define TEGRA_POWER_PWRREQ_POLARITY     (1 << 8)   /* core power request polarity */
127 #define TEGRA_POWER_PWRREQ_OE           (1 << 9)   /* core power request enable */
128 #define TEGRA_POWER_SYSCLK_POLARITY     (1 << 10)  /* sys clk polarity */
129 #define TEGRA_POWER_SYSCLK_OE           (1 << 11)  /* system clock enable */
130 #define TEGRA_POWER_PWRGATE_DIS         (1 << 12)  /* power gate disabled */
131 #define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* enter LP0 when CPU pwr gated */
132 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU power request polarity */
133 #define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU power request enable */
134 #define TEGRA_POWER_CPUPWRGOOD_EN       (1 << 19)  /* CPU power good enable */
135
136 #define PMC_CTRL                0x0
137 #define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
138 #define PMC_WAKE_MASK           0xc
139 #define PMC_WAKE_LEVEL          0x10
140 #define PMC_DPAD_ORIDE          0x1C
141 #define PMC_WAKE_DELAY          0xe0
142 #define PMC_DPD_SAMPLE          0x20
143
144 #define PMC_WAKE_STATUS         0x14
145 #define PMC_SW_WAKE_STATUS      0x18
146 #define PMC_COREPWRGOOD_TIMER   0x3c
147 #define PMC_CPUPWRGOOD_TIMER    0xc8
148 #define PMC_CPUPWROFF_TIMER     0xcc
149 #define PMC_COREPWROFF_TIMER    PMC_WAKE_DELAY
150
151 #define PMC_PWRGATE_TOGGLE      0x30
152 #define PWRGATE_TOGGLE_START    (1 << 8)
153 #define UN_PWRGATE_CPU          \
154         (PWRGATE_TOGGLE_START | TEGRA_CPU_POWERGATE_ID(TEGRA_POWERGATE_CPU))
155
156 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
157 #define PMC_SCRATCH4_WAKE_CLUSTER_MASK  (1<<31)
158 #endif
159
160 #define CLK_RESET_CCLK_BURST    0x20
161 #define CLK_RESET_CCLK_DIVIDER  0x24
162 #define CLK_RESET_PLLC_BASE     0x80
163 #define CLK_RESET_PLLM_BASE     0x90
164 #define CLK_RESET_PLLX_BASE     0xe0
165 #define CLK_RESET_PLLX_MISC     0xe4
166 #define CLK_RESET_PLLP_BASE     0xa0
167 #define CLK_RESET_PLLP_OUTA     0xa4
168 #define CLK_RESET_PLLP_OUTB     0xa8
169 #define CLK_RESET_PLLP_MISC     0xac
170
171 #define CLK_RESET_SOURCE_CSITE  0x1d4
172
173 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
174 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT    4
175 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT   0
176 #define CLK_RESET_CCLK_IDLE_POLICY         1
177 #define CLK_RESET_CCLK_RUN_POLICY          2
178 #define CLK_RESET_CCLK_BURST_POLICY_PLLM   3
179 #define CLK_RESET_CCLK_BURST_POLICY_PLLX   8
180
181 #define EMC_MRW_0               0x0e8
182 #define EMC_MRW_DEV_SELECTN     30
183 #define EMC_MRW_DEV_NONE        (3 << EMC_MRW_DEV_SELECTN)
184
185 #define MC_SECURITY_START       0x6c
186 #define MC_SECURITY_SIZE        0x70
187 #define MC_SECURITY_CFG2        0x7c
188
189 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
190 static struct clk *tegra_dfll;
191 #endif
192 static struct clk *tegra_pclk;
193 static const struct tegra_suspend_platform_data *pdata;
194 static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
195
196 #if defined(CONFIG_TEGRA_CLUSTER_CONTROL) && INSTRUMENT_CLUSTER_SWITCH
197 enum tegra_cluster_switch_time_id {
198         tegra_cluster_switch_time_id_start = 0,
199         tegra_cluster_switch_time_id_prolog,
200         tegra_cluster_switch_time_id_switch,
201         tegra_cluster_switch_time_id_epilog,
202         tegra_cluster_switch_time_id_max
203 };
204
205 static unsigned long
206                 tegra_cluster_switch_times[tegra_cluster_switch_time_id_max];
207 #define tegra_cluster_switch_time(flags, id) \
208         do { \
209                 barrier(); \
210                 if (flags & TEGRA_POWER_CLUSTER_MASK) { \
211                         void __iomem *timer_us = \
212                                                 IO_ADDRESS(TEGRA_TMRUS_BASE); \
213                         if (id < tegra_cluster_switch_time_id_max) \
214                                 tegra_cluster_switch_times[id] = \
215                                                         readl(timer_us); \
216                                 wmb(); \
217                 } \
218                 barrier(); \
219         } while(0)
220 #else
221 #define tegra_cluster_switch_time(flags, id) do {} while(0)
222 #endif
223
224 #ifdef CONFIG_PM_SLEEP
225 static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
226         [TEGRA_SUSPEND_NONE]    = "none",
227         [TEGRA_SUSPEND_LP2]     = "lp2",
228         [TEGRA_SUSPEND_LP1]     = "lp1",
229         [TEGRA_SUSPEND_LP0]     = "lp0",
230 };
231
232 unsigned long tegra_cpu_power_good_time(void)
233 {
234         if (WARN_ON_ONCE(!pdata))
235                 return 5000;
236
237         return pdata->cpu_timer;
238 }
239
240 unsigned long tegra_cpu_power_off_time(void)
241 {
242         if (WARN_ON_ONCE(!pdata))
243                 return 5000;
244
245         return pdata->cpu_off_timer;
246 }
247
248 unsigned long tegra_cpu_lp2_min_residency(void)
249 {
250         if (WARN_ON_ONCE(!pdata))
251                 return 2000;
252
253         return pdata->cpu_lp2_min_residency;
254 }
255
256 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
257 unsigned long tegra_min_residency_noncpu(void)
258 {
259         return pdata->min_residency_noncpu;
260 }
261
262 unsigned long tegra_min_residency_crail(void)
263 {
264         return pdata->min_residency_crail;
265 }
266 #endif
267
268 static void suspend_cpu_dfll_mode(void)
269 {
270 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
271         /* If DFLL is used as CPU clock source go to open loop mode */
272         if (!is_lp_cluster() && tegra_dfll &&
273             tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
274                 tegra_clk_cfg_ex(tegra_dfll, TEGRA_CLK_DFLL_LOCK, 0);
275 #endif
276 }
277
278 static void resume_cpu_dfll_mode(void)
279 {
280 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
281         /* If DFLL is used as CPU clock source restore closed loop mode */
282         if (!is_lp_cluster() && tegra_dfll &&
283             tegra_dvfs_rail_is_dfll_mode(tegra_cpu_rail))
284                 tegra_clk_cfg_ex(tegra_dfll, TEGRA_CLK_DFLL_LOCK, 1);
285 #endif
286 }
287
288 /*
289  * create_suspend_pgtable
290  *
291  * Creates a page table with identity mappings of physical memory and IRAM
292  * for use when the MMU is off, in addition to all the regular kernel mappings.
293  */
294 static __init int create_suspend_pgtable(void)
295 {
296         tegra_pgd = pgd_alloc(&init_mm);
297         if (!tegra_pgd)
298                 return -ENOMEM;
299
300         /* Only identity-map size of lowmem (high_memory - PAGE_OFFSET) */
301         identity_mapping_add(tegra_pgd, phys_to_virt(PHYS_OFFSET),
302                 high_memory, 0);
303         identity_mapping_add(tegra_pgd, IO_IRAM_VIRT,
304                 IO_IRAM_VIRT + SECTION_SIZE, 0);
305
306         /* inner/outer write-back/write-allocate, sharable */
307         tegra_pgd_phys = (virt_to_phys(tegra_pgd) & PAGE_MASK) | 0x4A;
308
309         return 0;
310 }
311
312 /* ensures that sufficient time is passed for a register write to
313  * serialize into the 32KHz domain */
314 static void pmc_32kwritel(u32 val, unsigned long offs)
315 {
316         writel(val, pmc + offs);
317         udelay(130);
318 }
319
320 static void set_power_timers(unsigned long us_on, unsigned long us_off,
321                              long rate)
322 {
323         static unsigned long last_us_off = 0;
324         unsigned long long ticks;
325         unsigned long long pclk;
326
327         if (WARN_ON_ONCE(rate <= 0))
328                 pclk = 100000000;
329         else
330                 pclk = rate;
331
332         if ((rate != tegra_last_pclk) || (us_off != last_us_off)) {
333                 ticks = (us_on * pclk) + 999999ull;
334                 do_div(ticks, 1000000);
335                 writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
336
337                 ticks = (us_off * pclk) + 999999ull;
338                 do_div(ticks, 1000000);
339                 writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
340                 wmb();
341         }
342         tegra_last_pclk = pclk;
343         last_us_off = us_off;
344 }
345
346 /*
347  * restore_cpu_complex
348  *
349  * restores cpu clock setting, clears flow controller
350  *
351  * Always called on CPU 0.
352  */
353 static void restore_cpu_complex(u32 mode)
354 {
355         int cpu = cpu_logical_map(smp_processor_id());
356         unsigned int reg;
357 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
358         unsigned int policy;
359 #endif
360
361 /*
362  * On Tegra11x PLLX and CPU burst policy is either preserved across LP2,
363  * or restored by common clock suspend/resume procedures. Hence, we don't
364  * need it here.
365  */
366 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
367         /* Is CPU complex already running on PLLX? */
368         reg = readl(clk_rst + CLK_RESET_CCLK_BURST);
369         policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
370
371         if (policy == CLK_RESET_CCLK_IDLE_POLICY)
372                 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
373         else if (policy == CLK_RESET_CCLK_RUN_POLICY)
374                 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
375         else
376                 BUG();
377
378         if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
379                 /* restore PLLX settings if CPU is on different PLL */
380                 writel(tegra_sctx.pllx_misc, clk_rst + CLK_RESET_PLLX_MISC);
381                 writel(tegra_sctx.pllx_base, clk_rst + CLK_RESET_PLLX_BASE);
382
383                 /* wait for PLL stabilization if PLLX was enabled */
384                 if (tegra_sctx.pllx_base & (1<<30)) {
385 #if USE_PLL_LOCK_BITS
386                         /* Enable lock detector */
387                         reg = readl(clk_rst + CLK_RESET_PLLX_MISC);
388                         reg |= 1<<18;
389                         writel(reg, clk_rst + CLK_RESET_PLLX_MISC);
390                         while (!(readl(clk_rst + CLK_RESET_PLLX_BASE) &
391                                  (1<<27)))
392                                 cpu_relax();
393
394                         udelay(PLL_POST_LOCK_DELAY);
395 #else
396                         udelay(300);
397 #endif
398                 }
399         }
400
401         /* Restore original burst policy setting for calls resulting from CPU
402            LP2 in idle or system suspend; keep cluster switch prolog setting
403            intact. */
404         if (!(mode & TEGRA_POWER_CLUSTER_MASK)) {
405                 writel(tegra_sctx.cclk_divider, clk_rst +
406                        CLK_RESET_CCLK_DIVIDER);
407                 writel(tegra_sctx.cpu_burst, clk_rst +
408                        CLK_RESET_CCLK_BURST);
409         }
410 #endif
411         writel(tegra_sctx.clk_csite_src, clk_rst + CLK_RESET_SOURCE_CSITE);
412
413         /* Do not power-gate CPU 0 when flow controlled */
414         reg = readl(FLOW_CTRL_CPU_CSR(cpu));
415         reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
416         reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
417         reg &= ~FLOW_CTRL_CSR_ENABLE;           /* clear enable */
418         reg |= FLOW_CTRL_CSR_INTR_FLAG;         /* clear intr */
419         reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event */
420         flowctrl_writel(reg, FLOW_CTRL_CPU_CSR(cpu));
421
422         /* If an immedidate cluster switch is being perfomed, restore the
423            local timer registers. For calls resulting from CPU LP2 in
424            idle or system suspend, the local timer was shut down and
425            timekeeping switched over to the global system timer. In this
426            case keep local timer disabled, and restore only periodic load. */
427         if (!(mode & (TEGRA_POWER_CLUSTER_MASK |
428                       TEGRA_POWER_CLUSTER_IMMEDIATE))) {
429 #ifdef CONFIG_ARM_ARCH_TIMER
430                 tegra_sctx.arch_timer.cntp_ctl = 0;
431 #endif
432 #ifdef CONFIG_HAVE_ARM_TWD
433                 tegra_sctx.twd.twd_ctrl = 0;
434 #endif
435         }
436 #ifdef CONFIG_ARM_ARCH_TIMER
437         arch_timer_resume(&tegra_sctx.arch_timer);
438 #endif
439 #ifdef CONFIG_HAVE_ARM_TWD
440         tegra_twd_resume(&tegra_sctx.twd);
441 #endif
442 }
443
444 /*
445  * suspend_cpu_complex
446  *
447  * saves pll state for use by restart_plls, prepares flow controller for
448  * transition to suspend state
449  *
450  * Must always be called on cpu 0.
451  */
452 static void suspend_cpu_complex(u32 mode)
453 {
454         int cpu = cpu_logical_map(smp_processor_id());
455         unsigned int reg;
456         int i;
457
458         BUG_ON(cpu != 0);
459
460         /* switch coresite to clk_m, save off original source */
461         tegra_sctx.clk_csite_src = readl(clk_rst + CLK_RESET_SOURCE_CSITE);
462         writel(3<<30, clk_rst + CLK_RESET_SOURCE_CSITE);
463
464         tegra_sctx.cpu_burst = readl(clk_rst + CLK_RESET_CCLK_BURST);
465         tegra_sctx.pllx_base = readl(clk_rst + CLK_RESET_PLLX_BASE);
466         tegra_sctx.pllx_misc = readl(clk_rst + CLK_RESET_PLLX_MISC);
467         tegra_sctx.pllp_base = readl(clk_rst + CLK_RESET_PLLP_BASE);
468         tegra_sctx.pllp_outa = readl(clk_rst + CLK_RESET_PLLP_OUTA);
469         tegra_sctx.pllp_outb = readl(clk_rst + CLK_RESET_PLLP_OUTB);
470         tegra_sctx.pllp_misc = readl(clk_rst + CLK_RESET_PLLP_MISC);
471         tegra_sctx.cclk_divider = readl(clk_rst + CLK_RESET_CCLK_DIVIDER);
472
473 #ifdef CONFIG_HAVE_ARM_TWD
474         tegra_twd_suspend(&tegra_sctx.twd);
475 #endif
476 #ifdef CONFIG_ARM_ARCH_TIMER
477         arch_timer_suspend(&tegra_sctx.arch_timer);
478 #endif
479
480         reg = readl(FLOW_CTRL_CPU_CSR(cpu));
481         reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
482         reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
483         reg |= FLOW_CTRL_CSR_INTR_FLAG;         /* clear intr flag */
484         reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event flag */
485 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
486         reg |= FLOW_CTRL_CSR_WFE_CPU0 << cpu;   /* enable power gating on wfe */
487 #else
488         reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu;   /* enable power gating on wfi */
489 #endif
490         reg |= FLOW_CTRL_CSR_ENABLE;            /* enable power gating */
491         flowctrl_writel(reg, FLOW_CTRL_CPU_CSR(cpu));
492
493         for (i = 0; i < num_possible_cpus(); i++) {
494                 if (i == cpu)
495                         continue;
496                 reg = readl(FLOW_CTRL_CPU_CSR(i));
497                 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
498                 reg |= FLOW_CTRL_CSR_INTR_FLAG;
499                 flowctrl_writel(reg, FLOW_CTRL_CPU_CSR(i));
500         }
501
502         tegra_gic_cpu_disable(true);
503 }
504
505 void tegra_clear_cpu_in_pd(int cpu)
506 {
507         spin_lock(&tegra_lp2_lock);
508         BUG_ON(!cpumask_test_cpu(cpu, &tegra_in_lp2));
509         cpumask_clear_cpu(cpu, &tegra_in_lp2);
510
511         /* Update the IRAM copy used by the reset handler. The IRAM copy
512            can't use used directly by cpumask_clear_cpu() because it uses
513            LDREX/STREX which requires the addressed location to be inner
514            cacheable and sharable which IRAM isn't. */
515         writel(tegra_in_lp2.bits[0], iram_cpu_lp2_mask);
516         dsb();
517
518         spin_unlock(&tegra_lp2_lock);
519 }
520
521 bool tegra_set_cpu_in_pd(int cpu)
522 {
523         bool last_cpu = false;
524
525         spin_lock(&tegra_lp2_lock);
526         BUG_ON(cpumask_test_cpu(cpu, &tegra_in_lp2));
527         cpumask_set_cpu(cpu, &tegra_in_lp2);
528
529         /* Update the IRAM copy used by the reset handler. The IRAM copy
530            can't use used directly by cpumask_set_cpu() because it uses
531            LDREX/STREX which requires the addressed location to be inner
532            cacheable and sharable which IRAM isn't. */
533         writel(tegra_in_lp2.bits[0], iram_cpu_lp2_mask);
534         dsb();
535
536         if ((cpu == 0) && cpumask_equal(&tegra_in_lp2, cpu_online_mask))
537                 last_cpu = true;
538 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
539         else if (cpu == 1)
540                 tegra2_cpu_set_resettable_soon();
541 #endif
542
543         spin_unlock(&tegra_lp2_lock);
544         return last_cpu;
545 }
546
547 static void tegra_sleep_core(enum tegra_suspend_mode mode,
548                              unsigned long v2p)
549 {
550 #ifdef CONFIG_TRUSTED_FOUNDATIONS
551         outer_flush_range(__pa(&tegra_resume_timestamps_start),
552                           __pa(&tegra_resume_timestamps_end));
553
554         if (mode == TEGRA_SUSPEND_LP0) {
555                 trace_smc_sleep_core(NVSEC_SMC_START);
556
557                 tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE3,
558                                   virt_to_phys(tegra_resume));
559         } else {
560                 trace_smc_sleep_core(NVSEC_SMC_START);
561
562                 tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE6,
563                                   (TEGRA_RESET_HANDLER_BASE +
564                                    tegra_cpu_reset_handler_offset));
565         }
566
567         trace_smc_sleep_core(NVSEC_SMC_DONE);
568 #endif
569 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
570         cpu_suspend(v2p, tegra2_sleep_core_finish);
571 #else
572         cpu_suspend(v2p, tegra3_sleep_core_finish);
573 #endif
574 }
575
576 static inline void tegra_sleep_cpu(unsigned long v2p)
577 {
578 #ifdef CONFIG_TRUSTED_FOUNDATIONS
579         outer_flush_range(__pa(&tegra_resume_timestamps_start),
580                           __pa(&tegra_resume_timestamps_end));
581         trace_smc_sleep_cpu(NVSEC_SMC_START);
582
583         tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4,
584                           (TEGRA_RESET_HANDLER_BASE +
585                            tegra_cpu_reset_handler_offset));
586
587         trace_smc_sleep_cpu(NVSEC_SMC_DONE);
588 #endif
589         cpu_suspend(v2p, tegra_sleep_cpu_finish);
590 }
591
592 unsigned int tegra_idle_power_down_last(unsigned int sleep_time,
593                                         unsigned int flags)
594 {
595         u32 reg;
596         unsigned int remain;
597 #ifdef CONFIG_CACHE_L2X0
598         pgd_t *pgd;
599 #endif
600
601         /* Only the last cpu down does the final suspend steps */
602         reg = readl(pmc + PMC_CTRL);
603         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
604         if (pdata->combined_req)
605                 reg &= ~TEGRA_POWER_PWRREQ_OE;
606         else
607                 reg |= TEGRA_POWER_PWRREQ_OE;
608
609         reg &= ~TEGRA_POWER_EFFECT_LP0;
610         writel(reg, pmc + PMC_CTRL);
611
612         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_start);
613
614         /*
615          * We can use clk_get_rate_all_locked() here, because all other cpus
616          * are in LP2 state and irqs are disabled
617          */
618         if (flags & TEGRA_POWER_CLUSTER_MASK) {
619                 trace_nvcpu_cluster(NVPOWER_CPU_CLUSTER_START);
620                 set_power_timers(pdata->cpu_timer, 2,
621                         clk_get_rate_all_locked(tegra_pclk));
622                 if (flags & TEGRA_POWER_CLUSTER_G) {
623                         /*
624                          * To reduce the vdd_cpu up latency when LP->G
625                          * transition. Before the transition, enable
626                          * the vdd_cpu rail.
627                          */
628                         if (is_lp_cluster()) {
629 #if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE)
630                                 reg = readl(FLOW_CTRL_CPU_PWR_CSR);
631                                 reg |= FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE;
632                                 writel(reg, FLOW_CTRL_CPU_PWR_CSR);
633 #else
634                                 writel(UN_PWRGATE_CPU,
635                                        pmc + PMC_PWRGATE_TOGGLE);
636 #endif
637                         }
638                 }
639                 tegra_cluster_switch_prolog(flags);
640         } else {
641                 suspend_cpu_dfll_mode();
642                 set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer,
643                         clk_get_rate_all_locked(tegra_pclk));
644 #if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE)
645                 reg = readl(FLOW_CTRL_CPU_CSR(0));
646                 reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
647                 if (is_lp_cluster()) {
648                         /* for LP cluster, there is no option for rail gating */
649                         if ((flags & TEGRA_POWER_CLUSTER_PART_MASK) ==
650                                                 TEGRA_POWER_CLUSTER_PART_MASK)
651                                 reg |= FLOW_CTRL_CSR_ENABLE_EXT_EMU;
652                         else if (flags)
653                                 reg |= FLOW_CTRL_CSR_ENABLE_EXT_NCPU;
654                 }
655                 else {
656                         if (flags & TEGRA_POWER_CLUSTER_PART_CRAIL)
657                                 reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
658                         if (flags & TEGRA_POWER_CLUSTER_PART_NONCPU)
659                                 reg |= FLOW_CTRL_CSR_ENABLE_EXT_NCPU;
660                 }
661                 writel(reg, FLOW_CTRL_CPU_CSR(0));
662 #endif
663         }
664
665         if (sleep_time)
666                 tegra_pd_set_trigger(sleep_time);
667
668         cpu_cluster_pm_enter();
669         suspend_cpu_complex(flags);
670         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_prolog);
671 #ifdef CONFIG_CACHE_L2X0
672         flush_cache_all();
673         /*
674          * No need to flush complete L2. Cleaning kernel and IO mappings
675          * is enough for the LP code sequence that has L2 disabled but
676          * MMU on.
677          */
678         pgd = cpu_get_pgd();
679         outer_clean_range(__pa(pgd + USER_PTRS_PER_PGD),
680                           __pa(pgd + PTRS_PER_PGD));
681         outer_disable();
682 #endif
683         tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
684
685         tegra_init_cache(false);
686
687 #ifdef CONFIG_TRUSTED_FOUNDATIONS
688 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
689         trace_smc_wake(tegra_resume_smc_entry_time, NVSEC_SMC_START);
690         trace_smc_wake(tegra_resume_smc_exit_time, NVSEC_SMC_DONE);
691 #endif
692 #endif
693
694         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_switch);
695         restore_cpu_complex(flags);
696         cpu_cluster_pm_exit();
697
698         remain = tegra_pd_timer_remain();
699         if (sleep_time)
700                 tegra_pd_set_trigger(0);
701
702         if (flags & TEGRA_POWER_CLUSTER_MASK) {
703                 tegra_cluster_switch_epilog(flags);
704                 if (is_idle_task(current))
705                         trace_nvcpu_cluster_rcuidle(NVPOWER_CPU_CLUSTER_DONE);
706                 else
707                         trace_nvcpu_cluster(NVPOWER_CPU_CLUSTER_DONE);
708         } else {
709                 resume_cpu_dfll_mode();
710         }
711         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_epilog);
712
713 #if INSTRUMENT_CLUSTER_SWITCH
714         if (flags & TEGRA_POWER_CLUSTER_MASK) {
715                 pr_err("%s: prolog %lu us, switch %lu us, epilog %lu us, total %lu us\n",
716                         is_lp_cluster() ? "G=>LP" : "LP=>G",
717                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog] -
718                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start],
719                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch] -
720                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog],
721                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
722                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch],
723                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
724                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start]);
725         }
726 #endif
727         return remain;
728 }
729
730 static int tegra_common_suspend(void)
731 {
732         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
733
734         tegra_sctx.mc[0] = readl(mc + MC_SECURITY_START);
735         tegra_sctx.mc[1] = readl(mc + MC_SECURITY_SIZE);
736         tegra_sctx.mc[2] = readl(mc + MC_SECURITY_CFG2);
737
738         /* copy the reset vector and SDRAM shutdown code into IRAM */
739         memcpy(iram_save, iram_code, iram_save_size);
740         memcpy(iram_code, tegra_iram_start(), iram_save_size);
741
742         return 0;
743 }
744
745 static void tegra_common_resume(void)
746 {
747         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
748 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
749         void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
750 #endif
751
752         /* Clear DPD sample */
753         writel(0x0, pmc + PMC_DPD_SAMPLE);
754
755         writel(tegra_sctx.mc[0], mc + MC_SECURITY_START);
756         writel(tegra_sctx.mc[1], mc + MC_SECURITY_SIZE);
757         writel(tegra_sctx.mc[2], mc + MC_SECURITY_CFG2);
758 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
759         /* trigger emc mode write */
760         writel(EMC_MRW_DEV_NONE, emc + EMC_MRW_0);
761 #endif
762         /* clear scratch registers shared by suspend and the reset pen */
763         writel(0x0, pmc + PMC_SCRATCH39);
764         writel(0x0, pmc + PMC_SCRATCH41);
765
766         /* restore IRAM */
767         memcpy(iram_code, iram_save, iram_save_size);
768 }
769
770 static int tegra_suspend_prepare_late(void)
771 {
772 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
773         disable_irq(INT_SYS_STATS_MON);
774 #endif
775         return 0;
776 }
777
778 static void tegra_suspend_wake(void)
779 {
780 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
781         enable_irq(INT_SYS_STATS_MON);
782 #endif
783 }
784
785 static void tegra_pm_set(enum tegra_suspend_mode mode)
786 {
787         u32 reg, boot_flag;
788         unsigned long rate = 32768;
789
790         reg = readl(pmc + PMC_CTRL);
791         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
792         if (pdata->combined_req)
793                 reg &= ~TEGRA_POWER_PWRREQ_OE;
794         else
795                 reg |= TEGRA_POWER_PWRREQ_OE;
796         reg &= ~TEGRA_POWER_EFFECT_LP0;
797
798         switch (mode) {
799         case TEGRA_SUSPEND_LP0:
800 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
801                 rate = clk_get_rate_all_locked(tegra_pclk);
802 #endif
803                 if (pdata->combined_req) {
804                         reg |= TEGRA_POWER_PWRREQ_OE;
805                         reg &= ~TEGRA_POWER_CPU_PWRREQ_OE;
806                 }
807
808                 /*
809                  * LP0 boots through the AVP, which then resumes the AVP to
810                  * the address in scratch 39, and the cpu to the address in
811                  * scratch 41 to tegra_resume
812                  */
813                 writel(0x0, pmc + PMC_SCRATCH39);
814
815                 /* Enable DPD sample to trigger sampling pads data and direction
816                  * in which pad will be driven during lp0 mode*/
817                 writel(0x1, pmc + PMC_DPD_SAMPLE);
818 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
819                 /* this is needed only for T11x, not for other chips */
820                 reg &= ~TEGRA_POWER_CPUPWRGOOD_EN;
821 #endif
822
823                 /* Set warmboot flag */
824                 boot_flag = readl(pmc + PMC_SCRATCH0);
825                 pmc_32kwritel(boot_flag | 1, PMC_SCRATCH0);
826
827                 pmc_32kwritel(tegra_lp0_vec_start, PMC_SCRATCH1);
828
829                 reg |= TEGRA_POWER_EFFECT_LP0;
830                 /* No break here. LP0 code falls through to write SCRATCH41 */
831         case TEGRA_SUSPEND_LP1:
832                 __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
833                 wmb();
834                 break;
835         case TEGRA_SUSPEND_LP2:
836                 rate = clk_get_rate(tegra_pclk);
837                 break;
838         case TEGRA_SUSPEND_NONE:
839                 return;
840         default:
841                 BUG();
842         }
843
844         set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer, rate);
845
846         pmc_32kwritel(reg, PMC_CTRL);
847 }
848
849 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
850         [TEGRA_SUSPEND_NONE] = "none",
851         [TEGRA_SUSPEND_LP2] = "LP2",
852         [TEGRA_SUSPEND_LP1] = "LP1",
853         [TEGRA_SUSPEND_LP0] = "LP0",
854 };
855
856 static int tegra_suspend_enter(suspend_state_t state)
857 {
858         int ret;
859         ktime_t delta;
860         struct timespec ts_entry, ts_exit;
861
862         if (pdata && pdata->board_suspend)
863                 pdata->board_suspend(current_suspend_mode, TEGRA_SUSPEND_BEFORE_PERIPHERAL);
864
865         read_persistent_clock(&ts_entry);
866
867         ret = tegra_suspend_dram(current_suspend_mode, 0);
868         if (ret) {
869                 pr_info("Aborting suspend, tegra_suspend_dram error=%d\n", ret);
870                 goto abort_suspend;
871         }
872
873         read_persistent_clock(&ts_exit);
874
875         if (timespec_compare(&ts_exit, &ts_entry) > 0) {
876                 delta = timespec_to_ktime(timespec_sub(ts_exit, ts_entry));
877
878                 tegra_dvfs_rail_pause(tegra_cpu_rail, delta, false);
879                 if (current_suspend_mode == TEGRA_SUSPEND_LP0)
880                         tegra_dvfs_rail_pause(tegra_core_rail, delta, false);
881                 else
882                         tegra_dvfs_rail_pause(tegra_core_rail, delta, true);
883         }
884
885 abort_suspend:
886         if (pdata && pdata->board_resume)
887                 pdata->board_resume(current_suspend_mode, TEGRA_RESUME_AFTER_PERIPHERAL);
888
889         return ret;
890 }
891
892 static void tegra_suspend_check_pwr_stats(void)
893 {
894         /* cpus and l2 are powered off later */
895         unsigned long pwrgate_partid_mask =
896 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
897                 (1 << TEGRA_POWERGATE_HEG)      |
898                 (1 << TEGRA_POWERGATE_SATA)     |
899                 (1 << TEGRA_POWERGATE_3D1)      |
900 #endif
901                 (1 << TEGRA_POWERGATE_3D)       |
902                 (1 << TEGRA_POWERGATE_VENC)     |
903                 (1 << TEGRA_POWERGATE_PCIE)     |
904                 (1 << TEGRA_POWERGATE_VDEC)     |
905                 (1 << TEGRA_POWERGATE_MPE);
906
907         int partid;
908
909         for (partid = 0; partid < TEGRA_NUM_POWERGATE; partid++)
910                 if ((1 << partid) & pwrgate_partid_mask)
911                         if (tegra_powergate_is_powered(partid))
912                                 pr_warning("partition %s is left on before suspend\n",
913                                         tegra_powergate_get_name(partid));
914
915         return;
916 }
917
918 int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
919 {
920         int err = 0;
921         u32 scratch37 = 0xDEADBEEF;
922         u32 reg;
923
924         if (WARN_ON(mode <= TEGRA_SUSPEND_NONE ||
925                 mode >= TEGRA_MAX_SUSPEND_MODE)) {
926                 err = -ENXIO;
927                 goto fail;
928         }
929
930         if (tegra_is_voice_call_active()) {
931                 /* backup the current value of scratch37 */
932                 scratch37 = readl(pmc + PMC_SCRATCH37);
933
934                 /* If voice call is active, set a flag in PMC_SCRATCH37 */
935                 reg = TEGRA_POWER_LP1_AUDIO;
936                 pmc_32kwritel(reg, PMC_SCRATCH37);
937         }
938
939         if ((mode == TEGRA_SUSPEND_LP0) && !tegra_pm_irq_lp0_allowed()) {
940                 pr_info("LP0 not used due to unsupported wakeup events\n");
941                 mode = TEGRA_SUSPEND_LP1;
942         }
943
944         if ((mode == TEGRA_SUSPEND_LP0) || (mode == TEGRA_SUSPEND_LP1))
945                 tegra_suspend_check_pwr_stats();
946
947         tegra_common_suspend();
948
949         tegra_pm_set(mode);
950
951         if (pdata && pdata->board_suspend)
952                 pdata->board_suspend(mode, TEGRA_SUSPEND_BEFORE_CPU);
953
954         local_fiq_disable();
955
956         trace_cpu_suspend(CPU_SUSPEND_START, tegra_rtc_read_ms());
957
958         if (mode == TEGRA_SUSPEND_LP0) {
959 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
960                 reg = readl(pmc + PMC_SCRATCH4);
961                 if (is_lp_cluster())
962                         reg |= PMC_SCRATCH4_WAKE_CLUSTER_MASK;
963                 else
964                         reg &= (~PMC_SCRATCH4_WAKE_CLUSTER_MASK);
965                 pmc_32kwritel(reg, PMC_SCRATCH4);
966 #endif
967                 tegra_tsc_suspend();
968                 tegra_lp0_suspend_mc();
969                 tegra_cpu_reset_handler_save();
970                 tegra_tsc_wait_for_suspend();
971                 tegra_smp_clear_power_mask();
972         }
973         else if (mode == TEGRA_SUSPEND_LP1)
974                 *iram_cpu_lp1_mask = 1;
975
976         suspend_cpu_complex(flags);
977
978 #if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE)
979         /* In case of LP0/1, program external power gating accordinly */
980         if (mode == TEGRA_SUSPEND_LP0 || mode == TEGRA_SUSPEND_LP1) {
981                 reg = readl(FLOW_CTRL_CPU_CSR(0));
982                 if (is_lp_cluster())
983                         reg |= FLOW_CTRL_CSR_ENABLE_EXT_NCPU; /* Non CPU */
984                 else
985                         reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;  /* CRAIL */
986                 flowctrl_writel(reg, FLOW_CTRL_CPU_CSR(0));
987         }
988 #endif
989
990         flush_cache_all();
991         outer_flush_all();
992         outer_disable();
993
994         if (mode == TEGRA_SUSPEND_LP2)
995                 tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
996         else
997                 tegra_sleep_core(mode, PHYS_OFFSET - PAGE_OFFSET);
998
999         tegra_init_cache(true);
1000
1001 #ifdef CONFIG_TRUSTED_FOUNDATIONS
1002 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
1003         trace_smc_wake(tegra_resume_smc_entry_time, NVSEC_SMC_START);
1004         trace_smc_wake(tegra_resume_smc_exit_time, NVSEC_SMC_DONE);
1005 #endif
1006
1007         if (mode == TEGRA_SUSPEND_LP0) {
1008                 trace_secureos_init(tegra_resume_entry_time,
1009                         NVSEC_SUSPEND_EXIT_DONE);
1010         }
1011 #endif
1012
1013         if (mode == TEGRA_SUSPEND_LP0) {
1014
1015                 /* CPUPWRGOOD_EN is not enabled in HW so disabling this, *
1016                 * Otherwise it is creating issue in cluster switch after LP0 *
1017 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1018                 reg = readl(pmc+PMC_CTRL);
1019                 reg |= TEGRA_POWER_CPUPWRGOOD_EN;
1020                 pmc_32kwritel(reg, PMC_CTRL);
1021 #endif
1022                 */
1023
1024                 tegra_tsc_resume();
1025                 tegra_cpu_reset_handler_restore();
1026                 tegra_lp0_resume_mc();
1027                 tegra_tsc_wait_for_resume();
1028         } else if (mode == TEGRA_SUSPEND_LP1)
1029                 *iram_cpu_lp1_mask = 0;
1030
1031         /* if scratch37 was clobbered during LP1, restore it */
1032         if (scratch37 != 0xDEADBEEF)
1033                 pmc_32kwritel(scratch37, PMC_SCRATCH37);
1034
1035         restore_cpu_complex(flags);
1036
1037         /* for platforms where the core & CPU power requests are
1038          * combined as a single request to the PMU, transition out
1039          * of LP0 state by temporarily enabling both requests
1040          */
1041         if (mode == TEGRA_SUSPEND_LP0 && pdata->combined_req) {
1042                 reg = readl(pmc + PMC_CTRL);
1043                 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
1044                 pmc_32kwritel(reg, PMC_CTRL);
1045                 reg &= ~TEGRA_POWER_PWRREQ_OE;
1046                 pmc_32kwritel(reg, PMC_CTRL);
1047         }
1048
1049         if (pdata && pdata->board_resume)
1050                 pdata->board_resume(mode, TEGRA_RESUME_AFTER_CPU);
1051
1052         trace_cpu_suspend(CPU_SUSPEND_DONE, tegra_rtc_read_ms());
1053
1054         local_fiq_enable();
1055
1056         tegra_common_resume();
1057
1058 fail:
1059         return err;
1060 }
1061
1062 /*
1063  * Function pointers to optional board specific function
1064  */
1065 void (*tegra_deep_sleep)(int);
1066 EXPORT_SYMBOL(tegra_deep_sleep);
1067
1068 static int tegra_suspend_prepare(void)
1069 {
1070         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
1071                 tegra_deep_sleep(1);
1072         return 0;
1073 }
1074
1075 static void tegra_suspend_finish(void)
1076 {
1077         if (pdata && pdata->cpu_resume_boost) {
1078                 int ret = tegra_suspended_target(pdata->cpu_resume_boost);
1079                 pr_info("Tegra: resume CPU boost to %u KHz: %s (%d)\n",
1080                         pdata->cpu_resume_boost, ret ? "Failed" : "OK", ret);
1081         }
1082
1083         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
1084                 tegra_deep_sleep(0);
1085 }
1086
1087 static const struct platform_suspend_ops tegra_suspend_ops = {
1088         .valid          = suspend_valid_only_mem,
1089         .prepare        = tegra_suspend_prepare,
1090         .finish         = tegra_suspend_finish,
1091         .prepare_late   = tegra_suspend_prepare_late,
1092         .wake           = tegra_suspend_wake,
1093         .enter          = tegra_suspend_enter,
1094 };
1095
1096 static ssize_t suspend_mode_show(struct kobject *kobj,
1097                                         struct kobj_attribute *attr, char *buf)
1098 {
1099         char *start = buf;
1100         char *end = buf + PAGE_SIZE;
1101
1102         start += scnprintf(start, end - start, "%s ", \
1103                                 tegra_suspend_name[current_suspend_mode]);
1104         start += scnprintf(start, end - start, "\n");
1105
1106         return start - buf;
1107 }
1108
1109 static ssize_t suspend_mode_store(struct kobject *kobj,
1110                                         struct kobj_attribute *attr,
1111                                         const char *buf, size_t n)
1112 {
1113         int len;
1114         const char *name_ptr;
1115         enum tegra_suspend_mode new_mode;
1116
1117         name_ptr = buf;
1118         while (*name_ptr && !isspace(*name_ptr))
1119                 name_ptr++;
1120         len = name_ptr - buf;
1121         if (!len)
1122                 goto bad_name;
1123         /* TEGRA_SUSPEND_NONE not allowed as suspend state */
1124         if (!(strncmp(buf, tegra_suspend_name[TEGRA_SUSPEND_NONE], len))
1125                 || !(strncmp(buf, tegra_suspend_name[TEGRA_SUSPEND_LP2], len))) {
1126                 pr_info("Illegal tegra suspend state: %s\n", buf);
1127                 goto bad_name;
1128         }
1129
1130         for (new_mode = TEGRA_SUSPEND_NONE; \
1131                         new_mode < TEGRA_MAX_SUSPEND_MODE; ++new_mode) {
1132                 if (!strncmp(buf, tegra_suspend_name[new_mode], len)) {
1133                         current_suspend_mode = new_mode;
1134                         break;
1135                 }
1136         }
1137
1138 bad_name:
1139         return n;
1140 }
1141
1142 static struct kobj_attribute suspend_mode_attribute =
1143         __ATTR(mode, 0644, suspend_mode_show, suspend_mode_store);
1144
1145 static struct kobject *suspend_kobj;
1146
1147 static int tegra_pm_enter_suspend(void)
1148 {
1149         pr_info("Entering suspend state %s\n", lp_state[current_suspend_mode]);
1150         suspend_cpu_dfll_mode();
1151         if (current_suspend_mode == TEGRA_SUSPEND_LP0)
1152                 tegra_lp0_cpu_mode(true);
1153         return 0;
1154 }
1155
1156 static void tegra_pm_enter_resume(void)
1157 {
1158         if (current_suspend_mode == TEGRA_SUSPEND_LP0)
1159                 tegra_lp0_cpu_mode(false);
1160         resume_cpu_dfll_mode();
1161         pr_info("Exited suspend state %s\n", lp_state[current_suspend_mode]);
1162 }
1163
1164 static struct syscore_ops tegra_pm_enter_syscore_ops = {
1165         .suspend = tegra_pm_enter_suspend,
1166         .resume = tegra_pm_enter_resume,
1167 };
1168
1169 static __init int tegra_pm_enter_syscore_init(void)
1170 {
1171         register_syscore_ops(&tegra_pm_enter_syscore_ops);
1172         return 0;
1173 }
1174 subsys_initcall(tegra_pm_enter_syscore_init);
1175 #endif
1176
1177 void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
1178 {
1179         u32 reg;
1180         u32 mode;
1181
1182 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
1183         tegra_dfll = clk_get_sys(NULL, "dfll_cpu");
1184         BUG_ON(IS_ERR(tegra_dfll));
1185 #endif
1186         tegra_pclk = clk_get_sys(NULL, "pclk");
1187         BUG_ON(IS_ERR(tegra_pclk));
1188         pdata = plat;
1189         (void)reg;
1190         (void)mode;
1191
1192         if (plat->suspend_mode == TEGRA_SUSPEND_LP2)
1193                 plat->suspend_mode = TEGRA_SUSPEND_LP0;
1194
1195 #ifndef CONFIG_PM_SLEEP
1196         if (plat->suspend_mode != TEGRA_SUSPEND_NONE) {
1197                 pr_warning("%s: Suspend requires CONFIG_PM_SLEEP -- "
1198                            "disabling suspend\n", __func__);
1199                 plat->suspend_mode = TEGRA_SUSPEND_NONE;
1200         }
1201 #else
1202         if (create_suspend_pgtable() < 0) {
1203                 pr_err("%s: PGD memory alloc failed -- LP0/LP1/LP2 unavailable\n",
1204                                 __func__);
1205                 plat->suspend_mode = TEGRA_SUSPEND_NONE;
1206                 goto fail;
1207         }
1208
1209         if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) &&
1210             (tegra_revision == TEGRA_REVISION_A01) &&
1211             (plat->suspend_mode == TEGRA_SUSPEND_LP0)) {
1212                 /* Tegra 3 A01 supports only LP1 */
1213                 pr_warning("%s: Suspend mode LP0 is not supported on A01 "
1214                            "-- disabling LP0\n", __func__);
1215                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
1216         }
1217         if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && tegra_lp0_vec_size &&
1218                 tegra_lp0_vec_relocate) {
1219                 unsigned char *reloc_lp0;
1220                 unsigned long tmp;
1221                 void __iomem *orig;
1222                 reloc_lp0 = kmalloc(tegra_lp0_vec_size + L1_CACHE_BYTES - 1,
1223                                         GFP_KERNEL);
1224                 WARN_ON(!reloc_lp0);
1225                 if (!reloc_lp0) {
1226                         pr_err("%s: Failed to allocate reloc_lp0\n",
1227                                 __func__);
1228                         goto out;
1229                 }
1230
1231                 orig = ioremap(tegra_lp0_vec_start, tegra_lp0_vec_size);
1232                 WARN_ON(!orig);
1233                 if (!orig) {
1234                         pr_err("%s: Failed to map tegra_lp0_vec_start %08lx\n",
1235                                 __func__, tegra_lp0_vec_start);
1236                         kfree(reloc_lp0);
1237                         goto out;
1238                 }
1239
1240                 tmp = (unsigned long) reloc_lp0;
1241                 tmp = (tmp + L1_CACHE_BYTES - 1) & ~(L1_CACHE_BYTES - 1);
1242                 reloc_lp0 = (unsigned char *)tmp;
1243                 memcpy(reloc_lp0, orig, tegra_lp0_vec_size);
1244                 iounmap(orig);
1245                 tegra_lp0_vec_start = virt_to_phys(reloc_lp0);
1246         }
1247
1248 out:
1249         if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && !tegra_lp0_vec_size) {
1250                 pr_warning("%s: Suspend mode LP0 requested, no lp0_vec "
1251                            "provided by bootlader -- disabling LP0\n",
1252                            __func__);
1253                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
1254         }
1255
1256         iram_save_size = tegra_iram_end() - tegra_iram_start();
1257
1258         iram_save = kmalloc(iram_save_size, GFP_KERNEL);
1259         if (!iram_save && (plat->suspend_mode >= TEGRA_SUSPEND_LP1)) {
1260                 pr_err("%s: unable to allocate memory for SDRAM self-refresh "
1261                        "-- LP0/LP1 unavailable\n", __func__);
1262                 plat->suspend_mode = TEGRA_SUSPEND_LP2;
1263         }
1264
1265 #ifdef CONFIG_TEGRA_LP1_950
1266         if (pdata->lp1_lowvolt_support) {
1267                 u32 lp1_core_lowvolt, lp1_core_highvolt;
1268                 memcpy(tegra_lp1_register_pmuslave_addr(), &pdata->pmuslave_addr, 4);
1269                 memcpy(tegra_lp1_register_i2c_base_addr(), &pdata->i2c_base_addr, 4);
1270
1271                 lp1_core_lowvolt = 0;
1272                 lp1_core_lowvolt = (pdata->lp1_core_volt_low << 8) | pdata->core_reg_addr;
1273                 memcpy(tegra_lp1_register_core_lowvolt(), &lp1_core_lowvolt, 4);
1274
1275                 lp1_core_highvolt = 0;
1276                 lp1_core_highvolt = (pdata->lp1_core_volt_high << 8) | pdata->core_reg_addr;
1277                 memcpy(tegra_lp1_register_core_highvolt(), &lp1_core_highvolt, 4);
1278         }
1279 #endif
1280         /* !!!FIXME!!! THIS IS TEGRA2 ONLY */
1281         /* Initialize scratch registers used for CPU LP2 synchronization */
1282         writel(0, pmc + PMC_SCRATCH37);
1283         writel(0, pmc + PMC_SCRATCH38);
1284         writel(0, pmc + PMC_SCRATCH39);
1285         writel(0, pmc + PMC_SCRATCH41);
1286
1287         /* Always enable CPU power request; just normal polarity is supported */
1288         reg = readl(pmc + PMC_CTRL);
1289         BUG_ON(reg & TEGRA_POWER_CPU_PWRREQ_POLARITY);
1290         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
1291         pmc_32kwritel(reg, PMC_CTRL);
1292
1293         /* Configure core power request and system clock control if LP0
1294            is supported */
1295         __raw_writel(pdata->core_timer, pmc + PMC_COREPWRGOOD_TIMER);
1296         __raw_writel(pdata->core_off_timer, pmc + PMC_COREPWROFF_TIMER);
1297
1298         reg = readl(pmc + PMC_CTRL);
1299
1300         if (!pdata->sysclkreq_high)
1301                 reg |= TEGRA_POWER_SYSCLK_POLARITY;
1302         else
1303                 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
1304
1305         if (!pdata->corereq_high)
1306                 reg |= TEGRA_POWER_PWRREQ_POLARITY;
1307         else
1308                 reg &= ~TEGRA_POWER_PWRREQ_POLARITY;
1309
1310         /* configure output inverters while the request is tristated */
1311         pmc_32kwritel(reg, PMC_CTRL);
1312
1313         /* now enable requests */
1314         reg |= TEGRA_POWER_SYSCLK_OE;
1315         if (!pdata->combined_req)
1316                 reg |= TEGRA_POWER_PWRREQ_OE;
1317         pmc_32kwritel(reg, PMC_CTRL);
1318
1319         if (pdata->suspend_mode == TEGRA_SUSPEND_LP0)
1320                 tegra_lp0_suspend_init();
1321
1322         suspend_set_ops(&tegra_suspend_ops);
1323
1324         /* Create /sys/power/suspend/type */
1325         suspend_kobj = kobject_create_and_add("suspend", power_kobj);
1326         if (suspend_kobj) {
1327                 if (sysfs_create_file(suspend_kobj, \
1328                                                 &suspend_mode_attribute.attr))
1329                         pr_err("%s: sysfs_create_file suspend type failed!\n",
1330                                                                 __func__);
1331         }
1332
1333         iram_cpu_lp2_mask = tegra_cpu_lp2_mask;
1334         iram_cpu_lp1_mask = tegra_cpu_lp1_mask;
1335
1336         /* clear io dpd settings before kernel */
1337         tegra_bl_io_dpd_cleanup();
1338
1339 fail:
1340 #endif
1341         if (plat->suspend_mode == TEGRA_SUSPEND_NONE)
1342                 tegra_pd_in_idle(false);
1343
1344         current_suspend_mode = plat->suspend_mode;
1345 }
1346
1347 unsigned long debug_uart_port_base = 0;
1348 EXPORT_SYMBOL(debug_uart_port_base);
1349
1350 static int tegra_debug_uart_suspend(void)
1351 {
1352         void __iomem *uart;
1353         u32 lcr;
1354
1355         if (!debug_uart_port_base)
1356                 return 0;
1357
1358         uart = IO_ADDRESS(debug_uart_port_base);
1359
1360         lcr = readb(uart + UART_LCR * 4);
1361
1362         tegra_sctx.uart[0] = lcr;
1363         tegra_sctx.uart[1] = readb(uart + UART_MCR * 4);
1364
1365         /* DLAB = 0 */
1366         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
1367
1368         tegra_sctx.uart[2] = readb(uart + UART_IER * 4);
1369
1370         /* DLAB = 1 */
1371         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
1372
1373         tegra_sctx.uart[3] = readb(uart + UART_DLL * 4);
1374         tegra_sctx.uart[4] = readb(uart + UART_DLM * 4);
1375
1376         writeb(lcr, uart + UART_LCR * 4);
1377
1378         return 0;
1379 }
1380
1381 static void tegra_debug_uart_resume(void)
1382 {
1383         void __iomem *uart;
1384         u32 lcr;
1385
1386         if (!debug_uart_port_base)
1387                 return;
1388
1389         uart = IO_ADDRESS(debug_uart_port_base);
1390
1391         lcr = tegra_sctx.uart[0];
1392
1393         writeb(tegra_sctx.uart[1], uart + UART_MCR * 4);
1394
1395         /* DLAB = 0 */
1396         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
1397
1398         writeb(UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_01 | UART_FCR_R_TRIG_01,
1399                         uart + UART_FCR * 4);
1400
1401         writeb(tegra_sctx.uart[2], uart + UART_IER * 4);
1402
1403         /* DLAB = 1 */
1404         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
1405
1406         writeb(tegra_sctx.uart[3], uart + UART_DLL * 4);
1407         writeb(tegra_sctx.uart[4], uart + UART_DLM * 4);
1408
1409         writeb(lcr, uart + UART_LCR * 4);
1410 }
1411
1412 static struct syscore_ops tegra_debug_uart_syscore_ops = {
1413         .suspend = tegra_debug_uart_suspend,
1414         .resume = tegra_debug_uart_resume,
1415 };
1416
1417 struct clk *debug_uart_clk = NULL;
1418 EXPORT_SYMBOL(debug_uart_clk);
1419
1420 void tegra_console_uart_suspend(void)
1421 {
1422         if (console_suspend_enabled && debug_uart_clk)
1423                 tegra_clk_disable_unprepare(debug_uart_clk);
1424 }
1425
1426 void tegra_console_uart_resume(void)
1427 {
1428         if (console_suspend_enabled && debug_uart_clk)
1429                 tegra_clk_prepare_enable(debug_uart_clk);
1430 }
1431
1432 static int tegra_debug_uart_syscore_init(void)
1433 {
1434         register_syscore_ops(&tegra_debug_uart_syscore_ops);
1435         return 0;
1436 }
1437 arch_initcall(tegra_debug_uart_syscore_init);