ARM: tegra: pm: suspend trace event
[linux-3.10.git] / arch / arm / mach-tegra / pm.c
1 /*
2  * arch/arm/mach-tegra/pm.c
3  *
4  * CPU complex suspend & resume functions for Tegra SoCs
5  *
6  * Copyright (c) 2009-2011, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/ctype.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/sched.h>
28 #include <linux/smp.h>
29 #include <linux/irq.h>
30 #include <linux/interrupt.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/debugfs.h>
34 #include <linux/delay.h>
35 #include <linux/suspend.h>
36 #include <linux/slab.h>
37 #include <linux/serial_reg.h>
38 #include <linux/seq_file.h>
39 #include <linux/uaccess.h>
40 #include <linux/syscore_ops.h>
41 #include <linux/cpu_pm.h>
42 #include <linux/clk/tegra.h>
43 #include <linux/export.h>
44 #include <linux/vmalloc.h>
45 #include <linux/memblock.h>
46 #include <linux/console.h>
47 #include <linux/tegra_audio.h>
48
49 #include <trace/events/power.h>
50
51 #include <asm/cacheflush.h>
52 #include <asm/hardware/cache-l2x0.h>
53 #include <asm/idmap.h>
54 #include <asm/localtimer.h>
55 #include <asm/pgalloc.h>
56 #include <asm/pgtable.h>
57 #include <asm/tlbflush.h>
58 #include <asm/suspend.h>
59
60 #include <mach/irqs.h>
61 #include <mach/powergate.h>
62
63 #include "board.h"
64 #include "clock.h"
65 #include "cpuidle.h"
66 #include "flowctrl.h"
67 #include "fuse.h"
68 #include "gic.h"
69 #include "iomap.h"
70 #include "pm.h"
71 #include "pm-irq.h"
72 #include "reset.h"
73 #include "sleep.h"
74 #include "timer.h"
75 #include "dvfs.h"
76 #include "cpu-tegra.h"
77
78 struct suspend_context {
79         /*
80          * The next 7 values are referenced by offset in __restart_plls
81          * in headsmp-t2.S, and should not be moved
82          */
83         u32 pllx_misc;
84         u32 pllx_base;
85         u32 pllp_misc;
86         u32 pllp_base;
87         u32 pllp_outa;
88         u32 pllp_outb;
89         u32 pll_timeout;
90
91         u32 cpu_burst;
92         u32 clk_csite_src;
93         u32 cclk_divider;
94
95         u32 mc[3];
96         u8 uart[5];
97
98         struct tegra_twd_context twd;
99 };
100
101 #ifdef CONFIG_PM_SLEEP
102 phys_addr_t tegra_pgd_phys;     /* pgd used by hotplug & LP2 bootup */
103 static pgd_t *tegra_pgd;
104 static DEFINE_SPINLOCK(tegra_lp2_lock);
105 static cpumask_t tegra_in_lp2;
106 static cpumask_t *iram_cpu_lp2_mask;
107 static unsigned long *iram_cpu_lp1_mask;
108 static u8 *iram_save;
109 static unsigned long iram_save_size;
110 static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA);
111 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
112 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
113 static int tegra_last_pclk;
114 #endif
115
116 struct suspend_context tegra_sctx;
117
118 #define TEGRA_POWER_PWRREQ_POLARITY     (1 << 8)   /* core power request polarity */
119 #define TEGRA_POWER_PWRREQ_OE           (1 << 9)   /* core power request enable */
120 #define TEGRA_POWER_SYSCLK_POLARITY     (1 << 10)  /* sys clk polarity */
121 #define TEGRA_POWER_SYSCLK_OE           (1 << 11)  /* system clock enable */
122 #define TEGRA_POWER_PWRGATE_DIS         (1 << 12)  /* power gate disabled */
123 #define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* enter LP0 when CPU pwr gated */
124 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU power request polarity */
125 #define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU power request enable */
126
127 #define PMC_CTRL                0x0
128 #define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
129 #define PMC_WAKE_MASK           0xc
130 #define PMC_WAKE_LEVEL          0x10
131 #define PMC_DPAD_ORIDE          0x1C
132 #define PMC_WAKE_DELAY          0xe0
133 #define PMC_DPD_SAMPLE          0x20
134
135 #define PMC_WAKE_STATUS         0x14
136 #define PMC_SW_WAKE_STATUS      0x18
137 #define PMC_COREPWRGOOD_TIMER   0x3c
138 #define PMC_CPUPWRGOOD_TIMER    0xc8
139 #define PMC_CPUPWROFF_TIMER     0xcc
140 #define PMC_COREPWROFF_TIMER    PMC_WAKE_DELAY
141
142 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
143 #define PMC_SCRATCH4_WAKE_CLUSTER_MASK  (1<<31)
144 #endif
145
146 #define CLK_RESET_CCLK_BURST    0x20
147 #define CLK_RESET_CCLK_DIVIDER  0x24
148 #define CLK_RESET_PLLC_BASE     0x80
149 #define CLK_RESET_PLLM_BASE     0x90
150 #define CLK_RESET_PLLX_BASE     0xe0
151 #define CLK_RESET_PLLX_MISC     0xe4
152 #define CLK_RESET_PLLP_BASE     0xa0
153 #define CLK_RESET_PLLP_OUTA     0xa4
154 #define CLK_RESET_PLLP_OUTB     0xa8
155 #define CLK_RESET_PLLP_MISC     0xac
156
157 #define CLK_RESET_SOURCE_CSITE  0x1d4
158
159 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
160 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT    4
161 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT   0
162 #define CLK_RESET_CCLK_IDLE_POLICY         1
163 #define CLK_RESET_CCLK_RUN_POLICY          2
164 #define CLK_RESET_CCLK_BURST_POLICY_PLLM   3
165 #define CLK_RESET_CCLK_BURST_POLICY_PLLX   8
166
167 #define EMC_MRW_0               0x0e8
168 #define EMC_MRW_DEV_SELECTN     30
169 #define EMC_MRW_DEV_NONE        (3 << EMC_MRW_DEV_SELECTN)
170
171 #define MC_SECURITY_START       0x6c
172 #define MC_SECURITY_SIZE        0x70
173 #define MC_SECURITY_CFG2        0x7c
174
175 struct dvfs_rail *tegra_cpu_rail;
176 static struct dvfs_rail *tegra_core_rail;
177 static struct clk *tegra_pclk;
178 static const struct tegra_suspend_platform_data *pdata;
179 static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
180
181 #if defined(CONFIG_TEGRA_CLUSTER_CONTROL) && INSTRUMENT_CLUSTER_SWITCH
182 enum tegra_cluster_switch_time_id {
183         tegra_cluster_switch_time_id_start = 0,
184         tegra_cluster_switch_time_id_prolog,
185         tegra_cluster_switch_time_id_switch,
186         tegra_cluster_switch_time_id_epilog,
187         tegra_cluster_switch_time_id_max
188 };
189
190 static unsigned long
191                 tegra_cluster_switch_times[tegra_cluster_switch_time_id_max];
192 #define tegra_cluster_switch_time(flags, id) \
193         do { \
194                 barrier(); \
195                 if (flags & TEGRA_POWER_CLUSTER_MASK) { \
196                         void __iomem *timer_us = \
197                                                 IO_ADDRESS(TEGRA_TMRUS_BASE); \
198                         if (id < tegra_cluster_switch_time_id_max) \
199                                 tegra_cluster_switch_times[id] = \
200                                                         readl(timer_us); \
201                                 wmb(); \
202                 } \
203                 barrier(); \
204         } while(0)
205 #else
206 #define tegra_cluster_switch_time(flags, id) do {} while(0)
207 #endif
208
209 #ifdef CONFIG_PM_SLEEP
210 static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
211         [TEGRA_SUSPEND_NONE]    = "none",
212         [TEGRA_SUSPEND_LP2]     = "lp2",
213         [TEGRA_SUSPEND_LP1]     = "lp1",
214         [TEGRA_SUSPEND_LP0]     = "lp0",
215 };
216
217 unsigned long tegra_cpu_power_good_time(void)
218 {
219         if (WARN_ON_ONCE(!pdata))
220                 return 5000;
221
222         return pdata->cpu_timer;
223 }
224
225 unsigned long tegra_cpu_power_off_time(void)
226 {
227         if (WARN_ON_ONCE(!pdata))
228                 return 5000;
229
230         return pdata->cpu_off_timer;
231 }
232
233 unsigned long tegra_cpu_lp2_min_residency(void)
234 {
235         if (WARN_ON_ONCE(!pdata))
236                 return 2000;
237
238         return pdata->cpu_lp2_min_residency;
239 }
240
241 /*
242  * create_suspend_pgtable
243  *
244  * Creates a page table with identity mappings of physical memory and IRAM
245  * for use when the MMU is off, in addition to all the regular kernel mappings.
246  */
247 static __init int create_suspend_pgtable(void)
248 {
249         tegra_pgd = pgd_alloc(&init_mm);
250         if (!tegra_pgd)
251                 return -ENOMEM;
252
253         /* Only identity-map size of lowmem (high_memory - PAGE_OFFSET) */
254         identity_mapping_add(tegra_pgd, phys_to_virt(PHYS_OFFSET),
255                 high_memory, 0);
256         identity_mapping_add(tegra_pgd, IO_IRAM_VIRT,
257                 IO_IRAM_VIRT + SECTION_SIZE, 0);
258
259         /* inner/outer write-back/write-allocate, sharable */
260         tegra_pgd_phys = (virt_to_phys(tegra_pgd) & PAGE_MASK) | 0x4A;
261
262         return 0;
263 }
264
265 /* ensures that sufficient time is passed for a register write to
266  * serialize into the 32KHz domain */
267 static void pmc_32kwritel(u32 val, unsigned long offs)
268 {
269         writel(val, pmc + offs);
270         udelay(130);
271 }
272
273 static void set_power_timers(unsigned long us_on, unsigned long us_off,
274                              long rate)
275 {
276         static unsigned long last_us_off = 0;
277         unsigned long long ticks;
278         unsigned long long pclk;
279
280         if (WARN_ON_ONCE(rate <= 0))
281                 pclk = 100000000;
282         else
283                 pclk = rate;
284
285         if ((rate != tegra_last_pclk) || (us_off != last_us_off)) {
286                 ticks = (us_on * pclk) + 999999ull;
287                 do_div(ticks, 1000000);
288                 writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
289
290                 ticks = (us_off * pclk) + 999999ull;
291                 do_div(ticks, 1000000);
292                 writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
293                 wmb();
294         }
295         tegra_last_pclk = pclk;
296         last_us_off = us_off;
297 }
298
299 /*
300  * restore_cpu_complex
301  *
302  * restores cpu clock setting, clears flow controller
303  *
304  * Always called on CPU 0.
305  */
306 static void restore_cpu_complex(u32 mode)
307 {
308         int cpu = smp_processor_id();
309         unsigned int reg, policy;
310
311         BUG_ON(cpu != 0);
312
313         /* Is CPU complex already running on PLLX? */
314         reg = readl(clk_rst + CLK_RESET_CCLK_BURST);
315         policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
316
317         if (policy == CLK_RESET_CCLK_IDLE_POLICY)
318                 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
319         else if (policy == CLK_RESET_CCLK_RUN_POLICY)
320                 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
321         else
322                 BUG();
323
324         if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
325                 /* restore PLLX settings if CPU is on different PLL */
326                 writel(tegra_sctx.pllx_misc, clk_rst + CLK_RESET_PLLX_MISC);
327                 writel(tegra_sctx.pllx_base, clk_rst + CLK_RESET_PLLX_BASE);
328
329                 /* wait for PLL stabilization if PLLX was enabled */
330                 if (tegra_sctx.pllx_base & (1<<30)) {
331 #if USE_PLL_LOCK_BITS
332                         /* Enable lock detector */
333                         reg = readl(clk_rst + CLK_RESET_PLLX_MISC);
334                         reg |= 1<<18;
335                         writel(reg, clk_rst + CLK_RESET_PLLX_MISC);
336                         while (!(readl(clk_rst + CLK_RESET_PLLX_BASE) &
337                                  (1<<27)))
338                                 cpu_relax();
339
340                         udelay(PLL_POST_LOCK_DELAY);
341 #else
342                         udelay(300);
343 #endif
344                 }
345         }
346
347         /* Restore original burst policy setting for calls resulting from CPU
348            LP2 in idle or system suspend; keep cluster switch prolog setting
349            intact. */
350         if (!(mode & TEGRA_POWER_CLUSTER_MASK)) {
351                 writel(tegra_sctx.cclk_divider, clk_rst +
352                        CLK_RESET_CCLK_DIVIDER);
353                 writel(tegra_sctx.cpu_burst, clk_rst +
354                        CLK_RESET_CCLK_BURST);
355         }
356
357         writel(tegra_sctx.clk_csite_src, clk_rst + CLK_RESET_SOURCE_CSITE);
358
359         /* Do not power-gate CPU 0 when flow controlled */
360         reg = flowctrl_read_cpu_csr(cpu);
361         reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
362         reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
363         reg &= ~FLOW_CTRL_CSR_ENABLE;           /* clear enable */
364         reg |= FLOW_CTRL_CSR_INTR_FLAG;         /* clear intr */
365         reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event */
366         flowctrl_write_cpu_csr(cpu, reg);
367
368         /* If an immedidate cluster switch is being perfomed, restore the
369            local timer registers. For calls resulting from CPU LP2 in
370            idle or system suspend, the local timer was shut down and
371            timekeeping switched over to the global system timer. In this
372            case keep local timer disabled, and restore only periodic load. */
373         if (!(mode & (TEGRA_POWER_CLUSTER_MASK |
374                       TEGRA_POWER_CLUSTER_IMMEDIATE)))
375                 tegra_sctx.twd.twd_ctrl = 0;
376         tegra_twd_resume(&tegra_sctx.twd);
377 }
378
379 /*
380  * suspend_cpu_complex
381  *
382  * saves pll state for use by restart_plls, prepares flow controller for
383  * transition to suspend state
384  *
385  * Must always be called on cpu 0.
386  */
387 static void suspend_cpu_complex(u32 mode)
388 {
389         int cpu = smp_processor_id();
390         unsigned int reg;
391         int i;
392
393         BUG_ON(cpu != 0);
394
395         /* switch coresite to clk_m, save off original source */
396         tegra_sctx.clk_csite_src = readl(clk_rst + CLK_RESET_SOURCE_CSITE);
397         writel(3<<30, clk_rst + CLK_RESET_SOURCE_CSITE);
398
399         tegra_sctx.cpu_burst = readl(clk_rst + CLK_RESET_CCLK_BURST);
400         tegra_sctx.pllx_base = readl(clk_rst + CLK_RESET_PLLX_BASE);
401         tegra_sctx.pllx_misc = readl(clk_rst + CLK_RESET_PLLX_MISC);
402         tegra_sctx.pllp_base = readl(clk_rst + CLK_RESET_PLLP_BASE);
403         tegra_sctx.pllp_outa = readl(clk_rst + CLK_RESET_PLLP_OUTA);
404         tegra_sctx.pllp_outb = readl(clk_rst + CLK_RESET_PLLP_OUTB);
405         tegra_sctx.pllp_misc = readl(clk_rst + CLK_RESET_PLLP_MISC);
406         tegra_sctx.cclk_divider = readl(clk_rst + CLK_RESET_CCLK_DIVIDER);
407
408         tegra_twd_suspend(&tegra_sctx.twd);
409
410         reg = flowctrl_read_cpu_csr(cpu);
411         reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
412         reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
413         reg |= FLOW_CTRL_CSR_INTR_FLAG;         /* clear intr flag */
414         reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event flag */
415 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
416         reg |= FLOW_CTRL_CSR_WFE_CPU0 << cpu;   /* enable power gating on wfe */
417 #else
418         reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu;   /* enable power gating on wfi */
419 #endif
420         reg |= FLOW_CTRL_CSR_ENABLE;            /* enable power gating */
421         flowctrl_write_cpu_csr(cpu, reg);
422
423         for (i = 0; i < num_possible_cpus(); i++) {
424                 if (i == cpu)
425                         continue;
426                 reg = flowctrl_read_cpu_csr(i);
427                 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
428                 reg |= FLOW_CTRL_CSR_INTR_FLAG;
429                 flowctrl_write_cpu_csr(i, reg);
430         }
431
432         tegra_gic_cpu_disable();
433 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
434         /* Tegra3 enters LPx states via WFI - do not propagate legacy IRQs
435            to CPU core to avoid fall through WFI (IRQ-to-flow controller wake
436            path is not affected). */
437         tegra_gic_pass_through_disable();
438 #endif
439 }
440
441 void tegra_clear_cpu_in_lp2(int cpu)
442 {
443         spin_lock(&tegra_lp2_lock);
444         BUG_ON(!cpumask_test_cpu(cpu, &tegra_in_lp2));
445         cpumask_clear_cpu(cpu, &tegra_in_lp2);
446
447         /* Update the IRAM copy used by the reset handler. The IRAM copy
448            can't use used directly by cpumask_clear_cpu() because it uses
449            LDREX/STREX which requires the addressed location to be inner
450            cacheable and sharable which IRAM isn't. */
451         writel(tegra_in_lp2.bits[0], iram_cpu_lp2_mask);
452         dsb();
453
454         spin_unlock(&tegra_lp2_lock);
455 }
456
457 bool tegra_set_cpu_in_lp2(int cpu)
458 {
459         bool last_cpu = false;
460
461         spin_lock(&tegra_lp2_lock);
462         BUG_ON(cpumask_test_cpu(cpu, &tegra_in_lp2));
463         cpumask_set_cpu(cpu, &tegra_in_lp2);
464
465         /* Update the IRAM copy used by the reset handler. The IRAM copy
466            can't use used directly by cpumask_set_cpu() because it uses
467            LDREX/STREX which requires the addressed location to be inner
468            cacheable and sharable which IRAM isn't. */
469         writel(tegra_in_lp2.bits[0], iram_cpu_lp2_mask);
470         dsb();
471
472         if ((cpu == 0) && cpumask_equal(&tegra_in_lp2, cpu_online_mask))
473                 last_cpu = true;
474 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
475         else if (cpu == 1)
476                 tegra2_cpu_set_resettable_soon();
477 #endif
478
479         spin_unlock(&tegra_lp2_lock);
480         return last_cpu;
481 }
482
483 static inline void tegra_sleep_cpu(unsigned long v2p)
484 {
485         cpu_suspend(v2p, tegra_sleep_cpu_finish);
486 }
487
488 unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
489 {
490         u32 mode;       /* hardware + software power mode flags */
491         unsigned int remain;
492         pgd_t *pgd;
493
494         /* Only the last cpu down does the final suspend steps */
495         mode = readl(pmc + PMC_CTRL);
496         mode |= TEGRA_POWER_CPU_PWRREQ_OE;
497         if (pdata->combined_req)
498                 mode &= ~TEGRA_POWER_PWRREQ_OE;
499         else
500                 mode |= TEGRA_POWER_PWRREQ_OE;
501         mode &= ~TEGRA_POWER_EFFECT_LP0;
502         writel(mode, pmc + PMC_CTRL);
503         mode |= flags;
504
505         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_start);
506
507         /*
508          * We can use clk_get_rate_all_locked() here, because all other cpus
509          * are in LP2 state and irqs are disabled
510          */
511         if (flags & TEGRA_POWER_CLUSTER_MASK) {
512                 trace_cpu_cluster(POWER_CPU_CLUSTER_START);
513                 set_power_timers(pdata->cpu_timer, 0,
514                         clk_get_rate_all_locked(tegra_pclk));
515                 tegra_cluster_switch_prolog(mode);
516         } else {
517                 set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer,
518                         clk_get_rate_all_locked(tegra_pclk));
519         }
520
521         if (sleep_time)
522                 tegra_lp2_set_trigger(sleep_time);
523
524         cpu_cluster_pm_enter();
525         suspend_cpu_complex(mode);
526         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_prolog);
527         flush_cache_all();
528         /*
529          * No need to flush complete L2. Cleaning kernel and IO mappings
530          * is enough for the LP code sequence that has L2 disabled but
531          * MMU on.
532          */
533         pgd = cpu_get_pgd();
534         outer_clean_range(__pa(pgd + USER_PTRS_PER_PGD),
535                           __pa(pgd + PTRS_PER_PGD));
536         outer_disable();
537
538         tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
539
540 #ifdef CONFIG_CACHE_L2X0
541         tegra_init_cache(false);
542         l2x0_enable();
543 #endif
544         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_switch);
545         restore_cpu_complex(mode);
546         cpu_cluster_pm_exit();
547
548         remain = tegra_lp2_timer_remain();
549         if (sleep_time)
550                 tegra_lp2_set_trigger(0);
551
552         if (flags & TEGRA_POWER_CLUSTER_MASK) {
553                 tegra_cluster_switch_epilog(mode);
554                 trace_cpu_cluster(POWER_CPU_CLUSTER_DONE);
555         }
556         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_epilog);
557
558 #if INSTRUMENT_CLUSTER_SWITCH
559         if (flags & TEGRA_POWER_CLUSTER_MASK) {
560                 pr_err("%s: prolog %lu us, switch %lu us, epilog %lu us, total %lu us\n",
561                         is_lp_cluster() ? "G=>LP" : "LP=>G",
562                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog] -
563                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start],
564                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch] -
565                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog],
566                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
567                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch],
568                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
569                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start]);
570         }
571 #endif
572         return remain;
573 }
574
575 static int tegra_common_suspend(void)
576 {
577         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
578
579         tegra_sctx.mc[0] = readl(mc + MC_SECURITY_START);
580         tegra_sctx.mc[1] = readl(mc + MC_SECURITY_SIZE);
581         tegra_sctx.mc[2] = readl(mc + MC_SECURITY_CFG2);
582
583         /* copy the reset vector and SDRAM shutdown code into IRAM */
584         memcpy(iram_save, iram_code, iram_save_size);
585         memcpy(iram_code, tegra_iram_start(), iram_save_size);
586
587         return 0;
588 }
589
590 static void tegra_common_resume(void)
591 {
592         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
593 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
594         void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
595 #endif
596
597         /* Clear DPD sample */
598         writel(0x0, pmc + PMC_DPD_SAMPLE);
599
600         writel(tegra_sctx.mc[0], mc + MC_SECURITY_START);
601         writel(tegra_sctx.mc[1], mc + MC_SECURITY_SIZE);
602         writel(tegra_sctx.mc[2], mc + MC_SECURITY_CFG2);
603 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
604         /* trigger emc mode write */
605         writel(EMC_MRW_DEV_NONE, emc + EMC_MRW_0);
606 #endif
607         /* clear scratch registers shared by suspend and the reset pen */
608         writel(0x0, pmc + PMC_SCRATCH39);
609         writel(0x0, pmc + PMC_SCRATCH41);
610
611         /* restore IRAM */
612         memcpy(iram_code, iram_save, iram_save_size);
613 }
614
615 static int tegra_suspend_prepare_late(void)
616 {
617 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
618         disable_irq(INT_SYS_STATS_MON);
619 #endif
620         return 0;
621 }
622
623 static void tegra_suspend_wake(void)
624 {
625 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
626         enable_irq(INT_SYS_STATS_MON);
627 #endif
628 }
629
630 static void tegra_pm_set(enum tegra_suspend_mode mode)
631 {
632         u32 reg, boot_flag;
633         unsigned long rate = 32768;
634
635         reg = readl(pmc + PMC_CTRL);
636         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
637         if (pdata->combined_req)
638                 reg &= ~TEGRA_POWER_PWRREQ_OE;
639         else
640                 reg |= TEGRA_POWER_PWRREQ_OE;
641         reg &= ~TEGRA_POWER_EFFECT_LP0;
642
643         switch (mode) {
644         case TEGRA_SUSPEND_LP0:
645 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
646                 rate = clk_get_rate_all_locked(tegra_pclk);
647 #endif
648                 if (pdata->combined_req) {
649                         reg |= TEGRA_POWER_PWRREQ_OE;
650                         reg &= ~TEGRA_POWER_CPU_PWRREQ_OE;
651                 }
652
653                 /*
654                  * LP0 boots through the AVP, which then resumes the AVP to
655                  * the address in scratch 39, and the cpu to the address in
656                  * scratch 41 to tegra_resume
657                  */
658                 writel(0x0, pmc + PMC_SCRATCH39);
659
660                 /* Enable DPD sample to trigger sampling pads data and direction
661                  * in which pad will be driven during lp0 mode*/
662                 writel(0x1, pmc + PMC_DPD_SAMPLE);
663
664                 /* Set warmboot flag */
665                 boot_flag = readl(pmc + PMC_SCRATCH0);
666                 pmc_32kwritel(boot_flag | 1, PMC_SCRATCH0);
667
668                 pmc_32kwritel(tegra_lp0_vec_start, PMC_SCRATCH1);
669
670                 reg |= TEGRA_POWER_EFFECT_LP0;
671                 /* No break here. LP0 code falls through to write SCRATCH41 */
672         case TEGRA_SUSPEND_LP1:
673                 __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
674                 wmb();
675                 break;
676         case TEGRA_SUSPEND_LP2:
677                 rate = clk_get_rate(tegra_pclk);
678                 break;
679         case TEGRA_SUSPEND_NONE:
680                 return;
681         default:
682                 BUG();
683         }
684
685         set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer, rate);
686
687         pmc_32kwritel(reg, PMC_CTRL);
688 }
689
690 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
691         [TEGRA_SUSPEND_NONE] = "none",
692         [TEGRA_SUSPEND_LP2] = "LP2",
693         [TEGRA_SUSPEND_LP1] = "LP1",
694         [TEGRA_SUSPEND_LP0] = "LP0",
695 };
696
697 static int tegra_suspend_enter(suspend_state_t state)
698 {
699         int ret;
700         ktime_t delta;
701         struct timespec ts_entry, ts_exit;
702
703         if (pdata && pdata->board_suspend)
704                 pdata->board_suspend(current_suspend_mode, TEGRA_SUSPEND_BEFORE_PERIPHERAL);
705
706         read_persistent_clock(&ts_entry);
707
708         ret = tegra_suspend_dram(current_suspend_mode, 0);
709         if (ret) {
710                 pr_info("Aborting suspend, tegra_suspend_dram error=%d\n", ret);
711                 goto abort_suspend;
712         }
713
714         read_persistent_clock(&ts_exit);
715
716         if (timespec_compare(&ts_exit, &ts_entry) > 0) {
717                 delta = timespec_to_ktime(timespec_sub(ts_exit, ts_entry));
718
719                 tegra_dvfs_rail_pause(tegra_cpu_rail, delta, false);
720                 if (current_suspend_mode == TEGRA_SUSPEND_LP0)
721                         tegra_dvfs_rail_pause(tegra_core_rail, delta, false);
722                 else
723                         tegra_dvfs_rail_pause(tegra_core_rail, delta, true);
724         }
725
726 abort_suspend:
727         if (pdata && pdata->board_resume)
728                 pdata->board_resume(current_suspend_mode, TEGRA_RESUME_AFTER_PERIPHERAL);
729
730         return ret;
731 }
732
733 static void tegra_suspend_check_pwr_stats(void)
734 {
735         /* cpus and l2 are powered off later */
736         unsigned long pwrgate_partid_mask =
737 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
738                 (1 << TEGRA_POWERGATE_HEG)      |
739                 (1 << TEGRA_POWERGATE_SATA)     |
740                 (1 << TEGRA_POWERGATE_3D1)      |
741 #endif
742                 (1 << TEGRA_POWERGATE_3D)       |
743                 (1 << TEGRA_POWERGATE_VENC)     |
744                 (1 << TEGRA_POWERGATE_PCIE)     |
745                 (1 << TEGRA_POWERGATE_VDEC)     |
746                 (1 << TEGRA_POWERGATE_MPE);
747
748         int partid;
749
750         for_each_set_bit(partid, &pwrgate_partid_mask, BITS_PER_LONG)
751                 if (tegra_powergate_is_powered(partid) == 1)
752                         pr_warning("partition %s is left on before suspend\n",
753                                 tegra_powergate_get_name(partid));
754
755         return;
756 }
757
758 int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
759 {
760         int err = 0;
761         u32 scratch37 = 0xDEADBEEF;
762
763         if (WARN_ON(mode <= TEGRA_SUSPEND_NONE ||
764                 mode >= TEGRA_MAX_SUSPEND_MODE)) {
765                 err = -ENXIO;
766                 goto fail;
767         }
768
769         if (tegra_is_voice_call_active()) {
770                 u32 reg;
771
772                 /* backup the current value of scratch37 */
773                 scratch37 = readl(pmc + PMC_SCRATCH37);
774
775                 /* If voice call is active, set a flag in PMC_SCRATCH37 */
776                 reg = TEGRA_POWER_LP1_AUDIO;
777                 pmc_32kwritel(reg, PMC_SCRATCH37);
778         }
779
780         if ((mode == TEGRA_SUSPEND_LP0) && !tegra_pm_irq_lp0_allowed()) {
781                 pr_info("LP0 not used due to unsupported wakeup events\n");
782                 mode = TEGRA_SUSPEND_LP1;
783         }
784
785         if ((mode == TEGRA_SUSPEND_LP0) || (mode == TEGRA_SUSPEND_LP1))
786                 tegra_suspend_check_pwr_stats();
787
788         tegra_common_suspend();
789
790         tegra_pm_set(mode);
791
792         if (pdata && pdata->board_suspend)
793                 pdata->board_suspend(mode, TEGRA_SUSPEND_BEFORE_CPU);
794
795         local_fiq_disable();
796
797         trace_cpu_suspend(CPU_SUSPEND_START);
798
799         cpu_pm_enter();
800         cpu_cluster_pm_enter();
801
802         if (mode == TEGRA_SUSPEND_LP0) {
803 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
804                 u32 reg = readl(pmc + PMC_SCRATCH4);
805                 if (is_lp_cluster())
806                         reg |= PMC_SCRATCH4_WAKE_CLUSTER_MASK;
807                 else
808                         reg &= (~PMC_SCRATCH4_WAKE_CLUSTER_MASK);
809                 pmc_32kwritel(reg, PMC_SCRATCH4);
810 #endif
811                 tegra_lp0_suspend_mc();
812                 tegra_cpu_reset_handler_save();
813
814         }
815         else if (mode == TEGRA_SUSPEND_LP1)
816                 *iram_cpu_lp1_mask = 1;
817
818         suspend_cpu_complex(flags);
819
820         flush_cache_all();
821         outer_flush_all();
822         outer_disable();
823
824         if (mode == TEGRA_SUSPEND_LP2)
825                 tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
826         else
827                 tegra_sleep_core(PHYS_OFFSET - PAGE_OFFSET);
828
829         tegra_init_cache(true);
830
831         if (mode == TEGRA_SUSPEND_LP0) {
832                 tegra_cpu_reset_handler_restore();
833                 tegra_lp0_resume_mc();
834         } else if (mode == TEGRA_SUSPEND_LP1)
835                 *iram_cpu_lp1_mask = 0;
836
837         /* if scratch37 was clobbered during LP1, restore it */
838         if (scratch37 != 0xDEADBEEF)
839                 pmc_32kwritel(scratch37, PMC_SCRATCH37);
840
841         restore_cpu_complex(flags);
842
843         /* for platforms where the core & CPU power requests are
844          * combined as a single request to the PMU, transition out
845          * of LP0 state by temporarily enabling both requests
846          */
847         if (mode == TEGRA_SUSPEND_LP0 && pdata->combined_req) {
848                 u32 reg;
849                 reg = readl(pmc + PMC_CTRL);
850                 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
851                 pmc_32kwritel(reg, PMC_CTRL);
852                 reg &= ~TEGRA_POWER_PWRREQ_OE;
853                 pmc_32kwritel(reg, PMC_CTRL);
854         }
855
856         cpu_cluster_pm_exit();
857         cpu_pm_exit();
858
859         if (pdata && pdata->board_resume)
860                 pdata->board_resume(mode, TEGRA_RESUME_AFTER_CPU);
861
862         trace_cpu_suspend(CPU_SUSPEND_DONE);
863
864         local_fiq_enable();
865
866         tegra_common_resume();
867
868 fail:
869         return err;
870 }
871
872 /*
873  * Function pointers to optional board specific function
874  */
875 void (*tegra_deep_sleep)(int);
876 EXPORT_SYMBOL(tegra_deep_sleep);
877
878 static int tegra_suspend_prepare(void)
879 {
880         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
881                 tegra_deep_sleep(1);
882         return 0;
883 }
884
885 static void tegra_suspend_finish(void)
886 {
887         if (pdata && pdata->cpu_resume_boost) {
888                 int ret = tegra_suspended_target(pdata->cpu_resume_boost);
889                 pr_info("Tegra: resume CPU boost to %u KHz: %s (%d)\n",
890                         pdata->cpu_resume_boost, ret ? "Failed" : "OK", ret);
891         }
892
893         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
894                 tegra_deep_sleep(0);
895 }
896
897 static const struct platform_suspend_ops tegra_suspend_ops = {
898         .valid          = suspend_valid_only_mem,
899         .prepare        = tegra_suspend_prepare,
900         .finish         = tegra_suspend_finish,
901         .prepare_late   = tegra_suspend_prepare_late,
902         .wake           = tegra_suspend_wake,
903         .enter          = tegra_suspend_enter,
904 };
905
906 static ssize_t suspend_mode_show(struct kobject *kobj,
907                                         struct kobj_attribute *attr, char *buf)
908 {
909         char *start = buf;
910         char *end = buf + PAGE_SIZE;
911
912         start += scnprintf(start, end - start, "%s ", \
913                                 tegra_suspend_name[current_suspend_mode]);
914         start += scnprintf(start, end - start, "\n");
915
916         return start - buf;
917 }
918
919 static ssize_t suspend_mode_store(struct kobject *kobj,
920                                         struct kobj_attribute *attr,
921                                         const char *buf, size_t n)
922 {
923         int len;
924         const char *name_ptr;
925         enum tegra_suspend_mode new_mode;
926
927         name_ptr = buf;
928         while (*name_ptr && !isspace(*name_ptr))
929                 name_ptr++;
930         len = name_ptr - buf;
931         if (!len)
932                 goto bad_name;
933         /* TEGRA_SUSPEND_NONE not allowed as suspend state */
934         if (!(strncmp(buf, tegra_suspend_name[TEGRA_SUSPEND_NONE], len))
935                 || !(strncmp(buf, tegra_suspend_name[TEGRA_SUSPEND_LP2], len))) {
936                 pr_info("Illegal tegra suspend state: %s\n", buf);
937                 goto bad_name;
938         }
939
940         for (new_mode = TEGRA_SUSPEND_NONE; \
941                         new_mode < TEGRA_MAX_SUSPEND_MODE; ++new_mode) {
942                 if (!strncmp(buf, tegra_suspend_name[new_mode], len)) {
943                         current_suspend_mode = new_mode;
944                         break;
945                 }
946         }
947
948 bad_name:
949         return n;
950 }
951
952 static struct kobj_attribute suspend_mode_attribute =
953         __ATTR(mode, 0644, suspend_mode_show, suspend_mode_store);
954
955 static struct kobject *suspend_kobj;
956
957 static int tegra_pm_enter_suspend(void)
958 {
959         pr_info("Entering suspend state %s\n", lp_state[current_suspend_mode]);
960         if (current_suspend_mode == TEGRA_SUSPEND_LP0)
961                 tegra_lp0_cpu_mode(true);
962         return 0;
963 }
964
965 static void tegra_pm_enter_resume(void)
966 {
967         if (current_suspend_mode == TEGRA_SUSPEND_LP0)
968                 tegra_lp0_cpu_mode(false);
969         pr_info("Exited suspend state %s\n", lp_state[current_suspend_mode]);
970 }
971
972 static struct syscore_ops tegra_pm_enter_syscore_ops = {
973         .suspend = tegra_pm_enter_suspend,
974         .resume = tegra_pm_enter_resume,
975 };
976
977 static __init int tegra_pm_enter_syscore_init(void)
978 {
979         register_syscore_ops(&tegra_pm_enter_syscore_ops);
980         return 0;
981 }
982 subsys_initcall(tegra_pm_enter_syscore_init);
983 #endif
984
985 void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
986 {
987         u32 reg;
988         u32 mode;
989
990         tegra_cpu_rail = tegra_dvfs_get_rail_by_name("vdd_cpu");
991         tegra_core_rail = tegra_dvfs_get_rail_by_name("vdd_core");
992         tegra_pclk = clk_get_sys(NULL, "pclk");
993         BUG_ON(IS_ERR(tegra_pclk));
994         pdata = plat;
995         (void)reg;
996         (void)mode;
997
998         if (plat->suspend_mode == TEGRA_SUSPEND_LP2)
999                 plat->suspend_mode = TEGRA_SUSPEND_LP0;
1000
1001 #ifndef CONFIG_PM_SLEEP
1002         if (plat->suspend_mode != TEGRA_SUSPEND_NONE) {
1003                 pr_warning("%s: Suspend requires CONFIG_PM_SLEEP -- "
1004                            "disabling suspend\n", __func__);
1005                 plat->suspend_mode = TEGRA_SUSPEND_NONE;
1006         }
1007 #else
1008         if (create_suspend_pgtable() < 0) {
1009                 pr_err("%s: PGD memory alloc failed -- LP0/LP1/LP2 unavailable\n",
1010                                 __func__);
1011                 plat->suspend_mode = TEGRA_SUSPEND_NONE;
1012                 goto fail;
1013         }
1014
1015         if ((tegra_chip_id == TEGRA30) &&
1016             (tegra_revision == TEGRA_REVISION_A01) &&
1017             (plat->suspend_mode == TEGRA_SUSPEND_LP0)) {
1018                 /* Tegra 3 A01 supports only LP1 */
1019                 pr_warning("%s: Suspend mode LP0 is not supported on A01 "
1020                            "-- disabling LP0\n", __func__);
1021                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
1022         }
1023         if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && tegra_lp0_vec_size &&
1024                 tegra_lp0_vec_relocate) {
1025                 unsigned char *reloc_lp0;
1026                 unsigned long tmp;
1027                 void __iomem *orig;
1028                 reloc_lp0 = kmalloc(tegra_lp0_vec_size + L1_CACHE_BYTES - 1,
1029                                         GFP_KERNEL);
1030                 WARN_ON(!reloc_lp0);
1031                 if (!reloc_lp0) {
1032                         pr_err("%s: Failed to allocate reloc_lp0\n",
1033                                 __func__);
1034                         goto out;
1035                 }
1036
1037                 orig = ioremap(tegra_lp0_vec_start, tegra_lp0_vec_size);
1038                 WARN_ON(!orig);
1039                 if (!orig) {
1040                         pr_err("%s: Failed to map tegra_lp0_vec_start %08lx\n",
1041                                 __func__, tegra_lp0_vec_start);
1042                         kfree(reloc_lp0);
1043                         goto out;
1044                 }
1045
1046                 tmp = (unsigned long) reloc_lp0;
1047                 tmp = (tmp + L1_CACHE_BYTES - 1) & ~(L1_CACHE_BYTES - 1);
1048                 reloc_lp0 = (unsigned char *)tmp;
1049                 memcpy(reloc_lp0, orig, tegra_lp0_vec_size);
1050                 iounmap(orig);
1051                 tegra_lp0_vec_start = virt_to_phys(reloc_lp0);
1052         }
1053
1054 out:
1055         if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && !tegra_lp0_vec_size) {
1056                 pr_warning("%s: Suspend mode LP0 requested, no lp0_vec "
1057                            "provided by bootlader -- disabling LP0\n",
1058                            __func__);
1059                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
1060         }
1061
1062         iram_save_size = tegra_iram_end() - tegra_iram_start();
1063
1064         iram_save = kmalloc(iram_save_size, GFP_KERNEL);
1065         if (!iram_save && (plat->suspend_mode >= TEGRA_SUSPEND_LP1)) {
1066                 pr_err("%s: unable to allocate memory for SDRAM self-refresh "
1067                        "-- LP0/LP1 unavailable\n", __func__);
1068                 plat->suspend_mode = TEGRA_SUSPEND_LP2;
1069         }
1070
1071         /* !!!FIXME!!! THIS IS TEGRA2 ONLY */
1072         /* Initialize scratch registers used for CPU LP2 synchronization */
1073         writel(0, pmc + PMC_SCRATCH37);
1074         writel(0, pmc + PMC_SCRATCH38);
1075         writel(0, pmc + PMC_SCRATCH39);
1076         writel(0, pmc + PMC_SCRATCH41);
1077
1078         /* Always enable CPU power request; just normal polarity is supported */
1079         reg = readl(pmc + PMC_CTRL);
1080         BUG_ON(reg & TEGRA_POWER_CPU_PWRREQ_POLARITY);
1081         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
1082         pmc_32kwritel(reg, PMC_CTRL);
1083
1084         /* Configure core power request and system clock control if LP0
1085            is supported */
1086         __raw_writel(pdata->core_timer, pmc + PMC_COREPWRGOOD_TIMER);
1087         __raw_writel(pdata->core_off_timer, pmc + PMC_COREPWROFF_TIMER);
1088
1089         reg = readl(pmc + PMC_CTRL);
1090
1091         if (!pdata->sysclkreq_high)
1092                 reg |= TEGRA_POWER_SYSCLK_POLARITY;
1093         else
1094                 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
1095
1096         if (!pdata->corereq_high)
1097                 reg |= TEGRA_POWER_PWRREQ_POLARITY;
1098         else
1099                 reg &= ~TEGRA_POWER_PWRREQ_POLARITY;
1100
1101         /* configure output inverters while the request is tristated */
1102         pmc_32kwritel(reg, PMC_CTRL);
1103
1104         /* now enable requests */
1105         reg |= TEGRA_POWER_SYSCLK_OE;
1106         if (!pdata->combined_req)
1107                 reg |= TEGRA_POWER_PWRREQ_OE;
1108         pmc_32kwritel(reg, PMC_CTRL);
1109
1110         if (pdata->suspend_mode == TEGRA_SUSPEND_LP0)
1111                 tegra_lp0_suspend_init();
1112
1113         suspend_set_ops(&tegra_suspend_ops);
1114
1115         /* Create /sys/power/suspend/type */
1116         suspend_kobj = kobject_create_and_add("suspend", power_kobj);
1117         if (suspend_kobj) {
1118                 if (sysfs_create_file(suspend_kobj, \
1119                                                 &suspend_mode_attribute.attr))
1120                         pr_err("%s: sysfs_create_file suspend type failed!\n",
1121                                                                 __func__);
1122         }
1123
1124         iram_cpu_lp2_mask = tegra_cpu_lp2_mask;
1125         iram_cpu_lp1_mask = tegra_cpu_lp1_mask;
1126 fail:
1127 #endif
1128         if (plat->suspend_mode == TEGRA_SUSPEND_NONE)
1129                 tegra_lp2_in_idle(false);
1130
1131         current_suspend_mode = plat->suspend_mode;
1132 }
1133
1134 unsigned long debug_uart_port_base = 0;
1135 EXPORT_SYMBOL(debug_uart_port_base);
1136
1137 static int tegra_debug_uart_suspend(void)
1138 {
1139         void __iomem *uart;
1140         u32 lcr;
1141
1142         if (!debug_uart_port_base)
1143                 return 0;
1144
1145         uart = IO_ADDRESS(debug_uart_port_base);
1146
1147         lcr = readb(uart + UART_LCR * 4);
1148
1149         tegra_sctx.uart[0] = lcr;
1150         tegra_sctx.uart[1] = readb(uart + UART_MCR * 4);
1151
1152         /* DLAB = 0 */
1153         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
1154
1155         tegra_sctx.uart[2] = readb(uart + UART_IER * 4);
1156
1157         /* DLAB = 1 */
1158         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
1159
1160         tegra_sctx.uart[3] = readb(uart + UART_DLL * 4);
1161         tegra_sctx.uart[4] = readb(uart + UART_DLM * 4);
1162
1163         writeb(lcr, uart + UART_LCR * 4);
1164
1165         return 0;
1166 }
1167
1168 static void tegra_debug_uart_resume(void)
1169 {
1170         void __iomem *uart;
1171         u32 lcr;
1172
1173         if (!debug_uart_port_base)
1174                 return;
1175
1176         uart = IO_ADDRESS(debug_uart_port_base);
1177
1178         lcr = tegra_sctx.uart[0];
1179
1180         writeb(tegra_sctx.uart[1], uart + UART_MCR * 4);
1181
1182         /* DLAB = 0 */
1183         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
1184
1185         writeb(UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_01 | UART_FCR_R_TRIG_01,
1186                         uart + UART_FCR * 4);
1187
1188         writeb(tegra_sctx.uart[2], uart + UART_IER * 4);
1189
1190         /* DLAB = 1 */
1191         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
1192
1193         writeb(tegra_sctx.uart[3], uart + UART_DLL * 4);
1194         writeb(tegra_sctx.uart[4], uart + UART_DLM * 4);
1195
1196         writeb(lcr, uart + UART_LCR * 4);
1197 }
1198
1199 static struct syscore_ops tegra_debug_uart_syscore_ops = {
1200         .suspend = tegra_debug_uart_suspend,
1201         .resume = tegra_debug_uart_resume,
1202 };
1203
1204 struct clk *debug_uart_clk = NULL;
1205 EXPORT_SYMBOL(debug_uart_clk);
1206
1207 void tegra_console_uart_suspend(void)
1208 {
1209         if (console_suspend_enabled && debug_uart_clk)
1210                 clk_disable(debug_uart_clk);
1211 }
1212
1213 void tegra_console_uart_resume(void)
1214 {
1215         if (console_suspend_enabled && debug_uart_clk)
1216                 clk_enable(debug_uart_clk);
1217 }
1218
1219 static int tegra_debug_uart_syscore_init(void)
1220 {
1221         register_syscore_ops(&tegra_debug_uart_syscore_ops);
1222         return 0;
1223 }
1224 arch_initcall(tegra_debug_uart_syscore_init);