arm: tegra: add Trusted Foundations hooks and driver
[linux-3.10.git] / arch / arm / mach-tegra / pm.c
1 /*
2  * arch/arm/mach-tegra/pm.c
3  *
4  * CPU complex suspend & resume functions for Tegra SoCs
5  *
6  * Copyright (c) 2009-2011, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/ctype.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/sched.h>
28 #include <linux/smp.h>
29 #include <linux/irq.h>
30 #include <linux/interrupt.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/debugfs.h>
34 #include <linux/delay.h>
35 #include <linux/suspend.h>
36 #include <linux/slab.h>
37 #include <linux/serial_reg.h>
38 #include <linux/seq_file.h>
39 #include <linux/uaccess.h>
40 #include <linux/syscore_ops.h>
41 #include <linux/cpu_pm.h>
42 #include <linux/clk/tegra.h>
43 #include <linux/export.h>
44 #include <linux/vmalloc.h>
45 #include <linux/memblock.h>
46 #include <linux/console.h>
47 #include <linux/tegra_audio.h>
48
49 #include <trace/events/power.h>
50
51 #include <asm/cacheflush.h>
52 #include <asm/hardware/cache-l2x0.h>
53 #include <asm/idmap.h>
54 #include <asm/localtimer.h>
55 #include <asm/pgalloc.h>
56 #include <asm/pgtable.h>
57 #include <asm/tlbflush.h>
58 #include <asm/suspend.h>
59
60 #include <mach/irqs.h>
61 #include <mach/powergate.h>
62
63 #include "board.h"
64 #include "clock.h"
65 #include "cpuidle.h"
66 #include "flowctrl.h"
67 #include "fuse.h"
68 #include "gic.h"
69 #include "iomap.h"
70 #include "pm.h"
71 #include "pm-irq.h"
72 #include "reset.h"
73 #include "sleep.h"
74 #include "timer.h"
75 #include "dvfs.h"
76 #include "cpu-tegra.h"
77
78 struct suspend_context {
79         /*
80          * The next 7 values are referenced by offset in __restart_plls
81          * in headsmp-t2.S, and should not be moved
82          */
83         u32 pllx_misc;
84         u32 pllx_base;
85         u32 pllp_misc;
86         u32 pllp_base;
87         u32 pllp_outa;
88         u32 pllp_outb;
89         u32 pll_timeout;
90
91         u32 cpu_burst;
92         u32 clk_csite_src;
93         u32 cclk_divider;
94
95         u32 mc[3];
96         u8 uart[5];
97
98         struct tegra_twd_context twd;
99 };
100
101 #ifdef CONFIG_PM_SLEEP
102 phys_addr_t tegra_pgd_phys;     /* pgd used by hotplug & LP2 bootup */
103 static pgd_t *tegra_pgd;
104 static DEFINE_SPINLOCK(tegra_lp2_lock);
105 static cpumask_t tegra_in_lp2;
106 static cpumask_t *iram_cpu_lp2_mask;
107 static unsigned long *iram_cpu_lp1_mask;
108 static u8 *iram_save;
109 static unsigned long iram_save_size;
110 static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA);
111 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
112 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
113 static int tegra_last_pclk;
114 #endif
115
116 struct suspend_context tegra_sctx;
117
118 #define TEGRA_POWER_PWRREQ_POLARITY     (1 << 8)   /* core power request polarity */
119 #define TEGRA_POWER_PWRREQ_OE           (1 << 9)   /* core power request enable */
120 #define TEGRA_POWER_SYSCLK_POLARITY     (1 << 10)  /* sys clk polarity */
121 #define TEGRA_POWER_SYSCLK_OE           (1 << 11)  /* system clock enable */
122 #define TEGRA_POWER_PWRGATE_DIS         (1 << 12)  /* power gate disabled */
123 #define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* enter LP0 when CPU pwr gated */
124 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU power request polarity */
125 #define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU power request enable */
126
127 #define PMC_CTRL                0x0
128 #define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
129 #define PMC_WAKE_MASK           0xc
130 #define PMC_WAKE_LEVEL          0x10
131 #define PMC_DPAD_ORIDE          0x1C
132 #define PMC_WAKE_DELAY          0xe0
133 #define PMC_DPD_SAMPLE          0x20
134
135 #define PMC_WAKE_STATUS         0x14
136 #define PMC_SW_WAKE_STATUS      0x18
137 #define PMC_COREPWRGOOD_TIMER   0x3c
138 #define PMC_CPUPWRGOOD_TIMER    0xc8
139 #define PMC_CPUPWROFF_TIMER     0xcc
140 #define PMC_COREPWROFF_TIMER    PMC_WAKE_DELAY
141
142 #define PMC_PWRGATE_TOGGLE      0x30
143 #define PWRGATE_TOGGLE_START    (1 << 8)
144 #define UN_PWRGATE_CPU          \
145         (PWRGATE_TOGGLE_START | TEGRA_CPU_POWERGATE_ID(TEGRA_POWERGATE_CPU))
146
147 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
148 #define PMC_SCRATCH4_WAKE_CLUSTER_MASK  (1<<31)
149 #endif
150
151 #define CLK_RESET_CCLK_BURST    0x20
152 #define CLK_RESET_CCLK_DIVIDER  0x24
153 #define CLK_RESET_PLLC_BASE     0x80
154 #define CLK_RESET_PLLM_BASE     0x90
155 #define CLK_RESET_PLLX_BASE     0xe0
156 #define CLK_RESET_PLLX_MISC     0xe4
157 #define CLK_RESET_PLLP_BASE     0xa0
158 #define CLK_RESET_PLLP_OUTA     0xa4
159 #define CLK_RESET_PLLP_OUTB     0xa8
160 #define CLK_RESET_PLLP_MISC     0xac
161
162 #define CLK_RESET_SOURCE_CSITE  0x1d4
163
164 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
165 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT    4
166 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT   0
167 #define CLK_RESET_CCLK_IDLE_POLICY         1
168 #define CLK_RESET_CCLK_RUN_POLICY          2
169 #define CLK_RESET_CCLK_BURST_POLICY_PLLM   3
170 #define CLK_RESET_CCLK_BURST_POLICY_PLLX   8
171
172 #define EMC_MRW_0               0x0e8
173 #define EMC_MRW_DEV_SELECTN     30
174 #define EMC_MRW_DEV_NONE        (3 << EMC_MRW_DEV_SELECTN)
175
176 #define MC_SECURITY_START       0x6c
177 #define MC_SECURITY_SIZE        0x70
178 #define MC_SECURITY_CFG2        0x7c
179
180 struct dvfs_rail *tegra_cpu_rail;
181 static struct dvfs_rail *tegra_core_rail;
182 static struct clk *tegra_pclk;
183 static const struct tegra_suspend_platform_data *pdata;
184 static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
185
186 #if defined(CONFIG_TEGRA_CLUSTER_CONTROL) && INSTRUMENT_CLUSTER_SWITCH
187 enum tegra_cluster_switch_time_id {
188         tegra_cluster_switch_time_id_start = 0,
189         tegra_cluster_switch_time_id_prolog,
190         tegra_cluster_switch_time_id_switch,
191         tegra_cluster_switch_time_id_epilog,
192         tegra_cluster_switch_time_id_max
193 };
194
195 static unsigned long
196                 tegra_cluster_switch_times[tegra_cluster_switch_time_id_max];
197 #define tegra_cluster_switch_time(flags, id) \
198         do { \
199                 barrier(); \
200                 if (flags & TEGRA_POWER_CLUSTER_MASK) { \
201                         void __iomem *timer_us = \
202                                                 IO_ADDRESS(TEGRA_TMRUS_BASE); \
203                         if (id < tegra_cluster_switch_time_id_max) \
204                                 tegra_cluster_switch_times[id] = \
205                                                         readl(timer_us); \
206                                 wmb(); \
207                 } \
208                 barrier(); \
209         } while(0)
210 #else
211 #define tegra_cluster_switch_time(flags, id) do {} while(0)
212 #endif
213
214 #ifdef CONFIG_PM_SLEEP
215 static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
216         [TEGRA_SUSPEND_NONE]    = "none",
217         [TEGRA_SUSPEND_LP2]     = "lp2",
218         [TEGRA_SUSPEND_LP1]     = "lp1",
219         [TEGRA_SUSPEND_LP0]     = "lp0",
220 };
221
222 unsigned long tegra_cpu_power_good_time(void)
223 {
224         if (WARN_ON_ONCE(!pdata))
225                 return 5000;
226
227         return pdata->cpu_timer;
228 }
229
230 unsigned long tegra_cpu_power_off_time(void)
231 {
232         if (WARN_ON_ONCE(!pdata))
233                 return 5000;
234
235         return pdata->cpu_off_timer;
236 }
237
238 unsigned long tegra_cpu_lp2_min_residency(void)
239 {
240         if (WARN_ON_ONCE(!pdata))
241                 return 2000;
242
243         return pdata->cpu_lp2_min_residency;
244 }
245
246 /*
247  * create_suspend_pgtable
248  *
249  * Creates a page table with identity mappings of physical memory and IRAM
250  * for use when the MMU is off, in addition to all the regular kernel mappings.
251  */
252 static __init int create_suspend_pgtable(void)
253 {
254         tegra_pgd = pgd_alloc(&init_mm);
255         if (!tegra_pgd)
256                 return -ENOMEM;
257
258         /* Only identity-map size of lowmem (high_memory - PAGE_OFFSET) */
259         identity_mapping_add(tegra_pgd, phys_to_virt(PHYS_OFFSET),
260                 high_memory, 0);
261         identity_mapping_add(tegra_pgd, IO_IRAM_VIRT,
262                 IO_IRAM_VIRT + SECTION_SIZE, 0);
263
264         /* inner/outer write-back/write-allocate, sharable */
265         tegra_pgd_phys = (virt_to_phys(tegra_pgd) & PAGE_MASK) | 0x4A;
266
267         return 0;
268 }
269
270 /* ensures that sufficient time is passed for a register write to
271  * serialize into the 32KHz domain */
272 static void pmc_32kwritel(u32 val, unsigned long offs)
273 {
274         writel(val, pmc + offs);
275         udelay(130);
276 }
277
278 static void set_power_timers(unsigned long us_on, unsigned long us_off,
279                              long rate)
280 {
281         static unsigned long last_us_off = 0;
282         unsigned long long ticks;
283         unsigned long long pclk;
284
285         if (WARN_ON_ONCE(rate <= 0))
286                 pclk = 100000000;
287         else
288                 pclk = rate;
289
290         if ((rate != tegra_last_pclk) || (us_off != last_us_off)) {
291                 ticks = (us_on * pclk) + 999999ull;
292                 do_div(ticks, 1000000);
293                 writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
294
295                 ticks = (us_off * pclk) + 999999ull;
296                 do_div(ticks, 1000000);
297                 writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
298                 wmb();
299         }
300         tegra_last_pclk = pclk;
301         last_us_off = us_off;
302 }
303
304 /*
305  * restore_cpu_complex
306  *
307  * restores cpu clock setting, clears flow controller
308  *
309  * Always called on CPU 0.
310  */
311 static void restore_cpu_complex(u32 mode)
312 {
313         int cpu = smp_processor_id();
314         unsigned int reg, policy;
315
316         BUG_ON(cpu != 0);
317
318         /* Is CPU complex already running on PLLX? */
319         reg = readl(clk_rst + CLK_RESET_CCLK_BURST);
320         policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
321
322         if (policy == CLK_RESET_CCLK_IDLE_POLICY)
323                 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
324         else if (policy == CLK_RESET_CCLK_RUN_POLICY)
325                 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
326         else
327                 BUG();
328
329         if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
330                 /* restore PLLX settings if CPU is on different PLL */
331                 writel(tegra_sctx.pllx_misc, clk_rst + CLK_RESET_PLLX_MISC);
332                 writel(tegra_sctx.pllx_base, clk_rst + CLK_RESET_PLLX_BASE);
333
334                 /* wait for PLL stabilization if PLLX was enabled */
335                 if (tegra_sctx.pllx_base & (1<<30)) {
336 #if USE_PLL_LOCK_BITS
337                         /* Enable lock detector */
338                         reg = readl(clk_rst + CLK_RESET_PLLX_MISC);
339                         reg |= 1<<18;
340                         writel(reg, clk_rst + CLK_RESET_PLLX_MISC);
341                         while (!(readl(clk_rst + CLK_RESET_PLLX_BASE) &
342                                  (1<<27)))
343                                 cpu_relax();
344
345                         udelay(PLL_POST_LOCK_DELAY);
346 #else
347                         udelay(300);
348 #endif
349                 }
350         }
351
352         /* Restore original burst policy setting for calls resulting from CPU
353            LP2 in idle or system suspend; keep cluster switch prolog setting
354            intact. */
355         if (!(mode & TEGRA_POWER_CLUSTER_MASK)) {
356                 writel(tegra_sctx.cclk_divider, clk_rst +
357                        CLK_RESET_CCLK_DIVIDER);
358                 writel(tegra_sctx.cpu_burst, clk_rst +
359                        CLK_RESET_CCLK_BURST);
360         }
361
362         writel(tegra_sctx.clk_csite_src, clk_rst + CLK_RESET_SOURCE_CSITE);
363
364         /* Do not power-gate CPU 0 when flow controlled */
365         reg = flowctrl_read_cpu_csr(cpu);
366         reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
367         reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
368         reg &= ~FLOW_CTRL_CSR_ENABLE;           /* clear enable */
369         reg |= FLOW_CTRL_CSR_INTR_FLAG;         /* clear intr */
370         reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event */
371         flowctrl_write_cpu_csr(cpu, reg);
372
373         /* If an immedidate cluster switch is being perfomed, restore the
374            local timer registers. For calls resulting from CPU LP2 in
375            idle or system suspend, the local timer was shut down and
376            timekeeping switched over to the global system timer. In this
377            case keep local timer disabled, and restore only periodic load. */
378         if (!(mode & (TEGRA_POWER_CLUSTER_MASK |
379                       TEGRA_POWER_CLUSTER_IMMEDIATE)))
380                 tegra_sctx.twd.twd_ctrl = 0;
381         tegra_twd_resume(&tegra_sctx.twd);
382 }
383
384 /*
385  * suspend_cpu_complex
386  *
387  * saves pll state for use by restart_plls, prepares flow controller for
388  * transition to suspend state
389  *
390  * Must always be called on cpu 0.
391  */
392 static void suspend_cpu_complex(u32 mode)
393 {
394         int cpu = smp_processor_id();
395         unsigned int reg;
396         int i;
397
398         BUG_ON(cpu != 0);
399
400         /* switch coresite to clk_m, save off original source */
401         tegra_sctx.clk_csite_src = readl(clk_rst + CLK_RESET_SOURCE_CSITE);
402         writel(3<<30, clk_rst + CLK_RESET_SOURCE_CSITE);
403
404         tegra_sctx.cpu_burst = readl(clk_rst + CLK_RESET_CCLK_BURST);
405         tegra_sctx.pllx_base = readl(clk_rst + CLK_RESET_PLLX_BASE);
406         tegra_sctx.pllx_misc = readl(clk_rst + CLK_RESET_PLLX_MISC);
407         tegra_sctx.pllp_base = readl(clk_rst + CLK_RESET_PLLP_BASE);
408         tegra_sctx.pllp_outa = readl(clk_rst + CLK_RESET_PLLP_OUTA);
409         tegra_sctx.pllp_outb = readl(clk_rst + CLK_RESET_PLLP_OUTB);
410         tegra_sctx.pllp_misc = readl(clk_rst + CLK_RESET_PLLP_MISC);
411         tegra_sctx.cclk_divider = readl(clk_rst + CLK_RESET_CCLK_DIVIDER);
412
413         tegra_twd_suspend(&tegra_sctx.twd);
414
415         reg = flowctrl_read_cpu_csr(cpu);
416         reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
417         reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
418         reg |= FLOW_CTRL_CSR_INTR_FLAG;         /* clear intr flag */
419         reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event flag */
420 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
421         reg |= FLOW_CTRL_CSR_WFE_CPU0 << cpu;   /* enable power gating on wfe */
422 #else
423         reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu;   /* enable power gating on wfi */
424 #endif
425         reg |= FLOW_CTRL_CSR_ENABLE;            /* enable power gating */
426         flowctrl_write_cpu_csr(cpu, reg);
427
428         for (i = 0; i < num_possible_cpus(); i++) {
429                 if (i == cpu)
430                         continue;
431                 reg = flowctrl_read_cpu_csr(i);
432                 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
433                 reg |= FLOW_CTRL_CSR_INTR_FLAG;
434                 flowctrl_write_cpu_csr(i, reg);
435         }
436
437         tegra_gic_cpu_disable();
438 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
439         /* Tegra3 enters LPx states via WFI - do not propagate legacy IRQs
440            to CPU core to avoid fall through WFI (IRQ-to-flow controller wake
441            path is not affected). */
442         tegra_gic_pass_through_disable();
443 #endif
444 }
445
446 void tegra_clear_cpu_in_lp2(int cpu)
447 {
448         spin_lock(&tegra_lp2_lock);
449         BUG_ON(!cpumask_test_cpu(cpu, &tegra_in_lp2));
450         cpumask_clear_cpu(cpu, &tegra_in_lp2);
451
452         /* Update the IRAM copy used by the reset handler. The IRAM copy
453            can't use used directly by cpumask_clear_cpu() because it uses
454            LDREX/STREX which requires the addressed location to be inner
455            cacheable and sharable which IRAM isn't. */
456         writel(tegra_in_lp2.bits[0], iram_cpu_lp2_mask);
457         dsb();
458
459         spin_unlock(&tegra_lp2_lock);
460 }
461
462 bool tegra_set_cpu_in_lp2(int cpu)
463 {
464         bool last_cpu = false;
465
466         spin_lock(&tegra_lp2_lock);
467         BUG_ON(cpumask_test_cpu(cpu, &tegra_in_lp2));
468         cpumask_set_cpu(cpu, &tegra_in_lp2);
469
470         /* Update the IRAM copy used by the reset handler. The IRAM copy
471            can't use used directly by cpumask_set_cpu() because it uses
472            LDREX/STREX which requires the addressed location to be inner
473            cacheable and sharable which IRAM isn't. */
474         writel(tegra_in_lp2.bits[0], iram_cpu_lp2_mask);
475         dsb();
476
477         if ((cpu == 0) && cpumask_equal(&tegra_in_lp2, cpu_online_mask))
478                 last_cpu = true;
479 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
480         else if (cpu == 1)
481                 tegra2_cpu_set_resettable_soon();
482 #endif
483
484         spin_unlock(&tegra_lp2_lock);
485         return last_cpu;
486 }
487
488 static void tegra_sleep_core(enum tegra_suspend_mode mode,
489                              unsigned long v2p)
490 {
491 #ifdef CONFIG_TRUSTED_FOUNDATIONS
492         if (mode == TEGRA_SUSPEND_LP0) {
493                 tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE3,
494                                   virt_to_phys(tegra_resume));
495         } else {
496                 tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE6,
497                                   (TEGRA_RESET_HANDLER_BASE +
498                                    tegra_cpu_reset_handler_offset));
499         }
500 #endif
501 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
502         cpu_suspend(v2p, tegra2_sleep_core_finish);
503 #else
504         cpu_suspend(v2p, tegra3_sleep_core_finish);
505 #endif
506 }
507
508 static inline void tegra_sleep_cpu(unsigned long v2p)
509 {
510 #ifdef CONFIG_TRUSTED_FOUNDATIONS
511         tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4,
512                           (TEGRA_RESET_HANDLER_BASE +
513                            tegra_cpu_reset_handler_offset));
514 #endif
515         cpu_suspend(v2p, tegra_sleep_cpu_finish);
516 }
517
518 unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
519 {
520         u32 mode;       /* hardware + software power mode flags */
521         unsigned int remain;
522         pgd_t *pgd;
523
524         /* Only the last cpu down does the final suspend steps */
525         mode = readl(pmc + PMC_CTRL);
526         mode |= TEGRA_POWER_CPU_PWRREQ_OE;
527         if (pdata->combined_req)
528                 mode &= ~TEGRA_POWER_PWRREQ_OE;
529         else
530                 mode |= TEGRA_POWER_PWRREQ_OE;
531         mode &= ~TEGRA_POWER_EFFECT_LP0;
532         writel(mode, pmc + PMC_CTRL);
533         mode |= flags;
534
535         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_start);
536
537         /*
538          * We can use clk_get_rate_all_locked() here, because all other cpus
539          * are in LP2 state and irqs are disabled
540          */
541         if (flags & TEGRA_POWER_CLUSTER_MASK) {
542                 trace_cpu_cluster(POWER_CPU_CLUSTER_START);
543                 set_power_timers(pdata->cpu_timer, 0,
544                         clk_get_rate_all_locked(tegra_pclk));
545                 if (flags & TEGRA_POWER_CLUSTER_G) {
546                         /*
547                          * To reduce the vdd_cpu up latency when LP->G
548                          * transition. Before the transition, enable
549                          * the vdd_cpu rail.
550                          */
551                         if (is_lp_cluster())
552                                 writel(UN_PWRGATE_CPU,
553                                        pmc + PMC_PWRGATE_TOGGLE);
554                 }
555                 tegra_cluster_switch_prolog(mode);
556         } else {
557                 set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer,
558                         clk_get_rate_all_locked(tegra_pclk));
559         }
560
561         if (sleep_time)
562                 tegra_lp2_set_trigger(sleep_time);
563
564         cpu_cluster_pm_enter();
565         suspend_cpu_complex(mode);
566         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_prolog);
567         flush_cache_all();
568         /*
569          * No need to flush complete L2. Cleaning kernel and IO mappings
570          * is enough for the LP code sequence that has L2 disabled but
571          * MMU on.
572          */
573         pgd = cpu_get_pgd();
574         outer_clean_range(__pa(pgd + USER_PTRS_PER_PGD),
575                           __pa(pgd + PTRS_PER_PGD));
576         outer_disable();
577
578         tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
579
580 #ifdef CONFIG_CACHE_L2X0
581         tegra_init_cache(false);
582 #endif
583         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_switch);
584         restore_cpu_complex(mode);
585         cpu_cluster_pm_exit();
586
587         remain = tegra_lp2_timer_remain();
588         if (sleep_time)
589                 tegra_lp2_set_trigger(0);
590
591         if (flags & TEGRA_POWER_CLUSTER_MASK) {
592                 tegra_cluster_switch_epilog(mode);
593                 trace_cpu_cluster(POWER_CPU_CLUSTER_DONE);
594         }
595         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_epilog);
596
597 #if INSTRUMENT_CLUSTER_SWITCH
598         if (flags & TEGRA_POWER_CLUSTER_MASK) {
599                 pr_err("%s: prolog %lu us, switch %lu us, epilog %lu us, total %lu us\n",
600                         is_lp_cluster() ? "G=>LP" : "LP=>G",
601                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog] -
602                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start],
603                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch] -
604                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog],
605                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
606                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch],
607                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
608                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start]);
609         }
610 #endif
611         return remain;
612 }
613
614 static int tegra_common_suspend(void)
615 {
616         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
617
618         tegra_sctx.mc[0] = readl(mc + MC_SECURITY_START);
619         tegra_sctx.mc[1] = readl(mc + MC_SECURITY_SIZE);
620         tegra_sctx.mc[2] = readl(mc + MC_SECURITY_CFG2);
621
622         /* copy the reset vector and SDRAM shutdown code into IRAM */
623         memcpy(iram_save, iram_code, iram_save_size);
624         memcpy(iram_code, tegra_iram_start(), iram_save_size);
625
626         return 0;
627 }
628
629 static void tegra_common_resume(void)
630 {
631         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
632 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
633         void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
634 #endif
635
636         /* Clear DPD sample */
637         writel(0x0, pmc + PMC_DPD_SAMPLE);
638
639         writel(tegra_sctx.mc[0], mc + MC_SECURITY_START);
640         writel(tegra_sctx.mc[1], mc + MC_SECURITY_SIZE);
641         writel(tegra_sctx.mc[2], mc + MC_SECURITY_CFG2);
642 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
643         /* trigger emc mode write */
644         writel(EMC_MRW_DEV_NONE, emc + EMC_MRW_0);
645 #endif
646         /* clear scratch registers shared by suspend and the reset pen */
647         writel(0x0, pmc + PMC_SCRATCH39);
648         writel(0x0, pmc + PMC_SCRATCH41);
649
650         /* restore IRAM */
651         memcpy(iram_code, iram_save, iram_save_size);
652 }
653
654 static int tegra_suspend_prepare_late(void)
655 {
656 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
657         disable_irq(INT_SYS_STATS_MON);
658 #endif
659         return 0;
660 }
661
662 static void tegra_suspend_wake(void)
663 {
664 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
665         enable_irq(INT_SYS_STATS_MON);
666 #endif
667 }
668
669 static void tegra_pm_set(enum tegra_suspend_mode mode)
670 {
671         u32 reg, boot_flag;
672         unsigned long rate = 32768;
673
674         reg = readl(pmc + PMC_CTRL);
675         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
676         if (pdata->combined_req)
677                 reg &= ~TEGRA_POWER_PWRREQ_OE;
678         else
679                 reg |= TEGRA_POWER_PWRREQ_OE;
680         reg &= ~TEGRA_POWER_EFFECT_LP0;
681
682         switch (mode) {
683         case TEGRA_SUSPEND_LP0:
684 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
685                 rate = clk_get_rate_all_locked(tegra_pclk);
686 #endif
687                 if (pdata->combined_req) {
688                         reg |= TEGRA_POWER_PWRREQ_OE;
689                         reg &= ~TEGRA_POWER_CPU_PWRREQ_OE;
690                 }
691
692                 /*
693                  * LP0 boots through the AVP, which then resumes the AVP to
694                  * the address in scratch 39, and the cpu to the address in
695                  * scratch 41 to tegra_resume
696                  */
697                 writel(0x0, pmc + PMC_SCRATCH39);
698
699                 /* Enable DPD sample to trigger sampling pads data and direction
700                  * in which pad will be driven during lp0 mode*/
701                 writel(0x1, pmc + PMC_DPD_SAMPLE);
702
703                 /* Set warmboot flag */
704                 boot_flag = readl(pmc + PMC_SCRATCH0);
705                 pmc_32kwritel(boot_flag | 1, PMC_SCRATCH0);
706
707                 pmc_32kwritel(tegra_lp0_vec_start, PMC_SCRATCH1);
708
709                 reg |= TEGRA_POWER_EFFECT_LP0;
710                 /* No break here. LP0 code falls through to write SCRATCH41 */
711         case TEGRA_SUSPEND_LP1:
712                 __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
713                 wmb();
714                 break;
715         case TEGRA_SUSPEND_LP2:
716                 rate = clk_get_rate(tegra_pclk);
717                 break;
718         case TEGRA_SUSPEND_NONE:
719                 return;
720         default:
721                 BUG();
722         }
723
724         set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer, rate);
725
726         pmc_32kwritel(reg, PMC_CTRL);
727 }
728
729 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
730         [TEGRA_SUSPEND_NONE] = "none",
731         [TEGRA_SUSPEND_LP2] = "LP2",
732         [TEGRA_SUSPEND_LP1] = "LP1",
733         [TEGRA_SUSPEND_LP0] = "LP0",
734 };
735
736 static int tegra_suspend_enter(suspend_state_t state)
737 {
738         int ret;
739         ktime_t delta;
740         struct timespec ts_entry, ts_exit;
741
742         if (pdata && pdata->board_suspend)
743                 pdata->board_suspend(current_suspend_mode, TEGRA_SUSPEND_BEFORE_PERIPHERAL);
744
745         read_persistent_clock(&ts_entry);
746
747         ret = tegra_suspend_dram(current_suspend_mode, 0);
748         if (ret) {
749                 pr_info("Aborting suspend, tegra_suspend_dram error=%d\n", ret);
750                 goto abort_suspend;
751         }
752
753         read_persistent_clock(&ts_exit);
754
755         if (timespec_compare(&ts_exit, &ts_entry) > 0) {
756                 delta = timespec_to_ktime(timespec_sub(ts_exit, ts_entry));
757
758                 tegra_dvfs_rail_pause(tegra_cpu_rail, delta, false);
759                 if (current_suspend_mode == TEGRA_SUSPEND_LP0)
760                         tegra_dvfs_rail_pause(tegra_core_rail, delta, false);
761                 else
762                         tegra_dvfs_rail_pause(tegra_core_rail, delta, true);
763         }
764
765 abort_suspend:
766         if (pdata && pdata->board_resume)
767                 pdata->board_resume(current_suspend_mode, TEGRA_RESUME_AFTER_PERIPHERAL);
768
769         return ret;
770 }
771
772 static void tegra_suspend_check_pwr_stats(void)
773 {
774         /* cpus and l2 are powered off later */
775         unsigned long pwrgate_partid_mask =
776 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
777                 (1 << TEGRA_POWERGATE_HEG)      |
778                 (1 << TEGRA_POWERGATE_SATA)     |
779                 (1 << TEGRA_POWERGATE_3D1)      |
780 #endif
781                 (1 << TEGRA_POWERGATE_3D)       |
782                 (1 << TEGRA_POWERGATE_VENC)     |
783                 (1 << TEGRA_POWERGATE_PCIE)     |
784                 (1 << TEGRA_POWERGATE_VDEC)     |
785                 (1 << TEGRA_POWERGATE_MPE);
786
787         int partid;
788
789         for_each_set_bit(partid, &pwrgate_partid_mask, BITS_PER_LONG)
790                 if (tegra_powergate_is_powered(partid) == 1)
791                         pr_warning("partition %s is left on before suspend\n",
792                                 tegra_powergate_get_name(partid));
793
794         return;
795 }
796
797 int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
798 {
799         int err = 0;
800         u32 scratch37 = 0xDEADBEEF;
801
802         if (WARN_ON(mode <= TEGRA_SUSPEND_NONE ||
803                 mode >= TEGRA_MAX_SUSPEND_MODE)) {
804                 err = -ENXIO;
805                 goto fail;
806         }
807
808         if (tegra_is_voice_call_active()) {
809                 u32 reg;
810
811                 /* backup the current value of scratch37 */
812                 scratch37 = readl(pmc + PMC_SCRATCH37);
813
814                 /* If voice call is active, set a flag in PMC_SCRATCH37 */
815                 reg = TEGRA_POWER_LP1_AUDIO;
816                 pmc_32kwritel(reg, PMC_SCRATCH37);
817         }
818
819         if ((mode == TEGRA_SUSPEND_LP0) && !tegra_pm_irq_lp0_allowed()) {
820                 pr_info("LP0 not used due to unsupported wakeup events\n");
821                 mode = TEGRA_SUSPEND_LP1;
822         }
823
824         if ((mode == TEGRA_SUSPEND_LP0) || (mode == TEGRA_SUSPEND_LP1))
825                 tegra_suspend_check_pwr_stats();
826
827         tegra_common_suspend();
828
829         tegra_pm_set(mode);
830
831         if (pdata && pdata->board_suspend)
832                 pdata->board_suspend(mode, TEGRA_SUSPEND_BEFORE_CPU);
833
834         local_fiq_disable();
835
836         trace_cpu_suspend(CPU_SUSPEND_START);
837
838         if (mode == TEGRA_SUSPEND_LP0) {
839 #ifdef CONFIG_TEGRA_CLUSTER_CONTROL
840                 u32 reg = readl(pmc + PMC_SCRATCH4);
841                 if (is_lp_cluster())
842                         reg |= PMC_SCRATCH4_WAKE_CLUSTER_MASK;
843                 else
844                         reg &= (~PMC_SCRATCH4_WAKE_CLUSTER_MASK);
845                 pmc_32kwritel(reg, PMC_SCRATCH4);
846 #endif
847                 tegra_lp0_suspend_mc();
848                 tegra_cpu_reset_handler_save();
849
850         }
851         else if (mode == TEGRA_SUSPEND_LP1)
852                 *iram_cpu_lp1_mask = 1;
853
854         suspend_cpu_complex(flags);
855
856         flush_cache_all();
857         outer_flush_all();
858         outer_disable();
859
860         if (mode == TEGRA_SUSPEND_LP2)
861                 tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
862         else
863                 tegra_sleep_core(mode, PHYS_OFFSET - PAGE_OFFSET);
864
865         tegra_init_cache(true);
866
867         if (mode == TEGRA_SUSPEND_LP0) {
868                 tegra_cpu_reset_handler_restore();
869                 tegra_lp0_resume_mc();
870         } else if (mode == TEGRA_SUSPEND_LP1)
871                 *iram_cpu_lp1_mask = 0;
872
873         /* if scratch37 was clobbered during LP1, restore it */
874         if (scratch37 != 0xDEADBEEF)
875                 pmc_32kwritel(scratch37, PMC_SCRATCH37);
876
877         restore_cpu_complex(flags);
878
879         /* for platforms where the core & CPU power requests are
880          * combined as a single request to the PMU, transition out
881          * of LP0 state by temporarily enabling both requests
882          */
883         if (mode == TEGRA_SUSPEND_LP0 && pdata->combined_req) {
884                 u32 reg;
885                 reg = readl(pmc + PMC_CTRL);
886                 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
887                 pmc_32kwritel(reg, PMC_CTRL);
888                 reg &= ~TEGRA_POWER_PWRREQ_OE;
889                 pmc_32kwritel(reg, PMC_CTRL);
890         }
891
892         if (pdata && pdata->board_resume)
893                 pdata->board_resume(mode, TEGRA_RESUME_AFTER_CPU);
894
895         trace_cpu_suspend(CPU_SUSPEND_DONE);
896
897         local_fiq_enable();
898
899         tegra_common_resume();
900
901 fail:
902         return err;
903 }
904
905 /*
906  * Function pointers to optional board specific function
907  */
908 void (*tegra_deep_sleep)(int);
909 EXPORT_SYMBOL(tegra_deep_sleep);
910
911 static int tegra_suspend_prepare(void)
912 {
913         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
914                 tegra_deep_sleep(1);
915         return 0;
916 }
917
918 static void tegra_suspend_finish(void)
919 {
920         if (pdata && pdata->cpu_resume_boost) {
921                 int ret = tegra_suspended_target(pdata->cpu_resume_boost);
922                 pr_info("Tegra: resume CPU boost to %u KHz: %s (%d)\n",
923                         pdata->cpu_resume_boost, ret ? "Failed" : "OK", ret);
924         }
925
926         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
927                 tegra_deep_sleep(0);
928 }
929
930 static const struct platform_suspend_ops tegra_suspend_ops = {
931         .valid          = suspend_valid_only_mem,
932         .prepare        = tegra_suspend_prepare,
933         .finish         = tegra_suspend_finish,
934         .prepare_late   = tegra_suspend_prepare_late,
935         .wake           = tegra_suspend_wake,
936         .enter          = tegra_suspend_enter,
937 };
938
939 static ssize_t suspend_mode_show(struct kobject *kobj,
940                                         struct kobj_attribute *attr, char *buf)
941 {
942         char *start = buf;
943         char *end = buf + PAGE_SIZE;
944
945         start += scnprintf(start, end - start, "%s ", \
946                                 tegra_suspend_name[current_suspend_mode]);
947         start += scnprintf(start, end - start, "\n");
948
949         return start - buf;
950 }
951
952 static ssize_t suspend_mode_store(struct kobject *kobj,
953                                         struct kobj_attribute *attr,
954                                         const char *buf, size_t n)
955 {
956         int len;
957         const char *name_ptr;
958         enum tegra_suspend_mode new_mode;
959
960         name_ptr = buf;
961         while (*name_ptr && !isspace(*name_ptr))
962                 name_ptr++;
963         len = name_ptr - buf;
964         if (!len)
965                 goto bad_name;
966         /* TEGRA_SUSPEND_NONE not allowed as suspend state */
967         if (!(strncmp(buf, tegra_suspend_name[TEGRA_SUSPEND_NONE], len))
968                 || !(strncmp(buf, tegra_suspend_name[TEGRA_SUSPEND_LP2], len))) {
969                 pr_info("Illegal tegra suspend state: %s\n", buf);
970                 goto bad_name;
971         }
972
973         for (new_mode = TEGRA_SUSPEND_NONE; \
974                         new_mode < TEGRA_MAX_SUSPEND_MODE; ++new_mode) {
975                 if (!strncmp(buf, tegra_suspend_name[new_mode], len)) {
976                         current_suspend_mode = new_mode;
977                         break;
978                 }
979         }
980
981 bad_name:
982         return n;
983 }
984
985 static struct kobj_attribute suspend_mode_attribute =
986         __ATTR(mode, 0644, suspend_mode_show, suspend_mode_store);
987
988 static struct kobject *suspend_kobj;
989
990 static int tegra_pm_enter_suspend(void)
991 {
992         pr_info("Entering suspend state %s\n", lp_state[current_suspend_mode]);
993         if (current_suspend_mode == TEGRA_SUSPEND_LP0)
994                 tegra_lp0_cpu_mode(true);
995         return 0;
996 }
997
998 static void tegra_pm_enter_resume(void)
999 {
1000         if (current_suspend_mode == TEGRA_SUSPEND_LP0)
1001                 tegra_lp0_cpu_mode(false);
1002         pr_info("Exited suspend state %s\n", lp_state[current_suspend_mode]);
1003 }
1004
1005 static struct syscore_ops tegra_pm_enter_syscore_ops = {
1006         .suspend = tegra_pm_enter_suspend,
1007         .resume = tegra_pm_enter_resume,
1008 };
1009
1010 static __init int tegra_pm_enter_syscore_init(void)
1011 {
1012         register_syscore_ops(&tegra_pm_enter_syscore_ops);
1013         return 0;
1014 }
1015 subsys_initcall(tegra_pm_enter_syscore_init);
1016 #endif
1017
1018 void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
1019 {
1020         u32 reg;
1021         u32 mode;
1022
1023         tegra_cpu_rail = tegra_dvfs_get_rail_by_name("vdd_cpu");
1024         tegra_core_rail = tegra_dvfs_get_rail_by_name("vdd_core");
1025         tegra_pclk = clk_get_sys(NULL, "pclk");
1026         BUG_ON(IS_ERR(tegra_pclk));
1027         pdata = plat;
1028         (void)reg;
1029         (void)mode;
1030
1031         if (plat->suspend_mode == TEGRA_SUSPEND_LP2)
1032                 plat->suspend_mode = TEGRA_SUSPEND_LP0;
1033
1034 #ifndef CONFIG_PM_SLEEP
1035         if (plat->suspend_mode != TEGRA_SUSPEND_NONE) {
1036                 pr_warning("%s: Suspend requires CONFIG_PM_SLEEP -- "
1037                            "disabling suspend\n", __func__);
1038                 plat->suspend_mode = TEGRA_SUSPEND_NONE;
1039         }
1040 #else
1041         if (create_suspend_pgtable() < 0) {
1042                 pr_err("%s: PGD memory alloc failed -- LP0/LP1/LP2 unavailable\n",
1043                                 __func__);
1044                 plat->suspend_mode = TEGRA_SUSPEND_NONE;
1045                 goto fail;
1046         }
1047
1048         if ((tegra_chip_id == TEGRA30) &&
1049             (tegra_revision == TEGRA_REVISION_A01) &&
1050             (plat->suspend_mode == TEGRA_SUSPEND_LP0)) {
1051                 /* Tegra 3 A01 supports only LP1 */
1052                 pr_warning("%s: Suspend mode LP0 is not supported on A01 "
1053                            "-- disabling LP0\n", __func__);
1054                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
1055         }
1056         if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && tegra_lp0_vec_size &&
1057                 tegra_lp0_vec_relocate) {
1058                 unsigned char *reloc_lp0;
1059                 unsigned long tmp;
1060                 void __iomem *orig;
1061                 reloc_lp0 = kmalloc(tegra_lp0_vec_size + L1_CACHE_BYTES - 1,
1062                                         GFP_KERNEL);
1063                 WARN_ON(!reloc_lp0);
1064                 if (!reloc_lp0) {
1065                         pr_err("%s: Failed to allocate reloc_lp0\n",
1066                                 __func__);
1067                         goto out;
1068                 }
1069
1070                 orig = ioremap(tegra_lp0_vec_start, tegra_lp0_vec_size);
1071                 WARN_ON(!orig);
1072                 if (!orig) {
1073                         pr_err("%s: Failed to map tegra_lp0_vec_start %08lx\n",
1074                                 __func__, tegra_lp0_vec_start);
1075                         kfree(reloc_lp0);
1076                         goto out;
1077                 }
1078
1079                 tmp = (unsigned long) reloc_lp0;
1080                 tmp = (tmp + L1_CACHE_BYTES - 1) & ~(L1_CACHE_BYTES - 1);
1081                 reloc_lp0 = (unsigned char *)tmp;
1082                 memcpy(reloc_lp0, orig, tegra_lp0_vec_size);
1083                 iounmap(orig);
1084                 tegra_lp0_vec_start = virt_to_phys(reloc_lp0);
1085         }
1086
1087 out:
1088         if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && !tegra_lp0_vec_size) {
1089                 pr_warning("%s: Suspend mode LP0 requested, no lp0_vec "
1090                            "provided by bootlader -- disabling LP0\n",
1091                            __func__);
1092                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
1093         }
1094
1095         iram_save_size = tegra_iram_end() - tegra_iram_start();
1096
1097         iram_save = kmalloc(iram_save_size, GFP_KERNEL);
1098         if (!iram_save && (plat->suspend_mode >= TEGRA_SUSPEND_LP1)) {
1099                 pr_err("%s: unable to allocate memory for SDRAM self-refresh "
1100                        "-- LP0/LP1 unavailable\n", __func__);
1101                 plat->suspend_mode = TEGRA_SUSPEND_LP2;
1102         }
1103
1104         /* !!!FIXME!!! THIS IS TEGRA2 ONLY */
1105         /* Initialize scratch registers used for CPU LP2 synchronization */
1106         writel(0, pmc + PMC_SCRATCH37);
1107         writel(0, pmc + PMC_SCRATCH38);
1108         writel(0, pmc + PMC_SCRATCH39);
1109         writel(0, pmc + PMC_SCRATCH41);
1110
1111         /* Always enable CPU power request; just normal polarity is supported */
1112         reg = readl(pmc + PMC_CTRL);
1113         BUG_ON(reg & TEGRA_POWER_CPU_PWRREQ_POLARITY);
1114         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
1115         pmc_32kwritel(reg, PMC_CTRL);
1116
1117         /* Configure core power request and system clock control if LP0
1118            is supported */
1119         __raw_writel(pdata->core_timer, pmc + PMC_COREPWRGOOD_TIMER);
1120         __raw_writel(pdata->core_off_timer, pmc + PMC_COREPWROFF_TIMER);
1121
1122         reg = readl(pmc + PMC_CTRL);
1123
1124         if (!pdata->sysclkreq_high)
1125                 reg |= TEGRA_POWER_SYSCLK_POLARITY;
1126         else
1127                 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
1128
1129         if (!pdata->corereq_high)
1130                 reg |= TEGRA_POWER_PWRREQ_POLARITY;
1131         else
1132                 reg &= ~TEGRA_POWER_PWRREQ_POLARITY;
1133
1134         /* configure output inverters while the request is tristated */
1135         pmc_32kwritel(reg, PMC_CTRL);
1136
1137         /* now enable requests */
1138         reg |= TEGRA_POWER_SYSCLK_OE;
1139         if (!pdata->combined_req)
1140                 reg |= TEGRA_POWER_PWRREQ_OE;
1141         pmc_32kwritel(reg, PMC_CTRL);
1142
1143         if (pdata->suspend_mode == TEGRA_SUSPEND_LP0)
1144                 tegra_lp0_suspend_init();
1145
1146         suspend_set_ops(&tegra_suspend_ops);
1147
1148         /* Create /sys/power/suspend/type */
1149         suspend_kobj = kobject_create_and_add("suspend", power_kobj);
1150         if (suspend_kobj) {
1151                 if (sysfs_create_file(suspend_kobj, \
1152                                                 &suspend_mode_attribute.attr))
1153                         pr_err("%s: sysfs_create_file suspend type failed!\n",
1154                                                                 __func__);
1155         }
1156
1157         iram_cpu_lp2_mask = tegra_cpu_lp2_mask;
1158         iram_cpu_lp1_mask = tegra_cpu_lp1_mask;
1159 fail:
1160 #endif
1161         if (plat->suspend_mode == TEGRA_SUSPEND_NONE)
1162                 tegra_lp2_in_idle(false);
1163
1164         current_suspend_mode = plat->suspend_mode;
1165 }
1166
1167 unsigned long debug_uart_port_base = 0;
1168 EXPORT_SYMBOL(debug_uart_port_base);
1169
1170 static int tegra_debug_uart_suspend(void)
1171 {
1172         void __iomem *uart;
1173         u32 lcr;
1174
1175         if (!debug_uart_port_base)
1176                 return 0;
1177
1178         uart = IO_ADDRESS(debug_uart_port_base);
1179
1180         lcr = readb(uart + UART_LCR * 4);
1181
1182         tegra_sctx.uart[0] = lcr;
1183         tegra_sctx.uart[1] = readb(uart + UART_MCR * 4);
1184
1185         /* DLAB = 0 */
1186         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
1187
1188         tegra_sctx.uart[2] = readb(uart + UART_IER * 4);
1189
1190         /* DLAB = 1 */
1191         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
1192
1193         tegra_sctx.uart[3] = readb(uart + UART_DLL * 4);
1194         tegra_sctx.uart[4] = readb(uart + UART_DLM * 4);
1195
1196         writeb(lcr, uart + UART_LCR * 4);
1197
1198         return 0;
1199 }
1200
1201 static void tegra_debug_uart_resume(void)
1202 {
1203         void __iomem *uart;
1204         u32 lcr;
1205
1206         if (!debug_uart_port_base)
1207                 return;
1208
1209         uart = IO_ADDRESS(debug_uart_port_base);
1210
1211         lcr = tegra_sctx.uart[0];
1212
1213         writeb(tegra_sctx.uart[1], uart + UART_MCR * 4);
1214
1215         /* DLAB = 0 */
1216         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
1217
1218         writeb(UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_01 | UART_FCR_R_TRIG_01,
1219                         uart + UART_FCR * 4);
1220
1221         writeb(tegra_sctx.uart[2], uart + UART_IER * 4);
1222
1223         /* DLAB = 1 */
1224         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
1225
1226         writeb(tegra_sctx.uart[3], uart + UART_DLL * 4);
1227         writeb(tegra_sctx.uart[4], uart + UART_DLM * 4);
1228
1229         writeb(lcr, uart + UART_LCR * 4);
1230 }
1231
1232 static struct syscore_ops tegra_debug_uart_syscore_ops = {
1233         .suspend = tegra_debug_uart_suspend,
1234         .resume = tegra_debug_uart_resume,
1235 };
1236
1237 struct clk *debug_uart_clk = NULL;
1238 EXPORT_SYMBOL(debug_uart_clk);
1239
1240 void tegra_console_uart_suspend(void)
1241 {
1242         if (console_suspend_enabled && debug_uart_clk)
1243                 clk_disable(debug_uart_clk);
1244 }
1245
1246 void tegra_console_uart_resume(void)
1247 {
1248         if (console_suspend_enabled && debug_uart_clk)
1249                 clk_enable(debug_uart_clk);
1250 }
1251
1252 static int tegra_debug_uart_syscore_init(void)
1253 {
1254         register_syscore_ops(&tegra_debug_uart_syscore_ops);
1255         return 0;
1256 }
1257 arch_initcall(tegra_debug_uart_syscore_init);