ARM: tegra: Catch early LP2 exits
[linux-3.10.git] / arch / arm / mach-tegra / pm.c
1 /*
2  * arch/arm/mach-tegra/pm.c
3  *
4  * CPU complex suspend & resume functions for Tegra SoCs
5  *
6  * Copyright (c) 2009-2011, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/ctype.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/sched.h>
28 #include <linux/smp.h>
29 #include <linux/irq.h>
30 #include <linux/interrupt.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
33 #include <linux/debugfs.h>
34 #include <linux/delay.h>
35 #include <linux/suspend.h>
36 #include <linux/slab.h>
37 #include <linux/serial_reg.h>
38 #include <linux/seq_file.h>
39 #include <linux/uaccess.h>
40 #include <linux/syscore_ops.h>
41 #include <linux/cpu_pm.h>
42 #include <linux/clk/tegra.h>
43 #include <linux/export.h>
44
45 #include <asm/cacheflush.h>
46 #include <asm/hardware/cache-l2x0.h>
47 #include <asm/idmap.h>
48 #include <asm/localtimer.h>
49 #include <asm/pgalloc.h>
50 #include <asm/tlbflush.h>
51
52 #include <mach/irqs.h>
53 #include <mach/powergate.h>
54
55 #include "board.h"
56 #include "clock.h"
57 #include "cpuidle.h"
58 #include "flowctrl.h"
59 #include "iomap.h"
60 #include "pm.h"
61 #include "pm-irq.h"
62 #include "sleep.h"
63 #include "fuse.h"
64
65 struct suspend_context {
66         /*
67          * The next 7 values are referenced by offset in __restart_plls
68          * in headsmp-t2.S, and should not be moved
69          */
70         u32 pllx_misc;
71         u32 pllx_base;
72         u32 pllp_misc;
73         u32 pllp_base;
74         u32 pllp_outa;
75         u32 pllp_outb;
76         u32 pll_timeout;
77
78         u32 cpu_burst;
79         u32 clk_csite_src;
80         u32 cclk_divider;
81
82         u32 mc[3];
83         u8 uart[5];
84 };
85
86 #ifdef CONFIG_PM_SLEEP
87 static DEFINE_SPINLOCK(tegra_lp2_lock);
88 static cpumask_t tegra_in_lp2;
89 static u8 *iram_save;
90 static unsigned long iram_save_size;
91 static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA);
92 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
93 static void __iomem *evp_reset =
94         IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100;
95 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
96 #endif
97
98 struct suspend_context tegra_sctx;
99
100 #define TEGRA_POWER_PWRREQ_POLARITY     (1 << 8)   /* core power request polarity */
101 #define TEGRA_POWER_PWRREQ_OE           (1 << 9)   /* core power request enable */
102 #define TEGRA_POWER_SYSCLK_POLARITY     (1 << 10)  /* sys clk polarity */
103 #define TEGRA_POWER_SYSCLK_OE           (1 << 11)  /* system clock enable */
104 #define TEGRA_POWER_PWRGATE_DIS         (1 << 12)  /* power gate disabled */
105 #define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* enter LP0 when CPU pwr gated */
106 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU power request polarity */
107 #define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU power request enable */
108
109 #define PMC_CTRL                0x0
110 #define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
111 #define PMC_WAKE_MASK           0xc
112 #define PMC_WAKE_LEVEL          0x10
113 #define PMC_DPAD_ORIDE          0x1C
114 #define PMC_WAKE_DELAY          0xe0
115 #define PMC_DPD_SAMPLE          0x20
116
117 #define PMC_WAKE_STATUS         0x14
118 #define PMC_SW_WAKE_STATUS      0x18
119 #define PMC_COREPWRGOOD_TIMER   0x3c
120 #define PMC_SCRATCH0            0x50
121 #define PMC_SCRATCH1            0x54
122 #define PMC_CPUPWRGOOD_TIMER    0xc8
123 #define PMC_CPUPWROFF_TIMER     0xcc
124 #define PMC_COREPWROFF_TIMER    PMC_WAKE_DELAY
125
126 #define CLK_RESET_CCLK_BURST    0x20
127 #define CLK_RESET_CCLK_DIVIDER  0x24
128 #define CLK_RESET_PLLC_BASE     0x80
129 #define CLK_RESET_PLLM_BASE     0x90
130 #define CLK_RESET_PLLX_BASE     0xe0
131 #define CLK_RESET_PLLX_MISC     0xe4
132 #define CLK_RESET_PLLP_BASE     0xa0
133 #define CLK_RESET_PLLP_OUTA     0xa4
134 #define CLK_RESET_PLLP_OUTB     0xa8
135 #define CLK_RESET_PLLP_MISC     0xac
136
137 #define CLK_RESET_SOURCE_CSITE  0x1d4
138
139 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
140 #define CLK_RESET_CCLK_BURST_POLICY_PLLM   3
141 #define CLK_RESET_CCLK_BURST_POLICY_PLLX   8
142
143 #define EMC_MRW_0               0x0e8
144 #define EMC_MRW_DEV_SELECTN     30
145 #define EMC_MRW_DEV_NONE        (3 << EMC_MRW_DEV_SELECTN)
146
147 #define MC_SECURITY_START       0x6c
148 #define MC_SECURITY_SIZE        0x70
149 #define MC_SECURITY_CFG2        0x7c
150
151 phys_addr_t tegra_pgd_phys;  /* pgd used by hotplug & LP2 bootup */
152 static pgd_t *tegra_pgd;
153
154 #ifdef CONFIG_PM_SLEEP
155 static int tegra_last_pclk;
156 #endif
157 static struct clk *tegra_pclk;
158 static const struct tegra_suspend_platform_data *pdata;
159 static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
160
161 static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
162         [TEGRA_SUSPEND_NONE]    = "none",
163         [TEGRA_SUSPEND_LP2]     = "lp2",
164         [TEGRA_SUSPEND_LP1]     = "lp1",
165         [TEGRA_SUSPEND_LP0]     = "lp0",
166 };
167
168 #if defined(CONFIG_PM_SLEEP) && INSTRUMENT_CLUSTER_SWITCH
169 enum tegra_cluster_switch_time_id {
170         tegra_cluster_switch_time_id_start = 0,
171         tegra_cluster_switch_time_id_prolog,
172         tegra_cluster_switch_time_id_switch,
173         tegra_cluster_switch_time_id_epilog,
174         tegra_cluster_switch_time_id_max
175 };
176
177 static unsigned long
178                 tegra_cluster_switch_times[tegra_cluster_switch_time_id_max];
179 #define tegra_cluster_switch_time(flags, id) \
180         do { \
181                 barrier(); \
182                 if (flags & TEGRA_POWER_CLUSTER_MASK) { \
183                         void __iomem *timer_us = \
184                                                 IO_ADDRESS(TEGRA_TMRUS_BASE); \
185                         if (id < tegra_cluster_switch_time_id_max) \
186                                 tegra_cluster_switch_times[id] = \
187                                                         readl(timer_us); \
188                                 wmb(); \
189                 } \
190                 barrier(); \
191         } while(0)
192 #else
193 #define tegra_cluster_switch_time(flags, id) do {} while(0)
194 #endif
195
196 unsigned long tegra_cpu_power_good_time(void)
197 {
198         if (WARN_ON_ONCE(!pdata))
199                 return 5000;
200
201         return pdata->cpu_timer;
202 }
203
204 unsigned long tegra_cpu_power_off_time(void)
205 {
206         if (WARN_ON_ONCE(!pdata))
207                 return 5000;
208
209         return pdata->cpu_off_timer;
210 }
211
212 unsigned long tegra_cpu_lp2_min_residency(void)
213 {
214         if (WARN_ON_ONCE(!pdata))
215                 return 2000;
216
217         return pdata->cpu_lp2_min_residency;
218 }
219
220 /*
221  * create_suspend_pgtable
222  *
223  * Creates a page table with identity mappings of physical memory and IRAM
224  * for use when the MMU is off, in addition to all the regular kernel mappings.
225  */
226 static int create_suspend_pgtable(void)
227 {
228         tegra_pgd = pgd_alloc(&init_mm);
229         if (!tegra_pgd)
230                 return -ENOMEM;
231
232         identity_mapping_add(tegra_pgd, phys_to_virt(PHYS_OFFSET),
233                 IO_IRAM_VIRT, 0);
234         identity_mapping_add(tegra_pgd, IO_IRAM_VIRT,
235                 IO_IRAM_VIRT + SECTION_SIZE, 0);
236
237         tegra_pgd_phys = virt_to_phys(tegra_pgd);
238
239         return 0;
240 }
241
242 #ifdef CONFIG_PM_SLEEP
243 /* ensures that sufficient time is passed for a register write to
244  * serialize into the 32KHz domain */
245 static void pmc_32kwritel(u32 val, unsigned long offs)
246 {
247         writel(val, pmc + offs);
248         udelay(130);
249 }
250
251 static void set_power_timers(unsigned long us_on, unsigned long us_off,
252                              long rate)
253 {
254         unsigned long long ticks;
255         unsigned long long pclk;
256
257         if (WARN_ON_ONCE(rate <= 0))
258                 pclk = 100000000;
259         else
260                 pclk = rate;
261
262         if (rate != tegra_last_pclk) {
263                 ticks = (us_on * pclk) + 999999ull;
264                 do_div(ticks, 1000000);
265                 writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
266
267                 ticks = (us_off * pclk) + 999999ull;
268                 do_div(ticks, 1000000);
269                 writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
270                 wmb();
271         }
272         tegra_last_pclk = pclk;
273 }
274
275 /*
276  * restore_cpu_complex
277  *
278  * restores cpu clock setting, clears flow controller
279  *
280  * always called on cpu 0, even when suspend_cpu_complex was called on cpu 1
281  * in idle
282  */
283 static void restore_cpu_complex(void)
284 {
285         unsigned int reg;
286         int i;
287
288         /* restore original burst policy setting */
289
290         writel(tegra_sctx.pllx_misc, clk_rst + CLK_RESET_PLLX_MISC);
291         writel(tegra_sctx.pllx_base, clk_rst + CLK_RESET_PLLX_BASE);
292         writel(tegra_sctx.pllp_misc, clk_rst + CLK_RESET_PLLP_MISC);
293         writel(tegra_sctx.pllp_base, clk_rst + CLK_RESET_PLLP_BASE);
294         writel(tegra_sctx.pllp_outa, clk_rst + CLK_RESET_PLLP_OUTA);
295         writel(tegra_sctx.pllp_outb, clk_rst + CLK_RESET_PLLP_OUTB);
296
297         /* Is CPU complex already running on PLLX? */
298         reg = readl(clk_rst + CLK_RESET_CCLK_BURST);
299         reg &= 0xF;
300         if (reg != 0x8) {
301                 /* restore original burst policy setting; PLLX state restored
302                  * by CPU boot-up code - wait for PLL stabilization if PLLX
303                  * was enabled */
304
305                 BUG_ON(readl(clk_rst + CLK_RESET_PLLX_BASE) !=
306                        tegra_sctx.pllx_base);
307
308                 if (tegra_sctx.pllx_base & (1<<30)) {
309 #if USE_PLL_LOCK_BITS
310                         /* Enable lock detector */
311                         reg = readl(clk_rst + CLK_RESET_PLLX_MISC);
312                         reg |= 1<<18;
313                         writel(reg, clk_rst + CLK_RESET_PLLX_MISC);
314                         while (!(readl(clk_rst + CLK_RESET_PLLX_BASE) &&
315                                  (1<<27)))
316                                 cpu_relax();
317 #else
318                         udelay(300);
319 #endif
320                 }
321                 writel(tegra_sctx.cclk_divider, clk_rst +
322                        CLK_RESET_CCLK_DIVIDER);
323                 writel(tegra_sctx.cpu_burst, clk_rst +
324                        CLK_RESET_CCLK_BURST);
325         }
326
327         writel(tegra_sctx.clk_csite_src, clk_rst + CLK_RESET_SOURCE_CSITE);
328
329         /* do not power-gate the CPU when flow controlled */
330         for (i = 0; i < num_possible_cpus(); i++) {
331                 reg = flowctrl_read_cpu_csr(i);
332                 reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
333                 reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
334                 reg &= ~FLOW_CTRL_CSR_ENABLE;           /* clear enable */
335                 reg |= FLOW_CTRL_CSR_INTR_FLAG;         /* clear intr */
336                 reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event */
337                 flowctrl_write_cpu_csr(i, reg);
338         }
339 }
340
341 /*
342  * suspend_cpu_complex
343  *
344  * saves pll state for use by restart_plls, prepares flow controller for
345  * transition to suspend state
346  *
347  * in suspend, always called on cpu 0
348  * in idle, called on the last cpu to request lp2
349  */
350 static void suspend_cpu_complex(void)
351 {
352         unsigned int reg;
353         int i;
354         int cpu = smp_processor_id();
355
356         /* switch coresite to clk_m, save off original source */
357         tegra_sctx.clk_csite_src = readl(clk_rst + CLK_RESET_SOURCE_CSITE);
358         writel(3<<30, clk_rst + CLK_RESET_SOURCE_CSITE);
359
360         tegra_sctx.cpu_burst = readl(clk_rst + CLK_RESET_CCLK_BURST);
361         tegra_sctx.pllx_base = readl(clk_rst + CLK_RESET_PLLX_BASE);
362         tegra_sctx.pllx_misc = readl(clk_rst + CLK_RESET_PLLX_MISC);
363         tegra_sctx.pllp_base = readl(clk_rst + CLK_RESET_PLLP_BASE);
364         tegra_sctx.pllp_outa = readl(clk_rst + CLK_RESET_PLLP_OUTA);
365         tegra_sctx.pllp_outb = readl(clk_rst + CLK_RESET_PLLP_OUTB);
366         tegra_sctx.pllp_misc = readl(clk_rst + CLK_RESET_PLLP_MISC);
367         tegra_sctx.cclk_divider = readl(clk_rst + CLK_RESET_CCLK_DIVIDER);
368
369         reg = flowctrl_read_cpu_csr(cpu);
370         reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;       /* clear wfe bitmap */
371         reg &= ~FLOW_CTRL_CSR_WFI_BITMAP;       /* clear wfi bitmap */
372         reg |= FLOW_CTRL_CSR_EVENT_FLAG;        /* clear event flag */
373 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
374         reg |= FLOW_CTRL_CSR_WFE_CPU0 << cpu;   /* enable power gating on wfe */
375 #else
376         reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu;   /* enable power gating on wfi */
377 #endif
378         reg |= FLOW_CTRL_CSR_ENABLE;            /* enable power gating */
379         flowctrl_write_cpu_csr(cpu, reg);
380
381         for (i = 0; i < num_possible_cpus(); i++) {
382                 if (i == cpu)
383                         continue;
384                 reg = flowctrl_read_cpu_csr(i);
385                 reg |= FLOW_CTRL_CSR_EVENT_FLAG;
386                 reg |= FLOW_CTRL_CSR_INTR_FLAG;
387                 flowctrl_write_cpu_csr(i, reg);
388                 flowctrl_write_cpu_halt(i, 0);
389         }
390 }
391
392 void tegra_clear_cpu_in_lp2(int cpu)
393 {
394         spin_lock(&tegra_lp2_lock);
395         cpumask_clear_cpu(cpu, &tegra_in_lp2);
396         spin_unlock(&tegra_lp2_lock);
397 }
398
399 bool tegra_set_cpu_in_lp2(int cpu)
400 {
401         bool last_cpu = false;
402
403         spin_lock(&tegra_lp2_lock);
404
405         cpumask_set_cpu(cpu, &tegra_in_lp2);
406         if (cpumask_equal(&tegra_in_lp2, cpu_online_mask))
407                 last_cpu = true;
408 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
409         else
410                 tegra2_cpu_set_resettable_soon();
411 #endif
412
413         spin_unlock(&tegra_lp2_lock);
414         return last_cpu;
415 }
416
417 unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags)
418 {
419         u32 reg;
420         unsigned int remain;
421
422         /* Only the last cpu down does the final suspend steps */
423         reg = readl(pmc + PMC_CTRL);
424         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
425         reg |= TEGRA_POWER_PWRREQ_OE;
426         reg |= flags;
427         reg &= ~TEGRA_POWER_EFFECT_LP0;
428         pmc_32kwritel(reg, PMC_CTRL);
429
430         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_start);
431
432         writel(virt_to_phys(tegra_resume), evp_reset);
433
434         /*
435          * We can use clk_get_rate_all_locked() here, because all other cpus
436          * are in LP2 state and irqs are disabled
437          */
438         set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer,
439                 clk_get_rate_all_locked(tegra_pclk));
440
441         if (flags & TEGRA_POWER_CLUSTER_MASK)
442                 tegra_cluster_switch_prolog(reg);
443
444         if (sleep_time)
445                 tegra_lp2_set_trigger(sleep_time);
446
447         cpu_cluster_pm_enter();
448
449         suspend_cpu_complex();
450         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_prolog);
451         flush_cache_all();
452         outer_flush_all();
453         outer_disable();
454
455         tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
456
457         l2x0_enable();
458         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_switch);
459         restore_cpu_complex();
460         cpu_cluster_pm_exit();
461
462         remain = tegra_lp2_timer_remain();
463         if (sleep_time)
464                 tegra_lp2_set_trigger(0);
465
466         if (flags & TEGRA_POWER_CLUSTER_MASK)
467                 tegra_cluster_switch_epilog(reg);
468
469         tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_epilog);
470
471 #if INSTRUMENT_CLUSTER_SWITCH
472         if (flags & TEGRA_POWER_CLUSTER_MASK) {
473                 pr_err("%s: prolog %lu us, switch %lu us, epilog %lu us, total %lu us\n",
474                         is_lp_cluster() ? "G=>LP" : "LP=>G",
475                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog] -
476                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start],
477                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch] -
478                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_prolog],
479                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
480                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_switch],
481                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_epilog] -
482                         tegra_cluster_switch_times[tegra_cluster_switch_time_id_start]);
483         }
484 #endif
485         return remain;
486 }
487
488 static int tegra_common_suspend(void)
489 {
490         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
491
492         tegra_sctx.mc[0] = readl(mc + MC_SECURITY_START);
493         tegra_sctx.mc[1] = readl(mc + MC_SECURITY_SIZE);
494         tegra_sctx.mc[2] = readl(mc + MC_SECURITY_CFG2);
495
496         /* copy the reset vector and SDRAM shutdown code into IRAM */
497         memcpy(iram_save, iram_code, iram_save_size);
498         memcpy(iram_code, tegra_iram_start(), iram_save_size);
499
500         return 0;
501 }
502
503 static void tegra_common_resume(void)
504 {
505         void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
506 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
507         void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
508 #endif
509
510         /* Clear DPD sample */
511         writel(0x0, pmc + PMC_DPD_SAMPLE);
512
513         writel(tegra_sctx.mc[0], mc + MC_SECURITY_START);
514         writel(tegra_sctx.mc[1], mc + MC_SECURITY_SIZE);
515         writel(tegra_sctx.mc[2], mc + MC_SECURITY_CFG2);
516 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
517         /* trigger emc mode write */
518         writel(EMC_MRW_DEV_NONE, emc + EMC_MRW_0);
519 #endif
520         /* clear scratch registers shared by suspend and the reset pen */
521         writel(0x0, pmc + PMC_SCRATCH39);
522         writel(0x0, pmc + PMC_SCRATCH41);
523
524         /* restore IRAM */
525         memcpy(iram_code, iram_save, iram_save_size);
526 }
527
528 static int tegra_suspend_prepare_late(void)
529 {
530 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
531         disable_irq(INT_SYS_STATS_MON);
532 #endif
533         return 0;
534 }
535
536 static void tegra_suspend_wake(void)
537 {
538 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
539         enable_irq(INT_SYS_STATS_MON);
540 #endif
541 }
542
543 static void tegra_pm_set(enum tegra_suspend_mode mode)
544 {
545         u32 reg;
546         unsigned long rate = 32768;
547
548         reg = readl(pmc + PMC_CTRL);
549         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
550         reg |= TEGRA_POWER_PWRREQ_OE;
551         reg &= ~TEGRA_POWER_EFFECT_LP0;
552
553         switch (mode) {
554         case TEGRA_SUSPEND_LP0:
555                 /*
556                  * lp0 boots through the AVP, which then resumes the AVP to
557                  * the address in scratch 39, and the cpu to the address in
558                  * scratch 41 to tegra_resume
559                  */
560                 writel(0x0, pmc + PMC_SCRATCH39);
561                 __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
562                 reg |= TEGRA_POWER_EFFECT_LP0;
563
564                 /* Enable DPD sample to trigger sampling pads data and direction
565                  * in which pad will be driven during lp0 mode*/
566                 writel(0x1, pmc + PMC_DPD_SAMPLE);
567                 break;
568         case TEGRA_SUSPEND_LP1:
569                 /*
570                  * lp1 boots through the normal cpu reset vector pointing to
571                  * tegra_lp1_reset in IRAM, which resumes the CPU to
572                  * the address in scratch 41 to tegra_resume
573                  */
574                 writel(tegra_lp1_reset() - tegra_iram_start() +
575                         TEGRA_IRAM_CODE_AREA, evp_reset);
576                 __raw_writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
577                 break;
578         case TEGRA_SUSPEND_LP2:
579                 /*
580                  * lp2 boots through the normal cpu reset vector directly to
581                  * tegra_resume
582                  */
583                 writel(virt_to_phys(tegra_resume), evp_reset);
584                 rate = clk_get_rate(tegra_pclk);
585                 break;
586         default:
587                 BUG();
588         }
589
590         set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer, rate);
591
592         pmc_32kwritel(reg, PMC_CTRL);
593
594         /* Set warmboot flag */
595         reg = readl(pmc + PMC_SCRATCH0);
596         pmc_32kwritel(reg | 1, PMC_SCRATCH0);
597
598         pmc_32kwritel(tegra_lp0_vec_start, PMC_SCRATCH1);
599 }
600
601 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
602         [TEGRA_SUSPEND_NONE] = "none",
603         [TEGRA_SUSPEND_LP2] = "LP2",
604         [TEGRA_SUSPEND_LP1] = "LP1",
605         [TEGRA_SUSPEND_LP0] = "LP0",
606 };
607
608 static int tegra_suspend_enter(suspend_state_t state)
609 {
610         return tegra_suspend_dram(current_suspend_mode);
611 }
612
613 static void tegra_suspend_check_pwr_stats(void)
614 {
615         /* cpus and l2 are powered off later */
616         unsigned long pwrgate_partid_mask =
617 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
618                 (1 << TEGRA_POWERGATE_HEG)      |
619                 (1 << TEGRA_POWERGATE_SATA)     |
620                 (1 << TEGRA_POWERGATE_3D1)      |
621 #endif
622                 (1 << TEGRA_POWERGATE_3D)       |
623                 (1 << TEGRA_POWERGATE_VENC)     |
624                 (1 << TEGRA_POWERGATE_PCIE)     |
625                 (1 << TEGRA_POWERGATE_VDEC)     |
626                 (1 << TEGRA_POWERGATE_MPE);
627
628         int partid;
629
630         for_each_set_bit(partid, &pwrgate_partid_mask, BITS_PER_LONG)
631                 if (tegra_powergate_is_powered(partid) == 1)
632                         pr_warning("partition %s is left on before suspend\n",
633                                 tegra_powergate_get_name(partid));
634
635         return;
636 }
637
638 int tegra_suspend_dram(enum tegra_suspend_mode mode)
639 {
640         BUG_ON(mode < 0 || mode >= TEGRA_MAX_SUSPEND_MODE);
641
642         if ((mode == TEGRA_SUSPEND_LP0) && !tegra_pm_irq_lp0_allowed()) {
643                 pr_info("LP0 not used due to unsupported wakeup events\n");
644                 mode = TEGRA_SUSPEND_LP1;
645         }
646
647         if ((mode == TEGRA_SUSPEND_LP0) || (mode == TEGRA_SUSPEND_LP1))
648                 tegra_suspend_check_pwr_stats();
649
650         tegra_common_suspend();
651
652         pr_info("Entering suspend state %s\n", lp_state[mode]);
653
654         tegra_pm_set(mode);
655
656         local_fiq_disable();
657
658         cpu_pm_enter();
659         cpu_cluster_pm_enter();
660
661         if (mode == TEGRA_SUSPEND_LP0)
662                 tegra_lp0_suspend_mc();
663
664         suspend_cpu_complex();
665         flush_cache_all();
666         outer_flush_all();
667         outer_disable();
668
669         if (mode == TEGRA_SUSPEND_LP2)
670                 tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
671         else
672                 tegra_sleep_core(PHYS_OFFSET - PAGE_OFFSET);
673
674         tegra_init_cache();
675
676         if (mode == TEGRA_SUSPEND_LP0)
677                 tegra_lp0_resume_mc();
678
679         restore_cpu_complex();
680
681         cpu_cluster_pm_exit();
682         cpu_pm_exit();
683
684         local_fiq_enable();
685
686         tegra_common_resume();
687
688         return 0;
689 }
690
691 /*
692  * Function pointers to optional board specific function
693  */
694 void (*tegra_deep_sleep)(int);
695 EXPORT_SYMBOL(tegra_deep_sleep);
696
697 static int tegra_suspend_prepare(void)
698 {
699         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
700                 tegra_deep_sleep(1);
701         return 0;
702 }
703
704 static void tegra_suspend_finish(void)
705 {
706         if ((current_suspend_mode == TEGRA_SUSPEND_LP0) && tegra_deep_sleep)
707                 tegra_deep_sleep(0);
708 }
709
710 static const struct platform_suspend_ops tegra_suspend_ops = {
711         .valid          = suspend_valid_only_mem,
712         .prepare        = tegra_suspend_prepare,
713         .finish         = tegra_suspend_finish,
714         .prepare_late   = tegra_suspend_prepare_late,
715         .wake           = tegra_suspend_wake,
716         .enter          = tegra_suspend_enter,
717 };
718
719 static ssize_t suspend_mode_show(struct kobject *kobj,
720                                         struct kobj_attribute *attr, char *buf)
721 {
722         char *start = buf;
723         char *end = buf + PAGE_SIZE;
724
725         start += scnprintf(start, end - start, "%s ", \
726                                 tegra_suspend_name[current_suspend_mode]);
727         start += scnprintf(start, end - start, "\n");
728
729         return start - buf;
730 }
731
732 static ssize_t suspend_mode_store(struct kobject *kobj,
733                                         struct kobj_attribute *attr,
734                                         const char *buf, size_t n)
735 {
736         int len;
737         const char *name_ptr;
738         enum tegra_suspend_mode new_mode;
739
740         name_ptr = buf;
741         while (*name_ptr && !isspace(*name_ptr))
742                 name_ptr++;
743         len = name_ptr - buf;
744         if (!len)
745                 goto bad_name;
746
747         for (new_mode = TEGRA_SUSPEND_NONE; \
748                         new_mode < TEGRA_MAX_SUSPEND_MODE; ++new_mode) {
749                 if (!strncmp(buf, tegra_suspend_name[new_mode], len)) {
750                         current_suspend_mode = new_mode;
751                         break;
752                 }
753         }
754
755 bad_name:
756         return n;
757 }
758
759 static struct kobj_attribute suspend_mode_attribute =
760         __ATTR(mode, 0666, suspend_mode_show, suspend_mode_store);
761
762 static struct kobject *suspend_kobj;
763 #endif
764
765 void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
766 {
767         u32 reg;
768         u32 mode;
769
770         tegra_pclk = clk_get_sys(NULL, "pclk");
771         BUG_ON(IS_ERR(tegra_pclk));
772         pdata = plat;
773         (void)reg;
774         (void)mode;
775
776         preset_lpj = loops_per_jiffy;
777
778         create_suspend_pgtable();
779
780 #ifdef CONFIG_PM_SLEEP
781
782         if ((tegra_chip_id == TEGRA30) &&
783             (tegra_revision == TEGRA_REVISION_A01) &&
784             (plat->suspend_mode == TEGRA_SUSPEND_LP0)) {
785                 /* Tegra 3 A01 supports only LP1 */
786                 pr_warning("%s: Suspend mode LP0 is not supported on A01 "
787                            "-- disabling LP0\n", __func__);
788                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
789         }
790
791         if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && !tegra_lp0_vec_size) {
792                 pr_warning("%s: Suspend mode LP0 requested, no lp0_vec "
793                            "provided by bootlader -- disabling LP0\n",
794                            __func__);
795                 plat->suspend_mode = TEGRA_SUSPEND_LP1;
796         }
797
798         iram_save_size = tegra_iram_end() - tegra_iram_start();
799
800         iram_save = kmalloc(iram_save_size, GFP_KERNEL);
801         if (!iram_save) {
802                 pr_err("%s: unable to allocate memory for SDRAM self-refresh "
803                        "-- LP0/LP1 unavailable\n", __func__);
804                 plat->suspend_mode = TEGRA_SUSPEND_LP2;
805         }
806
807         /* !!!FIXME!!! THIS IS TEGRA2 ONLY */
808         /* Initialize scratch registers used for CPU LP2 synchronization */
809         writel(0, pmc + PMC_SCRATCH37);
810         writel(0, pmc + PMC_SCRATCH38);
811         writel(0, pmc + PMC_SCRATCH39);
812         writel(0, pmc + PMC_SCRATCH41);
813
814         /* Always enable CPU power request; just normal polarity is supported */
815         reg = readl(pmc + PMC_CTRL);
816         BUG_ON(reg & TEGRA_POWER_CPU_PWRREQ_POLARITY);
817         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
818         pmc_32kwritel(reg, PMC_CTRL);
819
820         /* Configure core power request and system clock control if LP0
821            is supported */
822         __raw_writel(pdata->core_timer, pmc + PMC_COREPWRGOOD_TIMER);
823         __raw_writel(pdata->core_off_timer, pmc + PMC_COREPWROFF_TIMER);
824
825         reg = readl(pmc + PMC_CTRL);
826
827         if (!pdata->sysclkreq_high)
828                 reg |= TEGRA_POWER_SYSCLK_POLARITY;
829         else
830                 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
831
832         if (!pdata->corereq_high)
833                 reg |= TEGRA_POWER_PWRREQ_POLARITY;
834         else
835                 reg &= ~TEGRA_POWER_PWRREQ_POLARITY;
836
837         /* configure output inverters while the request is tristated */
838         pmc_32kwritel(reg, PMC_CTRL);
839
840         /* now enable requests */
841         reg |= TEGRA_POWER_SYSCLK_OE;
842         reg |= TEGRA_POWER_PWRREQ_OE;
843         pmc_32kwritel(reg, PMC_CTRL);
844
845         if (pdata->suspend_mode == TEGRA_SUSPEND_LP0)
846                 tegra_lp0_suspend_init();
847
848         suspend_set_ops(&tegra_suspend_ops);
849
850         /* Create /sys/power/suspend/type */
851         suspend_kobj = kobject_create_and_add("suspend", power_kobj);
852         if (suspend_kobj) {
853                 if (sysfs_create_file(suspend_kobj, \
854                                                 &suspend_mode_attribute.attr))
855                         pr_err("%s: sysfs_create_file suspend type failed!\n",
856                                                                 __func__);
857         }
858
859 #ifdef CONFIG_CPU_IDLE
860         if (plat->suspend_mode == TEGRA_SUSPEND_NONE)
861                 tegra_lp2_in_idle(false);
862 #endif
863 #else
864         if (plat->suspend_mode != TEGRA_SUSPEND_NONE) {
865                 pr_warning("%s: Suspend requires CONFIG_PM_SLEEP -- "
866                            "disabling suspend\n", __func__);
867                 plat->suspend_mode = TEGRA_SUSPEND_NONE;
868         }
869 #endif
870
871         current_suspend_mode = plat->suspend_mode;
872 }
873
874 static int tegra_debug_uart_suspend(void)
875 {
876         void __iomem *uart;
877         u32 lcr;
878
879         if (TEGRA_DEBUG_UART_BASE == 0)
880                 return 0;
881
882         uart = IO_ADDRESS(TEGRA_DEBUG_UART_BASE);
883
884         lcr = readb(uart + UART_LCR * 4);
885
886         tegra_sctx.uart[0] = lcr;
887         tegra_sctx.uart[1] = readb(uart + UART_MCR * 4);
888
889         /* DLAB = 0 */
890         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
891
892         tegra_sctx.uart[2] = readb(uart + UART_IER * 4);
893
894         /* DLAB = 1 */
895         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
896
897         tegra_sctx.uart[3] = readb(uart + UART_DLL * 4);
898         tegra_sctx.uart[4] = readb(uart + UART_DLM * 4);
899
900         writeb(lcr, uart + UART_LCR * 4);
901
902         return 0;
903 }
904
905 static void tegra_debug_uart_resume(void)
906 {
907         void __iomem *uart;
908         u32 lcr;
909
910         if (TEGRA_DEBUG_UART_BASE == 0)
911                 return;
912
913         uart = IO_ADDRESS(TEGRA_DEBUG_UART_BASE);
914
915         lcr = tegra_sctx.uart[0];
916
917         writeb(tegra_sctx.uart[1], uart + UART_MCR * 4);
918
919         /* DLAB = 0 */
920         writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
921
922         writeb(tegra_sctx.uart[2], uart + UART_IER * 4);
923
924         /* DLAB = 1 */
925         writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
926
927         writeb(tegra_sctx.uart[3], uart + UART_DLL * 4);
928         writeb(tegra_sctx.uart[4], uart + UART_DLM * 4);
929
930         writeb(lcr, uart + UART_LCR * 4);
931 }
932
933 static struct syscore_ops tegra_debug_uart_syscore_ops = {
934         .suspend = tegra_debug_uart_suspend,
935         .resume = tegra_debug_uart_resume,
936 };
937
938 static int tegra_debug_uart_syscore_init(void)
939 {
940         register_syscore_ops(&tegra_debug_uart_syscore_ops);
941         return 0;
942 }
943 arch_initcall(tegra_debug_uart_syscore_init);
944
945 #ifdef CONFIG_DEBUG_FS
946 static int tegra_suspend_debug_show(struct seq_file *s, void *data)
947 {
948         seq_printf(s, "%s\n", tegra_suspend_name[*(int *)s->private]);
949         return 0;
950 }
951
952 static int tegra_suspend_debug_open(struct inode *inode, struct file *file)
953 {
954         return single_open(file, tegra_suspend_debug_show, inode->i_private);
955 }
956
957 static int tegra_suspend_debug_write(struct file *file,
958         const char __user *user_buf, size_t count, loff_t *ppos)
959 {
960         char buf[32];
961         int buf_size;
962         int i;
963         struct seq_file *s = file->private_data;
964         enum tegra_suspend_mode *val = s->private;
965
966         memset(buf, 0x00, sizeof(buf));
967         buf_size = min(count, (sizeof(buf)-1));
968         if (copy_from_user(buf, user_buf, buf_size))
969                 return -EFAULT;
970
971         for (i = 0; i < TEGRA_MAX_SUSPEND_MODE; i++) {
972                 if (!strnicmp(buf, tegra_suspend_name[i],
973                     strlen(tegra_suspend_name[i]))) {
974                         if (i > pdata->suspend_mode)
975                                 return -EINVAL;
976                         *val = i;
977                         return count;
978                 }
979         }
980
981         return -EINVAL;
982 }
983
984 static const struct file_operations tegra_suspend_debug_fops = {
985         .open           = tegra_suspend_debug_open,
986         .write          = tegra_suspend_debug_write,
987         .read           = seq_read,
988         .llseek         = seq_lseek,
989         .release        = single_release,
990 };
991
992 static int __init tegra_suspend_debug_init(void)
993 {
994         struct dentry *d;
995
996         d = debugfs_create_file("suspend_mode", 0755, NULL,
997                 (void *)&current_suspend_mode, &tegra_suspend_debug_fops);
998         if (!d) {
999                 pr_info("Failed to create suspend_mode debug file\n");
1000                 return -ENOMEM;
1001         }
1002
1003         return 0;
1004 }
1005
1006 late_initcall(tegra_suspend_debug_init);
1007 #endif