2 * linux/arch/arm/mach-tegra/pinmux.c
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2011 NVIDIA Corporation.
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/spinlock.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_device.h>
27 #include <mach/pinmux.h>
31 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
32 #define TEGRA_PINMUX_HAS_IO_DIRECTION 1
35 #define HSM_EN(reg) (((reg) >> 2) & 0x1)
36 #define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
37 #define LPMD(reg) (((reg) >> 4) & 0x3)
38 #define DRVDN(reg, offset) (((reg) >> offset) & 0x1f)
39 #define DRVUP(reg, offset) (((reg) >> offset) & 0x1f)
40 #define SLWR(reg, offset) (((reg) >> offset) & 0x3)
41 #define SLWF(reg, offset) (((reg) >> offset) & 0x3)
43 static const struct tegra_pingroup_desc *pingroups;
44 static const struct tegra_drive_pingroup_desc *drive_pingroups;
45 static const int *gpio_to_pingroups_map;
46 static int pingroup_max;
48 static int gpio_to_pingroups_max;
50 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
51 #define TEGRA_MUX(mux) [TEGRA_MUX_##mux] = #mux,
54 [TEGRA_MUX_SAFE] = "<safe>",
57 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
58 [TEGRA_DRIVE_DIV_8] = "DIV_8",
59 [TEGRA_DRIVE_DIV_4] = "DIV_4",
60 [TEGRA_DRIVE_DIV_2] = "DIV_2",
61 [TEGRA_DRIVE_DIV_1] = "DIV_1",
64 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
65 [TEGRA_SLEW_FASTEST] = "FASTEST",
66 [TEGRA_SLEW_FAST] = "FAST",
67 [TEGRA_SLEW_SLOW] = "SLOW",
68 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
71 static DEFINE_SPINLOCK(mux_lock);
73 static const char *pingroup_name(int pg)
75 if (pg < 0 || pg >= pingroup_max)
78 return pingroups[pg].name;
81 static const char *func_name(enum tegra_mux_func func)
83 if (func == TEGRA_MUX_RSVD1)
86 if (func == TEGRA_MUX_RSVD2)
89 if (func == TEGRA_MUX_RSVD3)
92 if (func == TEGRA_MUX_RSVD4)
95 if (func == TEGRA_MUX_INVALID)
98 if (func < 0 || func >= TEGRA_MAX_MUX)
101 return tegra_mux_names[func];
105 static const char *tri_name(unsigned long val)
107 return val ? "TRISTATE" : "NORMAL";
110 static const char *pupd_name(unsigned long val)
127 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
128 static const char *lock_name(unsigned long val)
131 case TEGRA_PIN_LOCK_DEFAULT:
132 return "LOCK_DEFUALT";
134 case TEGRA_PIN_LOCK_DISABLE:
135 return "LOCK_DISABLE";
137 case TEGRA_PIN_LOCK_ENABLE:
138 return "LOCK_ENABLE";
140 return "LOCK_DEFAULT";
144 static const char *od_name(unsigned long val)
147 case TEGRA_PIN_OD_DEFAULT:
150 case TEGRA_PIN_OD_DISABLE:
153 case TEGRA_PIN_OD_ENABLE:
160 static const char *ioreset_name(unsigned long val)
163 case TEGRA_PIN_IO_RESET_DEFAULT:
164 return "IO_RESET_DEFAULT";
166 case TEGRA_PIN_IO_RESET_DISABLE:
167 return "IO_RESET_DISABLE";
169 case TEGRA_PIN_IO_RESET_ENABLE:
170 return "IO_RESET_ENABLE";
172 return "IO_RESET_DEFAULT";
177 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
178 static const char *io_name(unsigned long val)
194 static void __iomem **regs;
196 u32 pg_readl(u32 bank, u32 reg)
198 return readl(regs[bank] + reg);
201 void pg_writel(u32 val, u32 bank, u32 reg)
203 writel(val, regs[bank] + reg);
206 int tegra_pinmux_get_pingroup(int gpio_nr)
208 return gpio_to_pingroups_map[gpio_nr];
210 EXPORT_SYMBOL_GPL(tegra_pinmux_get_pingroup);
212 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
219 int pg = config->pingroup;
220 enum tegra_mux_func func = config->func;
222 if (pg < 0 || pg >= pingroup_max)
225 if (pingroups[pg].mux_reg < 0)
228 if (func == TEGRA_MUX_INVALID) {
229 pr_err("The pingroup %s is not recommended for option %s\n",
230 pingroup_name(pg), func_name(func));
238 if (func == TEGRA_MUX_SAFE)
239 func = pingroups[pg].func_safe;
241 if (func & TEGRA_MUX_RSVD) {
242 for (i = 0; i < 4; i++) {
243 if (pingroups[pg].funcs[i] & TEGRA_MUX_RSVD)
246 if (pingroups[pg].funcs[i] == func) {
253 for (i = 0; i < 4; i++) {
254 if (pingroups[pg].funcs[i] == func) {
263 pr_err("The pingroup %s is not supported option %s\n",
264 pingroup_name(pg), func_name(func));
270 pr_warn("The pingroup %s was configured to %s instead of %s\n",
271 pingroup_name(pg), func_name(pingroups[pg].funcs[mux]),
274 spin_lock_irqsave(&mux_lock, flags);
276 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
277 reg &= ~(0x3 << pingroups[pg].mux_bit);
278 reg |= mux << pingroups[pg].mux_bit;
279 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
281 reg |= ((config->io & 0x1) << 5);
283 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
285 spin_unlock_irqrestore(&mux_lock, flags);
290 int tegra_pinmux_get_func(int pg)
296 if (pg < 0 || pg >= pingroup_max)
299 if (pingroups[pg].mux_reg < 0)
302 spin_lock_irqsave(&mux_lock, flags);
304 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
305 mux = (reg >> pingroups[pg].mux_bit) & 0x3;
307 spin_unlock_irqrestore(&mux_lock, flags);
312 int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
317 if (pg < 0 || pg >= pingroup_max)
320 if (pingroups[pg].tri_reg < 0)
323 spin_lock_irqsave(&mux_lock, flags);
325 reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
326 reg &= ~(0x1 << pingroups[pg].tri_bit);
328 reg |= 1 << pingroups[pg].tri_bit;
329 pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
331 spin_unlock_irqrestore(&mux_lock, flags);
336 int tegra_pinmux_set_io(int pg, enum tegra_pin_io input)
338 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
341 if (pg < 0 || pg >= pingroup_max)
344 io = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
349 pg_writel(io, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
353 EXPORT_SYMBOL_GPL(tegra_pinmux_set_io);
355 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
356 static int tegra_pinmux_set_lock(int pg, enum tegra_pin_lock lock)
361 if (pg < 0 || pg >= pingroup_max)
364 if (pingroups[pg].mux_reg < 0)
367 if ((lock == TEGRA_PIN_LOCK_DEFAULT) || (pingroups[pg].lock_bit < 0))
370 spin_lock_irqsave(&mux_lock, flags);
372 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
373 reg &= ~(0x1 << pingroups[pg].lock_bit);
374 if (lock == TEGRA_PIN_LOCK_ENABLE)
375 reg |= (0x1 << pingroups[pg].lock_bit);
377 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
379 spin_unlock_irqrestore(&mux_lock, flags);
383 static int tegra_pinmux_set_od(int pg, enum tegra_pin_od od)
388 if (pg < 0 || pg >= pingroup_max)
391 if (pingroups[pg].mux_reg < 0)
394 if ((od == TEGRA_PIN_OD_DEFAULT) || (pingroups[pg].od_bit < 0))
397 spin_lock_irqsave(&mux_lock, flags);
399 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
400 reg &= ~(0x1 << pingroups[pg].od_bit);
401 if (od == TEGRA_PIN_OD_ENABLE)
402 reg |= 1 << pingroups[pg].od_bit;
404 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
406 spin_unlock_irqrestore(&mux_lock, flags);
411 static int tegra_pinmux_set_ioreset(int pg, enum tegra_pin_ioreset ioreset)
416 if (pg < 0 || pg >= pingroup_max)
419 if (pingroups[pg].mux_reg < 0)
422 if ((ioreset == TEGRA_PIN_IO_RESET_DEFAULT) || (pingroups[pg].ioreset_bit < 0))
425 spin_lock_irqsave(&mux_lock, flags);
427 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
428 reg &= ~(0x1 << pingroups[pg].ioreset_bit);
429 if (ioreset == TEGRA_PIN_IO_RESET_ENABLE)
430 reg |= 1 << pingroups[pg].ioreset_bit;
432 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
434 spin_unlock_irqrestore(&mux_lock, flags);
440 int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
445 if (pg < 0 || pg >= pingroup_max)
448 if (pingroups[pg].pupd_reg < 0)
451 if (pupd != TEGRA_PUPD_NORMAL &&
452 pupd != TEGRA_PUPD_PULL_DOWN &&
453 pupd != TEGRA_PUPD_PULL_UP)
457 spin_lock_irqsave(&mux_lock, flags);
459 reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
460 reg &= ~(0x3 << pingroups[pg].pupd_bit);
461 reg |= pupd << pingroups[pg].pupd_bit;
462 pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
464 spin_unlock_irqrestore(&mux_lock, flags);
469 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
471 int pingroup = config->pingroup;
472 enum tegra_mux_func func = config->func;
473 enum tegra_pullupdown pupd = config->pupd;
474 enum tegra_tristate tristate = config->tristate;
475 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
476 enum tegra_pin_lock lock = config->lock;
477 enum tegra_pin_od od = config->od;
478 enum tegra_pin_ioreset ioreset = config->ioreset;
482 if (pingroups[pingroup].mux_reg >= 0) {
483 err = tegra_pinmux_set_func(config);
485 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
486 pingroup_name(pingroup), func_name(func), err);
489 if (pingroups[pingroup].pupd_reg >= 0) {
490 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
492 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
493 pingroup_name(pingroup), pupd_name(pupd), err);
496 if (pingroups[pingroup].tri_reg >= 0) {
497 err = tegra_pinmux_set_tristate(pingroup, tristate);
499 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
500 pingroup_name(pingroup), tri_name(func), err);
503 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
504 if (pingroups[pingroup].mux_reg >= 0) {
505 err = tegra_pinmux_set_lock(pingroup, lock);
507 pr_err("pinmux: can't set pingroup %s lock to %s: %d\n",
508 pingroup_name(pingroup), lock_name(func), err);
511 if (pingroups[pingroup].mux_reg >= 0) {
512 err = tegra_pinmux_set_od(pingroup, od);
514 pr_err("pinmux: can't set pingroup %s od to %s: %d\n",
515 pingroup_name(pingroup), od_name(func), err);
518 if (pingroups[pingroup].mux_reg >= 0) {
519 err = tegra_pinmux_set_ioreset(pingroup, ioreset);
521 pr_err("pinmux: can't set pingroup %s ioreset to %s: %d\n",
522 pingroup_name(pingroup), ioreset_name(func), err);
527 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
531 for (i = 0; i < len; i++)
532 tegra_pinmux_config_pingroup(&config[i]);
534 EXPORT_SYMBOL(tegra_pinmux_config_table);
536 static const char *drive_pinmux_name(int pg)
538 if (pg < 0 || pg >= drive_max)
541 return drive_pingroups[pg].name;
544 static const char *enable_name(unsigned long val)
546 return val ? "ENABLE" : "DISABLE";
549 static const char *drive_name(unsigned long val)
551 if (val >= TEGRA_MAX_DRIVE)
554 return tegra_drive_names[val];
557 static const char *slew_name(unsigned long val)
559 if (val >= TEGRA_MAX_SLEW)
562 return tegra_slew_names[val];
565 static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
569 if (pg < 0 || pg >= drive_max)
572 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
575 spin_lock_irqsave(&mux_lock, flags);
577 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
578 if (hsm == TEGRA_HSM_ENABLE)
582 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
584 spin_unlock_irqrestore(&mux_lock, flags);
589 static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
593 if (pg < 0 || pg >= drive_max)
596 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
599 spin_lock_irqsave(&mux_lock, flags);
601 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
602 if (schmitt == TEGRA_SCHMITT_ENABLE)
606 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
608 spin_unlock_irqrestore(&mux_lock, flags);
613 static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
617 if (pg < 0 || pg >= drive_max)
620 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
623 spin_lock_irqsave(&mux_lock, flags);
625 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
628 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
630 spin_unlock_irqrestore(&mux_lock, flags);
635 static int tegra_drive_pinmux_set_pull_down(int pg,
636 enum tegra_pull_strength pull_down)
641 if (pg < 0 || pg >= drive_max)
644 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
647 spin_lock_irqsave(&mux_lock, flags);
649 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
650 reg &= ~(drive_pingroups[pg].drvdown_mask <<
651 drive_pingroups[pg].drvdown_offset);
652 reg |= pull_down << drive_pingroups[pg].drvdown_offset;
653 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
655 spin_unlock_irqrestore(&mux_lock, flags);
660 static int tegra_drive_pinmux_set_pull_up(int pg,
661 enum tegra_pull_strength pull_up)
666 if (pg < 0 || pg >= drive_max)
669 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
672 spin_lock_irqsave(&mux_lock, flags);
674 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
675 reg &= ~(drive_pingroups[pg].drvup_mask <<
676 drive_pingroups[pg].drvup_offset);
677 reg |= pull_up << drive_pingroups[pg].drvup_offset;
678 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
680 spin_unlock_irqrestore(&mux_lock, flags);
685 static int tegra_drive_pinmux_set_slew_rising(int pg,
686 enum tegra_slew slew_rising)
690 if (pg < 0 || pg >= drive_max)
693 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
696 spin_lock_irqsave(&mux_lock, flags);
698 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
699 reg &= ~(drive_pingroups[pg].slewrise_mask <<
700 drive_pingroups[pg].slewrise_offset);
701 reg |= slew_rising << drive_pingroups[pg].slewrise_offset;
702 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
704 spin_unlock_irqrestore(&mux_lock, flags);
709 static int tegra_drive_pinmux_set_slew_falling(int pg,
710 enum tegra_slew slew_falling)
714 if (pg < 0 || pg >= drive_max)
717 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
720 spin_lock_irqsave(&mux_lock, flags);
722 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
723 reg &= ~(drive_pingroups[pg].slewfall_mask <<
724 drive_pingroups[pg].slewfall_offset);
725 reg |= slew_falling << drive_pingroups[pg].slewfall_offset;
726 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
728 spin_unlock_irqrestore(&mux_lock, flags);
733 static void tegra_drive_pinmux_config_pingroup(int pingroup,
735 enum tegra_schmitt schmitt,
736 enum tegra_drive drive,
737 enum tegra_pull_strength pull_down,
738 enum tegra_pull_strength pull_up,
739 enum tegra_slew slew_rising,
740 enum tegra_slew slew_falling)
744 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
746 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
747 drive_pinmux_name(pingroup),
748 enable_name(hsm), err);
750 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
752 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
753 drive_pinmux_name(pingroup),
754 enable_name(schmitt), err);
756 err = tegra_drive_pinmux_set_drive(pingroup, drive);
758 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
759 drive_pinmux_name(pingroup),
760 drive_name(drive), err);
762 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
764 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
765 drive_pinmux_name(pingroup),
768 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
770 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
771 drive_pinmux_name(pingroup),
774 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
776 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
777 drive_pinmux_name(pingroup),
778 slew_name(slew_rising), err);
780 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
782 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
783 drive_pinmux_name(pingroup),
784 slew_name(slew_falling), err);
787 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
792 for (i = 0; i < len; i++)
793 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
799 config[i].slew_rising,
800 config[i].slew_falling);
803 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
807 struct tegra_pingroup_config c;
809 for (i = 0; i < len; i++) {
812 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
816 c.func = pingroups[c.pingroup].func_safe;
817 err = tegra_pinmux_set_func(&c);
819 pr_err("%s: tegra_pinmux_set_func returned %d setting "
820 "%s to %s\n", __func__, err,
821 pingroup_name(c.pingroup), func_name(c.func));
825 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
830 for (i = 0; i < len; i++) {
832 if (config[i].pingroup < 0 ||
833 config[i].pingroup >= pingroup_max) {
837 err = tegra_pinmux_set_func(&config[i]);
839 pr_err("%s: tegra_pinmux_set_func returned %d setting "
840 "%s to %s\n", __func__, err,
841 pingroup_name(config[i].pingroup),
842 func_name(config[i].func));
846 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
847 int len, enum tegra_tristate tristate)
853 for (i = 0; i < len; i++) {
854 pingroup = config[i].pingroup;
855 if (pingroups[pingroup].tri_reg > 0) {
856 err = tegra_pinmux_set_tristate(pingroup, tristate);
858 pr_err("pinmux: can't set pingroup %s tristate"
859 " to %s: %d\n", pingroup_name(pingroup),
860 tri_name(tristate), err);
865 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
866 int len, enum tegra_pullupdown pupd)
872 for (i = 0; i < len; i++) {
873 pingroup = config[i].pingroup;
874 if (pingroups[pingroup].pupd_reg > 0) {
875 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
877 pr_err("pinmux: can't set pingroup %s pullupdown"
878 " to %s: %d\n", pingroup_name(pingroup),
879 pupd_name(pupd), err);
884 static struct of_device_id tegra_pinmux_of_match[] = {
885 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
886 { .compatible = "nvidia,tegra20-pinmux-ctlr", tegra20_pinmux_init },
888 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
889 { .compatible = "nvidia,tegra30-pinmux-ctlr", tegra30_pinmux_init },
891 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
892 { .compatible = "nvidia,tegra11x-pinmux-ctlr", tegra11x_pinmux_init },
897 static int tegra_pinmux_probe(struct platform_device *pdev)
899 struct resource *res;
902 const struct of_device_id *match;
904 match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
907 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
908 &drive_pingroups, &drive_max, &gpio_to_pingroups_map,
909 &gpio_to_pingroups_max);
911 ((pinmux_init)(pdev->id_entry->driver_data))
912 (&pingroups, &pingroup_max,
913 &drive_pingroups, &drive_max,
914 &gpio_to_pingroups_map,
915 &gpio_to_pingroups_max);
918 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
924 for (i = 0; i < pingroup_max; i++) {
925 if (pingroups[i].tri_bank >= nbanks) {
926 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
930 if (pingroups[i].mux_bank >= nbanks) {
931 dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
935 if (pingroups[i].pupd_bank >= nbanks) {
936 dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
941 for (i = 0; i < drive_max; i++) {
942 if (drive_pingroups[i].reg_bank >= nbanks) {
944 "drive pingroup %d: bad reg_bank\n", i);
952 regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
954 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
958 for (i = 0; i < nbanks; i++) {
959 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
961 dev_err(&pdev->dev, "Missing MEM resource\n");
965 if (!devm_request_mem_region(&pdev->dev, res->start,
967 dev_name(&pdev->dev))) {
969 "Couldn't request MEM resource %d\n", i);
973 regs[i] = devm_ioremap(&pdev->dev, res->start,
976 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
984 static struct platform_device_id __devinitdata tegra_pinmux_id[] = {
985 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
986 { .name = "tegra20-pinmux-ctlr",
987 .driver_data = (kernel_ulong_t)tegra20_pinmux_init, },
989 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
990 { .name = "tegra30-pinmux-ctlr",
991 .driver_data = (kernel_ulong_t)tegra30_pinmux_init, },
993 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
994 { .name = "tegra11x-pinmux-ctlr",
995 .driver_data = (kernel_ulong_t)tegra11x_pinmux_init, },
1000 static struct platform_driver tegra_pinmux_driver = {
1002 .name = "tegra-pinmux-ctlr",
1003 .owner = THIS_MODULE,
1004 .of_match_table = tegra_pinmux_of_match,
1006 .id_table = tegra_pinmux_id,
1007 .probe = tegra_pinmux_probe,
1010 static int __init tegra_pinmux_init(void)
1012 return platform_driver_register(&tegra_pinmux_driver);
1014 postcore_initcall(tegra_pinmux_init);
1016 #ifdef CONFIG_DEBUG_FS
1018 #include <linux/debugfs.h>
1019 #include <linux/seq_file.h>
1021 static void dbg_pad_field(struct seq_file *s, int len)
1029 static int dbg_pinmux_show(struct seq_file *s, void *unused)
1034 for (i = 0; i < pingroup_max; i++) {
1040 if (!pingroups[i].name)
1043 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
1044 len = strlen(pingroups[i].name);
1045 dbg_pad_field(s, 15 - len);
1047 if (pingroups[i].mux_reg < 0) {
1048 seq_printf(s, "TEGRA_MUX_NONE");
1049 len = strlen("NONE");
1051 reg = pg_readl(pingroups[i].mux_bank,
1052 pingroups[i].mux_reg);
1053 mux = (reg >> pingroups[i].mux_bit) & 0x3;
1054 BUG_ON(pingroups[i].funcs[mux] == 0);
1055 if (pingroups[i].funcs[mux] == TEGRA_MUX_INVALID) {
1056 seq_printf(s, "TEGRA_MUX_INVALID");
1058 } else if (pingroups[i].funcs[mux] & TEGRA_MUX_RSVD) {
1059 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux);
1062 BUG_ON(!tegra_mux_names[pingroups[i].funcs[mux]]);
1063 seq_printf(s, "TEGRA_MUX_%s",
1064 tegra_mux_names[pingroups[i].funcs[mux]]);
1065 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
1068 dbg_pad_field(s, 13-len);
1070 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
1073 io = (pg_readl(pingroups[i].mux_bank,
1074 pingroups[i].mux_reg) >> 5) & 0x1;
1075 seq_printf(s, "TEGRA_PIN_%s", io_name(io));
1076 len = strlen(io_name(io));
1077 dbg_pad_field(s, 6 - len);
1080 if (pingroups[i].pupd_reg < 0) {
1081 seq_printf(s, "TEGRA_PUPD_NORMAL");
1082 len = strlen("NORMAL");
1084 reg = pg_readl(pingroups[i].pupd_bank,
1085 pingroups[i].pupd_reg);
1086 pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
1087 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
1088 len = strlen(pupd_name(pupd));
1090 dbg_pad_field(s, 9 - len);
1092 if (pingroups[i].tri_reg < 0) {
1093 seq_printf(s, "TEGRA_TRI_NORMAL");
1095 reg = pg_readl(pingroups[i].tri_bank,
1096 pingroups[i].tri_reg);
1097 tri = (reg >> pingroups[i].tri_bit) & 0x1;
1099 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
1101 seq_printf(s, "},\n");
1106 static int dbg_pinmux_open(struct inode *inode, struct file *file)
1108 return single_open(file, dbg_pinmux_show, &inode->i_private);
1111 static const struct file_operations debug_fops = {
1112 .open = dbg_pinmux_open,
1114 .llseek = seq_lseek,
1115 .release = single_release,
1118 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
1124 for (i = 0; i < drive_max; i++) {
1127 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
1128 drive_pingroups[i].name);
1129 len = strlen(drive_pingroups[i].name);
1130 dbg_pad_field(s, 7 - len);
1133 reg = pg_readl(drive_pingroups[i].reg_bank,
1134 drive_pingroups[i].reg);
1136 seq_printf(s, "TEGRA_HSM_ENABLE");
1139 seq_printf(s, "TEGRA_HSM_DISABLE");
1142 dbg_pad_field(s, 17 - len);
1144 if (SCHMT_EN(reg)) {
1145 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
1148 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
1151 dbg_pad_field(s, 22 - len);
1153 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
1154 len = strlen(drive_name(LPMD(reg)));
1155 dbg_pad_field(s, 5 - len);
1157 offset = drive_pingroups[i].drvdown_offset;
1158 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg, offset));
1159 len = DRVDN(reg, offset) < 10 ? 1 : 2;
1160 dbg_pad_field(s, 2 - len);
1162 offset = drive_pingroups[i].drvup_offset;
1163 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg, offset));
1164 len = DRVUP(reg, offset) < 10 ? 1 : 2;
1165 dbg_pad_field(s, 2 - len);
1167 offset = drive_pingroups[i].slewrise_offset;
1168 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg, offset)));
1169 len = strlen(slew_name(SLWR(reg, offset)));
1170 dbg_pad_field(s, 7 - len);
1172 offset= drive_pingroups[i].slewfall_offset;
1173 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg, offset)));
1175 seq_printf(s, "},\n");
1180 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
1182 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
1185 static const struct file_operations debug_drive_fops = {
1186 .open = dbg_drive_pinmux_open,
1188 .llseek = seq_lseek,
1189 .release = single_release,
1192 static int __init tegra_pinmux_debuginit(void)
1194 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
1195 NULL, NULL, &debug_fops);
1196 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
1197 NULL, NULL, &debug_drive_fops);
1200 late_initcall(tegra_pinmux_debuginit);