arch/arm/mach-tegra/pinmux.c

   1 /*
   2  * linux/arch/arm/mach-tegra/pinmux.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (C) 2011 NVIDIA Corporation.
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/errno.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/io.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_device.h>
  26
  27 #include <mach/pinmux.h>
  28
  29 #include "iomap.h"
  30
  31 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
  32 #define TEGRA_PINMUX_HAS_IO_DIRECTION 1
  33 #endif
  34
  35 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
  36 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
  37 #define LPMD(reg)       (((reg) >> 4) & 0x3)
  38 #define DRVDN(reg, offset)      (((reg) >> offset) & 0x1f)
  39 #define DRVUP(reg, offset)      (((reg) >> offset) & 0x1f)
  40 #define SLWR(reg, offset)       (((reg) >> offset) & 0x3)
  41 #define SLWF(reg, offset)       (((reg) >> offset) & 0x3)
  42
  43 static const struct tegra_pingroup_desc *pingroups;
  44 static const struct tegra_drive_pingroup_desc *drive_pingroups;
  45 static const int *gpio_to_pingroups_map;
  46 static int pingroup_max;
  47 static int drive_max;
  48 static int gpio_to_pingroups_max;
  49
  50 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
  51 #define TEGRA_MUX(mux) [TEGRA_MUX_##mux] = #mux,
  52         TEGRA_MUX_LIST
  53 #undef  TEGRA_MUX
  54         [TEGRA_MUX_SAFE] = "<safe>",
  55 };
  56
  57 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
  58         [TEGRA_DRIVE_DIV_8] = "DIV_8",
  59         [TEGRA_DRIVE_DIV_4] = "DIV_4",
  60         [TEGRA_DRIVE_DIV_2] = "DIV_2",
  61         [TEGRA_DRIVE_DIV_1] = "DIV_1",
  62 };
  63
  64 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
  65         [TEGRA_SLEW_FASTEST] = "FASTEST",
  66         [TEGRA_SLEW_FAST] = "FAST",
  67         [TEGRA_SLEW_SLOW] = "SLOW",
  68         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
  69 };
  70
  71 static DEFINE_SPINLOCK(mux_lock);
  72
  73 static const char *pingroup_name(int pg)
  74 {
  75         if (pg < 0 || pg >=  pingroup_max)
  76                 return "<UNKNOWN>";
  77
  78         return pingroups[pg].name;
  79 }
  80
  81 static const char *func_name(enum tegra_mux_func func)
  82 {
  83         if (func == TEGRA_MUX_RSVD1)
  84                 return "RSVD1";
  85
  86         if (func == TEGRA_MUX_RSVD2)
  87                 return "RSVD2";
  88
  89         if (func == TEGRA_MUX_RSVD3)
  90                 return "RSVD3";
  91
  92         if (func == TEGRA_MUX_RSVD4)
  93                 return "RSVD4";
  94
  95         if (func == TEGRA_MUX_INVALID)
  96                 return "INVALID";
  97
  98         if (func < 0 || func >=  TEGRA_MAX_MUX)
  99                 return "<UNKNOWN>";
 100
 101         return tegra_mux_names[func];
 102 }
 103
 104
 105 static const char *tri_name(unsigned long val)
 106 {
 107         return val ? "TRISTATE" : "NORMAL";
 108 }
 109
 110 static const char *pupd_name(unsigned long val)
 111 {
 112         switch (val) {
 113         case 0:
 114                 return "NORMAL";
 115
 116         case 1:
 117                 return "PULL_DOWN";
 118
 119         case 2:
 120                 return "PULL_UP";
 121
 122         default:
 123                 return "RSVD";
 124         }
 125 }
 126
 127 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
 128 static const char *lock_name(unsigned long val)
 129 {
 130         switch (val) {
 131         case TEGRA_PIN_LOCK_DEFAULT:
 132                 return "LOCK_DEFUALT";
 133
 134         case TEGRA_PIN_LOCK_DISABLE:
 135                 return "LOCK_DISABLE";
 136
 137         case TEGRA_PIN_LOCK_ENABLE:
 138                 return "LOCK_ENABLE";
 139         default:
 140                 return "LOCK_DEFAULT";
 141         }
 142 }
 143
 144 static const char *od_name(unsigned long val)
 145 {
 146         switch (val) {
 147         case TEGRA_PIN_OD_DEFAULT:
 148                 return "OD_DEFAULT";
 149
 150         case TEGRA_PIN_OD_DISABLE:
 151                 return "OD_DISABLE";
 152
 153         case TEGRA_PIN_OD_ENABLE:
 154                 return "OD_ENABLE";
 155         default:
 156                 return "OD_DEFAULT";
 157         }
 158 }
 159
 160 static const char *ioreset_name(unsigned long val)
 161 {
 162         switch (val) {
 163         case TEGRA_PIN_IO_RESET_DEFAULT:
 164                 return "IO_RESET_DEFAULT";
 165
 166         case TEGRA_PIN_IO_RESET_DISABLE:
 167                 return "IO_RESET_DISABLE";
 168
 169         case TEGRA_PIN_IO_RESET_ENABLE:
 170                 return "IO_RESET_ENABLE";
 171         default:
 172                 return "IO_RESET_DEFAULT";
 173         }
 174 }
 175 #endif
 176
 177 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
 178 static const char *io_name(unsigned long val)
 179 {
 180         switch (val) {
 181         case 0:
 182                 return "OUTPUT";
 183
 184         case 1:
 185                 return "INPUT";
 186
 187         default:
 188                 return "RSVD";
 189         }
 190 }
 191 #endif
 192
 193 static int nbanks;
 194 static void __iomem **regs;
 195
 196 u32 pg_readl(u32 bank, u32 reg)
 197 {
 198         return readl(regs[bank] + reg);
 199 }
 200
 201 void pg_writel(u32 val, u32 bank, u32 reg)
 202 {
 203         writel(val, regs[bank] + reg);
 204 }
 205
 206 int tegra_pinmux_get_pingroup(int gpio_nr)
 207 {
 208         return gpio_to_pingroups_map[gpio_nr];
 209 }
 210 EXPORT_SYMBOL_GPL(tegra_pinmux_get_pingroup);
 211
 212 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
 213 {
 214         int mux = -1;
 215         int i;
 216         int find = 0;
 217         unsigned long reg;
 218         unsigned long flags;
 219         int pg = config->pingroup;
 220         enum tegra_mux_func func = config->func;
 221
 222         if (pg < 0 || pg >=  pingroup_max)
 223                 return -ERANGE;
 224
 225         if (pingroups[pg].mux_reg < 0)
 226                 return -EINVAL;
 227
 228         if (func == TEGRA_MUX_INVALID) {
 229                 pr_err("The pingroup %s is not recommended for option %s\n",
 230                                 pingroup_name(pg), func_name(func));
 231                 WARN_ON(1);
 232                 return -EINVAL;
 233         }
 234
 235         if (func < 0)
 236                 return -ERANGE;
 237
 238         if (func == TEGRA_MUX_SAFE)
 239                 func = pingroups[pg].func_safe;
 240
 241         if (func & TEGRA_MUX_RSVD) {
 242                 for (i = 0; i < 4; i++) {
 243                         if (pingroups[pg].funcs[i] & TEGRA_MUX_RSVD)
 244                                 mux = i;
 245
 246                         if (pingroups[pg].funcs[i] == func) {
 247                                 mux = i;
 248                                 find = 1;
 249                                 break;
 250                         }
 251                 }
 252         } else {
 253                 for (i = 0; i < 4; i++) {
 254                         if (pingroups[pg].funcs[i] == func) {
 255                                 mux = i;
 256                                 find = 1;
 257                                 break;
 258                         }
 259                 }
 260         }
 261
 262         if (mux < 0) {
 263                 pr_err("The pingroup %s is not supported option %s\n",
 264                         pingroup_name(pg), func_name(func));
 265                 WARN_ON(1);
 266                 return -EINVAL;
 267         }
 268
 269         if (!find)
 270                 pr_warn("The pingroup %s was configured to %s instead of %s\n",
 271                         pingroup_name(pg), func_name(pingroups[pg].funcs[mux]),
 272                         func_name(func));
 273
 274         spin_lock_irqsave(&mux_lock, flags);
 275
 276         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 277         reg &= ~(0x3 << pingroups[pg].mux_bit);
 278         reg |= mux << pingroups[pg].mux_bit;
 279 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
 280         reg &= ~(0x1 << 5);
 281         reg |= ((config->io & 0x1) << 5);
 282 #endif
 283         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 284
 285         spin_unlock_irqrestore(&mux_lock, flags);
 286
 287         return 0;
 288 }
 289
 290 int tegra_pinmux_get_func(int pg)
 291 {
 292         int mux = -1;
 293         unsigned long reg;
 294         unsigned long flags;
 295
 296         if (pg < 0 || pg >=  pingroup_max)
 297                 return -ERANGE;
 298
 299         if (pingroups[pg].mux_reg < 0)
 300                 return -EINVAL;
 301
 302         spin_lock_irqsave(&mux_lock, flags);
 303
 304         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 305         mux = (reg >> pingroups[pg].mux_bit) & 0x3;
 306
 307         spin_unlock_irqrestore(&mux_lock, flags);
 308
 309         return mux;
 310 }
 311
 312 int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
 313 {
 314         unsigned long reg;
 315         unsigned long flags;
 316
 317         if (pg < 0 || pg >=  pingroup_max)
 318                 return -ERANGE;
 319
 320         if (pingroups[pg].tri_reg < 0)
 321                 return -EINVAL;
 322
 323         spin_lock_irqsave(&mux_lock, flags);
 324
 325         reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
 326         reg &= ~(0x1 << pingroups[pg].tri_bit);
 327         if (tristate)
 328                 reg |= 1 << pingroups[pg].tri_bit;
 329         pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
 330
 331         spin_unlock_irqrestore(&mux_lock, flags);
 332
 333         return 0;
 334 }
 335
 336 int tegra_pinmux_set_io(int pg, enum tegra_pin_io input)
 337 {
 338 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
 339         unsigned long io;
 340
 341         if (pg < 0 || pg >=  pingroup_max)
 342                 return -ERANGE;
 343
 344         io = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 345         if (input)
 346                 io |= 0x20;
 347         else
 348                 io &= ~(1 << 5);
 349         pg_writel(io, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 350 #endif
 351         return 0;
 352 }
 353 EXPORT_SYMBOL_GPL(tegra_pinmux_set_io);
 354
 355 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
 356 static int tegra_pinmux_set_lock(int pg, enum tegra_pin_lock lock)
 357 {
 358         unsigned long reg;
 359         unsigned long flags;
 360
 361         if (pg < 0 || pg >=  pingroup_max)
 362                 return -ERANGE;
 363
 364         if (pingroups[pg].mux_reg < 0)
 365                 return -EINVAL;
 366
 367         if ((lock == TEGRA_PIN_LOCK_DEFAULT) || (pingroups[pg].lock_bit < 0))
 368                 return 0;
 369
 370         spin_lock_irqsave(&mux_lock, flags);
 371
 372         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 373         reg &= ~(0x1 << pingroups[pg].lock_bit);
 374         if (lock == TEGRA_PIN_LOCK_ENABLE)
 375                 reg |= (0x1 << pingroups[pg].lock_bit);
 376
 377         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 378
 379         spin_unlock_irqrestore(&mux_lock, flags);
 380         return 0;
 381 }
 382
 383 static int tegra_pinmux_set_od(int pg, enum tegra_pin_od od)
 384 {
 385         unsigned long reg;
 386         unsigned long flags;
 387
 388         if (pg < 0 || pg >=  pingroup_max)
 389                 return -ERANGE;
 390
 391         if (pingroups[pg].mux_reg < 0)
 392                 return -EINVAL;
 393
 394         if ((od == TEGRA_PIN_OD_DEFAULT) || (pingroups[pg].od_bit < 0))
 395                 return 0;
 396
 397         spin_lock_irqsave(&mux_lock, flags);
 398
 399         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 400         reg &= ~(0x1 << pingroups[pg].od_bit);
 401         if (od == TEGRA_PIN_OD_ENABLE)
 402                 reg |= 1 << pingroups[pg].od_bit;
 403
 404         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 405
 406         spin_unlock_irqrestore(&mux_lock, flags);
 407
 408         return 0;
 409 }
 410
 411 static int tegra_pinmux_set_ioreset(int pg, enum tegra_pin_ioreset ioreset)
 412 {
 413         unsigned long reg;
 414         unsigned long flags;
 415
 416         if (pg < 0 || pg >=  pingroup_max)
 417                 return -ERANGE;
 418
 419         if (pingroups[pg].mux_reg < 0)
 420                 return -EINVAL;
 421
 422         if ((ioreset == TEGRA_PIN_IO_RESET_DEFAULT) || (pingroups[pg].ioreset_bit < 0))
 423                 return 0;
 424
 425         spin_lock_irqsave(&mux_lock, flags);
 426
 427         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 428         reg &= ~(0x1 << pingroups[pg].ioreset_bit);
 429         if (ioreset == TEGRA_PIN_IO_RESET_ENABLE)
 430                 reg |= 1 << pingroups[pg].ioreset_bit;
 431
 432         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
 433
 434         spin_unlock_irqrestore(&mux_lock, flags);
 435
 436         return 0;
 437 }
 438 #endif
 439
 440 int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
 441 {
 442         unsigned long reg;
 443         unsigned long flags;
 444
 445         if (pg < 0 || pg >=  pingroup_max)
 446                 return -ERANGE;
 447
 448         if (pingroups[pg].pupd_reg < 0)
 449                 return -EINVAL;
 450
 451         if (pupd != TEGRA_PUPD_NORMAL &&
 452             pupd != TEGRA_PUPD_PULL_DOWN &&
 453             pupd != TEGRA_PUPD_PULL_UP)
 454                 return -EINVAL;
 455
 456
 457         spin_lock_irqsave(&mux_lock, flags);
 458
 459         reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
 460         reg &= ~(0x3 << pingroups[pg].pupd_bit);
 461         reg |= pupd << pingroups[pg].pupd_bit;
 462         pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
 463
 464         spin_unlock_irqrestore(&mux_lock, flags);
 465
 466         return 0;
 467 }
 468
 469 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
 470 {
 471         int pingroup = config->pingroup;
 472         enum tegra_mux_func func     = config->func;
 473         enum tegra_pullupdown pupd   = config->pupd;
 474         enum tegra_tristate tristate = config->tristate;
 475 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
 476         enum tegra_pin_lock lock     = config->lock;
 477         enum tegra_pin_od od         = config->od;
 478         enum tegra_pin_ioreset ioreset = config->ioreset;
 479 #endif
 480         int err;
 481
 482         if (pingroups[pingroup].mux_reg >= 0) {
 483                 err = tegra_pinmux_set_func(config);
 484                 if (err < 0)
 485                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
 486                                pingroup_name(pingroup), func_name(func), err);
 487         }
 488
 489         if (pingroups[pingroup].pupd_reg >= 0) {
 490                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
 491                 if (err < 0)
 492                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
 493                                pingroup_name(pingroup), pupd_name(pupd), err);
 494         }
 495
 496         if (pingroups[pingroup].tri_reg >= 0) {
 497                 err = tegra_pinmux_set_tristate(pingroup, tristate);
 498                 if (err < 0)
 499                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
 500                                pingroup_name(pingroup), tri_name(func), err);
 501         }
 502
 503 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
 504         if (pingroups[pingroup].mux_reg >= 0) {
 505                 err = tegra_pinmux_set_lock(pingroup, lock);
 506                 if (err < 0)
 507                         pr_err("pinmux: can't set pingroup %s lock to %s: %d\n",
 508                                pingroup_name(pingroup), lock_name(func), err);
 509         }
 510
 511         if (pingroups[pingroup].mux_reg >= 0) {
 512                 err = tegra_pinmux_set_od(pingroup, od);
 513                 if (err < 0)
 514                         pr_err("pinmux: can't set pingroup %s od to %s: %d\n",
 515                                pingroup_name(pingroup), od_name(func), err);
 516         }
 517
 518         if (pingroups[pingroup].mux_reg >= 0) {
 519                 err = tegra_pinmux_set_ioreset(pingroup, ioreset);
 520                 if (err < 0)
 521                         pr_err("pinmux: can't set pingroup %s ioreset to %s: %d\n",
 522                                pingroup_name(pingroup), ioreset_name(func), err);
 523         }
 524 #endif
 525 }
 526
 527 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
 528 {
 529         int i;
 530
 531         for (i = 0; i < len; i++)
 532                 tegra_pinmux_config_pingroup(&config[i]);
 533 }
 534 EXPORT_SYMBOL(tegra_pinmux_config_table);
 535
 536 static const char *drive_pinmux_name(int pg)
 537 {
 538         if (pg < 0 || pg >=  drive_max)
 539                 return "<UNKNOWN>";
 540
 541         return drive_pingroups[pg].name;
 542 }
 543
 544 static const char *enable_name(unsigned long val)
 545 {
 546         return val ? "ENABLE" : "DISABLE";
 547 }
 548
 549 static const char *drive_name(unsigned long val)
 550 {
 551         if (val >= TEGRA_MAX_DRIVE)
 552                 return "<UNKNOWN>";
 553
 554         return tegra_drive_names[val];
 555 }
 556
 557 static const char *slew_name(unsigned long val)
 558 {
 559         if (val >= TEGRA_MAX_SLEW)
 560                 return "<UNKNOWN>";
 561
 562         return tegra_slew_names[val];
 563 }
 564
 565 static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
 566 {
 567         unsigned long flags;
 568         u32 reg;
 569         if (pg < 0 || pg >=  drive_max)
 570                 return -ERANGE;
 571
 572         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
 573                 return -EINVAL;
 574
 575         spin_lock_irqsave(&mux_lock, flags);
 576
 577         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 578         if (hsm == TEGRA_HSM_ENABLE)
 579                 reg |= (1 << 2);
 580         else
 581                 reg &= ~(1 << 2);
 582         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 583
 584         spin_unlock_irqrestore(&mux_lock, flags);
 585
 586         return 0;
 587 }
 588
 589 static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
 590 {
 591         unsigned long flags;
 592         u32 reg;
 593         if (pg < 0 || pg >=  drive_max)
 594                 return -ERANGE;
 595
 596         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
 597                 return -EINVAL;
 598
 599         spin_lock_irqsave(&mux_lock, flags);
 600
 601         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 602         if (schmitt == TEGRA_SCHMITT_ENABLE)
 603                 reg |= (1 << 3);
 604         else
 605                 reg &= ~(1 << 3);
 606         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 607
 608         spin_unlock_irqrestore(&mux_lock, flags);
 609
 610         return 0;
 611 }
 612
 613 static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
 614 {
 615         unsigned long flags;
 616         u32 reg;
 617         if (pg < 0 || pg >=  drive_max)
 618                 return -ERANGE;
 619
 620         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
 621                 return -EINVAL;
 622
 623         spin_lock_irqsave(&mux_lock, flags);
 624
 625         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 626         reg &= ~(0x3 << 4);
 627         reg |= drive << 4;
 628         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 629
 630         spin_unlock_irqrestore(&mux_lock, flags);
 631
 632         return 0;
 633 }
 634
 635 static int tegra_drive_pinmux_set_pull_down(int pg,
 636         enum tegra_pull_strength pull_down)
 637 {
 638         unsigned long flags;
 639         u32 reg;
 640
 641         if (pg < 0 || pg >= drive_max)
 642                 return -ERANGE;
 643
 644         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
 645                 return -EINVAL;
 646
 647         spin_lock_irqsave(&mux_lock, flags);
 648
 649         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 650         reg &= ~(drive_pingroups[pg].drvdown_mask <<
 651                 drive_pingroups[pg].drvdown_offset);
 652         reg |= pull_down << drive_pingroups[pg].drvdown_offset;
 653         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 654
 655         spin_unlock_irqrestore(&mux_lock, flags);
 656
 657         return 0;
 658 }
 659
 660 static int tegra_drive_pinmux_set_pull_up(int pg,
 661         enum tegra_pull_strength pull_up)
 662 {
 663         unsigned long flags;
 664         u32 reg;
 665
 666         if (pg < 0 || pg >=  drive_max)
 667                 return -ERANGE;
 668
 669         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
 670                 return -EINVAL;
 671
 672         spin_lock_irqsave(&mux_lock, flags);
 673
 674         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 675         reg &= ~(drive_pingroups[pg].drvup_mask <<
 676                 drive_pingroups[pg].drvup_offset);
 677         reg |= pull_up << drive_pingroups[pg].drvup_offset;
 678         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 679
 680         spin_unlock_irqrestore(&mux_lock, flags);
 681
 682         return 0;
 683 }
 684
 685 static int tegra_drive_pinmux_set_slew_rising(int pg,
 686         enum tegra_slew slew_rising)
 687 {
 688         unsigned long flags;
 689         u32 reg;
 690         if (pg < 0 || pg >=  drive_max)
 691                 return -ERANGE;
 692
 693         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
 694                 return -EINVAL;
 695
 696         spin_lock_irqsave(&mux_lock, flags);
 697
 698         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 699         reg &= ~(drive_pingroups[pg].slewrise_mask <<
 700                 drive_pingroups[pg].slewrise_offset);
 701         reg |= slew_rising << drive_pingroups[pg].slewrise_offset;
 702         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 703
 704         spin_unlock_irqrestore(&mux_lock, flags);
 705
 706         return 0;
 707 }
 708
 709 static int tegra_drive_pinmux_set_slew_falling(int pg,
 710         enum tegra_slew slew_falling)
 711 {
 712         unsigned long flags;
 713         u32 reg;
 714         if (pg < 0 || pg >=  drive_max)
 715                 return -ERANGE;
 716
 717         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
 718                 return -EINVAL;
 719
 720         spin_lock_irqsave(&mux_lock, flags);
 721
 722         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 723         reg &= ~(drive_pingroups[pg].slewfall_mask <<
 724                 drive_pingroups[pg].slewfall_offset);
 725         reg |= slew_falling << drive_pingroups[pg].slewfall_offset;
 726         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
 727
 728         spin_unlock_irqrestore(&mux_lock, flags);
 729
 730         return 0;
 731 }
 732
 733 static void tegra_drive_pinmux_config_pingroup(int pingroup,
 734                                           enum tegra_hsm hsm,
 735                                           enum tegra_schmitt schmitt,
 736                                           enum tegra_drive drive,
 737                                           enum tegra_pull_strength pull_down,
 738                                           enum tegra_pull_strength pull_up,
 739                                           enum tegra_slew slew_rising,
 740                                           enum tegra_slew slew_falling)
 741 {
 742         int err;
 743
 744         err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
 745         if (err < 0)
 746                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
 747                         drive_pinmux_name(pingroup),
 748                         enable_name(hsm), err);
 749
 750         err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
 751         if (err < 0)
 752                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
 753                         drive_pinmux_name(pingroup),
 754                         enable_name(schmitt), err);
 755
 756         err = tegra_drive_pinmux_set_drive(pingroup, drive);
 757         if (err < 0)
 758                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
 759                         drive_pinmux_name(pingroup),
 760                         drive_name(drive), err);
 761
 762         err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
 763         if (err < 0)
 764                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
 765                         drive_pinmux_name(pingroup),
 766                         pull_down, err);
 767
 768         err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
 769         if (err < 0)
 770                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
 771                         drive_pinmux_name(pingroup),
 772                         pull_up, err);
 773
 774         err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
 775         if (err < 0)
 776                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
 777                         drive_pinmux_name(pingroup),
 778                         slew_name(slew_rising), err);
 779
 780         err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
 781         if (err < 0)
 782                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
 783                         drive_pinmux_name(pingroup),
 784                         slew_name(slew_falling), err);
 785 }
 786
 787 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
 788         int len)
 789 {
 790         int i;
 791
 792         for (i = 0; i < len; i++)
 793                 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
 794                                                      config[i].hsm,
 795                                                      config[i].schmitt,
 796                                                      config[i].drive,
 797                                                      config[i].pull_down,
 798                                                      config[i].pull_up,
 799                                                      config[i].slew_rising,
 800                                                      config[i].slew_falling);
 801 }
 802
 803 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
 804         int len)
 805 {
 806         int i;
 807         struct tegra_pingroup_config c;
 808
 809         for (i = 0; i < len; i++) {
 810                 int err;
 811                 c = config[i];
 812                 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
 813                         WARN_ON(1);
 814                         continue;
 815                 }
 816                 c.func = pingroups[c.pingroup].func_safe;
 817                 err = tegra_pinmux_set_func(&c);
 818                 if (err < 0)
 819                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
 820                                "%s to %s\n", __func__, err,
 821                                pingroup_name(c.pingroup), func_name(c.func));
 822         }
 823 }
 824
 825 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
 826         int len)
 827 {
 828         int i;
 829
 830         for (i = 0; i < len; i++) {
 831                 int err;
 832                 if (config[i].pingroup < 0 ||
 833                     config[i].pingroup >= pingroup_max) {
 834                         WARN_ON(1);
 835                         continue;
 836                 }
 837                 err = tegra_pinmux_set_func(&config[i]);
 838                 if (err < 0)
 839                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
 840                                "%s to %s\n", __func__, err,
 841                                pingroup_name(config[i].pingroup),
 842                                func_name(config[i].func));
 843         }
 844 }
 845
 846 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
 847         int len, enum tegra_tristate tristate)
 848 {
 849         int i;
 850         int err;
 851         int pingroup;
 852
 853         for (i = 0; i < len; i++) {
 854                 pingroup = config[i].pingroup;
 855                 if (pingroups[pingroup].tri_reg > 0) {
 856                         err = tegra_pinmux_set_tristate(pingroup, tristate);
 857                         if (err < 0)
 858                                 pr_err("pinmux: can't set pingroup %s tristate"
 859                                         " to %s: %d\n", pingroup_name(pingroup),
 860                                         tri_name(tristate), err);
 861                 }
 862         }
 863 }
 864
 865 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
 866         int len, enum tegra_pullupdown pupd)
 867 {
 868         int i;
 869         int err;
 870         int pingroup;
 871
 872         for (i = 0; i < len; i++) {
 873                 pingroup = config[i].pingroup;
 874                 if (pingroups[pingroup].pupd_reg > 0) {
 875                         err = tegra_pinmux_set_pullupdown(pingroup, pupd);
 876                         if (err < 0)
 877                                 pr_err("pinmux: can't set pingroup %s pullupdown"
 878                                         " to %s: %d\n", pingroup_name(pingroup),
 879                                         pupd_name(pupd), err);
 880                 }
 881         }
 882 }
 883
 884 static struct of_device_id tegra_pinmux_of_match[] = {
 885 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 886         { .compatible = "nvidia,tegra20-pinmux-ctlr", tegra20_pinmux_init },
 887 #endif
 888 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 889         { .compatible = "nvidia,tegra30-pinmux-ctlr", tegra30_pinmux_init },
 890 #endif
 891 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
 892         { .compatible = "nvidia,tegra11x-pinmux-ctlr", tegra11x_pinmux_init },
 893 #endif
 894         { },
 895 };
 896
 897 static int tegra_pinmux_probe(struct platform_device *pdev)
 898 {
 899         struct resource *res;
 900         int i;
 901         int config_bad = 0;
 902         const struct of_device_id *match;
 903
 904         match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
 905
 906         if (match)
 907                 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
 908                         &drive_pingroups, &drive_max, &gpio_to_pingroups_map,
 909                         &gpio_to_pingroups_max);
 910         else
 911                 ((pinmux_init)(pdev->id_entry->driver_data))
 912                                         (&pingroups, &pingroup_max,
 913                                         &drive_pingroups, &drive_max,
 914                                         &gpio_to_pingroups_map,
 915                                         &gpio_to_pingroups_max);
 916
 917         for (i = 0; ; i++) {
 918                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 919                 if (!res)
 920                         break;
 921         }
 922         nbanks = i;
 923
 924         for (i = 0; i < pingroup_max; i++) {
 925                 if (pingroups[i].tri_bank >= nbanks) {
 926                         dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
 927                         config_bad = 1;
 928                 }
 929
 930                 if (pingroups[i].mux_bank >= nbanks) {
 931                         dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
 932                         config_bad = 1;
 933                 }
 934
 935                 if (pingroups[i].pupd_bank >= nbanks) {
 936                         dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
 937                         config_bad = 1;
 938                 }
 939         }
 940
 941         for (i = 0; i < drive_max; i++) {
 942                 if (drive_pingroups[i].reg_bank >= nbanks) {
 943                         dev_err(&pdev->dev,
 944                                 "drive pingroup %d: bad reg_bank\n", i);
 945                         config_bad = 1;
 946                 }
 947         }
 948
 949         if (config_bad)
 950                 return -ENODEV;
 951
 952         regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
 953         if (!regs) {
 954                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
 955                 return -ENODEV;
 956         }
 957
 958         for (i = 0; i < nbanks; i++) {
 959                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 960                 if (!res) {
 961                         dev_err(&pdev->dev, "Missing MEM resource\n");
 962                         return -ENODEV;
 963                 }
 964
 965                 if (!devm_request_mem_region(&pdev->dev, res->start,
 966                                             resource_size(res),
 967                                             dev_name(&pdev->dev))) {
 968                         dev_err(&pdev->dev,
 969                                 "Couldn't request MEM resource %d\n", i);
 970                         return -ENODEV;
 971                 }
 972
 973                 regs[i] = devm_ioremap(&pdev->dev, res->start,
 974                                         resource_size(res));
 975                 if (!regs) {
 976                         dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
 977                         return -ENODEV;
 978                 }
 979         }
 980
 981         return 0;
 982 }
 983
 984 static struct platform_device_id __devinitdata tegra_pinmux_id[] = {
 985 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 986         { .name = "tegra20-pinmux-ctlr",
 987           .driver_data = (kernel_ulong_t)tegra20_pinmux_init, },
 988 #endif
 989 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 990         { .name = "tegra30-pinmux-ctlr",
 991           .driver_data = (kernel_ulong_t)tegra30_pinmux_init, },
 992 #endif
 993 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
 994         { .name = "tegra11x-pinmux-ctlr",
 995           .driver_data = (kernel_ulong_t)tegra11x_pinmux_init, },
 996 #endif
 997         {},
 998 };
 999
1000 static struct platform_driver tegra_pinmux_driver = {
1001         .driver         = {
1002                 .name   = "tegra-pinmux-ctlr",
1003                 .owner  = THIS_MODULE,
1004                 .of_match_table = tegra_pinmux_of_match,
1005         },
1006         .id_table       = tegra_pinmux_id,
1007         .probe          = tegra_pinmux_probe,
1008 };
1009
1010 static int __init tegra_pinmux_init(void)
1011 {
1012         return platform_driver_register(&tegra_pinmux_driver);
1013 }
1014 postcore_initcall(tegra_pinmux_init);
1015
1016 #ifdef  CONFIG_DEBUG_FS
1017
1018 #include <linux/debugfs.h>
1019 #include <linux/seq_file.h>
1020
1021 static void dbg_pad_field(struct seq_file *s, int len)
1022 {
1023         seq_putc(s, ',');
1024
1025         while (len-- > -1)
1026                 seq_putc(s, ' ');
1027 }
1028
1029 static int dbg_pinmux_show(struct seq_file *s, void *unused)
1030 {
1031         int i;
1032         int len;
1033
1034         for (i = 0; i < pingroup_max; i++) {
1035                 unsigned long reg;
1036                 unsigned long tri;
1037                 unsigned long mux;
1038                 unsigned long pupd;
1039
1040                 if (!pingroups[i].name)
1041                         continue;
1042
1043                 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
1044                 len = strlen(pingroups[i].name);
1045                 dbg_pad_field(s, 15 - len);
1046
1047                 if (pingroups[i].mux_reg < 0) {
1048                         seq_printf(s, "TEGRA_MUX_NONE");
1049                         len = strlen("NONE");
1050                 } else {
1051                         reg = pg_readl(pingroups[i].mux_bank,
1052                                         pingroups[i].mux_reg);
1053                         mux = (reg >> pingroups[i].mux_bit) & 0x3;
1054                         BUG_ON(pingroups[i].funcs[mux] == 0);
1055                         if (pingroups[i].funcs[mux] ==  TEGRA_MUX_INVALID) {
1056                                 seq_printf(s, "TEGRA_MUX_INVALID");
1057                                 len = 7;
1058                         } else if (pingroups[i].funcs[mux] & TEGRA_MUX_RSVD) {
1059                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux);
1060                                 len = 5;
1061                         } else {
1062                                 BUG_ON(!tegra_mux_names[pingroups[i].funcs[mux]]);
1063                                 seq_printf(s, "TEGRA_MUX_%s",
1064                                            tegra_mux_names[pingroups[i].funcs[mux]]);
1065                                 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
1066                         }
1067                 }
1068                 dbg_pad_field(s, 13-len);
1069
1070 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
1071                 {
1072                         unsigned long io;
1073                         io = (pg_readl(pingroups[i].mux_bank,
1074                                         pingroups[i].mux_reg) >> 5) & 0x1;
1075                         seq_printf(s, "TEGRA_PIN_%s", io_name(io));
1076                         len = strlen(io_name(io));
1077                         dbg_pad_field(s, 6 - len);
1078                 }
1079 #endif
1080                 if (pingroups[i].pupd_reg < 0) {
1081                         seq_printf(s, "TEGRA_PUPD_NORMAL");
1082                         len = strlen("NORMAL");
1083                 } else {
1084                         reg = pg_readl(pingroups[i].pupd_bank,
1085                                         pingroups[i].pupd_reg);
1086                         pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
1087                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
1088                         len = strlen(pupd_name(pupd));
1089                 }
1090                 dbg_pad_field(s, 9 - len);
1091
1092                 if (pingroups[i].tri_reg < 0) {
1093                         seq_printf(s, "TEGRA_TRI_NORMAL");
1094                 } else {
1095                         reg = pg_readl(pingroups[i].tri_bank,
1096                                         pingroups[i].tri_reg);
1097                         tri = (reg >> pingroups[i].tri_bit) & 0x1;
1098
1099                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
1100                 }
1101                 seq_printf(s, "},\n");
1102         }
1103         return 0;
1104 }
1105
1106 static int dbg_pinmux_open(struct inode *inode, struct file *file)
1107 {
1108         return single_open(file, dbg_pinmux_show, &inode->i_private);
1109 }
1110
1111 static const struct file_operations debug_fops = {
1112         .open           = dbg_pinmux_open,
1113         .read           = seq_read,
1114         .llseek         = seq_lseek,
1115         .release        = single_release,
1116 };
1117
1118 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
1119 {
1120         int i;
1121         int len;
1122         u8 offset;
1123
1124         for (i = 0; i < drive_max; i++) {
1125                 u32 reg;
1126
1127                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
1128                         drive_pingroups[i].name);
1129                 len = strlen(drive_pingroups[i].name);
1130                 dbg_pad_field(s, 7 - len);
1131
1132
1133                 reg = pg_readl(drive_pingroups[i].reg_bank,
1134                                 drive_pingroups[i].reg);
1135                 if (HSM_EN(reg)) {
1136                         seq_printf(s, "TEGRA_HSM_ENABLE");
1137                         len = 16;
1138                 } else {
1139                         seq_printf(s, "TEGRA_HSM_DISABLE");
1140                         len = 17;
1141                 }
1142                 dbg_pad_field(s, 17 - len);
1143
1144                 if (SCHMT_EN(reg)) {
1145                         seq_printf(s, "TEGRA_SCHMITT_ENABLE");
1146                         len = 21;
1147                 } else {
1148                         seq_printf(s, "TEGRA_SCHMITT_DISABLE");
1149                         len = 22;
1150                 }
1151                 dbg_pad_field(s, 22 - len);
1152
1153                 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
1154                 len = strlen(drive_name(LPMD(reg)));
1155                 dbg_pad_field(s, 5 - len);
1156
1157                 offset = drive_pingroups[i].drvdown_offset;
1158                 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg, offset));
1159                 len = DRVDN(reg, offset) < 10 ? 1 : 2;
1160                 dbg_pad_field(s, 2 - len);
1161
1162                 offset = drive_pingroups[i].drvup_offset;
1163                 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg, offset));
1164                 len = DRVUP(reg, offset) < 10 ? 1 : 2;
1165                 dbg_pad_field(s, 2 - len);
1166
1167                 offset = drive_pingroups[i].slewrise_offset;
1168                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg, offset)));
1169                 len = strlen(slew_name(SLWR(reg, offset)));
1170                 dbg_pad_field(s, 7 - len);
1171
1172                 offset= drive_pingroups[i].slewfall_offset;
1173                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg, offset)));
1174
1175                 seq_printf(s, "},\n");
1176         }
1177         return 0;
1178 }
1179
1180 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
1181 {
1182         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
1183 }
1184
1185 static const struct file_operations debug_drive_fops = {
1186         .open           = dbg_drive_pinmux_open,
1187         .read           = seq_read,
1188         .llseek         = seq_lseek,
1189         .release        = single_release,
1190 };
1191
1192 static int __init tegra_pinmux_debuginit(void)
1193 {
1194         (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
1195                                         NULL, NULL, &debug_fops);
1196         (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
1197                                         NULL, NULL, &debug_drive_fops);
1198         return 0;
1199 }
1200 late_initcall(tegra_pinmux_debuginit);
1201 #endif