ARM: Build fix after Tegra14 K3.4 merge
[linux-3.10.git] / arch / arm / mach-tegra / pinmux.c
1 /*
2  * linux/arch/arm/mach-tegra/pinmux.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2011-2012 NVIDIA Corporation. All rights reserved.
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/spinlock.h>
23 #include <linux/io.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_device.h>
26
27 #include <mach/pinmux.h>
28
29 #include "iomap.h"
30
31 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
32 #define TEGRA_PINMUX_HAS_IO_DIRECTION 1
33 #endif
34
35 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
36 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
37 #define LPMD(reg)       (((reg) >> 4) & 0x3)
38 #define DRVDN(reg, offset)      (((reg) >> offset) & 0x1f)
39 #define DRVUP(reg, offset)      (((reg) >> offset) & 0x1f)
40 #define SLWR(reg, offset)       (((reg) >> offset) & 0x3)
41 #define SLWF(reg, offset)       (((reg) >> offset) & 0x3)
42
43 static const struct tegra_pingroup_desc *pingroups;
44 static const struct tegra_drive_pingroup_desc *drive_pingroups;
45 static const int *gpio_to_pingroups_map;
46 static int pingroup_max;
47 static int drive_max;
48 static int gpio_to_pingroups_max;
49
50 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
51 #define TEGRA_MUX(mux) [TEGRA_MUX_##mux] = #mux,
52         TEGRA_MUX_LIST
53 #undef  TEGRA_MUX
54         [TEGRA_MUX_SAFE] = "<safe>",
55 };
56
57 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
58         [TEGRA_DRIVE_DIV_8] = "DIV_8",
59         [TEGRA_DRIVE_DIV_4] = "DIV_4",
60         [TEGRA_DRIVE_DIV_2] = "DIV_2",
61         [TEGRA_DRIVE_DIV_1] = "DIV_1",
62 };
63
64 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
65         [TEGRA_SLEW_FASTEST] = "FASTEST",
66         [TEGRA_SLEW_FAST] = "FAST",
67         [TEGRA_SLEW_SLOW] = "SLOW",
68         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
69 };
70
71 static DEFINE_SPINLOCK(mux_lock);
72
73 static const char *pingroup_name(int pg)
74 {
75         if (pg < 0 || pg >=  pingroup_max)
76                 return "<UNKNOWN>";
77
78         return pingroups[pg].name;
79 }
80
81 static const char *func_name(enum tegra_mux_func func)
82 {
83         if (func == TEGRA_MUX_RSVD1)
84                 return "RSVD1";
85
86         if (func == TEGRA_MUX_RSVD2)
87                 return "RSVD2";
88
89         if (func == TEGRA_MUX_RSVD3)
90                 return "RSVD3";
91
92         if (func == TEGRA_MUX_RSVD4)
93                 return "RSVD4";
94
95         if (func == TEGRA_MUX_INVALID)
96                 return "INVALID";
97
98         if (func < 0 || func >=  TEGRA_MAX_MUX)
99                 return "<UNKNOWN>";
100
101         return tegra_mux_names[func];
102 }
103
104
105 static const char *tri_name(unsigned long val)
106 {
107         return val ? "TRISTATE" : "NORMAL";
108 }
109
110 static const char *pupd_name(unsigned long val)
111 {
112         switch (val) {
113         case 0:
114                 return "NORMAL";
115
116         case 1:
117                 return "PULL_DOWN";
118
119         case 2:
120                 return "PULL_UP";
121
122         default:
123                 return "RSVD";
124         }
125 }
126
127 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
128 static const char *lock_name(unsigned long val)
129 {
130         switch (val) {
131         case TEGRA_PIN_LOCK_DEFAULT:
132                 return "LOCK_DEFUALT";
133
134         case TEGRA_PIN_LOCK_DISABLE:
135                 return "LOCK_DISABLE";
136
137         case TEGRA_PIN_LOCK_ENABLE:
138                 return "LOCK_ENABLE";
139         default:
140                 return "LOCK_DEFAULT";
141         }
142 }
143
144 static const char *od_name(unsigned long val)
145 {
146         switch (val) {
147         case TEGRA_PIN_OD_DEFAULT:
148                 return "OD_DEFAULT";
149
150         case TEGRA_PIN_OD_DISABLE:
151                 return "OD_DISABLE";
152
153         case TEGRA_PIN_OD_ENABLE:
154                 return "OD_ENABLE";
155         default:
156                 return "OD_DEFAULT";
157         }
158 }
159
160 static const char *ioreset_name(unsigned long val)
161 {
162         switch (val) {
163         case TEGRA_PIN_IO_RESET_DEFAULT:
164                 return "IO_RESET_DEFAULT";
165
166         case TEGRA_PIN_IO_RESET_DISABLE:
167                 return "IO_RESET_DISABLE";
168
169         case TEGRA_PIN_IO_RESET_ENABLE:
170                 return "IO_RESET_ENABLE";
171         default:
172                 return "IO_RESET_DEFAULT";
173         }
174 }
175 #endif
176
177 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
178 static const char *io_name(unsigned long val)
179 {
180         switch (val) {
181         case 0:
182                 return "OUTPUT";
183
184         case 1:
185                 return "INPUT";
186
187         default:
188                 return "RSVD";
189         }
190 }
191 #endif
192
193 static int nbanks;
194 static void __iomem **regs;
195
196 u32 pg_readl(u32 bank, u32 reg)
197 {
198         return readl(regs[bank] + reg);
199 }
200
201 void pg_writel(u32 val, u32 bank, u32 reg)
202 {
203         writel(val, regs[bank] + reg);
204 }
205
206 int tegra_pinmux_get_pingroup(int gpio_nr)
207 {
208         return gpio_to_pingroups_map[gpio_nr];
209 }
210 EXPORT_SYMBOL_GPL(tegra_pinmux_get_pingroup);
211
212 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
213 {
214         int mux = -1;
215         int i;
216         int find = 0;
217         unsigned long reg;
218         unsigned long flags;
219         int pg = config->pingroup;
220         enum tegra_mux_func func = config->func;
221
222         if (pg < 0 || pg >=  pingroup_max)
223                 return -ERANGE;
224
225         if (pingroups[pg].mux_reg < 0)
226                 return -EINVAL;
227
228         if (func == TEGRA_MUX_INVALID) {
229                 pr_err("The pingroup %s is not recommended for option %s\n",
230                                 pingroup_name(pg), func_name(func));
231                 WARN_ON(1);
232                 return -EINVAL;
233         }
234
235         if (func < 0)
236                 return -ERANGE;
237
238         if (func == TEGRA_MUX_SAFE)
239                 func = pingroups[pg].func_safe;
240
241         if (func & TEGRA_MUX_RSVD) {
242                 for (i = 0; i < 4; i++) {
243                         if (pingroups[pg].funcs[i] & TEGRA_MUX_RSVD)
244                                 mux = i;
245
246                         if (pingroups[pg].funcs[i] == func) {
247                                 mux = i;
248                                 find = 1;
249                                 break;
250                         }
251                 }
252         } else {
253                 for (i = 0; i < 4; i++) {
254                         if (pingroups[pg].funcs[i] == func) {
255                                 mux = i;
256                                 find = 1;
257                                 break;
258                         }
259                 }
260         }
261
262         if (mux < 0) {
263                 pr_err("The pingroup %s is not supported option %s\n",
264                         pingroup_name(pg), func_name(func));
265                 WARN_ON(1);
266                 return -EINVAL;
267         }
268
269         if (!find)
270                 pr_warn("The pingroup %s was configured to %s instead of %s\n",
271                         pingroup_name(pg), func_name(pingroups[pg].funcs[mux]),
272                         func_name(func));
273
274         spin_lock_irqsave(&mux_lock, flags);
275
276         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
277         reg &= ~(0x3 << pingroups[pg].mux_bit);
278         reg |= mux << pingroups[pg].mux_bit;
279 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
280         reg &= ~(0x1 << 5);
281         reg |= ((config->io & 0x1) << 5);
282 #endif
283         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
284
285         spin_unlock_irqrestore(&mux_lock, flags);
286
287         return 0;
288 }
289
290 int tegra_pinmux_get_func(int pg)
291 {
292         int mux = -1;
293         unsigned long reg;
294         unsigned long flags;
295
296         if (pg < 0 || pg >=  pingroup_max)
297                 return -ERANGE;
298
299         if (pingroups[pg].mux_reg < 0)
300                 return -EINVAL;
301
302         spin_lock_irqsave(&mux_lock, flags);
303
304         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
305         mux = (reg >> pingroups[pg].mux_bit) & 0x3;
306
307         spin_unlock_irqrestore(&mux_lock, flags);
308
309         return mux;
310 }
311
312 int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
313 {
314         unsigned long reg;
315         unsigned long flags;
316
317         if (pg < 0 || pg >=  pingroup_max)
318                 return -ERANGE;
319
320         if (pingroups[pg].tri_reg < 0)
321                 return -EINVAL;
322
323         spin_lock_irqsave(&mux_lock, flags);
324
325         reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
326         reg &= ~(0x1 << pingroups[pg].tri_bit);
327         if (tristate)
328                 reg |= 1 << pingroups[pg].tri_bit;
329         pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
330
331         spin_unlock_irqrestore(&mux_lock, flags);
332
333         return 0;
334 }
335
336 int tegra_pinmux_set_io(int pg, enum tegra_pin_io input)
337 {
338 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
339         unsigned long io;
340
341         if (pg < 0 || pg >=  pingroup_max)
342                 return -ERANGE;
343
344         io = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
345         if (input)
346                 io |= 0x20;
347         else
348                 io &= ~(1 << 5);
349         pg_writel(io, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
350 #endif
351         return 0;
352 }
353 EXPORT_SYMBOL_GPL(tegra_pinmux_set_io);
354
355 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
356 static int tegra_pinmux_set_lock(int pg, enum tegra_pin_lock lock)
357 {
358         unsigned long reg;
359         unsigned long flags;
360
361         if (pg < 0 || pg >=  pingroup_max)
362                 return -ERANGE;
363
364         if (pingroups[pg].mux_reg < 0)
365                 return -EINVAL;
366
367         if ((lock == TEGRA_PIN_LOCK_DEFAULT) || (pingroups[pg].lock_bit < 0))
368                 return 0;
369
370         spin_lock_irqsave(&mux_lock, flags);
371
372         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
373         reg &= ~(0x1 << pingroups[pg].lock_bit);
374         if (lock == TEGRA_PIN_LOCK_ENABLE)
375                 reg |= (0x1 << pingroups[pg].lock_bit);
376
377         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
378
379         spin_unlock_irqrestore(&mux_lock, flags);
380         return 0;
381 }
382
383 static int tegra_pinmux_set_od(int pg, enum tegra_pin_od od)
384 {
385         unsigned long reg;
386         unsigned long flags;
387
388         if (pg < 0 || pg >=  pingroup_max)
389                 return -ERANGE;
390
391         if (pingroups[pg].mux_reg < 0)
392                 return -EINVAL;
393
394         if ((od == TEGRA_PIN_OD_DEFAULT) || (pingroups[pg].od_bit < 0))
395                 return 0;
396
397         spin_lock_irqsave(&mux_lock, flags);
398
399         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
400         reg &= ~(0x1 << pingroups[pg].od_bit);
401         if (od == TEGRA_PIN_OD_ENABLE)
402                 reg |= 1 << pingroups[pg].od_bit;
403
404         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
405
406         spin_unlock_irqrestore(&mux_lock, flags);
407
408         return 0;
409 }
410
411 static int tegra_pinmux_set_ioreset(int pg, enum tegra_pin_ioreset ioreset)
412 {
413         unsigned long reg;
414         unsigned long flags;
415
416         if (pg < 0 || pg >=  pingroup_max)
417                 return -ERANGE;
418
419         if (pingroups[pg].mux_reg < 0)
420                 return -EINVAL;
421
422         if ((ioreset == TEGRA_PIN_IO_RESET_DEFAULT) || (pingroups[pg].ioreset_bit < 0))
423                 return 0;
424
425         spin_lock_irqsave(&mux_lock, flags);
426
427         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
428         reg &= ~(0x1 << pingroups[pg].ioreset_bit);
429         if (ioreset == TEGRA_PIN_IO_RESET_ENABLE)
430                 reg |= 1 << pingroups[pg].ioreset_bit;
431
432         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
433
434         spin_unlock_irqrestore(&mux_lock, flags);
435
436         return 0;
437 }
438
439 static int tegra_pinmux_set_rcv_sel(int pg, enum tegra_pin_rcv_sel rcv_sel)
440 {
441         unsigned long reg;
442         unsigned long flags;
443
444         if (pg < 0 || pg >=  pingroup_max)
445                 return -ERANGE;
446
447         if (pingroups[pg].mux_reg < 0)
448                 return -EINVAL;
449
450         if ((rcv_sel == TEGRA_PIN_RCV_SEL_DEFAULT) || (pingroups[pg].rcv_sel_bit < 0))
451                 return 0;
452
453         spin_lock_irqsave(&mux_lock, flags);
454
455         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
456         reg &= ~(0x1 << pingroups[pg].rcv_sel_bit);
457         if (rcv_sel == TEGRA_PIN_RCV_SEL_HIGH)
458                 reg |= 1 << pingroups[pg].rcv_sel_bit;
459
460         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
461
462         spin_unlock_irqrestore(&mux_lock, flags);
463
464         return 0;
465 }
466 #endif
467
468 int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
469 {
470         unsigned long reg;
471         unsigned long flags;
472
473         if (pg < 0 || pg >=  pingroup_max)
474                 return -ERANGE;
475
476         if (pingroups[pg].pupd_reg < 0)
477                 return -EINVAL;
478
479         if (pupd != TEGRA_PUPD_NORMAL &&
480             pupd != TEGRA_PUPD_PULL_DOWN &&
481             pupd != TEGRA_PUPD_PULL_UP)
482                 return -EINVAL;
483
484
485         spin_lock_irqsave(&mux_lock, flags);
486
487         reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
488         reg &= ~(0x3 << pingroups[pg].pupd_bit);
489         reg |= pupd << pingroups[pg].pupd_bit;
490         pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
491
492         spin_unlock_irqrestore(&mux_lock, flags);
493
494         return 0;
495 }
496
497 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
498 {
499         int pingroup = config->pingroup;
500         enum tegra_mux_func func     = config->func;
501         enum tegra_pullupdown pupd   = config->pupd;
502         enum tegra_tristate tristate = config->tristate;
503 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
504         enum tegra_pin_lock lock     = config->lock;
505         enum tegra_pin_od od         = config->od;
506         enum tegra_pin_ioreset ioreset = config->ioreset;
507         enum tegra_pin_rcv_sel rcv_sel = config->rcv_sel;
508 #endif
509         int err;
510
511         if (pingroups[pingroup].mux_reg >= 0) {
512                 err = tegra_pinmux_set_func(config);
513                 if (err < 0)
514                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
515                                pingroup_name(pingroup), func_name(func), err);
516         }
517
518         if (pingroups[pingroup].pupd_reg >= 0) {
519                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
520                 if (err < 0)
521                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
522                                pingroup_name(pingroup), pupd_name(pupd), err);
523         }
524
525         if (pingroups[pingroup].tri_reg >= 0) {
526                 err = tegra_pinmux_set_tristate(pingroup, tristate);
527                 if (err < 0)
528                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
529                                pingroup_name(pingroup), tri_name(func), err);
530         }
531
532 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
533         if (pingroups[pingroup].mux_reg >= 0) {
534                 err = tegra_pinmux_set_lock(pingroup, lock);
535                 if (err < 0)
536                         pr_err("pinmux: can't set pingroup %s lock to %s: %d\n",
537                                pingroup_name(pingroup), lock_name(func), err);
538         }
539
540         if (pingroups[pingroup].mux_reg >= 0) {
541                 err = tegra_pinmux_set_od(pingroup, od);
542                 if (err < 0)
543                         pr_err("pinmux: can't set pingroup %s od to %s: %d\n",
544                                pingroup_name(pingroup), od_name(func), err);
545         }
546
547         if (pingroups[pingroup].mux_reg >= 0) {
548                 err = tegra_pinmux_set_ioreset(pingroup, ioreset);
549                 if (err < 0)
550                         pr_err("pinmux: can't set pingroup %s ioreset to %s: %d\n",
551                                pingroup_name(pingroup), ioreset_name(func), err);
552         }
553         if (pingroups[pingroup].mux_reg >= 0) {
554                 err = tegra_pinmux_set_rcv_sel(pingroup, rcv_sel);
555                 if (err < 0)
556                         pr_err("pinmux: can't set pingroup %s rcv_sel to %s: %d\n",
557                                pingroup_name(pingroup), tri_name(func), err);
558         }
559 #endif
560 }
561
562 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
563 {
564         int i;
565
566         for (i = 0; i < len; i++)
567                 tegra_pinmux_config_pingroup(&config[i]);
568 }
569 EXPORT_SYMBOL(tegra_pinmux_config_table);
570
571 static const char *drive_pinmux_name(int pg)
572 {
573         if (pg < 0 || pg >=  drive_max)
574                 return "<UNKNOWN>";
575
576         return drive_pingroups[pg].name;
577 }
578
579 static const char *enable_name(unsigned long val)
580 {
581         return val ? "ENABLE" : "DISABLE";
582 }
583
584 static const char *drive_name(unsigned long val)
585 {
586         if (val >= TEGRA_MAX_DRIVE)
587                 return "<UNKNOWN>";
588
589         return tegra_drive_names[val];
590 }
591
592 static const char *slew_name(unsigned long val)
593 {
594         if (val >= TEGRA_MAX_SLEW)
595                 return "<UNKNOWN>";
596
597         return tegra_slew_names[val];
598 }
599
600 static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
601 {
602         unsigned long flags;
603         u32 reg;
604         if (pg < 0 || pg >=  drive_max)
605                 return -ERANGE;
606
607         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
608                 return -EINVAL;
609
610         spin_lock_irqsave(&mux_lock, flags);
611
612         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
613         if (hsm == TEGRA_HSM_ENABLE)
614                 reg |= (1 << 2);
615         else
616                 reg &= ~(1 << 2);
617         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
618
619         spin_unlock_irqrestore(&mux_lock, flags);
620
621         return 0;
622 }
623
624 static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
625 {
626         unsigned long flags;
627         u32 reg;
628         if (pg < 0 || pg >=  drive_max)
629                 return -ERANGE;
630
631         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
632                 return -EINVAL;
633
634         spin_lock_irqsave(&mux_lock, flags);
635
636         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
637         if (schmitt == TEGRA_SCHMITT_ENABLE)
638                 reg |= (1 << 3);
639         else
640                 reg &= ~(1 << 3);
641         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
642
643         spin_unlock_irqrestore(&mux_lock, flags);
644
645         return 0;
646 }
647
648 static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
649 {
650         unsigned long flags;
651         u32 reg;
652         if (pg < 0 || pg >=  drive_max)
653                 return -ERANGE;
654
655         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
656                 return -EINVAL;
657
658         spin_lock_irqsave(&mux_lock, flags);
659
660         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
661         reg &= ~(0x3 << 4);
662         reg |= drive << 4;
663         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
664
665         spin_unlock_irqrestore(&mux_lock, flags);
666
667         return 0;
668 }
669
670 int tegra_drive_pinmux_set_pull_down(int pg,
671         enum tegra_pull_strength pull_down)
672 {
673         unsigned long flags;
674         u32 reg;
675
676         if (pg < 0 || pg >= drive_max)
677                 return -ERANGE;
678
679         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
680                 return -EINVAL;
681
682         spin_lock_irqsave(&mux_lock, flags);
683
684         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
685         reg &= ~(drive_pingroups[pg].drvdown_mask <<
686                 drive_pingroups[pg].drvdown_offset);
687         reg |= pull_down << drive_pingroups[pg].drvdown_offset;
688         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
689
690         spin_unlock_irqrestore(&mux_lock, flags);
691
692         return 0;
693 }
694
695 int tegra_drive_pinmux_set_pull_up(int pg,
696         enum tegra_pull_strength pull_up)
697 {
698         unsigned long flags;
699         u32 reg;
700
701         if (pg < 0 || pg >=  drive_max)
702                 return -ERANGE;
703
704         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
705                 return -EINVAL;
706
707         spin_lock_irqsave(&mux_lock, flags);
708
709         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
710         reg &= ~(drive_pingroups[pg].drvup_mask <<
711                 drive_pingroups[pg].drvup_offset);
712         reg |= pull_up << drive_pingroups[pg].drvup_offset;
713         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
714
715         spin_unlock_irqrestore(&mux_lock, flags);
716
717         return 0;
718 }
719
720 static int tegra_drive_pinmux_set_slew_rising(int pg,
721         enum tegra_slew slew_rising)
722 {
723         unsigned long flags;
724         u32 reg;
725         if (pg < 0 || pg >=  drive_max)
726                 return -ERANGE;
727
728         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
729                 return -EINVAL;
730
731         spin_lock_irqsave(&mux_lock, flags);
732
733         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
734         reg &= ~(drive_pingroups[pg].slewrise_mask <<
735                 drive_pingroups[pg].slewrise_offset);
736         reg |= slew_rising << drive_pingroups[pg].slewrise_offset;
737         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
738
739         spin_unlock_irqrestore(&mux_lock, flags);
740
741         return 0;
742 }
743
744 static int tegra_drive_pinmux_set_slew_falling(int pg,
745         enum tegra_slew slew_falling)
746 {
747         unsigned long flags;
748         u32 reg;
749         if (pg < 0 || pg >=  drive_max)
750                 return -ERANGE;
751
752         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
753                 return -EINVAL;
754
755         spin_lock_irqsave(&mux_lock, flags);
756
757         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
758         reg &= ~(drive_pingroups[pg].slewfall_mask <<
759                 drive_pingroups[pg].slewfall_offset);
760         reg |= slew_falling << drive_pingroups[pg].slewfall_offset;
761         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
762
763         spin_unlock_irqrestore(&mux_lock, flags);
764
765         return 0;
766 }
767
768 static int tegra_drive_pinmux_set_drive_type(int pg,
769         enum tegra_drive_type drive_type)
770 {
771         unsigned long flags;
772         u32 reg;
773         if (pg < 0 || pg >=  drive_max)
774                 return -ERANGE;
775
776         if (drive_type < 0 || drive_type >= TEGRA_MAX_DRIVE_TYPE)
777                 return -EINVAL;
778
779         spin_lock_irqsave(&mux_lock, flags);
780
781         if (drive_pingroups[pg].drvtype_valid) {
782                 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
783                 reg &= ~(drive_pingroups[pg].drvtype_mask <<
784                         drive_pingroups[pg].drvtype_offset);
785                 reg |= drive_type << drive_pingroups[pg].drvtype_offset;
786                 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
787         }
788
789         spin_unlock_irqrestore(&mux_lock, flags);
790
791         return 0;
792 }
793
794 static void tegra_drive_pinmux_config_pingroup(int pingroup,
795                                           enum tegra_hsm hsm,
796                                           enum tegra_schmitt schmitt,
797                                           enum tegra_drive drive,
798                                           enum tegra_pull_strength pull_down,
799                                           enum tegra_pull_strength pull_up,
800                                           enum tegra_slew slew_rising,
801                                           enum tegra_slew slew_falling,
802                                           enum tegra_drive_type drive_type)
803 {
804         int err;
805
806         err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
807         if (err < 0)
808                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
809                         drive_pinmux_name(pingroup),
810                         enable_name(hsm), err);
811
812         err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
813         if (err < 0)
814                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
815                         drive_pinmux_name(pingroup),
816                         enable_name(schmitt), err);
817
818         err = tegra_drive_pinmux_set_drive(pingroup, drive);
819         if (err < 0)
820                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
821                         drive_pinmux_name(pingroup),
822                         drive_name(drive), err);
823
824         err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
825         if (err < 0)
826                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
827                         drive_pinmux_name(pingroup),
828                         pull_down, err);
829
830         err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
831         if (err < 0)
832                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
833                         drive_pinmux_name(pingroup),
834                         pull_up, err);
835
836         err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
837         if (err < 0)
838                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
839                         drive_pinmux_name(pingroup),
840                         slew_name(slew_rising), err);
841
842         err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
843         if (err < 0)
844                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
845                         drive_pinmux_name(pingroup),
846                         slew_name(slew_falling), err);
847
848         err = tegra_drive_pinmux_set_drive_type(pingroup, drive_type);
849         if (err < 0)
850                 pr_err("pinmux: can't set pingroup %s driver type to %d: %d\n",
851                         drive_pinmux_name(pingroup),
852                         drive_type, err);
853 }
854
855 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
856         int len)
857 {
858         int i;
859
860         for (i = 0; i < len; i++)
861                 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
862                                                      config[i].hsm,
863                                                      config[i].schmitt,
864                                                      config[i].drive,
865                                                      config[i].pull_down,
866                                                      config[i].pull_up,
867                                                      config[i].slew_rising,
868                                                      config[i].slew_falling,
869                                                      config[i].drive_type);
870 }
871
872 int tegra_drive_get_pingroup(struct device *dev)
873 {
874         unsigned long flags;
875         int pg = -1;
876         const char *dev_id;
877
878         if (!dev)
879                 return -EINVAL;
880
881         spin_lock_irqsave(&mux_lock, flags);
882
883         dev_id = dev_name(dev);
884         for (pg = 0; pg < drive_max; pg++)
885                 if (drive_pingroups[pg].dev_id &&
886                         !(strcmp(drive_pingroups[pg].dev_id, dev_id)))
887                         break;
888
889         spin_unlock_irqrestore(&mux_lock, flags);
890
891         return pg;
892 }
893
894 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
895         int len)
896 {
897         int i;
898         struct tegra_pingroup_config c;
899
900         for (i = 0; i < len; i++) {
901                 int err;
902                 c = config[i];
903                 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
904                         WARN_ON(1);
905                         continue;
906                 }
907                 c.func = pingroups[c.pingroup].func_safe;
908                 err = tegra_pinmux_set_func(&c);
909                 if (err < 0)
910                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
911                                "%s to %s\n", __func__, err,
912                                pingroup_name(c.pingroup), func_name(c.func));
913         }
914 }
915
916 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
917         int len)
918 {
919         int i;
920
921         for (i = 0; i < len; i++) {
922                 int err;
923                 if (config[i].pingroup < 0 ||
924                     config[i].pingroup >= pingroup_max) {
925                         WARN_ON(1);
926                         continue;
927                 }
928                 err = tegra_pinmux_set_func(&config[i]);
929                 if (err < 0)
930                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
931                                "%s to %s\n", __func__, err,
932                                pingroup_name(config[i].pingroup),
933                                func_name(config[i].func));
934         }
935 }
936
937 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
938         int len, enum tegra_tristate tristate)
939 {
940         int i;
941         int err;
942         int pingroup;
943
944         for (i = 0; i < len; i++) {
945                 pingroup = config[i].pingroup;
946                 if (pingroups[pingroup].tri_reg > 0) {
947                         err = tegra_pinmux_set_tristate(pingroup, tristate);
948                         if (err < 0)
949                                 pr_err("pinmux: can't set pingroup %s tristate"
950                                         " to %s: %d\n", pingroup_name(pingroup),
951                                         tri_name(tristate), err);
952                 }
953         }
954 }
955
956 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
957         int len, enum tegra_pullupdown pupd)
958 {
959         int i;
960         int err;
961         int pingroup;
962
963         for (i = 0; i < len; i++) {
964                 pingroup = config[i].pingroup;
965                 if (pingroups[pingroup].pupd_reg > 0) {
966                         err = tegra_pinmux_set_pullupdown(pingroup, pupd);
967                         if (err < 0)
968                                 pr_err("pinmux: can't set pingroup %s pullupdown"
969                                         " to %s: %d\n", pingroup_name(pingroup),
970                                         pupd_name(pupd), err);
971                 }
972         }
973 }
974
975 static struct of_device_id tegra_pinmux_of_match[] = {
976 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
977         { .compatible = "nvidia,tegra20-pinmux-ctl", tegra20_pinmux_init },
978 #endif
979 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
980         { .compatible = "nvidia,tegra30-pinmux-ctl", tegra30_pinmux_init },
981 #endif
982 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
983         { .compatible = "nvidia,tegra11x-pinmux-ctl", tegra11x_pinmux_init },
984 #endif
985 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
986         { .compatible = "nvidia,tegra14x-pinmux", tegra14x_pinmux_init },
987 #endif
988         { },
989 };
990
991 static int tegra_pinmux_probe(struct platform_device *pdev)
992 {
993         struct resource *res;
994         int i;
995         int config_bad = 0;
996         const struct of_device_id *match;
997
998         match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
999
1000         if (match)
1001                 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
1002                         &drive_pingroups, &drive_max, &gpio_to_pingroups_map,
1003                         &gpio_to_pingroups_max);
1004         else
1005                 ((pinmux_init)(pdev->id_entry->driver_data))
1006                                         (&pingroups, &pingroup_max,
1007                                         &drive_pingroups, &drive_max,
1008                                         &gpio_to_pingroups_map,
1009                                         &gpio_to_pingroups_max);
1010
1011         for (i = 0; ; i++) {
1012                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1013                 if (!res)
1014                         break;
1015         }
1016         nbanks = i;
1017
1018         for (i = 0; i < pingroup_max; i++) {
1019                 if (pingroups[i].tri_bank >= nbanks) {
1020                         dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
1021                         config_bad = 1;
1022                 }
1023
1024                 if (pingroups[i].mux_bank >= nbanks) {
1025                         dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
1026                         config_bad = 1;
1027                 }
1028
1029                 if (pingroups[i].pupd_bank >= nbanks) {
1030                         dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
1031                         config_bad = 1;
1032                 }
1033         }
1034
1035         for (i = 0; i < drive_max; i++) {
1036                 if (drive_pingroups[i].reg_bank >= nbanks) {
1037                         dev_err(&pdev->dev,
1038                                 "drive pingroup %d: bad reg_bank\n", i);
1039                         config_bad = 1;
1040                 }
1041         }
1042
1043         if (config_bad)
1044                 return -ENODEV;
1045
1046         regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
1047         if (!regs) {
1048                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
1049                 return -ENODEV;
1050         }
1051
1052         for (i = 0; i < nbanks; i++) {
1053                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1054                 if (!res) {
1055                         dev_err(&pdev->dev, "Missing MEM resource\n");
1056                         return -ENODEV;
1057                 }
1058
1059                 if (!devm_request_mem_region(&pdev->dev, res->start,
1060                                             resource_size(res),
1061                                             dev_name(&pdev->dev))) {
1062                         dev_err(&pdev->dev,
1063                                 "Couldn't request MEM resource %d\n", i);
1064                         return -ENODEV;
1065                 }
1066
1067                 regs[i] = devm_ioremap(&pdev->dev, res->start,
1068                                         resource_size(res));
1069                 if (!regs) {
1070                         dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
1071                         return -ENODEV;
1072                 }
1073         }
1074
1075         return 0;
1076 }
1077
1078 static struct platform_device_id __devinitdata tegra_pinmux_id[] = {
1079 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1080         { .name = "tegra20-pinmux-ctl",
1081           .driver_data = (kernel_ulong_t)tegra20_pinmux_init, },
1082 #endif
1083 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1084         { .name = "tegra30-pinmux-ctl",
1085           .driver_data = (kernel_ulong_t)tegra30_pinmux_init, },
1086 #endif
1087 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1088         { .name = "tegra11x-pinmux-ctl",
1089           .driver_data = (kernel_ulong_t)tegra11x_pinmux_init, },
1090 #endif
1091 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
1092         { .name = "tegra14x-pinmux",
1093           .driver_data = (kernel_ulong_t)tegra14x_pinmux_init, },
1094 #endif
1095         {},
1096 };
1097
1098 static struct platform_driver tegra_pinmux_driver = {
1099         .driver         = {
1100                 .name   = "tegra-pinmux-ctl",
1101                 .owner  = THIS_MODULE,
1102                 .of_match_table = tegra_pinmux_of_match,
1103         },
1104         .id_table       = tegra_pinmux_id,
1105         .probe          = tegra_pinmux_probe,
1106 };
1107
1108 static int __init tegra_pinmux_init(void)
1109 {
1110         return platform_driver_register(&tegra_pinmux_driver);
1111 }
1112 postcore_initcall(tegra_pinmux_init);
1113
1114 #ifdef  CONFIG_DEBUG_FS
1115
1116 #include <linux/debugfs.h>
1117 #include <linux/seq_file.h>
1118
1119 static void dbg_pad_field(struct seq_file *s, int len)
1120 {
1121         seq_putc(s, ',');
1122
1123         while (len-- > -1)
1124                 seq_putc(s, ' ');
1125 }
1126
1127 static int dbg_pinmux_show(struct seq_file *s, void *unused)
1128 {
1129         int i;
1130         int len;
1131
1132         for (i = 0; i < pingroup_max; i++) {
1133                 unsigned long reg;
1134                 unsigned long tri;
1135                 unsigned long mux;
1136                 unsigned long pupd;
1137
1138                 if (!pingroups[i].name)
1139                         continue;
1140
1141                 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
1142                 len = strlen(pingroups[i].name);
1143                 dbg_pad_field(s, 15 - len);
1144
1145                 if (pingroups[i].mux_reg < 0) {
1146                         seq_printf(s, "TEGRA_MUX_NONE");
1147                         len = strlen("NONE");
1148                 } else {
1149                         reg = pg_readl(pingroups[i].mux_bank,
1150                                         pingroups[i].mux_reg);
1151                         mux = (reg >> pingroups[i].mux_bit) & 0x3;
1152                         BUG_ON(pingroups[i].funcs[mux] == 0);
1153                         if (pingroups[i].funcs[mux] ==  TEGRA_MUX_INVALID) {
1154                                 seq_printf(s, "TEGRA_MUX_INVALID");
1155                                 len = 7;
1156                         } else if (pingroups[i].funcs[mux] & TEGRA_MUX_RSVD) {
1157                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux);
1158                                 len = 5;
1159                         } else {
1160                                 BUG_ON(!tegra_mux_names[pingroups[i].funcs[mux]]);
1161                                 seq_printf(s, "TEGRA_MUX_%s",
1162                                            tegra_mux_names[pingroups[i].funcs[mux]]);
1163                                 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
1164                         }
1165                 }
1166                 dbg_pad_field(s, 13-len);
1167
1168 #if defined(TEGRA_PINMUX_HAS_IO_DIRECTION)
1169                 {
1170                         unsigned long io;
1171                         io = (pg_readl(pingroups[i].mux_bank,
1172                                         pingroups[i].mux_reg) >> 5) & 0x1;
1173                         seq_printf(s, "TEGRA_PIN_%s", io_name(io));
1174                         len = strlen(io_name(io));
1175                         dbg_pad_field(s, 6 - len);
1176                 }
1177 #endif
1178                 if (pingroups[i].pupd_reg < 0) {
1179                         seq_printf(s, "TEGRA_PUPD_NORMAL");
1180                         len = strlen("NORMAL");
1181                 } else {
1182                         reg = pg_readl(pingroups[i].pupd_bank,
1183                                         pingroups[i].pupd_reg);
1184                         pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
1185                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
1186                         len = strlen(pupd_name(pupd));
1187                 }
1188                 dbg_pad_field(s, 9 - len);
1189
1190                 if (pingroups[i].tri_reg < 0) {
1191                         seq_printf(s, "TEGRA_TRI_NORMAL");
1192                 } else {
1193                         reg = pg_readl(pingroups[i].tri_bank,
1194                                         pingroups[i].tri_reg);
1195                         tri = (reg >> pingroups[i].tri_bit) & 0x1;
1196
1197                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
1198                 }
1199                 seq_printf(s, "},\n");
1200         }
1201         return 0;
1202 }
1203
1204 static int dbg_pinmux_open(struct inode *inode, struct file *file)
1205 {
1206         return single_open(file, dbg_pinmux_show, &inode->i_private);
1207 }
1208
1209 static const struct file_operations debug_fops = {
1210         .open           = dbg_pinmux_open,
1211         .read           = seq_read,
1212         .llseek         = seq_lseek,
1213         .release        = single_release,
1214 };
1215
1216 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
1217 {
1218         int i;
1219         int len;
1220         u8 offset;
1221
1222         for (i = 0; i < drive_max; i++) {
1223                 u32 reg;
1224
1225                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
1226                         drive_pingroups[i].name);
1227                 len = strlen(drive_pingroups[i].name);
1228                 dbg_pad_field(s, 7 - len);
1229
1230
1231                 reg = pg_readl(drive_pingroups[i].reg_bank,
1232                                 drive_pingroups[i].reg);
1233                 if (HSM_EN(reg)) {
1234                         seq_printf(s, "TEGRA_HSM_ENABLE");
1235                         len = 16;
1236                 } else {
1237                         seq_printf(s, "TEGRA_HSM_DISABLE");
1238                         len = 17;
1239                 }
1240                 dbg_pad_field(s, 17 - len);
1241
1242                 if (SCHMT_EN(reg)) {
1243                         seq_printf(s, "TEGRA_SCHMITT_ENABLE");
1244                         len = 21;
1245                 } else {
1246                         seq_printf(s, "TEGRA_SCHMITT_DISABLE");
1247                         len = 22;
1248                 }
1249                 dbg_pad_field(s, 22 - len);
1250
1251                 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
1252                 len = strlen(drive_name(LPMD(reg)));
1253                 dbg_pad_field(s, 5 - len);
1254
1255                 offset = drive_pingroups[i].drvdown_offset;
1256                 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg, offset));
1257                 len = DRVDN(reg, offset) < 10 ? 1 : 2;
1258                 dbg_pad_field(s, 2 - len);
1259
1260                 offset = drive_pingroups[i].drvup_offset;
1261                 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg, offset));
1262                 len = DRVUP(reg, offset) < 10 ? 1 : 2;
1263                 dbg_pad_field(s, 2 - len);
1264
1265                 offset = drive_pingroups[i].slewrise_offset;
1266                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg, offset)));
1267                 len = strlen(slew_name(SLWR(reg, offset)));
1268                 dbg_pad_field(s, 7 - len);
1269
1270                 offset= drive_pingroups[i].slewfall_offset;
1271                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg, offset)));
1272
1273                 seq_printf(s, "},\n");
1274         }
1275         return 0;
1276 }
1277
1278 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
1279 {
1280         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
1281 }
1282
1283 static const struct file_operations debug_drive_fops = {
1284         .open           = dbg_drive_pinmux_open,
1285         .read           = seq_read,
1286         .llseek         = seq_lseek,
1287         .release        = single_release,
1288 };
1289
1290 static int __init tegra_pinmux_debuginit(void)
1291 {
1292         (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
1293                                         NULL, NULL, &debug_fops);
1294         (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
1295                                         NULL, NULL, &debug_drive_fops);
1296         return 0;
1297 }
1298 late_initcall(tegra_pinmux_debuginit);
1299 #endif