Revert "ARM: tegra: Remove pre-pinctrl pinmux driver"
[linux-3.10.git] / arch / arm / mach-tegra / pinmux.c
1 /*
2  * linux/arch/arm/mach-tegra/pinmux.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25
26 #include <mach/pinmux.h>
27
28 #include "iomap.h"
29
30 #define HSM_EN(reg)     (((reg) >> 2) & 0x1)
31 #define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
32 #define LPMD(reg)       (((reg) >> 4) & 0x3)
33 #define DRVDN(reg)      (((reg) >> 12) & 0x1f)
34 #define DRVUP(reg)      (((reg) >> 20) & 0x1f)
35 #define SLWR(reg)       (((reg) >> 28) & 0x3)
36 #define SLWF(reg)       (((reg) >> 30) & 0x3)
37
38 static const struct tegra_pingroup_desc *pingroups;
39 static const struct tegra_drive_pingroup_desc *drive_pingroups;
40 static int pingroup_max;
41 static int drive_max;
42
43 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
44         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
45         [TEGRA_MUX_APB_CLK] = "APB_CLK",
46         [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
47         [TEGRA_MUX_CRT] = "CRT",
48         [TEGRA_MUX_DAP1] = "DAP1",
49         [TEGRA_MUX_DAP2] = "DAP2",
50         [TEGRA_MUX_DAP3] = "DAP3",
51         [TEGRA_MUX_DAP4] = "DAP4",
52         [TEGRA_MUX_DAP5] = "DAP5",
53         [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
54         [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
55         [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
56         [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
57         [TEGRA_MUX_GMI] = "GMI",
58         [TEGRA_MUX_GMI_INT] = "GMI_INT",
59         [TEGRA_MUX_HDMI] = "HDMI",
60         [TEGRA_MUX_I2C] = "I2C",
61         [TEGRA_MUX_I2C2] = "I2C2",
62         [TEGRA_MUX_I2C3] = "I2C3",
63         [TEGRA_MUX_IDE] = "IDE",
64         [TEGRA_MUX_IRDA] = "IRDA",
65         [TEGRA_MUX_KBC] = "KBC",
66         [TEGRA_MUX_MIO] = "MIO",
67         [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
68         [TEGRA_MUX_NAND] = "NAND",
69         [TEGRA_MUX_OSC] = "OSC",
70         [TEGRA_MUX_OWR] = "OWR",
71         [TEGRA_MUX_PCIE] = "PCIE",
72         [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
73         [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
74         [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
75         [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
76         [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
77         [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
78         [TEGRA_MUX_PWM] = "PWM",
79         [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
80         [TEGRA_MUX_PWR_ON] = "PWR_ON",
81         [TEGRA_MUX_RTCK] = "RTCK",
82         [TEGRA_MUX_SDIO1] = "SDIO1",
83         [TEGRA_MUX_SDIO2] = "SDIO2",
84         [TEGRA_MUX_SDIO3] = "SDIO3",
85         [TEGRA_MUX_SDIO4] = "SDIO4",
86         [TEGRA_MUX_SFLASH] = "SFLASH",
87         [TEGRA_MUX_SPDIF] = "SPDIF",
88         [TEGRA_MUX_SPI1] = "SPI1",
89         [TEGRA_MUX_SPI2] = "SPI2",
90         [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
91         [TEGRA_MUX_SPI3] = "SPI3",
92         [TEGRA_MUX_SPI4] = "SPI4",
93         [TEGRA_MUX_TRACE] = "TRACE",
94         [TEGRA_MUX_TWC] = "TWC",
95         [TEGRA_MUX_UARTA] = "UARTA",
96         [TEGRA_MUX_UARTB] = "UARTB",
97         [TEGRA_MUX_UARTC] = "UARTC",
98         [TEGRA_MUX_UARTD] = "UARTD",
99         [TEGRA_MUX_UARTE] = "UARTE",
100         [TEGRA_MUX_ULPI] = "ULPI",
101         [TEGRA_MUX_VI] = "VI",
102         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
103         [TEGRA_MUX_XIO] = "XIO",
104         [TEGRA_MUX_BLINK] = "BLINK",
105         [TEGRA_MUX_CEC] = "CEC",
106         [TEGRA_MUX_CLK12] = "CLK12",
107         [TEGRA_MUX_DAP] = "DAP",
108         [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
109         [TEGRA_MUX_DDR] = "DDR",
110         [TEGRA_MUX_DEV3] = "DEV3",
111         [TEGRA_MUX_DTV] = "DTV",
112         [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
113         [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
114         [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
115         [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
116         [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
117         [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
118         [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
119         [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
120         [TEGRA_MUX_HDA] = "HDA",
121         [TEGRA_MUX_HSI] = "HSI",
122         [TEGRA_MUX_I2C4] = "I2C4",
123         [TEGRA_MUX_I2C5] = "I2C5",
124         [TEGRA_MUX_I2CPWR] = "I2CPWR",
125         [TEGRA_MUX_I2S0] = "I2S0",
126         [TEGRA_MUX_I2S1] = "I2S1",
127         [TEGRA_MUX_I2S2] = "I2S2",
128         [TEGRA_MUX_I2S3] = "I2S3",
129         [TEGRA_MUX_I2S4] = "I2S4",
130         [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
131         [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
132         [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
133         [TEGRA_MUX_PWM0] = "PWM0",
134         [TEGRA_MUX_PWM1] = "PWM2",
135         [TEGRA_MUX_PWM2] = "PWM2",
136         [TEGRA_MUX_PWM3] = "PWM3",
137         [TEGRA_MUX_SATA] = "SATA",
138         [TEGRA_MUX_SPI5] = "SPI5",
139         [TEGRA_MUX_SPI6] = "SPI6",
140         [TEGRA_MUX_SYSCLK] = "SYSCLK",
141         [TEGRA_MUX_VGP1] = "VGP1",
142         [TEGRA_MUX_VGP2] = "VGP2",
143         [TEGRA_MUX_VGP3] = "VGP3",
144         [TEGRA_MUX_VGP4] = "VGP4",
145         [TEGRA_MUX_VGP5] = "VGP5",
146         [TEGRA_MUX_VGP6] = "VGP6",
147         [TEGRA_MUX_SAFE] = "<safe>",
148 };
149
150 static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
151         [TEGRA_DRIVE_DIV_8] = "DIV_8",
152         [TEGRA_DRIVE_DIV_4] = "DIV_4",
153         [TEGRA_DRIVE_DIV_2] = "DIV_2",
154         [TEGRA_DRIVE_DIV_1] = "DIV_1",
155 };
156
157 static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
158         [TEGRA_SLEW_FASTEST] = "FASTEST",
159         [TEGRA_SLEW_FAST] = "FAST",
160         [TEGRA_SLEW_SLOW] = "SLOW",
161         [TEGRA_SLEW_SLOWEST] = "SLOWEST",
162 };
163
164 static DEFINE_SPINLOCK(mux_lock);
165
166 static const char *pingroup_name(int pg)
167 {
168         if (pg < 0 || pg >=  pingroup_max)
169                 return "<UNKNOWN>";
170
171         return pingroups[pg].name;
172 }
173
174 static const char *func_name(enum tegra_mux_func func)
175 {
176         if (func == TEGRA_MUX_RSVD1)
177                 return "RSVD1";
178
179         if (func == TEGRA_MUX_RSVD2)
180                 return "RSVD2";
181
182         if (func == TEGRA_MUX_RSVD3)
183                 return "RSVD3";
184
185         if (func == TEGRA_MUX_RSVD4)
186                 return "RSVD4";
187
188         if (func == TEGRA_MUX_NONE)
189                 return "NONE";
190
191         if (func < 0 || func >=  TEGRA_MAX_MUX)
192                 return "<UNKNOWN>";
193
194         return tegra_mux_names[func];
195 }
196
197
198 static const char *tri_name(unsigned long val)
199 {
200         return val ? "TRISTATE" : "NORMAL";
201 }
202
203 static const char *pupd_name(unsigned long val)
204 {
205         switch (val) {
206         case 0:
207                 return "NORMAL";
208
209         case 1:
210                 return "PULL_DOWN";
211
212         case 2:
213                 return "PULL_UP";
214
215         default:
216                 return "RSVD";
217         }
218 }
219
220 static int nbanks;
221 static void __iomem **regs;
222
223 static inline u32 pg_readl(u32 bank, u32 reg)
224 {
225         return readl(regs[bank] + reg);
226 }
227
228 static inline void pg_writel(u32 val, u32 bank, u32 reg)
229 {
230         writel(val, regs[bank] + reg);
231 }
232
233 static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
234 {
235         int mux = -1;
236         int i;
237         unsigned long reg;
238         unsigned long flags;
239         int pg = config->pingroup;
240         enum tegra_mux_func func = config->func;
241
242         if (pg < 0 || pg >=  pingroup_max)
243                 return -ERANGE;
244
245         if (pingroups[pg].mux_reg < 0)
246                 return -EINVAL;
247
248         if (func < 0)
249                 return -ERANGE;
250
251         if (func == TEGRA_MUX_SAFE)
252                 func = pingroups[pg].func_safe;
253
254         if (func & TEGRA_MUX_RSVD) {
255                 mux = func & 0x3;
256         } else {
257                 for (i = 0; i < 4; i++) {
258                         if (pingroups[pg].funcs[i] == func) {
259                                 mux = i;
260                                 break;
261                         }
262                 }
263         }
264
265         if (mux < 0)
266                 return -EINVAL;
267
268         spin_lock_irqsave(&mux_lock, flags);
269
270         reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
271         reg &= ~(0x3 << pingroups[pg].mux_bit);
272         reg |= mux << pingroups[pg].mux_bit;
273         pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
274
275         spin_unlock_irqrestore(&mux_lock, flags);
276
277         return 0;
278 }
279
280 int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
281 {
282         unsigned long reg;
283         unsigned long flags;
284
285         if (pg < 0 || pg >=  pingroup_max)
286                 return -ERANGE;
287
288         if (pingroups[pg].tri_reg < 0)
289                 return -EINVAL;
290
291         spin_lock_irqsave(&mux_lock, flags);
292
293         reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
294         reg &= ~(0x1 << pingroups[pg].tri_bit);
295         if (tristate)
296                 reg |= 1 << pingroups[pg].tri_bit;
297         pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
298
299         spin_unlock_irqrestore(&mux_lock, flags);
300
301         return 0;
302 }
303
304 int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
305 {
306         unsigned long reg;
307         unsigned long flags;
308
309         if (pg < 0 || pg >=  pingroup_max)
310                 return -ERANGE;
311
312         if (pingroups[pg].pupd_reg < 0)
313                 return -EINVAL;
314
315         if (pupd != TEGRA_PUPD_NORMAL &&
316             pupd != TEGRA_PUPD_PULL_DOWN &&
317             pupd != TEGRA_PUPD_PULL_UP)
318                 return -EINVAL;
319
320
321         spin_lock_irqsave(&mux_lock, flags);
322
323         reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
324         reg &= ~(0x3 << pingroups[pg].pupd_bit);
325         reg |= pupd << pingroups[pg].pupd_bit;
326         pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
327
328         spin_unlock_irqrestore(&mux_lock, flags);
329
330         return 0;
331 }
332
333 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
334 {
335         int pingroup = config->pingroup;
336         enum tegra_mux_func func     = config->func;
337         enum tegra_pullupdown pupd   = config->pupd;
338         enum tegra_tristate tristate = config->tristate;
339         int err;
340
341         if (pingroups[pingroup].mux_reg >= 0) {
342                 err = tegra_pinmux_set_func(config);
343                 if (err < 0)
344                         pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
345                                pingroup_name(pingroup), func_name(func), err);
346         }
347
348         if (pingroups[pingroup].pupd_reg >= 0) {
349                 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
350                 if (err < 0)
351                         pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
352                                pingroup_name(pingroup), pupd_name(pupd), err);
353         }
354
355         if (pingroups[pingroup].tri_reg >= 0) {
356                 err = tegra_pinmux_set_tristate(pingroup, tristate);
357                 if (err < 0)
358                         pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
359                                pingroup_name(pingroup), tri_name(func), err);
360         }
361 }
362
363 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
364 {
365         int i;
366
367         for (i = 0; i < len; i++)
368                 tegra_pinmux_config_pingroup(&config[i]);
369 }
370
371 static const char *drive_pinmux_name(int pg)
372 {
373         if (pg < 0 || pg >=  drive_max)
374                 return "<UNKNOWN>";
375
376         return drive_pingroups[pg].name;
377 }
378
379 static const char *enable_name(unsigned long val)
380 {
381         return val ? "ENABLE" : "DISABLE";
382 }
383
384 static const char *drive_name(unsigned long val)
385 {
386         if (val >= TEGRA_MAX_DRIVE)
387                 return "<UNKNOWN>";
388
389         return tegra_drive_names[val];
390 }
391
392 static const char *slew_name(unsigned long val)
393 {
394         if (val >= TEGRA_MAX_SLEW)
395                 return "<UNKNOWN>";
396
397         return tegra_slew_names[val];
398 }
399
400 static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
401 {
402         unsigned long flags;
403         u32 reg;
404         if (pg < 0 || pg >=  drive_max)
405                 return -ERANGE;
406
407         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
408                 return -EINVAL;
409
410         spin_lock_irqsave(&mux_lock, flags);
411
412         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
413         if (hsm == TEGRA_HSM_ENABLE)
414                 reg |= (1 << 2);
415         else
416                 reg &= ~(1 << 2);
417         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
418
419         spin_unlock_irqrestore(&mux_lock, flags);
420
421         return 0;
422 }
423
424 static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
425 {
426         unsigned long flags;
427         u32 reg;
428         if (pg < 0 || pg >=  drive_max)
429                 return -ERANGE;
430
431         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
432                 return -EINVAL;
433
434         spin_lock_irqsave(&mux_lock, flags);
435
436         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
437         if (schmitt == TEGRA_SCHMITT_ENABLE)
438                 reg |= (1 << 3);
439         else
440                 reg &= ~(1 << 3);
441         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
442
443         spin_unlock_irqrestore(&mux_lock, flags);
444
445         return 0;
446 }
447
448 static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
449 {
450         unsigned long flags;
451         u32 reg;
452         if (pg < 0 || pg >=  drive_max)
453                 return -ERANGE;
454
455         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
456                 return -EINVAL;
457
458         spin_lock_irqsave(&mux_lock, flags);
459
460         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
461         reg &= ~(0x3 << 4);
462         reg |= drive << 4;
463         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
464
465         spin_unlock_irqrestore(&mux_lock, flags);
466
467         return 0;
468 }
469
470 static int tegra_drive_pinmux_set_pull_down(int pg,
471         enum tegra_pull_strength pull_down)
472 {
473         unsigned long flags;
474         u32 reg;
475         if (pg < 0 || pg >=  drive_max)
476                 return -ERANGE;
477
478         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
479                 return -EINVAL;
480
481         spin_lock_irqsave(&mux_lock, flags);
482
483         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
484         reg &= ~(0x1f << 12);
485         reg |= pull_down << 12;
486         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
487
488         spin_unlock_irqrestore(&mux_lock, flags);
489
490         return 0;
491 }
492
493 static int tegra_drive_pinmux_set_pull_up(int pg,
494         enum tegra_pull_strength pull_up)
495 {
496         unsigned long flags;
497         u32 reg;
498         if (pg < 0 || pg >=  drive_max)
499                 return -ERANGE;
500
501         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
502                 return -EINVAL;
503
504         spin_lock_irqsave(&mux_lock, flags);
505
506         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
507         reg &= ~(0x1f << 12);
508         reg |= pull_up << 12;
509         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
510
511         spin_unlock_irqrestore(&mux_lock, flags);
512
513         return 0;
514 }
515
516 static int tegra_drive_pinmux_set_slew_rising(int pg,
517         enum tegra_slew slew_rising)
518 {
519         unsigned long flags;
520         u32 reg;
521         if (pg < 0 || pg >=  drive_max)
522                 return -ERANGE;
523
524         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
525                 return -EINVAL;
526
527         spin_lock_irqsave(&mux_lock, flags);
528
529         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
530         reg &= ~(0x3 << 28);
531         reg |= slew_rising << 28;
532         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
533
534         spin_unlock_irqrestore(&mux_lock, flags);
535
536         return 0;
537 }
538
539 static int tegra_drive_pinmux_set_slew_falling(int pg,
540         enum tegra_slew slew_falling)
541 {
542         unsigned long flags;
543         u32 reg;
544         if (pg < 0 || pg >=  drive_max)
545                 return -ERANGE;
546
547         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
548                 return -EINVAL;
549
550         spin_lock_irqsave(&mux_lock, flags);
551
552         reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
553         reg &= ~(0x3 << 30);
554         reg |= slew_falling << 30;
555         pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
556
557         spin_unlock_irqrestore(&mux_lock, flags);
558
559         return 0;
560 }
561
562 static void tegra_drive_pinmux_config_pingroup(int pingroup,
563                                           enum tegra_hsm hsm,
564                                           enum tegra_schmitt schmitt,
565                                           enum tegra_drive drive,
566                                           enum tegra_pull_strength pull_down,
567                                           enum tegra_pull_strength pull_up,
568                                           enum tegra_slew slew_rising,
569                                           enum tegra_slew slew_falling)
570 {
571         int err;
572
573         err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
574         if (err < 0)
575                 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
576                         drive_pinmux_name(pingroup),
577                         enable_name(hsm), err);
578
579         err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
580         if (err < 0)
581                 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
582                         drive_pinmux_name(pingroup),
583                         enable_name(schmitt), err);
584
585         err = tegra_drive_pinmux_set_drive(pingroup, drive);
586         if (err < 0)
587                 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
588                         drive_pinmux_name(pingroup),
589                         drive_name(drive), err);
590
591         err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
592         if (err < 0)
593                 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
594                         drive_pinmux_name(pingroup),
595                         pull_down, err);
596
597         err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
598         if (err < 0)
599                 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
600                         drive_pinmux_name(pingroup),
601                         pull_up, err);
602
603         err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
604         if (err < 0)
605                 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
606                         drive_pinmux_name(pingroup),
607                         slew_name(slew_rising), err);
608
609         err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
610         if (err < 0)
611                 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
612                         drive_pinmux_name(pingroup),
613                         slew_name(slew_falling), err);
614 }
615
616 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
617         int len)
618 {
619         int i;
620
621         for (i = 0; i < len; i++)
622                 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
623                                                      config[i].hsm,
624                                                      config[i].schmitt,
625                                                      config[i].drive,
626                                                      config[i].pull_down,
627                                                      config[i].pull_up,
628                                                      config[i].slew_rising,
629                                                      config[i].slew_falling);
630 }
631
632 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
633         int len)
634 {
635         int i;
636         struct tegra_pingroup_config c;
637
638         for (i = 0; i < len; i++) {
639                 int err;
640                 c = config[i];
641                 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
642                         WARN_ON(1);
643                         continue;
644                 }
645                 c.func = pingroups[c.pingroup].func_safe;
646                 err = tegra_pinmux_set_func(&c);
647                 if (err < 0)
648                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
649                                "%s to %s\n", __func__, err,
650                                pingroup_name(c.pingroup), func_name(c.func));
651         }
652 }
653
654 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
655         int len)
656 {
657         int i;
658
659         for (i = 0; i < len; i++) {
660                 int err;
661                 if (config[i].pingroup < 0 ||
662                     config[i].pingroup >= pingroup_max) {
663                         WARN_ON(1);
664                         continue;
665                 }
666                 err = tegra_pinmux_set_func(&config[i]);
667                 if (err < 0)
668                         pr_err("%s: tegra_pinmux_set_func returned %d setting "
669                                "%s to %s\n", __func__, err,
670                                pingroup_name(config[i].pingroup),
671                                func_name(config[i].func));
672         }
673 }
674
675 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
676         int len, enum tegra_tristate tristate)
677 {
678         int i;
679         int err;
680         int pingroup;
681
682         for (i = 0; i < len; i++) {
683                 pingroup = config[i].pingroup;
684                 if (pingroups[pingroup].tri_reg >= 0) {
685                         err = tegra_pinmux_set_tristate(pingroup, tristate);
686                         if (err < 0)
687                                 pr_err("pinmux: can't set pingroup %s tristate"
688                                         " to %s: %d\n", pingroup_name(pingroup),
689                                         tri_name(tristate), err);
690                 }
691         }
692 }
693
694 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
695         int len, enum tegra_pullupdown pupd)
696 {
697         int i;
698         int err;
699         int pingroup;
700
701         for (i = 0; i < len; i++) {
702                 pingroup = config[i].pingroup;
703                 if (pingroups[pingroup].pupd_reg >= 0) {
704                         err = tegra_pinmux_set_pullupdown(pingroup, pupd);
705                         if (err < 0)
706                                 pr_err("pinmux: can't set pingroup %s pullupdown"
707                                         " to %s: %d\n", pingroup_name(pingroup),
708                                         pupd_name(pupd), err);
709                 }
710         }
711 }
712
713 static struct of_device_id tegra_pinmux_of_match[] = {
714 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
715         { .compatible = "nvidia,tegra20-pinmux-disabled", tegra20_pinmux_init },
716 #endif
717 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
718         { .compatible = "nvidia,tegra30-pinmux-disabled", tegra30_pinmux_init },
719 #endif
720         { },
721 };
722
723 static int tegra_pinmux_probe(struct platform_device *pdev)
724 {
725         struct resource *res;
726         int i;
727         int config_bad = 0;
728         const struct of_device_id *match;
729
730         match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
731
732         if (match)
733                 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
734                         &drive_pingroups, &drive_max);
735 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
736         else
737                 /* no device tree available, so we must be on tegra20 */
738                 tegra20_pinmux_init(&pingroups, &pingroup_max,
739                                         &drive_pingroups, &drive_max);
740 #else
741         pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
742 #endif
743
744         for (i = 0; ; i++) {
745                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
746                 if (!res)
747                         break;
748         }
749         nbanks = i;
750
751         for (i = 0; i < pingroup_max; i++) {
752                 if (pingroups[i].tri_bank >= nbanks) {
753                         dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
754                         config_bad = 1;
755                 }
756
757                 if (pingroups[i].mux_bank >= nbanks) {
758                         dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
759                         config_bad = 1;
760                 }
761
762                 if (pingroups[i].pupd_bank >= nbanks) {
763                         dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
764                         config_bad = 1;
765                 }
766         }
767
768         for (i = 0; i < drive_max; i++) {
769                 if (drive_pingroups[i].reg_bank >= nbanks) {
770                         dev_err(&pdev->dev,
771                                 "drive pingroup %d: bad reg_bank\n", i);
772                         config_bad = 1;
773                 }
774         }
775
776         if (config_bad)
777                 return -ENODEV;
778
779         regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
780         if (!regs) {
781                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
782                 return -ENODEV;
783         }
784
785         for (i = 0; i < nbanks; i++) {
786                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
787                 if (!res) {
788                         dev_err(&pdev->dev, "Missing MEM resource\n");
789                         return -ENODEV;
790                 }
791
792                 if (!devm_request_mem_region(&pdev->dev, res->start,
793                                             resource_size(res),
794                                             dev_name(&pdev->dev))) {
795                         dev_err(&pdev->dev,
796                                 "Couldn't request MEM resource %d\n", i);
797                         return -ENODEV;
798                 }
799
800                 regs[i] = devm_ioremap(&pdev->dev, res->start,
801                                         resource_size(res));
802                 if (!regs) {
803                         dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
804                         return -ENODEV;
805                 }
806         }
807
808         return 0;
809 }
810
811 static struct platform_driver tegra_pinmux_driver = {
812         .driver         = {
813                 .name   = "tegra-pinmux-disabled",
814                 .owner  = THIS_MODULE,
815                 .of_match_table = tegra_pinmux_of_match,
816         },
817         .probe          = tegra_pinmux_probe,
818 };
819
820 static int __init tegra_pinmux_init(void)
821 {
822         return platform_driver_register(&tegra_pinmux_driver);
823 }
824 postcore_initcall(tegra_pinmux_init);
825
826 #ifdef  CONFIG_DEBUG_FS
827
828 #include <linux/debugfs.h>
829 #include <linux/seq_file.h>
830
831 static void dbg_pad_field(struct seq_file *s, int len)
832 {
833         seq_putc(s, ',');
834
835         while (len-- > -1)
836                 seq_putc(s, ' ');
837 }
838
839 static int dbg_pinmux_show(struct seq_file *s, void *unused)
840 {
841         int i;
842         int len;
843
844         for (i = 0; i < pingroup_max; i++) {
845                 unsigned long reg;
846                 unsigned long tri;
847                 unsigned long mux;
848                 unsigned long pupd;
849
850                 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
851                 len = strlen(pingroups[i].name);
852                 dbg_pad_field(s, 5 - len);
853
854                 if (pingroups[i].mux_reg < 0) {
855                         seq_printf(s, "TEGRA_MUX_NONE");
856                         len = strlen("NONE");
857                 } else {
858                         reg = pg_readl(pingroups[i].mux_bank,
859                                         pingroups[i].mux_reg);
860                         mux = (reg >> pingroups[i].mux_bit) & 0x3;
861                         if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
862                                 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
863                                 len = 5;
864                         } else {
865                                 seq_printf(s, "TEGRA_MUX_%s",
866                                            tegra_mux_names[pingroups[i].funcs[mux]]);
867                                 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
868                         }
869                 }
870                 dbg_pad_field(s, 13-len);
871
872                 if (pingroups[i].pupd_reg < 0) {
873                         seq_printf(s, "TEGRA_PUPD_NORMAL");
874                         len = strlen("NORMAL");
875                 } else {
876                         reg = pg_readl(pingroups[i].pupd_bank,
877                                         pingroups[i].pupd_reg);
878                         pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
879                         seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
880                         len = strlen(pupd_name(pupd));
881                 }
882                 dbg_pad_field(s, 9 - len);
883
884                 if (pingroups[i].tri_reg < 0) {
885                         seq_printf(s, "TEGRA_TRI_NORMAL");
886                 } else {
887                         reg = pg_readl(pingroups[i].tri_bank,
888                                         pingroups[i].tri_reg);
889                         tri = (reg >> pingroups[i].tri_bit) & 0x1;
890
891                         seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
892                 }
893                 seq_printf(s, "},\n");
894         }
895         return 0;
896 }
897
898 static int dbg_pinmux_open(struct inode *inode, struct file *file)
899 {
900         return single_open(file, dbg_pinmux_show, &inode->i_private);
901 }
902
903 static const struct file_operations debug_fops = {
904         .open           = dbg_pinmux_open,
905         .read           = seq_read,
906         .llseek         = seq_lseek,
907         .release        = single_release,
908 };
909
910 static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
911 {
912         int i;
913         int len;
914
915         for (i = 0; i < drive_max; i++) {
916                 u32 reg;
917
918                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
919                         drive_pingroups[i].name);
920                 len = strlen(drive_pingroups[i].name);
921                 dbg_pad_field(s, 7 - len);
922
923
924                 reg = pg_readl(drive_pingroups[i].reg_bank,
925                                 drive_pingroups[i].reg);
926                 if (HSM_EN(reg)) {
927                         seq_printf(s, "TEGRA_HSM_ENABLE");
928                         len = 16;
929                 } else {
930                         seq_printf(s, "TEGRA_HSM_DISABLE");
931                         len = 17;
932                 }
933                 dbg_pad_field(s, 17 - len);
934
935                 if (SCHMT_EN(reg)) {
936                         seq_printf(s, "TEGRA_SCHMITT_ENABLE");
937                         len = 21;
938                 } else {
939                         seq_printf(s, "TEGRA_SCHMITT_DISABLE");
940                         len = 22;
941                 }
942                 dbg_pad_field(s, 22 - len);
943
944                 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
945                 len = strlen(drive_name(LPMD(reg)));
946                 dbg_pad_field(s, 5 - len);
947
948                 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
949                 len = DRVDN(reg) < 10 ? 1 : 2;
950                 dbg_pad_field(s, 2 - len);
951
952                 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
953                 len = DRVUP(reg) < 10 ? 1 : 2;
954                 dbg_pad_field(s, 2 - len);
955
956                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
957                 len = strlen(slew_name(SLWR(reg)));
958                 dbg_pad_field(s, 7 - len);
959
960                 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
961
962                 seq_printf(s, "},\n");
963         }
964         return 0;
965 }
966
967 static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
968 {
969         return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
970 }
971
972 static const struct file_operations debug_drive_fops = {
973         .open           = dbg_drive_pinmux_open,
974         .read           = seq_read,
975         .llseek         = seq_lseek,
976         .release        = single_release,
977 };
978
979 static int __init tegra_pinmux_debuginit(void)
980 {
981         (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
982                                         NULL, NULL, &debug_fops);
983         (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
984                                         NULL, NULL, &debug_drive_fops);
985         return 0;
986 }
987 late_initcall(tegra_pinmux_debuginit);
988 #endif