ARM: Build fix after Tegra14 K3.4 merge
[linux-3.10.git] / arch / arm / mach-tegra / pinmux-t14-tables.c
1 /*
2  * linux/arch/arm/mach-tegra/pinmux-t14-tables.c
3  *
4  * Common pinmux configurations for Tegra14x SoCs
5  *
6  * Copyright (C) 2012 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/spinlock.h>
26 #include <linux/io.h>
27 #include <linux/init.h>
28 #include <linux/string.h>
29 #include <linux/syscore_ops.h>
30 #include <linux/bug.h>
31 #include <linux/bitops.h>
32
33 #include <mach/pinmux.h>
34 #include <mach/pinmux-t14.h>
35 #include "gpio-names.h"
36 #include "iomap.h"
37
38 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
39
40 #define TRISTATE                (1<<4)
41 #define PMC_IO_DPD_REQ_0        0x1B8
42 #define PMC_IO_DPD2_REQ_0       0x1C0
43
44 #define PINGROUP_REG_A  0x868
45 #define MUXCTL_REG_A    0x3000
46
47 #define SET_DRIVE_PINGROUP(pg_name, r, drv_down_offset, drv_down_mask, drv_up_offset, drv_up_mask,      \
48         slew_rise_offset, slew_rise_mask, slew_fall_offset, slew_fall_mask)     \
49         [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
50                 .name = #pg_name,                               \
51                 .reg_bank = 0,                                  \
52                 .reg = ((r) - PINGROUP_REG_A),                  \
53                 .drvup_offset = drv_up_offset,                  \
54                 .drvup_mask = drv_up_mask,                      \
55                 .drvdown_offset = drv_down_offset,              \
56                 .drvdown_mask = drv_down_mask,                  \
57                 .slewrise_offset = slew_rise_offset,            \
58                 .slewrise_mask = slew_rise_mask,                \
59                 .slewfall_offset = slew_fall_offset,            \
60                 .slewfall_mask = slew_fall_mask,                \
61         }
62
63 #define DEFAULT_DRIVE_PINGROUP(pg_name, r)              \
64         [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {          \
65                 .name = #pg_name,                       \
66                 .reg_bank = 0,                          \
67                 .reg = ((r) - PINGROUP_REG_A),          \
68                 .drvup_offset = 20,                     \
69                 .drvup_mask = 0x1f,                     \
70                 .drvdown_offset = 12,                   \
71                 .drvdown_mask = 0x1f,                   \
72                 .slewrise_offset = 28,                  \
73                 .slewrise_mask = 0x3,                   \
74                 .slewfall_offset = 30,                  \
75                 .slewfall_mask = 0x3,                   \
76         }
77
78 const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
79         DEFAULT_DRIVE_PINGROUP(AO1,             0x868),
80         DEFAULT_DRIVE_PINGROUP(AO2,             0x86c),
81         DEFAULT_DRIVE_PINGROUP(CDEV1,           0x884),
82         DEFAULT_DRIVE_PINGROUP(CDEV2,           0x888),
83         DEFAULT_DRIVE_PINGROUP(CSUS,            0x88c),
84         DEFAULT_DRIVE_PINGROUP(DAP1,            0x890),
85         DEFAULT_DRIVE_PINGROUP(DAP2,            0x894),
86         DEFAULT_DRIVE_PINGROUP(DBG,             0x8a0),
87         DEFAULT_DRIVE_PINGROUP(SDIO3,           0x8b0),
88         DEFAULT_DRIVE_PINGROUP(UART2,           0x8c0),
89         DEFAULT_DRIVE_PINGROUP(UART3,           0x8c4),
90         DEFAULT_DRIVE_PINGROUP(PAD,             0x8e8),
91         DEFAULT_DRIVE_PINGROUP(SDIO1,           0x8ec),
92         DEFAULT_DRIVE_PINGROUP(DDC,             0x8fc),
93         DEFAULT_DRIVE_PINGROUP(GMA,             0x900),
94         DEFAULT_DRIVE_PINGROUP(GME,             0x910),
95         DEFAULT_DRIVE_PINGROUP(OWR,             0x920),
96         DEFAULT_DRIVE_PINGROUP(CEC,             0x938),
97         DEFAULT_DRIVE_PINGROUP(DAP5,            0x998),
98         DEFAULT_DRIVE_PINGROUP(DMIC0,           0x9a0),
99         DEFAULT_DRIVE_PINGROUP(DMIC1,           0x9a4),
100         DEFAULT_DRIVE_PINGROUP(AO3,             0x9a8),
101         DEFAULT_DRIVE_PINGROUP(SPI2,            0x9ac),
102         DEFAULT_DRIVE_PINGROUP(AO0,             0x9b0),
103         DEFAULT_DRIVE_PINGROUP(DCA,             0x9b8),
104         DEFAULT_DRIVE_PINGROUP(SPI3,            0x9bc),
105
106 };
107
108 #define PINGROUP(pg_name, gpio_nr, vdd, f0, f1, f2, f3, fs, iod, reg)   \
109         [TEGRA_PINGROUP_ ## pg_name] = {                        \
110                 .name = #pg_name,                               \
111                 .vddio = TEGRA_VDDIO_ ## vdd,                   \
112                 .funcs = {                                      \
113                         TEGRA_MUX_ ## f0,                       \
114                         TEGRA_MUX_ ## f1,                       \
115                         TEGRA_MUX_ ## f2,                       \
116                         TEGRA_MUX_ ## f3,                       \
117                 },                                              \
118                 .gpionr = TEGRA_GPIO_ ## gpio_nr,               \
119                 .func_safe = TEGRA_MUX_ ## fs,                  \
120                 .tri_bank = 1,                                  \
121                 .tri_reg = ((reg) - MUXCTL_REG_A),              \
122                 .tri_bit = 4,                                   \
123                 .mux_bank = 1,                                  \
124                 .mux_reg = ((reg) - MUXCTL_REG_A),              \
125                 .mux_bit = 0,                                   \
126                 .pupd_bank = 1,                                 \
127                 .pupd_reg = ((reg) - MUXCTL_REG_A),             \
128                 .pupd_bit = 2,                                  \
129                 .io_default = TEGRA_PIN_ ## iod,                \
130                 .od_bit = 6,                                    \
131                 .lock_bit = 7,                                  \
132                 .ioreset_bit = 8,                               \
133         }
134
135 /* !!!FIXME!!! FILL IN fSafe COLUMN IN TABLE ....... */
136 #define PINGROUPS       \
137         /*       NAME             GPIO          VDD         f0          f1          f2          f3           fSafe       io     reg */\
138         PINGROUP(SDMMC1_CLK,      PA0,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3048),\
139         PINGROUP(SDMMC1_CMD,      PA1,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x304c),\
140         PINGROUP(SDMMC1_DAT3,     PA2,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3050),\
141         PINGROUP(SDMMC1_DAT2,     PA3,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3054),\
142         PINGROUP(SDMMC1_DAT1,     PA4,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3058),\
143         PINGROUP(SDMMC1_DAT0,     PA5,          SDMMC1,     SDMMC1,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x305c),\
144         PINGROUP(DDC_SCL,         PN6,          LCD,        I2C4,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3114),\
145         PINGROUP(DDC_SDA,         PN7,          LCD,        I2C4,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3118),\
146         PINGROUP(UART2_RXD,       PF6,          UART,       UARTB,      I2S3,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3164),\
147         PINGROUP(UART2_TXD,       PF5,          UART,       UARTB,      I2S3,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3168),\
148         PINGROUP(UART2_RTS_N,     PF7,          UART,       UARTB,      I2S3,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x316c),\
149         PINGROUP(UART2_CTS_N,     PG0,          UART,       UARTB,      I2S3,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3170),\
150         PINGROUP(UART3_TXD,       PK0,          SYS,        UARTC,      SPI2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3174),\
151         PINGROUP(UART3_RXD,       PK1,          SYS,        UARTC,      SPI2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3178),\
152         PINGROUP(UART3_CTS_N,     PK3,          SYS,        UARTC,      SPI2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x317c),\
153         PINGROUP(UART3_RTS_N,     PK2,          SYS,        UARTC,      SPI2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3180),\
154         PINGROUP(GEN2_I2C_SCL,    PL5,          SYS,        I2C2,       UARTD,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3250),\
155         PINGROUP(GEN2_I2C_SDA,    PL6,          SYS,        I2C2,       UARTD,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3254),\
156         PINGROUP(SDMMC4_CLK,      PC0,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3258),\
157         PINGROUP(SDMMC4_CMD,      PC1,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x325c),\
158         PINGROUP(SDMMC4_DAT0,     PC2,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3260),\
159         PINGROUP(SDMMC4_DAT1,     PC3,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3264),\
160         PINGROUP(SDMMC4_DAT2,     PC4,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3268),\
161         PINGROUP(SDMMC4_DAT3,     PC5,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x326c),\
162         PINGROUP(SDMMC4_DAT4,     PC6,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3270),\
163         PINGROUP(SDMMC4_DAT5,     PC7,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3274),\
164         PINGROUP(SDMMC4_DAT6,     PD0,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3278),\
165         PINGROUP(SDMMC4_DAT7,     PD1,          SDMMC4,     SDMMC4,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x327c),\
166         PINGROUP(CAM_I2C_SCL,     PR2,          CAM,        I2C3,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3290),\
167         PINGROUP(CAM_I2C_SDA,     PR3,          CAM,        I2C3,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3294),\
168         PINGROUP(JTAG_RTCK,       INVALID,      SYS,        RTCK,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x32b0),\
169         PINGROUP(PWR_I2C_SCL,     PV7,          SYS,        I2CPWR,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x32b4),\
170         PINGROUP(PWR_I2C_SDA,     PW0,          SYS,        I2CPWR,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x32b8),\
171         PINGROUP(KB_ROW0,         PV1,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x32bc),\
172         PINGROUP(KB_ROW1,         PV2,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x32c0),\
173         PINGROUP(KB_ROW2,         PV3,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x32c4),\
174         PINGROUP(KB_COL0,         PV4,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x32fc),\
175         PINGROUP(KB_COL1,         PV5,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3300),\
176         PINGROUP(KB_COL2,         PV6,          SYS,        KBC,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3304),\
177         PINGROUP(RF_CLK_REQ,      INVALID,      SYS,        SYSCLK,     RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3320),\
178         PINGROUP(SOC_PWR_REQ,     INVALID,      SYS,        PWRON,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3324),\
179         PINGROUP(CPU_PWR_REQ,     INVALID,      SYS,        CPU,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3328),\
180         PINGROUP(PWR_INT_N,       INVALID,      SYS,        PMI,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x332c),\
181         PINGROUP(CLK_32K_IN,      INVALID,      SYS,        CLK,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3330),\
182         PINGROUP(OWR,             PV0,          SYS,        OWR,        RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3334),\
183         PINGROUP(DAP1_FS,         PE0,          AUDIO,      I2S0,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3338),\
184         PINGROUP(DAP1_DIN,        PE1,          AUDIO,      I2S0,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x333c),\
185         PINGROUP(DAP1_DOUT,       PE2,          AUDIO,      I2S0,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3340),\
186         PINGROUP(DAP1_SCLK,       PE3,          AUDIO,      I2S0,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3344),\
187         PINGROUP(CLK1_OUT,        PF0,          AUDIO,      EXTPERIPH1, RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x334c),\
188         PINGROUP(DAP2_FS,         PK4,          AUDIO,      I2S1,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3358),\
189         PINGROUP(DAP2_DIN,        PK6,          AUDIO,      I2S1,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x335c),\
190         PINGROUP(DAP2_DOUT,       PK7,          AUDIO,      I2S1,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3360),\
191         PINGROUP(DAP2_SCLK,       PK5,          AUDIO,      I2S1,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3364),\
192         PINGROUP(SPI2_MOSI,       PH2,          AUDIO,      SPI2,       DTV,        RSVD2,      RSVD3,       RSVD,      INPUT,  0x3368),\
193         PINGROUP(SPI2_MISO,       PH3,          AUDIO,      SPI2,       DTV,        RSVD2,      RSVD3,       RSVD,      INPUT,  0x336c),\
194         PINGROUP(SPI2_CS0_N,      PH5,          AUDIO,      SPI2,       DTV,        RSVD2,      RSVD3,       RSVD,      INPUT,  0x3370),\
195         PINGROUP(SPI2_SCK,        PH4,          AUDIO,      SPI2,       DTV,        RSVD2,      RSVD3,       RSVD,      INPUT,  0x3374),\
196         PINGROUP(SPI2_CS1_N,      PH6,          AUDIO,      SPI2,       SPI1,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3388),\
197         PINGROUP(SPI2_CS2_N,      PH1,          AUDIO,      SPI2,       SPI1,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x338c),\
198         PINGROUP(SDMMC3_CLK,      PB0,          SDMMC3,     SDMMC3,     TRACE,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3390),\
199         PINGROUP(SDMMC3_CMD,      PB1,          SDMMC3,     SDMMC3,     TRACE,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3394),\
200         PINGROUP(SDMMC3_DAT0,     PB5,          SDMMC3,     SDMMC3,     TRACE,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3398),\
201         PINGROUP(SDMMC3_DAT1,     PB4,          SDMMC3,     SDMMC3,     TRACE,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x339c),\
202         PINGROUP(SDMMC3_DAT2,     PB3,          SDMMC3,     SDMMC3,     TRACE,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x33a0),\
203         PINGROUP(SDMMC3_DAT3,     PB2,          SDMMC3,     SDMMC3,     TRACE,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x33a4),\
204         PINGROUP(RESET_OUT_N,     INVALID,      SYS,        RESET_OUT_N,RSVD1,      RSVD2,      RSVD3,       RSVD,      OUTPUT, 0x3408),\
205         PINGROUP(ALS_PROX_INT_L,  PN0,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x340c),\
206         PINGROUP(AP_GPS_EN,       PH7,          AUDIO,      RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3410),\
207         PINGROUP(AP_GPS_RST,      PI0,          AUDIO,      RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3414),\
208         PINGROUP(AP_WAKE_BT,      PM1,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3418),\
209         PINGROUP(AP_WIFI_EN,      PL7,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x341c),\
210         PINGROUP(AP_WIFI_RST,     PM0,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3420),\
211         PINGROUP(BT_RESET_L,      PM3,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3428),\
212         PINGROUP(BT_WAKE_AP,      PM2,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x342c),\
213         PINGROUP(DAP5_DIN,        PG6,          AUDIO,      I2S4,       SPI1,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3430),\
214         PINGROUP(DAP5_DOUT,       PG7,          AUDIO,      I2S4,       SPI1,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3434),\
215         PINGROUP(DAP5_FS,         PG5,          AUDIO,      I2S4,       SPI1,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3438),\
216         PINGROUP(DAP5_SCLK,       PH0,          AUDIO,      I2S4,       SPI1,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x343c),\
217         PINGROUP(DCA_LPM,         PG2,          AUDIO,      DISPLAYA,   DISPLAYB,   PWM3,       RSVD3,       RSVD,      INPUT,  0x3440),\
218         PINGROUP(DCA_LSC,         PG3,          AUDIO,      DISPLAYA,   DISPLAYB,   RSVD2,      RSVD3,       RSVD,      INPUT,  0x3444),\
219         PINGROUP(DCA_LSPII,       PG1,          AUDIO,      DISPLAYA,   DISPLAYB,   RSVD2,      RSVD3,       RSVD,      INPUT,  0x3448),\
220         PINGROUP(DCA_LVS,         PG4,          AUDIO,      DISPLAYA,   DISPLAYB,   RSVD2,      RSVD3,       RSVD,      INPUT,  0x344c),\
221         PINGROUP(DMIC0_CLK,       PE4,          AUDIO,      DMIC0,      I2S2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3450),\
222         PINGROUP(DMIC0_DATA,      PE5,          AUDIO,      DMIC0,      I2S2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3454),\
223         PINGROUP(DMIC1_CLK,       PE6,          AUDIO,      DMIC1,      I2S2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x3458),\
224         PINGROUP(DMIC1_DATA,      PE7,          AUDIO,      DMIC1,      I2S2,       RSVD2,      RSVD3,       RSVD,      INPUT,  0x345c),\
225         PINGROUP(GPS_AP_INT,      PI1,          AUDIO,      RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3460),\
226         PINGROUP(AP_READY,        PN4,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3464),\
227         PINGROUP(I2C1_SCL,        PF1,          AUDIO,      I2C1,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3468),\
228         PINGROUP(I2C1_SDA,        PF2,          AUDIO,      I2C1,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x346c),\
229         PINGROUP(I2C6_SCL,        PF3,          AUDIO,      I2C6,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3470),\
230         PINGROUP(I2C6_SDA,        PF4,          AUDIO,      I2C6,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3474),\
231         PINGROUP(MODEM_WAKE_AP,   PN3,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x347c),\
232         PINGROUP(MOTION_INT_L,    PM7,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3480),\
233         PINGROUP(NFC_DATA_EN,     PM6,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3484),\
234         PINGROUP(NFC_EN,          PM5,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3488),\
235         PINGROUP(NFC_INT_L,       PM4,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x348c),\
236         PINGROUP(SPI3_CS0_N,      PL3,          UART,       SPI3,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3494),\
237         PINGROUP(SPI3_CS1_N,      PL4,          UART,       SPI3,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3498),\
238         PINGROUP(SPI3_MISO,       PL1,          UART,       SPI3,       UARTD,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x349c),\
239         PINGROUP(SPI3_MOSI,       PL0,          UART,       SPI3,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34a0),\
240         PINGROUP(SPI3_SCLK,       PL2,          UART,       SPI3,       UARTD,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34a4),\
241         PINGROUP(TOUCH_INT_L,     PN1,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34a8),\
242         PINGROUP(TOUCH_RESET_L,   PN2,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34ac),\
243         PINGROUP(GPIO_PO0,        PO0,          UART,       UARTD,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34b0),\
244         PINGROUP(GPIO_PO1,        PO1,          UART,       UARTD,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34b4),\
245         PINGROUP(GPIO_PO2,        PO2,          UART,       UARTD,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34b8),\
246         PINGROUP(GPIO_PO3,        PO3,          UART,       UARTD,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34bc),\
247         PINGROUP(CAM1_MCLK,       PR0,          CAM,        VI,         VI_ALT1,    VI_ALT3,    RSVD3,       RSVD,      INPUT,  0x34c0),\
248         PINGROUP(CAM2_MCLK,       PR1,          CAM,        VI,         VI_ALT1,    VI_ALT3,    RSVD3,       RSVD,      INPUT,  0x34c4),\
249         PINGROUP(GPIO_PS0,        PS0,          CAM,        VGP1,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34c8),\
250         PINGROUP(GPIO_PS1,        PS1,          CAM,        VGP2,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34cc),\
251         PINGROUP(GPIO_PS2,        PS2,          CAM,        VGP3,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34d0),\
252         PINGROUP(GPIO_PS3,        PS3,          CAM,        VGP4,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34d4),\
253         PINGROUP(GPIO_PS4,        PS4,          CAM,        VGP5,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34d8),\
254         PINGROUP(GPIO_PS5,        PS5,          CAM,        VGP6,       RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34dc),\
255         PINGROUP(DDR0_A0,         PP0,          DDR,        DDR0,       UARTA,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34e4),\
256         PINGROUP(DDR0_A1,         PP1,          DDR,        DDR0,       UARTA,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34e8),\
257         PINGROUP(DDR0_A2,         PP2,          DDR,        DDR0,       UARTA,      RSVD2,      SPI3,        RSVD,      INPUT,  0x34ec),\
258         PINGROUP(DDR0_A3,         PP3,          DDR,        DDR0,       UARTA,      RSVD2,      SPI3,        RSVD,      INPUT,  0x34f0),\
259         PINGROUP(UART1_RXD,       PQ1,          UART,       UARTA,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34f4),\
260         PINGROUP(UART1_TXD,       PQ0,          UART,       UARTA,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34f8),\
261         PINGROUP(UART1_RTS_N,     PQ2,          UART,       UARTA,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x34fc),\
262         PINGROUP(UART1_CTS_N,     PQ3,          UART,       UARTA,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3500),\
263         PINGROUP(GPIO_PO4,        PO4,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3504),\
264         PINGROUP(GPIO_PO5,        PO5,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3508),\
265         PINGROUP(GPIO_PO6,        PO6,          UART,       RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x350c),\
266         PINGROUP(PG_OC,           INVALID,      SYS,        RSVD0,      RSVD1,      RSVD2,      RSVD3,       RSVD,      INPUT,  0x3510),
267
268 const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
269         PINGROUPS
270 };
271
272 #undef PINGROUP
273
274 #define PINGROUP(pg_name, gpio_nr, vdd, f0, f1, f2, f3, fs, iod, reg)   \
275         [TEGRA_GPIO_##gpio_nr] =  TEGRA_PINGROUP_ ##pg_name\
276
277 const int gpio_to_pingroup[TEGRA_MAX_GPIO] = {
278         PINGROUPS
279
280 };
281
282 #define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
283         {                                                       \
284                 .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
285                 .hsm = TEGRA_HSM_##_hsm,                        \
286                 .schmitt = TEGRA_SCHMITT_##_schmitt,            \
287                 .drive = TEGRA_DRIVE_##_drive,                  \
288                 .pull_down = TEGRA_PULL_##_pulldn_drive,        \
289                 .pull_up = TEGRA_PULL_##_pullup_drive,          \
290                 .slew_rising = TEGRA_SLEW_##_pulldn_slew,       \
291                 .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
292         }
293
294 static __initdata struct tegra_drive_pingroup_config t14x_def_drive_pinmux[] = {
295 };
296
297 #ifdef CONFIG_PM_SLEEP
298
299 static u32 pinmux_reg[TEGRA_MAX_PINGROUP +
300                       ARRAY_SIZE(tegra_soc_drive_pingroups)];
301
302 static int tegra14x_pinmux_suspend(void)
303 {
304         unsigned int i;
305         u32 *ctx = pinmux_reg;
306
307         for (i = 0; i < TEGRA_MAX_PINGROUP; i++)
308                 *ctx++ = pg_readl(tegra_soc_pingroups[i].mux_bank,
309                                 tegra_soc_pingroups[i].mux_reg);
310
311         for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
312                 *ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg_bank,
313                                 tegra_soc_drive_pingroups[i].reg);
314
315         return 0;
316 }
317
318 static void tegra14x_pinmux_resume(void)
319 {
320         unsigned int i;
321         u32 *ctx = pinmux_reg;
322         u32 *tmp = pinmux_reg;
323         u32 reg_value;
324
325         for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
326                 reg_value = *tmp++;
327                 reg_value |= TRISTATE;
328                 pg_writel(reg_value, tegra_soc_pingroups[i].mux_bank,
329                         tegra_soc_pingroups[i].mux_reg);
330         }
331
332         writel(0x400fffff, pmc + PMC_IO_DPD_REQ_0);
333         writel(0x40001fff, pmc + PMC_IO_DPD2_REQ_0);
334
335         for (i = 0; i < TEGRA_MAX_PINGROUP; i++)
336                 pg_writel(*ctx++, tegra_soc_pingroups[i].mux_bank,
337                         tegra_soc_pingroups[i].mux_reg);
338
339         for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
340                 pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg_bank,
341                         tegra_soc_drive_pingroups[i].reg);
342 }
343
344 static struct syscore_ops tegra14x_pinmux_syscore_ops = {
345         .suspend = tegra14x_pinmux_suspend,
346         .resume = tegra14x_pinmux_resume,
347 };
348 #endif
349
350 void __devinit tegra14x_pinmux_init(const struct tegra_pingroup_desc **pg,
351                 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
352                 int *pgdrive_max, const int **gpiomap, int *gpiomap_max)
353 {
354         *pg = tegra_soc_pingroups;
355         *pg_max = TEGRA_MAX_PINGROUP;
356         *pgdrive = tegra_soc_drive_pingroups;
357         *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
358         *gpiomap = gpio_to_pingroup;
359         *gpiomap_max = TEGRA_MAX_GPIO;
360
361 #ifdef CONFIG_PM_SLEEP
362         register_syscore_ops(&tegra14x_pinmux_syscore_ops);
363 #endif
364 }
365
366 void tegra14x_default_pinmux(void)
367 {
368         tegra_drive_pinmux_config_table(t14x_def_drive_pinmux,
369                                         ARRAY_SIZE(t14x_def_drive_pinmux));
370 }