ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / latency_allowance.c
1 /*
2  * arch/arm/mach-tegra/latency_allowance.c
3  *
4  * Copyright (C) 2011-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/debugfs.h>
21 #include <linux/moduleparam.h>
22 #include <linux/seq_file.h>
23 #include <linux/err.h>
24 #include <linux/spinlock_types.h>
25 #include <linux/spinlock.h>
26 #include <linux/stringify.h>
27 #include <linux/clk.h>
28 #include <linux/clk/tegra.h>
29 #include <linux/syscore_ops.h>
30 #include <linux/tegra-soc.h>
31 #include <asm/bug.h>
32 #include <asm/io.h>
33 #include <asm/string.h>
34 #include <mach/latency_allowance.h>
35 #include "la_priv.h"
36
37 #define TEST_LA_CODE            0
38
39 /* Bug 995270 */
40 #define HACK_LA_FIFO 1
41 static int default_set_la(enum tegra_la_id id, unsigned int bw_mbps);
42
43 static struct la_chip_specific cs;
44 module_param_named(disable_la, cs.disable_la, bool, S_IRUGO | S_IWUSR);
45 module_param_named(disable_ptsa, cs.disable_ptsa, bool, S_IRUGO | S_IWUSR);
46 module_param_named(disable_disp_ptsa,
47         cs.disable_disp_ptsa, bool, S_IRUGO | S_IWUSR);
48 module_param_named(disable_bbc_ptsa,
49         cs.disable_bbc_ptsa, bool, S_IRUGO | S_IWUSR);
50
51 /* FIXME!!:- This function needs to be implemented properly. */
52 unsigned int tegra_get_dvfs_time_nsec(unsigned long emc_freq_mhz)
53 {
54         if ((emc_freq_mhz >= 100) && (emc_freq_mhz <= 120))
55                 return 6679;
56         else if ((emc_freq_mhz >= 200) && (emc_freq_mhz <= 220))
57                 return 3954;
58         else if ((emc_freq_mhz >= 400) && (emc_freq_mhz <= 420))
59                 return 2396;
60         else if ((emc_freq_mhz >= 780) && (emc_freq_mhz <= 800))
61                 return 1583;
62         else if ((emc_freq_mhz >= 920) && (emc_freq_mhz <= 940))
63                 return 1452;
64         else
65                 return 3000;
66 }
67
68 static void init_chip_specific(void)
69 {
70         enum tegra_chipid cid;
71
72         if (!tegra_platform_is_silicon())
73                 return;
74
75         cs.set_la = default_set_la;
76         memset(&cs.id_to_index[0], 0xFF, sizeof(cs.id_to_index));
77         spin_lock_init(&cs.lock);
78
79         cid = tegra_get_chipid();
80
81         switch (cid) {
82 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
83         case TEGRA_CHIPID_TEGRA3:
84                 tegra_la_get_t3_specific(&cs);
85                 break;
86 #endif
87 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
88         case TEGRA_CHIPID_TEGRA11:
89                 tegra_la_get_t11x_specific(&cs);
90                 break;
91 #endif
92 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
93         case TEGRA_CHIPID_TEGRA14:
94                 tegra_la_get_t14x_specific(&cs);
95                 break;
96 #endif
97 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
98         case TEGRA_CHIPID_TEGRA12:
99                 tegra_la_get_t12x_specific(&cs);
100                 break;
101 #endif
102         default:
103                 cs.set_la = NULL;
104         }
105 }
106
107 struct la_to_dc_params tegra_get_la_to_dc_params(void)
108 {
109         return cs.la_params;
110 }
111
112 static void set_la(struct la_client_info *ci, int la)
113 {
114         unsigned long reg_read;
115         unsigned long reg_write;
116         int idx = cs.id_to_index[ci->id];
117
118         spin_lock(&cs.lock);
119         reg_read = readl(ci->reg_addr);
120         reg_write = (reg_read & ~ci->mask) |
121                         (la << ci->shift);
122         writel(reg_write, ci->reg_addr);
123         cs.scaling_info[idx].la_set = la;
124         ci->la_set = la;
125         la_debug("reg_addr=0x%x, read=0x%x, write=0x%x",
126                 (u32)ci->reg_addr, (u32)reg_read, (u32)reg_write);
127         spin_unlock(&cs.lock);
128 }
129
130 static int default_set_la(enum tegra_la_id id, unsigned int bw_mbps)
131 {
132         int ideal_la;
133         int la_to_set;
134         unsigned int fifo_size_in_atoms;
135         int bytes_per_atom = cs.atom_size;
136         const int fifo_scale = 4;               /* 25% of the FIFO */
137         struct la_client_info *ci;
138         int idx = cs.id_to_index[id];
139
140         if (!tegra_platform_is_silicon())
141                 return 0;
142
143         VALIDATE_ID(id, &cs);
144         VALIDATE_BW(bw_mbps);
145
146         ci = &cs.la_info_array[idx];
147         fifo_size_in_atoms = ci->fifo_size_in_atoms;
148
149 #ifdef CONFIG_TEGRA_MC_PTSA
150         if (id >= TEGRA_LA_DISPLAY_0A && id <= TEGRA_LA_DISPLAY_HCB) {
151                 cs.disp_bw_array[id - TEGRA_LA_DISPLAY_0A] = bw_mbps;
152                 if (cs.update_display_ptsa_rate)
153                         cs.update_display_ptsa_rate(cs.disp_bw_array);
154         }
155 #endif
156 #if HACK_LA_FIFO
157         /* pretend that our FIFO is only as deep as the lowest fullness
158          * we expect to see */
159         if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_HCB))
160                 fifo_size_in_atoms /= fifo_scale;
161 #endif
162
163         if (bw_mbps == 0) {
164                 la_to_set = cs.la_max_value;
165         } else {
166                 ideal_la = (fifo_size_in_atoms * bytes_per_atom * 1000) /
167                            (bw_mbps * cs.ns_per_tick);
168                 la_to_set = ideal_la -
169                             (ci->expiration_in_ns / cs.ns_per_tick) - 1;
170         }
171
172         la_debug("\n%s:id=%d,idx=%d, bw=%dmbps, la_to_set=%d",
173                 __func__, id, idx, bw_mbps, la_to_set);
174         la_to_set = (la_to_set < 0) ? 0 : la_to_set;
175         cs.scaling_info[idx].actual_la_to_set = la_to_set;
176         la_to_set = (la_to_set > cs.la_max_value) ? cs.la_max_value : la_to_set;
177
178         set_la(ci, la_to_set);
179         return 0;
180 }
181
182 int tegra_set_disp_latency_allowance(enum tegra_la_id id,
183                                         unsigned int bw_mbps,
184                                         struct dc_to_la_params disp_params) {
185         if (cs.set_disp_la)
186                 return cs.set_disp_la(id, bw_mbps, disp_params);
187         else if (cs.set_la)
188                 return cs.set_la(id, bw_mbps);
189         return 0;
190 }
191
192 /* Sets latency allowance based on clients memory bandwitdh requirement.
193  * Bandwidth passed is in mega bytes per second.
194  */
195 int tegra_set_latency_allowance(enum tegra_la_id id, unsigned int bw_mbps)
196 {
197         if (cs.set_la)
198                 return cs.set_la(id, bw_mbps);
199         return 0;
200 }
201
202 int tegra_set_camera_ptsa(enum tegra_la_id id,
203                         unsigned int bw_mbps,
204                         int is_hiso)
205 {
206         if (cs.update_camera_ptsa_rate)
207                 return cs.update_camera_ptsa_rate(id, bw_mbps, is_hiso);
208         else if (cs.set_la)
209                 return cs.set_la(id, bw_mbps);
210         return 0;
211 }
212
213 /* Thresholds for scaling are specified in % of fifo freeness.
214  * If threshold_low is specified as 20%, it means when the fifo free
215  * between 0 to 20%, use la as programmed_la.
216  * If threshold_mid is specified as 50%, it means when the fifo free
217  * between 20 to 50%, use la as programmed_la/2 .
218  * If threshold_high is specified as 80%, it means when the fifo free
219  * between 50 to 80%, use la as programmed_la/4.
220  * When the fifo is free between 80 to 100%, use la as 0(highest priority).
221  */
222 int tegra_enable_latency_scaling(enum tegra_la_id id,
223                                     unsigned int threshold_low,
224                                     unsigned int threshold_mid,
225                                     unsigned int threshold_high)
226 {
227         if (cs.enable_la_scaling)
228                 return cs.enable_la_scaling(id, threshold_low,
229                         threshold_mid, threshold_high);
230         return 0;
231 }
232
233 void tegra_disable_latency_scaling(enum tegra_la_id id)
234 {
235         if (cs.disable_la_scaling) {
236                 cs.disable_la_scaling(id);
237         }
238 }
239
240 void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick)
241 {
242         int i = 0;
243         int la;
244         unsigned long reg_read;
245         unsigned long reg_write;
246         unsigned long scale_factor = new_ns_per_tick / cs.ns_per_tick;
247
248         if (scale_factor > 1) {
249                 spin_lock(&cs.lock);
250                 cs.ns_per_tick = new_ns_per_tick;
251                 for (i = 0; i < cs.la_info_array_size - 1; i++) {
252                         reg_read = readl(cs.la_info_array[i].reg_addr);
253                         la = ((reg_read & cs.la_info_array[i].mask) >>
254                                 cs.la_info_array[i].shift) / scale_factor;
255
256                         reg_write = (reg_read & ~cs.la_info_array[i].mask) |
257                                         (la << cs.la_info_array[i].shift);
258                         writel(reg_write, cs.la_info_array[i].reg_addr);
259                         cs.scaling_info[i].la_set = la;
260                 }
261                 spin_unlock(&cs.lock);
262
263 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
264                 /* Re-scale G2PR, G2SR, G2DR, G2DW with updated ns_per_tick */
265                 tegra_set_latency_allowance(TEGRA_LA_G2PR, 20);
266                 tegra_set_latency_allowance(TEGRA_LA_G2SR, 20);
267                 tegra_set_latency_allowance(TEGRA_LA_G2DR, 20);
268                 tegra_set_latency_allowance(TEGRA_LA_G2DW, 20);
269 #endif
270         }
271 }
272
273 static int la_regs_show(struct seq_file *s, void *unused)
274 {
275         int i;
276         unsigned long la;
277
278         /* iterate the list, but don't print MAX_ID */
279         for (i = 0; i < cs.la_info_array_size - 1; i++) {
280                 la = (readl(cs.la_info_array[i].reg_addr) &
281                         cs.la_info_array[i].mask) >> cs.la_info_array[i].shift;
282                 seq_printf(s, "%-16s: %4lu\n", cs.la_info_array[i].name, la);
283         }
284
285         return 0;
286 }
287
288 static int dbg_la_regs_open(struct inode *inode, struct file *file)
289 {
290         return single_open(file, la_regs_show, inode->i_private);
291 }
292
293 static const struct file_operations regs_fops = {
294         .open           = dbg_la_regs_open,
295         .read           = seq_read,
296         .llseek         = seq_lseek,
297         .release        = single_release,
298 };
299
300 static int __init tegra_latency_allowance_debugfs_init(void)
301 {
302         if (cs.latency_debug_dir)
303                 return 0;
304
305         cs.latency_debug_dir = debugfs_create_dir("tegra_latency", NULL);
306
307         debugfs_create_file("la_info", S_IRUGO, cs.latency_debug_dir, NULL,
308                 &regs_fops);
309
310         return 0;
311 }
312
313 static int tegra_la_suspend(void)
314 {
315         if (cs.suspend)
316                 return cs.suspend();
317         return 0;
318 }
319
320 static void tegra_la_resume(void)
321 {
322         int i;
323
324         if (cs.resume) {
325                 cs.resume();
326                 return;
327         }
328         for (i = 0; i < cs.la_info_array_size; i++) {
329                 if (cs.la_info_array[i].la_set)
330                         set_la(&cs.la_info_array[i],
331                                 cs.la_info_array[i].la_set);
332         }
333         if (cs.init_ptsa)
334                 cs.init_ptsa();
335 }
336
337 static struct syscore_ops tegra_la_syscore_ops = {
338         .suspend = tegra_la_suspend,
339         .resume = tegra_la_resume,
340 };
341
342 static __init int tegra_la_syscore_init(void)
343 {
344         register_syscore_ops(&tegra_la_syscore_ops);
345         return 0;
346 }
347
348 static int __init tegra_latency_allowance_init(void)
349 {
350         unsigned int i;
351         enum tegra_chipid cid = tegra_get_chipid();
352
353         init_chip_specific();
354
355         for (i = 0; i < cs.la_info_array_size; i++)
356                 cs.id_to_index[cs.la_info_array[i].id] = i;
357
358         for (i = 0; i < cs.la_info_array_size; i++) {
359                 if (cs.la_info_array[i].init_la) {
360                         unsigned int la_to_set = 0;
361
362                         if ((cid == TEGRA_CHIPID_TEGRA12) &&
363                                 (cs.la_info_array[i].id == ID(MSENCSRD))) {
364                                 /* This is a special case. */
365                                 struct clk *emc_clk = clk_get(NULL, "emc");
366                                 unsigned long emc_freq_mhz =
367                                                         clk_get_rate(emc_clk) /
368                                                         1000000;
369                                 unsigned int val_1 = 53;
370                                 unsigned int val_2 = 24;
371
372                                 if (210 > emc_freq_mhz)
373                                         val_1 = val_1 * 210 / emc_freq_mhz;
374
375                                 if (574 > emc_freq_mhz)
376                                         val_2 = val_2 * 574 / emc_freq_mhz;
377
378                                 la_to_set = min3((unsigned int)
379                                                         T12X_MC_LA_MAX_VALUE,
380                                                 val_1,
381                                                 val_2);
382                         } else if (cs.la_info_array[i].la_ref_clk_mhz != 0) {
383                                 /* In this case we need to scale LA with emc
384                                    frequency. */
385                                 struct clk *emc_clk = clk_get(NULL, "emc");
386                                 unsigned long emc_freq_mhz =
387                                                         clk_get_rate(emc_clk) /
388                                                         1000000;
389
390                                 if (cs.la_info_array[i].la_ref_clk_mhz <=
391                                         emc_freq_mhz) {
392                                         la_to_set =
393                                                 min((unsigned long)
394                                                 cs.la_info_array[i].init_la,
395                                                 (unsigned long)
396                                                         T12X_MC_LA_MAX_VALUE);
397                                 } else {
398                                         la_to_set =
399                                         min(cs.la_info_array[i].init_la *
400                                         cs.la_info_array[i].la_ref_clk_mhz /
401                                         emc_freq_mhz,
402                                         (unsigned long)T12X_MC_LA_MAX_VALUE);
403                                 }
404                         } else
405                                 la_to_set = cs.la_info_array[i].init_la;
406
407                         set_la(&cs.la_info_array[i],
408                                 la_to_set);
409                 }
410         }
411 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
412         tegra_set_latency_allowance(TEGRA_LA_G2PR, 20);
413         tegra_set_latency_allowance(TEGRA_LA_G2SR, 20);
414         tegra_set_latency_allowance(TEGRA_LA_G2DR, 20);
415         tegra_set_latency_allowance(TEGRA_LA_G2DW, 20);
416 #endif
417
418         if (cs.init_ptsa)
419                 cs.init_ptsa();
420         return 0;
421 }
422
423 late_initcall(tegra_latency_allowance_debugfs_init);
424 subsys_initcall(tegra_la_syscore_init);
425 core_initcall(tegra_latency_allowance_init);
426
427 #if TEST_LA_CODE
428 #define PRINT_ID_IDX_MAPPING 0
429 static int __init test_la(void)
430 {
431         int i;
432         int err;
433         enum tegra_la_id id = 0;
434         int repeat_count = 5;
435
436 #if PRINT_ID_IDX_MAPPING
437         for (i = 0; i < ID(MAX_ID); i++)
438                 pr_info("ID=0x%x, Idx=0x%x", i, cs.id_to_index[i]);
439 #endif
440
441         do {
442                 for (id = 0; id < TEGRA_LA_MAX_ID; id++) {
443                         err = tegra_set_latency_allowance(id, 200);
444                         if (err)
445                                 la_debug("\n***tegra_set_latency_allowance,"
446                                         " err=%d", err);
447                 }
448
449                 for (id = 0; id < TEGRA_LA_MAX_ID; id++) {
450                         if (id >= ID(DISPLAY_0AB) && id <= ID(DISPLAY_HCB))
451                                 continue;
452                         if (id >= ID(VI_WSB) && id <= ID(VI_WY))
453                                 continue;
454                         err = tegra_enable_latency_scaling(id, 20, 50, 80);
455                         if (err)
456                                 la_debug("\n***tegra_enable_latency_scaling,"
457                                         " err=%d", err);
458                 }
459
460                 la_debug("la_scaling_enable_count =%d",
461                         cs.la_scaling_enable_count);
462                 for (id = 0; id < TEGRA_LA_MAX_ID; id++) {
463                         if (id >= ID(DISPLAY_0AB) && id <= ID(DISPLAY_HCB))
464                                 continue;
465                         if (id >= ID(VI_WSB) && id <= ID(VI_WY))
466                                 continue;
467                         tegra_disable_latency_scaling(id);
468                 }
469                 la_debug("la_scaling_enable_count=%d",
470                         cs.la_scaling_enable_count);
471         } while (--repeat_count);
472         return 0;
473 }
474
475 late_initcall(test_la);
476 #endif