ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / pinmux-t14.h
1 /*
2  * linux/arch/arm/mach-tegra/include/mach/pinmux-t14.h
3  *
4  * Copyright (C) 2012 NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #ifndef __MACH_TEGRA_PINMUX_T14_H
18 #define __MACH_TEGRA_PINMUX_T14_H
19
20 #define TEGRA_PINMUX_HAS_IO_DIRECTION   1
21
22 void tegra14x_default_pinmux(void);
23
24 enum tegra_pingroup {
25         TEGRA_PINGROUP_SDMMC1_CLK,
26         TEGRA_PINGROUP_SDMMC1_CMD,
27         TEGRA_PINGROUP_SDMMC1_DAT3,
28         TEGRA_PINGROUP_SDMMC1_DAT2,
29         TEGRA_PINGROUP_SDMMC1_DAT1,
30         TEGRA_PINGROUP_SDMMC1_DAT0,
31         TEGRA_PINGROUP_DDC_SCL,
32         TEGRA_PINGROUP_DDC_SDA,
33         TEGRA_PINGROUP_UART2_RXD,
34         TEGRA_PINGROUP_UART2_TXD,
35         TEGRA_PINGROUP_UART2_RTS_N,
36         TEGRA_PINGROUP_UART2_CTS_N,
37         TEGRA_PINGROUP_UART3_TXD,
38         TEGRA_PINGROUP_UART3_RXD,
39         TEGRA_PINGROUP_UART3_CTS_N,
40         TEGRA_PINGROUP_UART3_RTS_N,
41         TEGRA_PINGROUP_GEN2_I2C_SDA,
42         TEGRA_PINGROUP_GEN2_I2C_SCL,
43         TEGRA_PINGROUP_SDMMC4_CLK,
44         TEGRA_PINGROUP_SDMMC4_CMD,
45         TEGRA_PINGROUP_SDMMC4_DAT0,
46         TEGRA_PINGROUP_SDMMC4_DAT1,
47         TEGRA_PINGROUP_SDMMC4_DAT2,
48         TEGRA_PINGROUP_SDMMC4_DAT3,
49         TEGRA_PINGROUP_SDMMC4_DAT4,
50         TEGRA_PINGROUP_SDMMC4_DAT5,
51         TEGRA_PINGROUP_SDMMC4_DAT6,
52         TEGRA_PINGROUP_SDMMC4_DAT7,
53         TEGRA_PINGROUP_CAM_I2C_SCL,
54         TEGRA_PINGROUP_CAM_I2C_SDA,
55         TEGRA_PINGROUP_JTAG_RTCK,
56         TEGRA_PINGROUP_PWR_I2C_SCL,
57         TEGRA_PINGROUP_PWR_I2C_SDA,
58         TEGRA_PINGROUP_KB_ROW0,
59         TEGRA_PINGROUP_KB_ROW1,
60         TEGRA_PINGROUP_KB_ROW2,
61         TEGRA_PINGROUP_KB_COL0,
62         TEGRA_PINGROUP_KB_COL1,
63         TEGRA_PINGROUP_KB_COL2,
64         TEGRA_PINGROUP_RF_CLK_REQ,
65         TEGRA_PINGROUP_SOC_PWR_REQ,
66         TEGRA_PINGROUP_CPU_PWR_REQ,
67         TEGRA_PINGROUP_PWR_INT_N,
68         TEGRA_PINGROUP_CLK_32K_IN,
69         TEGRA_PINGROUP_OWR,
70         TEGRA_PINGROUP_DAP1_FS,
71         TEGRA_PINGROUP_DAP1_DIN,
72         TEGRA_PINGROUP_DAP1_DOUT,
73         TEGRA_PINGROUP_DAP1_SCLK,
74         TEGRA_PINGROUP_CLK1_OUT,
75         TEGRA_PINGROUP_DAP2_FS,
76         TEGRA_PINGROUP_DAP2_DIN,
77         TEGRA_PINGROUP_DAP2_DOUT,
78         TEGRA_PINGROUP_DAP2_SCLK,
79         TEGRA_PINGROUP_SPI2_MOSI,
80         TEGRA_PINGROUP_SPI2_MISO,
81         TEGRA_PINGROUP_SPI2_CS0_N,
82         TEGRA_PINGROUP_SPI2_SCK,
83         TEGRA_PINGROUP_SPI2_CS1_N,
84         TEGRA_PINGROUP_SPI2_CS2_N,
85         TEGRA_PINGROUP_SDMMC3_CLK,
86         TEGRA_PINGROUP_SDMMC3_CMD,
87         TEGRA_PINGROUP_SDMMC3_DAT0,
88         TEGRA_PINGROUP_SDMMC3_DAT1,
89         TEGRA_PINGROUP_SDMMC3_DAT2,
90         TEGRA_PINGROUP_SDMMC3_DAT3,
91         TEGRA_PINGROUP_RESET_OUT_N,
92         TEGRA_PINGROUP_ALS_PROX_INT_L,
93         TEGRA_PINGROUP_AP_GPS_EN,
94         TEGRA_PINGROUP_AP_GPS_RST,
95         TEGRA_PINGROUP_AP_WAKE_BT,
96         TEGRA_PINGROUP_AP_WIFI_EN,
97         TEGRA_PINGROUP_AP_WIFI_RST,
98         TEGRA_PINGROUP_BT_RESET_L,
99         TEGRA_PINGROUP_BT_WAKE_AP,
100         TEGRA_PINGROUP_DAP5_DIN,
101         TEGRA_PINGROUP_DAP5_DOUT,
102         TEGRA_PINGROUP_DAP5_FS,
103         TEGRA_PINGROUP_DAP5_SCLK,
104         TEGRA_PINGROUP_DCA_LPM,
105         TEGRA_PINGROUP_DCA_LSC,
106         TEGRA_PINGROUP_DCA_LSPII,
107         TEGRA_PINGROUP_DCA_LVS,
108         TEGRA_PINGROUP_DMIC0_CLK,
109         TEGRA_PINGROUP_DMIC0_DATA,
110         TEGRA_PINGROUP_DMIC1_CLK,
111         TEGRA_PINGROUP_DMIC1_DATA,
112         TEGRA_PINGROUP_GPS_AP_INT,
113         TEGRA_PINGROUP_AP_READY,
114         TEGRA_PINGROUP_HDMI_CEC,
115         TEGRA_PINGROUP_I2C1_SCL,
116         TEGRA_PINGROUP_I2C1_SDA,
117         TEGRA_PINGROUP_I2C6_SCL,
118         TEGRA_PINGROUP_I2C6_SDA,
119         TEGRA_PINGROUP_MODEM_WAKE_AP,
120         TEGRA_PINGROUP_MOTION_INT_L,
121         TEGRA_PINGROUP_NFC_DATA_EN,
122         TEGRA_PINGROUP_NFC_EN,
123         TEGRA_PINGROUP_NFC_INT_L,
124         TEGRA_PINGROUP_SPI3_CS0_N,
125         TEGRA_PINGROUP_SPI3_CS1_N,
126         TEGRA_PINGROUP_SPI3_MISO,
127         TEGRA_PINGROUP_SPI3_MOSI,
128         TEGRA_PINGROUP_SPI3_SCK,
129         TEGRA_PINGROUP_TOUCH_INT_L,
130         TEGRA_PINGROUP_TOUCH_RESET_L,
131         TEGRA_PINGROUP_GPIO_PO0,
132         TEGRA_PINGROUP_GPIO_PO1,
133         TEGRA_PINGROUP_GPIO_PO2,
134         TEGRA_PINGROUP_GPIO_PO3,
135         TEGRA_PINGROUP_CAM1_MCLK,
136         TEGRA_PINGROUP_CAM2_MCLK,
137         TEGRA_PINGROUP_GPIO_PS0,
138         TEGRA_PINGROUP_GPIO_PS1,
139         TEGRA_PINGROUP_GPIO_PS2,
140         TEGRA_PINGROUP_GPIO_PS3,
141         TEGRA_PINGROUP_GPIO_PS4,
142         TEGRA_PINGROUP_GPIO_PS5,
143         TEGRA_PINGROUP_DDR0_A0,
144         TEGRA_PINGROUP_DDR0_A1,
145         TEGRA_PINGROUP_DDR0_A2,
146         TEGRA_PINGROUP_DDR0_A3,
147         TEGRA_PINGROUP_UART1_RXD,
148         TEGRA_PINGROUP_UART1_TXD,
149         TEGRA_PINGROUP_UART1_RTS_N,
150         TEGRA_PINGROUP_UART1_CTS_N,
151         TEGRA_PINGROUP_GPIO_PO4,
152         TEGRA_PINGROUP_GPIO_PO5,
153         TEGRA_PINGROUP_GPIO_PO6,
154         TEGRA_PINGROUP_PG_OC,
155         TEGRA_PINGROUP_BCL,
156         TEGRA_MAX_PINGROUP,
157 };
158
159 enum tegra_drive_pingroup {
160         TEGRA_DRIVE_PINGROUP_AO1 = 0,
161         TEGRA_DRIVE_PINGROUP_AO2,
162         TEGRA_DRIVE_PINGROUP_CDEV1,
163         TEGRA_DRIVE_PINGROUP_CDEV2,
164         TEGRA_DRIVE_PINGROUP_CSUS,
165         TEGRA_DRIVE_PINGROUP_DAP1,
166         TEGRA_DRIVE_PINGROUP_DAP2,
167         TEGRA_DRIVE_PINGROUP_DBG,
168         TEGRA_DRIVE_PINGROUP_SDIO3,
169         TEGRA_DRIVE_PINGROUP_UART2,
170         TEGRA_DRIVE_PINGROUP_UART3,
171         TEGRA_DRIVE_PINGROUP_PAD,
172         TEGRA_DRIVE_PINGROUP_SDIO1,
173         TEGRA_DRIVE_PINGROUP_DDC,
174         TEGRA_DRIVE_PINGROUP_GMA,
175         TEGRA_DRIVE_PINGROUP_GME,
176         TEGRA_DRIVE_PINGROUP_OWR,
177         TEGRA_DRIVE_PINGROUP_UAD,
178         TEGRA_DRIVE_PINGROUP_CEC,
179         TEGRA_DRIVE_PINGROUP_DAP5,
180         TEGRA_DRIVE_PINGROUP_DMIC0,
181         TEGRA_DRIVE_PINGROUP_DMIC1,
182         TEGRA_DRIVE_PINGROUP_AO3,
183         TEGRA_DRIVE_PINGROUP_SPI2,
184         TEGRA_DRIVE_PINGROUP_AO0,
185         TEGRA_DRIVE_PINGROUP_DCA,
186         TEGRA_DRIVE_PINGROUP_SPI3,
187         TEGRA_MAX_DRIVE_PINGROUP,
188 };
189
190 #endif