ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / pinmux-t12.h
1 /*
2  * linux/arch/arm/mach-tegra/include/mach/pinmux-t12.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2011-2013 NVIDIA CORPORATION. All rights reserved.
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #ifndef __MACH_TEGRA_PINMUX_T12_H
19 #define __MACH_TEGRA_PINMUX_T12_H
20
21 #include <mach/pinmux.h>
22
23 #define DEFAULT_DRIVE(_name)                                    \
24         {                                                       \
25                 .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
26                 .hsm = TEGRA_HSM_DISABLE,                       \
27                 .schmitt = TEGRA_SCHMITT_ENABLE,                \
28                 .drive = TEGRA_DRIVE_DIV_1,                     \
29                 .pull_down = TEGRA_PULL_31,                     \
30                 .pull_up = TEGRA_PULL_31,                       \
31                 .slew_rising = TEGRA_SLEW_SLOWEST,              \
32                 .slew_falling = TEGRA_SLEW_SLOWEST,             \
33         }
34 /* Setting the drive strength of pins
35  * hsm: Enable High speed mode (ENABLE/DISABLE)
36  * Schimit: Enable/disable schimit (ENABLE/DISABLE)
37  * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
38  * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
39  *                strength code. Value from 0 to 31.
40  * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
41  *                strength code. Value from 0 to 31.
42  * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
43  *                code 11 is least slewing of signal. code 00 is highest
44  *                slewing of the signal.
45  *                Value - FASTEST, FAST, SLOW, SLOWEST
46  * pullup_slew -  Driver Output Pull-Down slew control code -
47  *                code 11 is least slewing of signal. code 00 is highest
48  *                slewing of the signal.
49  *                Value - FASTEST, FAST, SLOW, SLOWEST
50  */
51 #define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
52         {                                               \
53                 .pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
54                 .hsm = TEGRA_HSM_##_hsm,                    \
55                 .schmitt = TEGRA_SCHMITT_##_schmitt,        \
56                 .drive = TEGRA_DRIVE_##_drive,              \
57                 .pull_down = TEGRA_PULL_##_pulldn_drive,    \
58                 .pull_up = TEGRA_PULL_##_pullup_drive,          \
59                 .slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
60                 .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
61         }
62
63 /* Setting the drive strength of pins
64  * hsm: Enable High speed mode (ENABLE/DISABLE)
65  * Schimit: Enable/disable schimit (ENABLE/DISABLE)
66  * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
67  * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
68  *                strength code. Value from 0 to 31.
69  * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
70  *                strength code. Value from 0 to 31.
71  * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
72  *                code 11 is least slewing of signal. code 00 is highest
73  *                slewing of the signal.
74  *                Value - FASTEST, FAST, SLOW, SLOWEST
75  * pullup_slew -  Driver Output Pull-Down slew control code -
76  *                code 11 is least slewing of signal. code 00 is highest
77  *                slewing of the signal.
78  *                Value - FASTEST, FAST, SLOW, SLOWEST
79  * drive_type - Drive type to be used depending on the resistors.
80  */
81
82 #define SET_DRIVE_WITH_TYPE(_name, _hsm, _schmitt, _drive, _pulldn_drive,\
83                 _pullup_drive, _pulldn_slew, _pullup_slew, _drive_type) \
84         {                                                               \
85                 .pingroup = TEGRA_DRIVE_PINGROUP_##_name,               \
86                 .hsm = TEGRA_HSM_##_hsm,                                \
87                 .schmitt = TEGRA_SCHMITT_##_schmitt,                    \
88                 .drive = TEGRA_DRIVE_##_drive,                          \
89                 .pull_down = TEGRA_PULL_##_pulldn_drive,                \
90                 .pull_up = TEGRA_PULL_##_pullup_drive,                  \
91                 .slew_rising = TEGRA_SLEW_##_pulldn_slew,               \
92                 .slew_falling = TEGRA_SLEW_##_pullup_slew,              \
93                 .drive_type = TEGRA_DRIVE_TYPE_##_drive_type,           \
94         }
95
96 #define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)       \
97         {                                                       \
98                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
99                 .func           = TEGRA_MUX_##_mux,             \
100                 .pupd           = TEGRA_PUPD_##_pupd,           \
101                 .tristate       = TEGRA_TRI_##_tri,             \
102                 .io             = TEGRA_PIN_##_io,              \
103                 .lock           = TEGRA_PIN_LOCK_DEFAULT,       \
104                 .od             = TEGRA_PIN_OD_DEFAULT,         \
105                 .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
106         }
107
108 #define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
109         {                                                       \
110                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
111                 .func           = TEGRA_MUX_##_mux,             \
112                 .pupd           = TEGRA_PUPD_##_pupd,           \
113                 .tristate       = TEGRA_TRI_##_tri,             \
114                 .io             = TEGRA_PIN_##_io,              \
115                 .lock           = TEGRA_PIN_LOCK_##_lock,       \
116                 .od             = TEGRA_PIN_OD_##_od,           \
117                 .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
118         }
119
120 #define DDC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _rcv_sel) \
121         {                                                       \
122                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
123                 .func           = TEGRA_MUX_##_mux,             \
124                 .pupd           = TEGRA_PUPD_##_pupd,           \
125                 .tristate       = TEGRA_TRI_##_tri,             \
126                 .io             = TEGRA_PIN_##_io,              \
127                 .lock           = TEGRA_PIN_LOCK_##_lock,       \
128                 .rcv_sel        = TEGRA_PIN_RCV_SEL_##_rcv_sel,         \
129                 .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
130         }
131
132 #define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
133         {                                                       \
134                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
135                 .func           = TEGRA_MUX_##_mux,             \
136                 .pupd           = TEGRA_PUPD_##_pupd,           \
137                 .tristate       = TEGRA_TRI_##_tri,             \
138                 .io             = TEGRA_PIN_##_io,              \
139                 .lock           = TEGRA_PIN_LOCK_##_lock,       \
140                 .od             = TEGRA_PIN_OD_DEFAULT,         \
141                 .ioreset        = TEGRA_PIN_IO_RESET_##_ioreset \
142         }
143
144 #define CEC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od)   \
145         {                                                       \
146                 .pingroup   = TEGRA_PINGROUP_##_pingroup,       \
147                 .func       = TEGRA_MUX_##_mux,                 \
148                 .pupd       = TEGRA_PUPD_##_pupd,               \
149                 .tristate   = TEGRA_TRI_##_tri,                 \
150                 .io         = TEGRA_PIN_##_io,                  \
151                 .lock       = TEGRA_PIN_LOCK_##_lock,           \
152                 .od         = TEGRA_PIN_OD_##_od,               \
153                 .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
154         }
155
156 #define GPIO_PINMUX(_pingroup, _pupd, _tri, _io, _od)   \
157         {                                                       \
158                 .pingroup   = TEGRA_PINGROUP_##_pingroup,       \
159                 .func       = TEGRA_MUX_SAFE,                   \
160                 .pupd       = TEGRA_PUPD_##_pupd,               \
161                 .tristate   = TEGRA_TRI_##_tri,                 \
162                 .io         = TEGRA_PIN_##_io,                  \
163                 .lock       = TEGRA_PIN_LOCK_DEFAULT,           \
164                 .od         = TEGRA_PIN_OD_##_od,               \
165                 .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
166         }
167
168 #define GPIO_PINMUX_NON_OD(_pingroup, _pupd, _tri, _io) \
169         {                                                       \
170                 .pingroup   = TEGRA_PINGROUP_##_pingroup,       \
171                 .func       = TEGRA_MUX_SAFE,                   \
172                 .pupd       = TEGRA_PUPD_##_pupd,               \
173                 .tristate   = TEGRA_TRI_##_tri,                 \
174                 .io         = TEGRA_PIN_##_io,                  \
175                 .lock       = TEGRA_PIN_LOCK_DEFAULT,           \
176                 .od         = TEGRA_PIN_OD_DEFAULT,             \
177                 .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
178         }
179
180 #define UNUSED_PINMUX(_pingroup)        \
181         {                                                       \
182                 .pingroup   = TEGRA_PINGROUP_##_pingroup,       \
183                 .func       = TEGRA_MUX_SAFE,                   \
184                 .pupd       = TEGRA_PUPD_PULL_DOWN,             \
185                 .tristate   = TEGRA_TRI_TRISTATE,               \
186                 .io         = TEGRA_PIN_OUTPUT,                 \
187                 .lock       = TEGRA_PIN_LOCK_DEFAULT,           \
188                 .od         = TEGRA_PIN_OD_DEFAULT,             \
189                 .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
190         }
191
192 #define USB_PINMUX CEC_PINMUX
193
194 #define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value)    \
195         {                                       \
196                 .gpio_nr        = _gpio,        \
197                 .is_input       = _is_input,    \
198                 .value          = _value,       \
199         }
200
201 void tegra12x_default_pinmux(void);
202
203 enum tegra_pingroup {
204         TEGRA_PINGROUP_ULPI_DATA0,
205         TEGRA_PINGROUP_ULPI_DATA1,
206         TEGRA_PINGROUP_ULPI_DATA2,
207         TEGRA_PINGROUP_ULPI_DATA3,
208         TEGRA_PINGROUP_ULPI_DATA4,
209         TEGRA_PINGROUP_ULPI_DATA5,
210         TEGRA_PINGROUP_ULPI_DATA6,
211         TEGRA_PINGROUP_ULPI_DATA7,
212         TEGRA_PINGROUP_ULPI_CLK,
213         TEGRA_PINGROUP_ULPI_DIR,
214         TEGRA_PINGROUP_ULPI_NXT,
215         TEGRA_PINGROUP_ULPI_STP,
216         TEGRA_PINGROUP_DAP3_FS,
217         TEGRA_PINGROUP_DAP3_DIN,
218         TEGRA_PINGROUP_DAP3_DOUT,
219         TEGRA_PINGROUP_DAP3_SCLK,
220         TEGRA_PINGROUP_GPIO_PV0,
221         TEGRA_PINGROUP_GPIO_PV1,
222         TEGRA_PINGROUP_SDMMC1_CLK,
223         TEGRA_PINGROUP_SDMMC1_CMD,
224         TEGRA_PINGROUP_SDMMC1_DAT3,
225         TEGRA_PINGROUP_SDMMC1_DAT2,
226         TEGRA_PINGROUP_SDMMC1_DAT1,
227         TEGRA_PINGROUP_SDMMC1_DAT0,
228         TEGRA_PINGROUP_CLK2_OUT,
229         TEGRA_PINGROUP_CLK2_REQ,
230         TEGRA_PINGROUP_HDMI_INT,
231         TEGRA_PINGROUP_DDC_SCL,
232         TEGRA_PINGROUP_DDC_SDA,
233         TEGRA_PINGROUP_UART2_RXD,
234         TEGRA_PINGROUP_UART2_TXD,
235         TEGRA_PINGROUP_UART2_RTS_N,
236         TEGRA_PINGROUP_UART2_CTS_N,
237         TEGRA_PINGROUP_UART3_TXD,
238         TEGRA_PINGROUP_UART3_RXD,
239         TEGRA_PINGROUP_UART3_CTS_N,
240         TEGRA_PINGROUP_UART3_RTS_N,
241         TEGRA_PINGROUP_GPIO_PU0,
242         TEGRA_PINGROUP_GPIO_PU1,
243         TEGRA_PINGROUP_GPIO_PU2,
244         TEGRA_PINGROUP_GPIO_PU3,
245         TEGRA_PINGROUP_GPIO_PU4,
246         TEGRA_PINGROUP_GPIO_PU5,
247         TEGRA_PINGROUP_GPIO_PU6,
248         TEGRA_PINGROUP_GEN1_I2C_SDA,
249         TEGRA_PINGROUP_GEN1_I2C_SCL,
250         TEGRA_PINGROUP_DAP4_FS,
251         TEGRA_PINGROUP_DAP4_DIN,
252         TEGRA_PINGROUP_DAP4_DOUT,
253         TEGRA_PINGROUP_DAP4_SCLK,
254         TEGRA_PINGROUP_CLK3_OUT,
255         TEGRA_PINGROUP_CLK3_REQ,
256         TEGRA_PINGROUP_GPIO_PC7,
257         TEGRA_PINGROUP_GPIO_PI5,
258         TEGRA_PINGROUP_GPIO_PI7,
259         TEGRA_PINGROUP_GPIO_PK0,
260         TEGRA_PINGROUP_GPIO_PK1,
261         TEGRA_PINGROUP_GPIO_PJ0,
262         TEGRA_PINGROUP_GPIO_PJ2,
263         TEGRA_PINGROUP_GPIO_PK3,
264         TEGRA_PINGROUP_GPIO_PK4,
265         TEGRA_PINGROUP_GPIO_PK2,
266         TEGRA_PINGROUP_GPIO_PI3,
267         TEGRA_PINGROUP_GPIO_PI6,
268         TEGRA_PINGROUP_GPIO_PG0,
269         TEGRA_PINGROUP_GPIO_PG1,
270         TEGRA_PINGROUP_GPIO_PG2,
271         TEGRA_PINGROUP_GPIO_PG3,
272         TEGRA_PINGROUP_GPIO_PG4,
273         TEGRA_PINGROUP_GPIO_PG5,
274         TEGRA_PINGROUP_GPIO_PG6,
275         TEGRA_PINGROUP_GPIO_PG7,
276         TEGRA_PINGROUP_GPIO_PH0,
277         TEGRA_PINGROUP_GPIO_PH1,
278         TEGRA_PINGROUP_GPIO_PH2,
279         TEGRA_PINGROUP_GPIO_PH3,
280         TEGRA_PINGROUP_GPIO_PH4,
281         TEGRA_PINGROUP_GPIO_PH5,
282         TEGRA_PINGROUP_GPIO_PH6,
283         TEGRA_PINGROUP_GPIO_PH7,
284         TEGRA_PINGROUP_GPIO_PJ7,
285         TEGRA_PINGROUP_GPIO_PB0,
286         TEGRA_PINGROUP_GPIO_PB1,
287         TEGRA_PINGROUP_GPIO_PK7,
288         TEGRA_PINGROUP_GPIO_PI0,
289         TEGRA_PINGROUP_GPIO_PI1,
290         TEGRA_PINGROUP_GPIO_PI2,
291         TEGRA_PINGROUP_GPIO_PI4,
292         TEGRA_PINGROUP_GEN2_I2C_SCL,
293         TEGRA_PINGROUP_GEN2_I2C_SDA,
294         TEGRA_PINGROUP_SDMMC4_CLK,
295         TEGRA_PINGROUP_SDMMC4_CMD,
296         TEGRA_PINGROUP_SDMMC4_DAT0,
297         TEGRA_PINGROUP_SDMMC4_DAT1,
298         TEGRA_PINGROUP_SDMMC4_DAT2,
299         TEGRA_PINGROUP_SDMMC4_DAT3,
300         TEGRA_PINGROUP_SDMMC4_DAT4,
301         TEGRA_PINGROUP_SDMMC4_DAT5,
302         TEGRA_PINGROUP_SDMMC4_DAT6,
303         TEGRA_PINGROUP_SDMMC4_DAT7,
304         TEGRA_PINGROUP_CAM_MCLK,
305         TEGRA_PINGROUP_GPIO_PCC1,
306         TEGRA_PINGROUP_GPIO_PBB0,
307         TEGRA_PINGROUP_CAM_I2C_SCL,
308         TEGRA_PINGROUP_CAM_I2C_SDA,
309         TEGRA_PINGROUP_GPIO_PBB3,
310         TEGRA_PINGROUP_GPIO_PBB4,
311         TEGRA_PINGROUP_GPIO_PBB5,
312         TEGRA_PINGROUP_GPIO_PBB6,
313         TEGRA_PINGROUP_GPIO_PBB7,
314         TEGRA_PINGROUP_GPIO_PCC2,
315         TEGRA_PINGROUP_JTAG_RTCK,
316         TEGRA_PINGROUP_PWR_I2C_SCL,
317         TEGRA_PINGROUP_PWR_I2C_SDA,
318         TEGRA_PINGROUP_KB_ROW0,
319         TEGRA_PINGROUP_KB_ROW1,
320         TEGRA_PINGROUP_KB_ROW2,
321         TEGRA_PINGROUP_KB_ROW3,
322         TEGRA_PINGROUP_KB_ROW4,
323         TEGRA_PINGROUP_KB_ROW5,
324         TEGRA_PINGROUP_KB_ROW6,
325         TEGRA_PINGROUP_KB_ROW7,
326         TEGRA_PINGROUP_KB_ROW8,
327         TEGRA_PINGROUP_KB_ROW9,
328         TEGRA_PINGROUP_KB_ROW10,
329         TEGRA_PINGROUP_KB_ROW11,
330         TEGRA_PINGROUP_KB_ROW12,
331         TEGRA_PINGROUP_KB_ROW13,
332         TEGRA_PINGROUP_KB_ROW14,
333         TEGRA_PINGROUP_KB_ROW15,
334         TEGRA_PINGROUP_KB_COL0,
335         TEGRA_PINGROUP_KB_COL1,
336         TEGRA_PINGROUP_KB_COL2,
337         TEGRA_PINGROUP_KB_COL3,
338         TEGRA_PINGROUP_KB_COL4,
339         TEGRA_PINGROUP_KB_COL5,
340         TEGRA_PINGROUP_KB_COL6,
341         TEGRA_PINGROUP_KB_COL7,
342         TEGRA_PINGROUP_CLK_32K_OUT,
343         TEGRA_PINGROUP_CORE_PWR_REQ,
344         TEGRA_PINGROUP_CPU_PWR_REQ,
345         TEGRA_PINGROUP_PWR_INT_N,
346         TEGRA_PINGROUP_CLK_32K_IN,
347         TEGRA_PINGROUP_OWR,
348         TEGRA_PINGROUP_DAP1_FS,
349         TEGRA_PINGROUP_DAP1_DIN,
350         TEGRA_PINGROUP_DAP1_DOUT,
351         TEGRA_PINGROUP_DAP1_SCLK,
352         TEGRA_PINGROUP_DAP_MCLK1_REQ,
353         TEGRA_PINGROUP_DAP_MCLK1,
354         TEGRA_PINGROUP_SPDIF_IN,
355         TEGRA_PINGROUP_SPDIF_OUT,
356         TEGRA_PINGROUP_DAP2_FS,
357         TEGRA_PINGROUP_DAP2_DIN,
358         TEGRA_PINGROUP_DAP2_DOUT,
359         TEGRA_PINGROUP_DAP2_SCLK,
360         TEGRA_PINGROUP_DVFS_PWM,
361         TEGRA_PINGROUP_GPIO_X1_AUD,
362         TEGRA_PINGROUP_GPIO_X3_AUD,
363         TEGRA_PINGROUP_DVFS_CLK,
364         TEGRA_PINGROUP_GPIO_X4_AUD,
365         TEGRA_PINGROUP_GPIO_X5_AUD,
366         TEGRA_PINGROUP_GPIO_X6_AUD,
367         TEGRA_PINGROUP_GPIO_X7_AUD,
368         TEGRA_PINGROUP_SDMMC3_CLK,
369         TEGRA_PINGROUP_SDMMC3_CMD,
370         TEGRA_PINGROUP_SDMMC3_DAT0,
371         TEGRA_PINGROUP_SDMMC3_DAT1,
372         TEGRA_PINGROUP_SDMMC3_DAT2,
373         TEGRA_PINGROUP_SDMMC3_DAT3,
374         TEGRA_PINGROUP_PEX_L0_RST_N,
375         TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
376         TEGRA_PINGROUP_PEX_WAKE_N,
377         TEGRA_PINGROUP_PEX_L1_RST_N,
378         TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
379         TEGRA_PINGROUP_HDMI_CEC,
380         TEGRA_PINGROUP_SDMMC1_WP_N,
381         TEGRA_PINGROUP_SDMMC3_CD_N,
382         TEGRA_PINGROUP_GPIO_W2_AUD,
383         TEGRA_PINGROUP_GPIO_W3_AUD,
384         TEGRA_PINGROUP_USB_VBUS_EN0,
385         TEGRA_PINGROUP_USB_VBUS_EN1,
386         TEGRA_PINGROUP_SDMMC3_CLK_LB_OUT,
387         TEGRA_PINGROUP_SDMMC3_CLK_LB_IN,
388         TEGRA_PINGROUP_GMI_CLK_LB,
389         TEGRA_PINGROUP_RESET_OUT_N,
390         TEGRA_PINGROUP_KB_ROW16,
391         TEGRA_PINGROUP_KB_ROW17,
392         TEGRA_PINGROUP_USB_VBUS_EN2,
393         TEGRA_PINGROUP_GPIO_PFF2,
394         TEGRA_PINGROUP_DP_HPD,
395
396         /* Unused on T124 */
397         TEGRA_PINGROUP_SDMMC4_RST_N,
398         TEGRA_PINGROUP_GMI_WP_N,
399         TEGRA_PINGROUP_GMI_IORDY,
400         TEGRA_PINGROUP_GMI_WAIT,
401         TEGRA_PINGROUP_GMI_ADV_N,
402         TEGRA_PINGROUP_GMI_CLK,
403         TEGRA_PINGROUP_GMI_CS0_N,
404         TEGRA_PINGROUP_GMI_CS1_N,
405         TEGRA_PINGROUP_GMI_CS2_N,
406         TEGRA_PINGROUP_GMI_CS3_N,
407         TEGRA_PINGROUP_GMI_CS4_N,
408         TEGRA_PINGROUP_GMI_CS6_N,
409         TEGRA_PINGROUP_GMI_CS7_N,
410         TEGRA_PINGROUP_GMI_AD0,
411         TEGRA_PINGROUP_GMI_AD1,
412         TEGRA_PINGROUP_GMI_AD2,
413         TEGRA_PINGROUP_GMI_AD3,
414         TEGRA_PINGROUP_GMI_AD4,
415         TEGRA_PINGROUP_GMI_AD5,
416         TEGRA_PINGROUP_GMI_AD6,
417         TEGRA_PINGROUP_GMI_AD7,
418         TEGRA_PINGROUP_GMI_AD8,
419         TEGRA_PINGROUP_GMI_AD9,
420         TEGRA_PINGROUP_GMI_AD10,
421         TEGRA_PINGROUP_GMI_AD11,
422         TEGRA_PINGROUP_GMI_AD12,
423         TEGRA_PINGROUP_GMI_AD13,
424         TEGRA_PINGROUP_GMI_AD14,
425         TEGRA_PINGROUP_GMI_AD15,
426         TEGRA_PINGROUP_GMI_A16,
427         TEGRA_PINGROUP_GMI_A17,
428         TEGRA_PINGROUP_GMI_A18,
429         TEGRA_PINGROUP_GMI_A19,
430         TEGRA_PINGROUP_GMI_WR_N,
431         TEGRA_PINGROUP_GMI_OE_N,
432         TEGRA_PINGROUP_GMI_DQS_P,
433         TEGRA_PINGROUP_GMI_DQS = TEGRA_PINGROUP_GMI_DQS_P,
434         TEGRA_PINGROUP_GMI_RST_N,
435         TEGRA_PINGROUP_SYS_CLK_REQ,
436         TEGRA_PINGROUP_CLK1_REQ,
437         TEGRA_PINGROUP_CLK1_OUT,
438         TEGRA_PINGROUP_SPI2_MOSI,
439         TEGRA_PINGROUP_SPI2_MISO,
440         TEGRA_PINGROUP_SPI2_CS0_N,
441         TEGRA_PINGROUP_SPI2_SCK,
442         TEGRA_PINGROUP_SPI1_MOSI,
443         TEGRA_PINGROUP_SPI1_SCK,
444         TEGRA_PINGROUP_SPI1_CS0_N,
445         TEGRA_PINGROUP_SPI1_MISO,
446         TEGRA_PINGROUP_SPI1_CS1_N,
447         TEGRA_PINGROUP_SPI1_CS2_N,
448         TEGRA_MAX_PINGROUP,
449 };
450
451 enum tegra_drive_pingroup {
452         TEGRA_DRIVE_PINGROUP_AO1 = 0,
453         TEGRA_DRIVE_PINGROUP_AO2,
454         TEGRA_DRIVE_PINGROUP_AT1,
455         TEGRA_DRIVE_PINGROUP_AT2,
456         TEGRA_DRIVE_PINGROUP_AT3,
457         TEGRA_DRIVE_PINGROUP_AT4,
458         TEGRA_DRIVE_PINGROUP_AT5,
459         TEGRA_DRIVE_PINGROUP_CDEV1,
460         TEGRA_DRIVE_PINGROUP_CDEV2,
461         TEGRA_DRIVE_PINGROUP_DAP1,
462         TEGRA_DRIVE_PINGROUP_DAP2,
463         TEGRA_DRIVE_PINGROUP_DAP3,
464         TEGRA_DRIVE_PINGROUP_DAP4,
465         TEGRA_DRIVE_PINGROUP_DBG,
466         TEGRA_DRIVE_PINGROUP_SDIO3,
467         TEGRA_DRIVE_PINGROUP_SPI,
468         TEGRA_DRIVE_PINGROUP_UAA,
469         TEGRA_DRIVE_PINGROUP_UAB,
470         TEGRA_DRIVE_PINGROUP_UART2,
471         TEGRA_DRIVE_PINGROUP_UART3,
472         TEGRA_DRIVE_PINGROUP_SDIO1,
473         TEGRA_DRIVE_PINGROUP_DDC,
474         TEGRA_DRIVE_PINGROUP_GMA,
475         TEGRA_DRIVE_PINGROUP_GME,
476         TEGRA_DRIVE_PINGROUP_GMF,
477         TEGRA_DRIVE_PINGROUP_GMG,
478         TEGRA_DRIVE_PINGROUP_GMH,
479         TEGRA_DRIVE_PINGROUP_OWR,
480         TEGRA_DRIVE_PINGROUP_UAD,
481         TEGRA_DRIVE_PINGROUP_GPV,
482         TEGRA_DRIVE_PINGROUP_DEV3,
483         TEGRA_DRIVE_PINGROUP_CEC,
484         TEGRA_DRIVE_PINGROUP_AT6,
485         TEGRA_DRIVE_PINGROUP_DAP5,
486         TEGRA_DRIVE_PINGROUP_VBUS,
487         TEGRA_DRIVE_PINGROUP_AO3,
488         TEGRA_DRIVE_PINGROUP_AO0,
489         TEGRA_DRIVE_PINGROUP_HV0,
490         TEGRA_DRIVE_PINGROUP_SDIO4,
491         TEGRA_DRIVE_PINGROUP_AO4,
492         TEGRA_DRIVE_PINGROUP_CSUS,
493         TEGRA_MAX_DRIVE_PINGROUP,
494 };
495
496 #endif