ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / pinmux-t11.h
1 /*
2  * linux/arch/arm/mach-tegra/include/mach/pinmux-t11.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2011-2013 NVIDIA CORPORATION.  All rights reserved.
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #ifndef __MACH_TEGRA_PINMUX_T11_H
19 #define __MACH_TEGRA_PINMUX_T11_H
20
21 #include <mach/pinmux.h>
22
23 #define DEFAULT_DRIVE(_name)                                    \
24         {                                                       \
25                 .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
26                 .hsm = TEGRA_HSM_DISABLE,                       \
27                 .schmitt = TEGRA_SCHMITT_ENABLE,                \
28                 .drive = TEGRA_DRIVE_DIV_1,                     \
29                 .pull_down = TEGRA_PULL_31,                     \
30                 .pull_up = TEGRA_PULL_31,                       \
31                 .slew_rising = TEGRA_SLEW_SLOWEST,              \
32                 .slew_falling = TEGRA_SLEW_SLOWEST,             \
33         }
34 /* Setting the drive strength of pins
35  * hsm: Enable High speed mode (ENABLE/DISABLE)
36  * Schimit: Enable/disable schimit (ENABLE/DISABLE)
37  * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
38  * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
39  *                strength code. Value from 0 to 31.
40  * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
41  *                strength code. Value from 0 to 31.
42  * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
43  *                code 11 is least slewing of signal. code 00 is highest
44  *                slewing of the signal.
45  *                Value - FASTEST, FAST, SLOW, SLOWEST
46  * pullup_slew -  Driver Output Pull-Down slew control code -
47  *                code 11 is least slewing of signal. code 00 is highest
48  *                slewing of the signal.
49  *                Value - FASTEST, FAST, SLOW, SLOWEST
50  */
51 #define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
52         {                                               \
53                 .pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
54                 .hsm = TEGRA_HSM_##_hsm,                    \
55                 .schmitt = TEGRA_SCHMITT_##_schmitt,        \
56                 .drive = TEGRA_DRIVE_##_drive,              \
57                 .pull_down = TEGRA_PULL_##_pulldn_drive,    \
58                 .pull_up = TEGRA_PULL_##_pullup_drive,          \
59                 .slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
60                 .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
61         }
62
63 /* Setting the drive strength of pins
64  * hsm: Enable High speed mode (ENABLE/DISABLE)
65  * Schimit: Enable/disable schimit (ENABLE/DISABLE)
66  * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
67  * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
68  *                strength code. Value from 0 to 31.
69  * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
70  *                strength code. Value from 0 to 31.
71  * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
72  *                code 11 is least slewing of signal. code 00 is highest
73  *                slewing of the signal.
74  *                Value - FASTEST, FAST, SLOW, SLOWEST
75  * pullup_slew -  Driver Output Pull-Down slew control code -
76  *                code 11 is least slewing of signal. code 00 is highest
77  *                slewing of the signal.
78  *                Value - FASTEST, FAST, SLOW, SLOWEST
79  * drive_type - Drive type to be used depending on the resistors.
80  */
81
82 #define SET_DRIVE_WITH_TYPE(_name, _hsm, _schmitt, _drive, _pulldn_drive,\
83                 _pullup_drive, _pulldn_slew, _pullup_slew, _drive_type) \
84         {                                                               \
85                 .pingroup = TEGRA_DRIVE_PINGROUP_##_name,               \
86                 .hsm = TEGRA_HSM_##_hsm,                                \
87                 .schmitt = TEGRA_SCHMITT_##_schmitt,                    \
88                 .drive = TEGRA_DRIVE_##_drive,                          \
89                 .pull_down = TEGRA_PULL_##_pulldn_drive,                \
90                 .pull_up = TEGRA_PULL_##_pullup_drive,                  \
91                 .slew_rising = TEGRA_SLEW_##_pulldn_slew,               \
92                 .slew_falling = TEGRA_SLEW_##_pullup_slew,              \
93                 .drive_type = TEGRA_DRIVE_TYPE_##_drive_type,           \
94         }
95
96 #define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)       \
97         {                                                       \
98                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
99                 .func           = TEGRA_MUX_##_mux,             \
100                 .pupd           = TEGRA_PUPD_##_pupd,           \
101                 .tristate       = TEGRA_TRI_##_tri,             \
102                 .io             = TEGRA_PIN_##_io,              \
103                 .lock           = TEGRA_PIN_LOCK_DEFAULT,       \
104                 .od             = TEGRA_PIN_OD_DEFAULT,         \
105                 .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
106         }
107
108 #define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
109         {                                                       \
110                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
111                 .func           = TEGRA_MUX_##_mux,             \
112                 .pupd           = TEGRA_PUPD_##_pupd,           \
113                 .tristate       = TEGRA_TRI_##_tri,             \
114                 .io             = TEGRA_PIN_##_io,              \
115                 .lock           = TEGRA_PIN_LOCK_##_lock,       \
116                 .od             = TEGRA_PIN_OD_##_od,           \
117                 .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
118         }
119
120 #define DDC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _rcv_sel) \
121         {                                                       \
122                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
123                 .func           = TEGRA_MUX_##_mux,             \
124                 .pupd           = TEGRA_PUPD_##_pupd,           \
125                 .tristate       = TEGRA_TRI_##_tri,             \
126                 .io             = TEGRA_PIN_##_io,              \
127                 .lock           = TEGRA_PIN_LOCK_##_lock,       \
128                 .rcv_sel        = TEGRA_PIN_RCV_SEL_##_rcv_sel,         \
129                 .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
130         }
131
132 #define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
133         {                                                       \
134                 .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
135                 .func           = TEGRA_MUX_##_mux,             \
136                 .pupd           = TEGRA_PUPD_##_pupd,           \
137                 .tristate       = TEGRA_TRI_##_tri,             \
138                 .io             = TEGRA_PIN_##_io,              \
139                 .lock           = TEGRA_PIN_LOCK_##_lock,       \
140                 .od             = TEGRA_PIN_OD_DEFAULT,         \
141                 .ioreset        = TEGRA_PIN_IO_RESET_##_ioreset \
142         }
143
144 #define CEC_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od)   \
145         {                                                       \
146                 .pingroup   = TEGRA_PINGROUP_##_pingroup,       \
147                 .func       = TEGRA_MUX_##_mux,                 \
148                 .pupd       = TEGRA_PUPD_##_pupd,               \
149                 .tristate   = TEGRA_TRI_##_tri,                 \
150                 .io         = TEGRA_PIN_##_io,                  \
151                 .lock       = TEGRA_PIN_LOCK_##_lock,           \
152                 .od         = TEGRA_PIN_OD_##_od,               \
153                 .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
154         }
155
156 #define GPIO_PINMUX(_pingroup, _pupd, _tri, _io, _od)   \
157         {                                                       \
158                 .pingroup   = TEGRA_PINGROUP_##_pingroup,       \
159                 .func       = TEGRA_MUX_SAFE,                   \
160                 .pupd       = TEGRA_PUPD_##_pupd,               \
161                 .tristate   = TEGRA_TRI_##_tri,                 \
162                 .io         = TEGRA_PIN_##_io,                  \
163                 .lock       = TEGRA_PIN_LOCK_DEFAULT,           \
164                 .od         = TEGRA_PIN_OD_##_od,               \
165                 .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
166         }
167
168 #define UNUSED_PINMUX(_pingroup)        \
169         {                                                       \
170                 .pingroup   = TEGRA_PINGROUP_##_pingroup,       \
171                 .func       = TEGRA_MUX_SAFE,                   \
172                 .pupd       = TEGRA_PUPD_PULL_DOWN,             \
173                 .tristate   = TEGRA_TRI_TRISTATE,               \
174                 .io         = TEGRA_PIN_OUTPUT,                 \
175                 .lock       = TEGRA_PIN_LOCK_DEFAULT,           \
176                 .od         = TEGRA_PIN_OD_DEFAULT,             \
177                 .ioreset    = TEGRA_PIN_IO_RESET_DEFAULT,       \
178         }
179
180 #define USB_PINMUX CEC_PINMUX
181
182 #define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value)    \
183         {                                       \
184                 .gpio_nr        = _gpio,        \
185                 .is_input       = _is_input,    \
186                 .value          = _value,       \
187         }
188
189 void tegra11x_default_pinmux(void);
190
191 enum tegra_pingroup {
192         TEGRA_PINGROUP_ULPI_DATA0,
193         TEGRA_PINGROUP_ULPI_DATA1,
194         TEGRA_PINGROUP_ULPI_DATA2,
195         TEGRA_PINGROUP_ULPI_DATA3,
196         TEGRA_PINGROUP_ULPI_DATA4,
197         TEGRA_PINGROUP_ULPI_DATA5,
198         TEGRA_PINGROUP_ULPI_DATA6,
199         TEGRA_PINGROUP_ULPI_DATA7,
200         TEGRA_PINGROUP_ULPI_CLK,
201         TEGRA_PINGROUP_ULPI_DIR,
202         TEGRA_PINGROUP_ULPI_NXT,
203         TEGRA_PINGROUP_ULPI_STP,
204         TEGRA_PINGROUP_DAP3_FS,
205         TEGRA_PINGROUP_DAP3_DIN,
206         TEGRA_PINGROUP_DAP3_DOUT,
207         TEGRA_PINGROUP_DAP3_SCLK,
208         TEGRA_PINGROUP_GPIO_PV0,
209         TEGRA_PINGROUP_GPIO_PV1,
210         TEGRA_PINGROUP_SDMMC1_CLK,
211         TEGRA_PINGROUP_SDMMC1_CMD,
212         TEGRA_PINGROUP_SDMMC1_DAT3,
213         TEGRA_PINGROUP_SDMMC1_DAT2,
214         TEGRA_PINGROUP_SDMMC1_DAT1,
215         TEGRA_PINGROUP_SDMMC1_DAT0,
216         TEGRA_PINGROUP_CLK2_OUT,
217         TEGRA_PINGROUP_CLK2_REQ,
218         TEGRA_PINGROUP_HDMI_INT,
219         TEGRA_PINGROUP_DDC_SCL,
220         TEGRA_PINGROUP_DDC_SDA,
221         TEGRA_PINGROUP_UART2_RXD,
222         TEGRA_PINGROUP_UART2_TXD,
223         TEGRA_PINGROUP_UART2_RTS_N,
224         TEGRA_PINGROUP_UART2_CTS_N,
225         TEGRA_PINGROUP_UART3_TXD,
226         TEGRA_PINGROUP_UART3_RXD,
227         TEGRA_PINGROUP_UART3_CTS_N,
228         TEGRA_PINGROUP_UART3_RTS_N,
229         TEGRA_PINGROUP_GPIO_PU0,
230         TEGRA_PINGROUP_GPIO_PU1,
231         TEGRA_PINGROUP_GPIO_PU2,
232         TEGRA_PINGROUP_GPIO_PU3,
233         TEGRA_PINGROUP_GPIO_PU4,
234         TEGRA_PINGROUP_GPIO_PU5,
235         TEGRA_PINGROUP_GPIO_PU6,
236         TEGRA_PINGROUP_GEN1_I2C_SDA,
237         TEGRA_PINGROUP_GEN1_I2C_SCL,
238         TEGRA_PINGROUP_DAP4_FS,
239         TEGRA_PINGROUP_DAP4_DIN,
240         TEGRA_PINGROUP_DAP4_DOUT,
241         TEGRA_PINGROUP_DAP4_SCLK,
242         TEGRA_PINGROUP_CLK3_OUT,
243         TEGRA_PINGROUP_CLK3_REQ,
244         TEGRA_PINGROUP_GMI_WP_N,
245         TEGRA_PINGROUP_GMI_IORDY,
246         TEGRA_PINGROUP_GMI_WAIT,
247         TEGRA_PINGROUP_GMI_ADV_N,
248         TEGRA_PINGROUP_GMI_CLK,
249         TEGRA_PINGROUP_GMI_CS0_N,
250         TEGRA_PINGROUP_GMI_CS1_N,
251         TEGRA_PINGROUP_GMI_CS2_N,
252         TEGRA_PINGROUP_GMI_CS3_N,
253         TEGRA_PINGROUP_GMI_CS4_N,
254         TEGRA_PINGROUP_GMI_CS6_N,
255         TEGRA_PINGROUP_GMI_CS7_N,
256         TEGRA_PINGROUP_GMI_AD0,
257         TEGRA_PINGROUP_GMI_AD1,
258         TEGRA_PINGROUP_GMI_AD2,
259         TEGRA_PINGROUP_GMI_AD3,
260         TEGRA_PINGROUP_GMI_AD4,
261         TEGRA_PINGROUP_GMI_AD5,
262         TEGRA_PINGROUP_GMI_AD6,
263         TEGRA_PINGROUP_GMI_AD7,
264         TEGRA_PINGROUP_GMI_AD8,
265         TEGRA_PINGROUP_GMI_AD9,
266         TEGRA_PINGROUP_GMI_AD10,
267         TEGRA_PINGROUP_GMI_AD11,
268         TEGRA_PINGROUP_GMI_AD12,
269         TEGRA_PINGROUP_GMI_AD13,
270         TEGRA_PINGROUP_GMI_AD14,
271         TEGRA_PINGROUP_GMI_AD15,
272         TEGRA_PINGROUP_GMI_A16,
273         TEGRA_PINGROUP_GMI_A17,
274         TEGRA_PINGROUP_GMI_A18,
275         TEGRA_PINGROUP_GMI_A19,
276         TEGRA_PINGROUP_GMI_WR_N,
277         TEGRA_PINGROUP_GMI_OE_N,
278         TEGRA_PINGROUP_GMI_DQS_P,
279         TEGRA_PINGROUP_GMI_DQS = TEGRA_PINGROUP_GMI_DQS_P,
280         TEGRA_PINGROUP_GMI_RST_N,
281         TEGRA_PINGROUP_GEN2_I2C_SCL,
282         TEGRA_PINGROUP_GEN2_I2C_SDA,
283         TEGRA_PINGROUP_SDMMC4_CLK,
284         TEGRA_PINGROUP_SDMMC4_CMD,
285         TEGRA_PINGROUP_SDMMC4_DAT0,
286         TEGRA_PINGROUP_SDMMC4_DAT1,
287         TEGRA_PINGROUP_SDMMC4_DAT2,
288         TEGRA_PINGROUP_SDMMC4_DAT3,
289         TEGRA_PINGROUP_SDMMC4_DAT4,
290         TEGRA_PINGROUP_SDMMC4_DAT5,
291         TEGRA_PINGROUP_SDMMC4_DAT6,
292         TEGRA_PINGROUP_SDMMC4_DAT7,
293         TEGRA_PINGROUP_CAM_MCLK,
294         TEGRA_PINGROUP_GPIO_PCC1,
295         TEGRA_PINGROUP_GPIO_PBB0,
296         TEGRA_PINGROUP_CAM_I2C_SCL,
297         TEGRA_PINGROUP_CAM_I2C_SDA,
298         TEGRA_PINGROUP_GPIO_PBB3,
299         TEGRA_PINGROUP_GPIO_PBB4,
300         TEGRA_PINGROUP_GPIO_PBB5,
301         TEGRA_PINGROUP_GPIO_PBB6,
302         TEGRA_PINGROUP_GPIO_PBB7,
303         TEGRA_PINGROUP_GPIO_PCC2,
304         TEGRA_PINGROUP_JTAG_RTCK,
305         TEGRA_PINGROUP_PWR_I2C_SCL,
306         TEGRA_PINGROUP_PWR_I2C_SDA,
307         TEGRA_PINGROUP_KB_ROW0,
308         TEGRA_PINGROUP_KB_ROW1,
309         TEGRA_PINGROUP_KB_ROW2,
310         TEGRA_PINGROUP_KB_ROW3,
311         TEGRA_PINGROUP_KB_ROW4,
312         TEGRA_PINGROUP_KB_ROW5,
313         TEGRA_PINGROUP_KB_ROW6,
314         TEGRA_PINGROUP_KB_ROW7,
315         TEGRA_PINGROUP_KB_ROW8,
316         TEGRA_PINGROUP_KB_ROW9,
317         TEGRA_PINGROUP_KB_ROW10,
318         TEGRA_PINGROUP_KB_COL0,
319         TEGRA_PINGROUP_KB_COL1,
320         TEGRA_PINGROUP_KB_COL2,
321         TEGRA_PINGROUP_KB_COL3,
322         TEGRA_PINGROUP_KB_COL4,
323         TEGRA_PINGROUP_KB_COL5,
324         TEGRA_PINGROUP_KB_COL6,
325         TEGRA_PINGROUP_KB_COL7,
326         TEGRA_PINGROUP_CLK_32K_OUT,
327         TEGRA_PINGROUP_SYS_CLK_REQ,
328         TEGRA_PINGROUP_CORE_PWR_REQ,
329         TEGRA_PINGROUP_CPU_PWR_REQ,
330         TEGRA_PINGROUP_PWR_INT_N,
331         TEGRA_PINGROUP_CLK_32K_IN,
332         TEGRA_PINGROUP_OWR,
333         TEGRA_PINGROUP_DAP1_FS,
334         TEGRA_PINGROUP_DAP1_DIN,
335         TEGRA_PINGROUP_DAP1_DOUT,
336         TEGRA_PINGROUP_DAP1_SCLK,
337         TEGRA_PINGROUP_CLK1_REQ,
338         TEGRA_PINGROUP_CLK1_OUT,
339         TEGRA_PINGROUP_SPDIF_IN,
340         TEGRA_PINGROUP_SPDIF_OUT,
341         TEGRA_PINGROUP_DAP2_FS,
342         TEGRA_PINGROUP_DAP2_DIN,
343         TEGRA_PINGROUP_DAP2_DOUT,
344         TEGRA_PINGROUP_DAP2_SCLK,
345         TEGRA_PINGROUP_DVFS_PWM,
346         TEGRA_PINGROUP_GPIO_X1_AUD,
347         TEGRA_PINGROUP_GPIO_X3_AUD,
348         TEGRA_PINGROUP_DVFS_CLK,
349         TEGRA_PINGROUP_GPIO_X4_AUD,
350         TEGRA_PINGROUP_GPIO_X5_AUD,
351         TEGRA_PINGROUP_GPIO_X6_AUD,
352         TEGRA_PINGROUP_GPIO_X7_AUD,
353         TEGRA_PINGROUP_SDMMC3_CLK,
354         TEGRA_PINGROUP_SDMMC3_CMD,
355         TEGRA_PINGROUP_SDMMC3_DAT0,
356         TEGRA_PINGROUP_SDMMC3_DAT1,
357         TEGRA_PINGROUP_SDMMC3_DAT2,
358         TEGRA_PINGROUP_SDMMC3_DAT3,
359         TEGRA_PINGROUP_HDMI_CEC,
360         TEGRA_PINGROUP_SDMMC1_WP_N,
361         TEGRA_PINGROUP_SDMMC3_CD_N,
362         TEGRA_PINGROUP_GPIO_W2_AUD,
363         TEGRA_PINGROUP_GPIO_W3_AUD,
364         TEGRA_PINGROUP_USB_VBUS_EN0,
365         TEGRA_PINGROUP_USB_VBUS_EN1,
366         TEGRA_PINGROUP_SDMMC3_CLK_LB_IN,
367         TEGRA_PINGROUP_SDMMC3_CLK_LB_OUT,
368         TEGRA_PINGROUP_NAND_GMI_CLK_LB,
369         TEGRA_PINGROUP_RESET_OUT_N,
370         TEGRA_MAX_PINGROUP,
371 };
372
373 enum tegra_drive_pingroup {
374         TEGRA_DRIVE_PINGROUP_AO1 = 0,
375         TEGRA_DRIVE_PINGROUP_AO2,
376         TEGRA_DRIVE_PINGROUP_AT1,
377         TEGRA_DRIVE_PINGROUP_AT2,
378         TEGRA_DRIVE_PINGROUP_AT3,
379         TEGRA_DRIVE_PINGROUP_AT4,
380         TEGRA_DRIVE_PINGROUP_AT5,
381         TEGRA_DRIVE_PINGROUP_CDEV1,
382         TEGRA_DRIVE_PINGROUP_CDEV2,
383         TEGRA_DRIVE_PINGROUP_DAP1,
384         TEGRA_DRIVE_PINGROUP_DAP2,
385         TEGRA_DRIVE_PINGROUP_DAP3,
386         TEGRA_DRIVE_PINGROUP_DAP4,
387         TEGRA_DRIVE_PINGROUP_DBG,
388         TEGRA_DRIVE_PINGROUP_SDIO3,
389         TEGRA_DRIVE_PINGROUP_SPI,
390         TEGRA_DRIVE_PINGROUP_UAA,
391         TEGRA_DRIVE_PINGROUP_UAB,
392         TEGRA_DRIVE_PINGROUP_UART2,
393         TEGRA_DRIVE_PINGROUP_UART3,
394         TEGRA_DRIVE_PINGROUP_SDIO1,
395         TEGRA_DRIVE_PINGROUP_DDC,
396         TEGRA_DRIVE_PINGROUP_GMA,
397         TEGRA_DRIVE_PINGROUP_GME,
398         TEGRA_DRIVE_PINGROUP_GMF,
399         TEGRA_DRIVE_PINGROUP_GMG,
400         TEGRA_DRIVE_PINGROUP_GMH,
401         TEGRA_DRIVE_PINGROUP_OWR,
402         TEGRA_DRIVE_PINGROUP_UAD,
403         TEGRA_DRIVE_PINGROUP_DEV3,
404         TEGRA_DRIVE_PINGROUP_CEC,
405         TEGRA_DRIVE_PINGROUP_AT6,
406         TEGRA_DRIVE_PINGROUP_DAP5,
407         TEGRA_DRIVE_PINGROUP_VBUS,
408         TEGRA_MAX_DRIVE_PINGROUP,
409 };
410
411 #ifdef CONFIG_PM_SLEEP
412 void tegra11x_set_sleep_pinmux(struct tegra_pingroup_config *config, int size);
413 #else
414 static inline void
415 tegra11x_set_sleep_pinmux(struct tegra_pingroup_config *config, int size) {}
416 #endif
417 #endif