ARM: tegra: la: Add support for latency allowance.
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / latency_allowance.h
1 /*
2  * arch/arm/mach-tegra/include/mach/latency_allowance.h
3  *
4  * Copyright (C) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #ifndef _MACH_TEGRA_LATENCY_ALLOWANCE_H_
18 #define _MACH_TEGRA_LATENCY_ALLOWANCE_H_
19
20 enum tegra_la_id {
21         TEGRA_LA_AFIR = 0,
22         TEGRA_LA_AFIW,
23         TEGRA_LA_AVPC_ARM7R,
24         TEGRA_LA_AVPC_ARM7W,
25         TEGRA_LA_DISPLAY_0A,
26         TEGRA_LA_DISPLAY_0B,
27         TEGRA_LA_DISPLAY_0C,
28         TEGRA_LA_DISPLAY_1B,
29         TEGRA_LA_DISPLAY_HC,
30         TEGRA_LA_DISPLAY_0AB,
31         TEGRA_LA_DISPLAY_0BB,
32         TEGRA_LA_DISPLAY_0CB,
33         TEGRA_LA_DISPLAY_1BB,
34         TEGRA_LA_DISPLAY_HCB,
35         TEGRA_LA_EPPUP,
36         TEGRA_LA_EPPU,
37         TEGRA_LA_EPPV,
38         TEGRA_LA_EPPY,
39         TEGRA_LA_G2PR,
40         TEGRA_LA_G2SR,
41         TEGRA_LA_G2DR,
42         TEGRA_LA_G2DW,
43         TEGRA_LA_HOST1X_DMAR,
44         TEGRA_LA_HOST1XR,
45         TEGRA_LA_HOST1XW,
46         TEGRA_LA_HDAR,
47         TEGRA_LA_HDAW,
48         TEGRA_LA_ISPW,
49         TEGRA_LA_MPCORER,
50         TEGRA_LA_MPCOREW,
51         TEGRA_LA_MPCORE_LPR,
52         TEGRA_LA_MPCORE_LPW,
53         TEGRA_LA_MPE_UNIFBR,
54         TEGRA_LA_MPE_IPRED,
55         TEGRA_LA_MPE_AMEMRD,
56         TEGRA_LA_MPE_CSRD,
57         TEGRA_LA_MPE_UNIFBW,
58         TEGRA_LA_MPE_CSWR,
59         TEGRA_LA_FDCDRD,
60         TEGRA_LA_IDXSRD,
61         TEGRA_LA_TEXSRD,
62         TEGRA_LA_FDCDWR,
63         TEGRA_LA_FDCDRD2,
64         TEGRA_LA_IDXSRD2,
65         TEGRA_LA_TEXSRD2,
66         TEGRA_LA_FDCDWR2,
67         TEGRA_LA_PPCS_AHBDMAR,
68         TEGRA_LA_PPCS_AHBSLVR,
69         TEGRA_LA_PPCS_AHBDMAW,
70         TEGRA_LA_PPCS_AHBSLVW,
71         TEGRA_LA_PTCR,
72         TEGRA_LA_SATAR,
73         TEGRA_LA_SATAW,
74         TEGRA_LA_VDE_BSEVR,
75         TEGRA_LA_VDE_MBER,
76         TEGRA_LA_VDE_MCER,
77         TEGRA_LA_VDE_TPER,
78         TEGRA_LA_VDE_BSEVW,
79         TEGRA_LA_VDE_DBGW,
80         TEGRA_LA_VDE_MBEW,
81         TEGRA_LA_VDE_TPMW,
82         TEGRA_LA_VI_RUV,
83         TEGRA_LA_VI_WSB,
84         TEGRA_LA_VI_WU,
85         TEGRA_LA_VI_WV,
86         TEGRA_LA_VI_WY,
87         TEGRA_LA_MAX_ID
88 };
89
90 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_TEGRA_FPGA_PLATFORM)
91 static inline int tegra_set_latency_allowance(enum tegra_la_id id,
92                                                 int bandwidth_in_mbps)
93 {
94         return 0;
95 }
96
97 static inline int tegra_enable_latency_scaling(enum tegra_la_id id,
98                                                 unsigned int threshold_low,
99                                                 unsigned int threshold_mid,
100                                                 unsigned int threshold_high)
101 {
102         return 0;
103 }
104
105 static inline void tegra_disable_latency_scaling(enum tegra_la_id id)
106 {
107         return 0;
108 }
109 #else
110 int tegra_set_latency_allowance(enum tegra_la_id id,
111                                 unsigned int bandwidth_in_mbps);
112
113 int tegra_enable_latency_scaling(enum tegra_la_id id,
114                                     unsigned int threshold_low,
115                                     unsigned int threshold_mid,
116                                     unsigned int threshold_high);
117
118 void tegra_disable_latency_scaling(enum tegra_la_id id);
119 #endif
120
121 #endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */