arm: tegra: la: la and ptsa updates for t14x.
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / latency_allowance.h
1 /*
2  * arch/arm/mach-tegra/include/mach/latency_allowance.h
3  *
4  * Copyright (C) 2011-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #ifndef _MACH_TEGRA_LATENCY_ALLOWANCE_H_
18 #define _MACH_TEGRA_LATENCY_ALLOWANCE_H_
19
20 enum tegra_la_id {
21         TEGRA_LA_AFIR = 0,                      /* T30 specific */
22         TEGRA_LA_AFIW,                          /* T30 specific */
23         TEGRA_LA_AVPC_ARM7R,
24         TEGRA_LA_AVPC_ARM7W,
25         TEGRA_LA_DISPLAY_0A,
26         TEGRA_LA_DISPLAY_0B,
27         TEGRA_LA_DISPLAY_0C,
28         TEGRA_LA_DISPLAY_1B,                    /* T30 specific */
29         TEGRA_LA_DISPLAY_HC,
30         TEGRA_LA_DISPLAY_0AB,
31         TEGRA_LA_DISPLAY_0BB,
32         TEGRA_LA_DISPLAY_0CB,
33         TEGRA_LA_DISPLAY_1BB,                   /* T30 specific */
34         TEGRA_LA_DISPLAY_HCB,
35         TEGRA_LA_DISPLAY_T,                     /* T14x specific */
36         TEGRA_LA_DISPLAYD,                      /* T14x specific */
37         TEGRA_LA_EPPUP,
38         TEGRA_LA_EPPU,
39         TEGRA_LA_EPPV,
40         TEGRA_LA_EPPY,
41         TEGRA_LA_G2PR,
42         TEGRA_LA_G2SR,
43         TEGRA_LA_G2DR,
44         TEGRA_LA_G2DW,
45         TEGRA_LA_HOST1X_DMAR,
46         TEGRA_LA_HOST1XR,
47         TEGRA_LA_HOST1XW,
48         TEGRA_LA_HDAR,
49         TEGRA_LA_HDAW,
50         TEGRA_LA_ISPW,
51         TEGRA_LA_MPCORER,
52         TEGRA_LA_MPCOREW,
53         TEGRA_LA_MPCORE_LPR,
54         TEGRA_LA_MPCORE_LPW,
55         TEGRA_LA_MPE_UNIFBR,                    /* T30 specific */
56         TEGRA_LA_MPE_IPRED,                     /* T30 specific */
57         TEGRA_LA_MPE_AMEMRD,                    /* T30 specific */
58         TEGRA_LA_MPE_CSRD,                      /* T30 specific */
59         TEGRA_LA_MPE_UNIFBW,                    /* T30 specific */
60         TEGRA_LA_MPE_CSWR,                      /* T30 specific */
61         TEGRA_LA_FDCDRD,
62         TEGRA_LA_IDXSRD,
63         TEGRA_LA_TEXSRD,
64         TEGRA_LA_TEXL2SRD = TEGRA_LA_TEXSRD,    /* T11x, T14x specific */
65         TEGRA_LA_FDCDWR,
66         TEGRA_LA_FDCDRD2,
67         TEGRA_LA_IDXSRD2,                       /* T30 specific */
68         TEGRA_LA_TEXSRD2,                       /* T30 specific */
69         TEGRA_LA_FDCDWR2,
70         TEGRA_LA_PPCS_AHBDMAR,
71         TEGRA_LA_PPCS_AHBSLVR,
72         TEGRA_LA_PPCS_AHBDMAW,
73         TEGRA_LA_PPCS_AHBSLVW,
74         TEGRA_LA_PTCR,
75         TEGRA_LA_SATAR,                         /* T30 specific */
76         TEGRA_LA_SATAW,                         /* T30 specific */
77         TEGRA_LA_VDE_BSEVR,
78         TEGRA_LA_VDE_MBER,
79         TEGRA_LA_VDE_MCER,
80         TEGRA_LA_VDE_TPER,
81         TEGRA_LA_VDE_BSEVW,
82         TEGRA_LA_VDE_DBGW,
83         TEGRA_LA_VDE_MBEW,
84         TEGRA_LA_VDE_TPMW,
85         TEGRA_LA_VI_RUV,                        /* T30 specific */
86         TEGRA_LA_VI_WSB,
87         TEGRA_LA_VI_WU,
88         TEGRA_LA_VI_WV,
89         TEGRA_LA_VI_WY,
90
91         TEGRA_LA_MSENCSRD,                      /* T11x, T14x specific */
92         TEGRA_LA_MSENCSWR,                      /* T11x, T14x specific */
93         TEGRA_LA_XUSB_HOSTR,                    /* T11x specific */
94         TEGRA_LA_XUSB_HOSTW,                    /* T11x specific */
95         TEGRA_LA_XUSB_DEVR,                     /* T11x specific */
96         TEGRA_LA_XUSB_DEVW,                     /* T11x specific */
97         TEGRA_LA_FDCDRD3,                       /* T11x specific */
98         TEGRA_LA_FDCDRD4,                       /* T11x specific */
99         TEGRA_LA_FDCDWR3,                       /* T11x specific */
100         TEGRA_LA_FDCDWR4,                       /* T11x specific */
101         TEGRA_LA_EMUCIFR,                       /* T11x, T14x specific */
102         TEGRA_LA_EMUCIFW,                       /* T11x, T14x specific */
103         TEGRA_LA_TSECSRD,                       /* T11x, T14x specific */
104         TEGRA_LA_TSECSWR,                       /* T11x, T14x specific */
105
106         TEGRA_LA_VI_W,                          /* T14x specific */
107         TEGRA_LA_ISP_RA,                        /* T14x specific */
108         TEGRA_LA_ISP_WA,                        /* T14x specific */
109         TEGRA_LA_ISP_WB,                        /* T14x specific */
110         TEGRA_LA_BBCR,                          /* T14x specific */
111         TEGRA_LA_BBCW,                          /* T14x specific */
112         TEGRA_LA_BBCLLR,                        /* T14x specific */
113         TEGRA_LA_MAX_ID
114 };
115
116 int tegra_set_latency_allowance(enum tegra_la_id id,
117                                 unsigned int bandwidth_in_mbps);
118
119 void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick);
120
121 int tegra_enable_latency_scaling(enum tegra_la_id id,
122                                     unsigned int threshold_low,
123                                     unsigned int threshold_mid,
124                                     unsigned int threshold_high);
125
126 void tegra_disable_latency_scaling(enum tegra_la_id id);
127
128 #endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */