ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / latency_allowance.h
1 /*
2  * arch/arm/mach-tegra/include/mach/latency_allowance.h
3  *
4  * Copyright (C) 2011-2013, NVIDIA CORPORATION. All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #ifndef _MACH_TEGRA_LATENCY_ALLOWANCE_H_
18 #define _MACH_TEGRA_LATENCY_ALLOWANCE_H_
19
20 #define FIRST_DISP_CLIENT_ID    TEGRA_LA_DISPLAY_0A
21 #define DISP_CLIENT_LA_ID(id)   (id - FIRST_DISP_CLIENT_ID)
22
23
24 /* Note:- When adding new display realted IDs, please add them adjacent/amongst
25           the existing display related IDs. This is required because certain
26           display related macros/strcuts assume that all display related
27           tegra_la_ids are adjacent to each other.
28
29           Please observe the same guidelines as display clients, when adding new
30           camera clients. All camera clients need to be located adjacent to each
31           other in tegra_la_id. This is required because certain camera related
32           macros/structs assume that all camera related tegra_la_ids are
33           adjacent to each other. */
34 enum tegra_la_id {
35         TEGRA_LA_AFIR = 0,                      /* T30 specific */
36         TEGRA_LA_AFIW,                          /* T30 specific */
37         TEGRA_LA_AVPC_ARM7R,
38         TEGRA_LA_AVPC_ARM7W,
39         TEGRA_LA_DISPLAY_0A,
40         TEGRA_LA_DISPLAY_0B,
41         TEGRA_LA_DISPLAY_0C,
42         TEGRA_LA_DISPLAY_1B,                    /* T30 specific */
43         TEGRA_LA_DISPLAY_HC,
44         TEGRA_LA_DISPLAY_0AB,
45         TEGRA_LA_DISPLAY_0BB,
46         TEGRA_LA_DISPLAY_0CB,
47         TEGRA_LA_DISPLAY_1BB,                   /* T30 specific */
48         TEGRA_LA_DISPLAY_HCB,
49         TEGRA_LA_DISPLAY_T,                     /* T14x specific */
50         TEGRA_LA_DISPLAYD,                      /* T14x specific */
51         TEGRA_LA_EPPUP,
52         TEGRA_LA_EPPU,
53         TEGRA_LA_EPPV,
54         TEGRA_LA_EPPY,
55         TEGRA_LA_G2PR,
56         TEGRA_LA_G2SR,
57         TEGRA_LA_G2DR,
58         TEGRA_LA_G2DW,
59         TEGRA_LA_GPUSRD,                        /* T12x specific */
60         TEGRA_LA_GPUSWR,                        /* T12x specific */
61         TEGRA_LA_HOST1X_DMAR,
62         TEGRA_LA_HOST1XR,
63         TEGRA_LA_HOST1XW,
64         TEGRA_LA_HDAR,
65         TEGRA_LA_HDAW,
66         TEGRA_LA_ISPW,
67         TEGRA_LA_MPCORER,
68         TEGRA_LA_MPCOREW,
69         TEGRA_LA_MPCORE_LPR,
70         TEGRA_LA_MPCORE_LPW,
71         TEGRA_LA_MPE_UNIFBR,                    /* T30 specific */
72         TEGRA_LA_MPE_IPRED,                     /* T30 specific */
73         TEGRA_LA_MPE_AMEMRD,                    /* T30 specific */
74         TEGRA_LA_MPE_CSRD,                      /* T30 specific */
75         TEGRA_LA_MPE_UNIFBW,                    /* T30 specific */
76         TEGRA_LA_MPE_CSWR,                      /* T30 specific */
77         TEGRA_LA_FDCDRD,
78         TEGRA_LA_IDXSRD,
79         TEGRA_LA_TEXSRD,
80         TEGRA_LA_TEXL2SRD = TEGRA_LA_TEXSRD,    /* T11x, T14x specific */
81         TEGRA_LA_FDCDWR,
82         TEGRA_LA_FDCDRD2,
83         TEGRA_LA_IDXSRD2,                       /* T30 specific */
84         TEGRA_LA_TEXSRD2,                       /* T30 specific */
85         TEGRA_LA_FDCDWR2,
86         TEGRA_LA_PPCS_AHBDMAR,
87         TEGRA_LA_PPCS_AHBSLVR,
88         TEGRA_LA_PPCS_AHBDMAW,
89         TEGRA_LA_PPCS_AHBSLVW,
90         TEGRA_LA_PTCR,
91         TEGRA_LA_SATAR,                         /* T30 specific */
92         TEGRA_LA_SATAW,                         /* T30 specific */
93         TEGRA_LA_VDE_BSEVR,
94         TEGRA_LA_VDE_MBER,
95         TEGRA_LA_VDE_MCER,
96         TEGRA_LA_VDE_TPER,
97         TEGRA_LA_VDE_BSEVW,
98         TEGRA_LA_VDE_DBGW,
99         TEGRA_LA_VDE_MBEW,
100         TEGRA_LA_VDE_TPMW,
101         TEGRA_LA_VI_RUV,                        /* T30 specific */
102         TEGRA_LA_VI_WSB,
103         TEGRA_LA_VI_WU,
104         TEGRA_LA_VI_WV,
105         TEGRA_LA_VI_WY,
106
107         TEGRA_LA_MSENCSRD,                      /* T11x, T14x specific */
108         TEGRA_LA_MSENCSWR,                      /* T11x, T14x specific */
109         TEGRA_LA_XUSB_HOSTR,                    /* T11x specific */
110         TEGRA_LA_XUSB_HOSTW,                    /* T11x specific */
111         TEGRA_LA_XUSB_DEVR,                     /* T11x specific */
112         TEGRA_LA_XUSB_DEVW,                     /* T11x specific */
113         TEGRA_LA_FDCDRD3,                       /* T11x specific */
114         TEGRA_LA_FDCDRD4,                       /* T11x specific */
115         TEGRA_LA_FDCDWR3,                       /* T11x specific */
116         TEGRA_LA_FDCDWR4,                       /* T11x specific */
117         TEGRA_LA_EMUCIFR,                       /* T11x, T14x specific */
118         TEGRA_LA_EMUCIFW,                       /* T11x, T14x specific */
119         TEGRA_LA_TSECSRD,                       /* T11x, T14x specific */
120         TEGRA_LA_TSECSWR,                       /* T11x, T14x specific */
121
122         TEGRA_LA_VI_W,                          /* T14x specific */
123         TEGRA_LA_ISP_RA,                        /* T14x specific */
124         TEGRA_LA_ISP_WA,                        /* T14x specific */
125         TEGRA_LA_ISP_WB,                        /* T14x specific */
126         TEGRA_LA_ISP_RAB,                       /* T12x specific */
127         TEGRA_LA_ISP_WAB,                       /* T12x specific */
128         TEGRA_LA_ISP_WBB,                       /* T12x specific */
129         TEGRA_LA_BBCR,                          /* T14x specific */
130         TEGRA_LA_BBCW,                          /* T14x specific */
131         TEGRA_LA_BBCLLR,                        /* T14x specific */
132         TEGRA_LA_SDMMCR,                        /* T12x specific */
133         TEGRA_LA_SDMMCRA,                       /* T12x specific */
134         TEGRA_LA_SDMMCRAA,                      /* T12x specific */
135         TEGRA_LA_SDMMCRAB,                      /* T12x specific */
136         TEGRA_LA_SDMMCW,                        /* T12x specific */
137         TEGRA_LA_SDMMCWA,                       /* T12x specific */
138         TEGRA_LA_SDMMCWAA,                      /* T12x specific */
139         TEGRA_LA_SDMMCWAB,                      /* T12x specific */
140         TEGRA_LA_VICSRD,                        /* T12x specific */
141         TEGRA_LA_VICSWR,                        /* T12x specific */
142         TEGRA_LA_MAX_ID
143 };
144
145 enum disp_win_type {
146         TEGRA_LA_DISP_WIN_TYPE_FULL,
147         TEGRA_LA_DISP_WIN_TYPE_FULLA,
148         TEGRA_LA_DISP_WIN_TYPE_FULLB,
149         TEGRA_LA_DISP_WIN_TYPE_SIMPLE,
150         TEGRA_LA_DISP_WIN_TYPE_CURSOR,
151         TEGRA_LA_DISP_WIN_TYPE_NUM_TYPES
152 };
153
154 struct disp_client {
155         enum disp_win_type win_type;
156         unsigned int mccif_size_bytes;
157         unsigned int line_buf_sz_bytes;
158 };
159
160 struct dc_to_la_params {
161         unsigned int thresh_lwm_bytes;
162         unsigned int spool_up_buffering_adj_bytes;
163         unsigned int total_dc0_bw;
164         unsigned int total_dc1_bw;
165 };
166
167 struct la_to_dc_params {
168         unsigned int fp_factor;
169         unsigned int (*la_real_to_fp)(unsigned int val);
170         unsigned int (*la_fp_to_real)(unsigned int val);
171         unsigned int static_la_minus_snap_arb_to_row_srt_emcclks_fp;
172         unsigned int dram_width_bits;
173         unsigned int disp_catchup_factor_fp;
174 };
175
176 int tegra_set_disp_latency_allowance(enum tegra_la_id id,
177                                         unsigned int bandwidth_in_mbps,
178                                         struct dc_to_la_params disp_params);
179
180 int tegra_set_latency_allowance(enum tegra_la_id id,
181                                 unsigned int bandwidth_in_mbps);
182
183 int tegra_set_camera_ptsa(enum tegra_la_id id,
184                         unsigned int bw_mbps,
185                         int is_hiso);
186
187 void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick);
188
189 int tegra_enable_latency_scaling(enum tegra_la_id id,
190                                     unsigned int threshold_low,
191                                     unsigned int threshold_mid,
192                                     unsigned int threshold_high);
193
194 void tegra_disable_latency_scaling(enum tegra_la_id id);
195
196 struct la_to_dc_params tegra_get_la_to_dc_params(void);
197
198 /* FIXME!!:- This function needs to be implemented properly elsewhere. */
199 unsigned int tegra_get_dvfs_time_nsec(unsigned long emc_freq_mhz);
200
201 extern const struct disp_client *tegra_la_disp_clients_info;
202
203 #endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */