[ARM] tegra_i2s_audio: support mono capture
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / i2s.h
1 /*
2  * arch/arm/mach-tegra/include/mach/i2s.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  *      Iliyan Malchev <malchev@google.com>
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #ifndef __ARCH_ARM_MACH_TEGRA_I2S_H
21 #define __ARCH_ARM_MACH_TEGRA_I2S_H
22
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/platform_device.h>
26
27 /* Offsets from TEGRA_I2S1_BASE and TEGRA_I2S2_BASE */
28
29 #define I2S_I2S_CTRL_0                  0
30 #define I2S_I2S_STATUS_0                4
31 #define I2S_I2S_TIMING_0                8
32 #define I2S_I2S_FIFO_SCR_0              0x0c
33 #define I2S_I2S_PCM_CTRL_0              0x10
34 #define I2S_I2S_NW_CTRL_0               0x14
35 #define I2S_I2S_TDM_CTRL_0              0x20
36 #define I2S_I2S_TDM_TX_RX_CTRL_0        0x24
37 #define I2S_I2S_FIFO1_0                 0x40
38 #define I2S_I2S_FIFO2_0                 0x80
39
40 /*
41  * I2S_I2S_CTRL_0
42  */
43
44 #define I2S_I2S_CTRL_FIFO2_TX_ENABLE            (1<<30)
45 #define I2S_I2S_CTRL_FIFO1_ENABLE               (1<<29)
46 #define I2S_I2S_CTRL_FIFO2_ENABLE               (1<<28)
47 #define I2S_I2S_CTRL_FIFO1_RX_ENABLE            (1<<27)
48 #define I2S_I2S_CTRL_FIFO_LPBK_ENABLE           (1<<26)
49 #define I2S_I2S_CTRL_MASTER_ENABLE              (1<<25)
50 #define I2S_I2S_CTRL_L_R_CTRL                   (1<<24) /* 0 = L/R: low/high */
51
52 #define I2S_BIT_FORMAT_I2S 0
53 #define I2S_BIT_FORMAT_RJM 1
54 #define I2S_BIT_FORMAT_LJM 2
55 #define I2S_BIT_FORMAT_DSP 3
56 #define I2S_BIT_FORMAT_SHIFT 10
57
58 #define I2S_I2S_CTRL_BIT_FORMAT_MASK            (3<<10)
59 #define I2S_I2S_CTRL_BIT_FORMAT_I2S             (I2S_BIT_FORMAT_I2S<<10)
60 #define I2S_I2S_CTRL_BIT_FORMAT_RJM             (I2S_BIT_FORMAT_RJM<<10)
61 #define I2S_I2S_CTRL_BIT_FORMAT_LJM             (I2S_BIT_FORMAT_LJM<<10)
62 #define I2S_I2S_CTRL_BIT_FORMAT_DSP             (I2S_BIT_FORMAT_DSP<<10)
63
64 #define I2S_BIT_SIZE_16 0
65 #define I2S_BIT_SIZE_20 1
66 #define I2S_BIT_SIZE_24 2
67 #define I2S_BIT_SIZE_32 3
68 #define I2S_BIT_SIZE_SHIFT 8
69
70 #define I2S_I2S_CTRL_BIT_SIZE_MASK      (3 << I2S_BIT_SIZE_SHIFT)
71 #define I2S_I2S_CTRL_BIT_SIZE_16        (I2S_BIT_SIZE_16 << I2S_BIT_SIZE_SHIFT)
72 #define I2S_I2S_CTRL_BIT_SIZE_20        (I2S_BIT_SIZE_20 << I2S_BIT_SIZE_SHIFT)
73 #define I2S_I2S_CTRL_BIT_SIZE_24        (I2S_BIT_SIZE_24 << I2S_BIT_SIZE_SHIFT)
74 #define I2S_I2S_CTRL_BIT_SIZE_32        (I2S_BIT_SIZE_32 << I2S_BIT_SIZE_SHIFT)
75
76 #define I2S_FIFO_16_LSB 0
77 #define I2S_FIFO_20_LSB 1
78 #define I2S_FIFO_24_LSB 2
79 #define I2S_FIFO_32     3
80 #define I2S_FIFO_PACKED 7
81 #define I2S_FIFO_SHIFT  4
82
83 #define I2S_I2S_CTRL_FIFO_FORMAT_MASK           (7<<4)
84 #define I2S_I2S_CTRL_FIFO_FORMAT_16_LSB         \
85                 (I2S_FIFO_16_LSB << I2S_FIFO_SHIFT)
86 #define I2S_I2S_CTRL_FIFO_FORMAT_20_LSB         \
87                 (I2S_FIFO_20_LSB << I2S_FIFO_SHIFT)
88 #define I2S_I2S_CTRL_FIFO_FORMAT_24_LSB         \
89                 (I2S_FIFO_24_LSB << I2S_FIFO_SHIFT)
90 #define I2S_I2S_CTRL_FIFO_FORMAT_32             \
91                 (I2S_FIFO_32 << I2S_FIFO_SHIFT)
92 #define I2S_I2S_CTRL_FIFO_FORMAT_PACKED         \
93                 (I2S_FIFO_PACKED << I2S_FIFO_SHIFT)
94
95 #define I2S_I2S_IE_FIFO1_ERR                    (1<<3)
96 #define I2S_I2S_IE_FIFO2_ERR                    (1<<2)
97 #define I2S_I2S_QE_FIFO1                        (1<<1)
98 #define I2S_I2S_QE_FIFO2                        (1<<0)
99
100 /*
101  * I2S_I2S_STATUS_0
102  */
103
104 #define I2S_I2S_STATUS_FIFO1_RDY                (1<<31)
105 #define I2S_I2S_STATUS_FIFO2_RDY                (1<<30)
106 #define I2S_I2S_STATUS_FIFO1_BSY                (1<<29)
107 #define I2S_I2S_STATUS_FIFO2_BSY                (1<<28)
108 #define I2S_I2S_STATUS_FIFO1_ERR                (1<<3)
109 #define I2S_I2S_STATUS_FIFO2_ERR                (1<<2)
110 #define I2S_I2S_STATUS_QS_FIFO1                 (1<<1)
111 #define I2S_I2S_STATUS_QS_FIFO2                 (1<<0)
112
113 /*
114  * I2S_I2S_TIMING_0
115  */
116
117 #define I2S_I2S_TIMING_NON_SYM_ENABLE           (1<<12)
118 #define I2S_I2S_TIMING_CHANNEL_BIT_COUNT_MASK   0x7ff
119 #define I2S_I2S_TIMING_CHANNEL_BIT_COUNT        (1<<0)
120
121 /*
122  * I2S_I2S_FIFO_SCR_0
123  */
124
125 #define I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK  0x3f
126 #define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
127 #define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
128
129 #define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_MASK    (0x3f<<24)
130 #define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_MASK    (0x3f<<16)
131
132 #define I2S_I2S_FIFO_SCR_FIFO2_CLR                      (1<<12)
133 #define I2S_I2S_FIFO_SCR_FIFO1_CLR                      (1<<8)
134
135 #define I2S_FIFO_ATN_LVL_ONE_SLOT       0
136 #define I2S_FIFO_ATN_LVL_FOUR_SLOTS     1
137 #define I2S_FIFO_ATN_LVL_EIGHT_SLOTS    2
138 #define I2S_FIFO_ATN_LVL_TWELVE_SLOTS   3
139 #define I2S_FIFO2_ATN_LVL_SHIFT         4
140 #define I2S_FIFO1_ATN_LVL_SHIFT         0
141
142 #define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK             \
143                 (3 << I2S_FIFO2_ATN_LVL_SHIFT)
144 #define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT         \
145                 (I2S_FIFO_ATN_LVL_ONE_SLOT     << I2S_FIFO2_ATN_LVL_SHIFT)
146 #define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS       \
147                 (I2S_FIFO_ATN_LVL_FOUR_SLOTS   << I2S_FIFO2_ATN_LVL_SHIFT)
148 #define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS      \
149                 (I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << I2S_FIFO2_ATN_LVL_SHIFT)
150 #define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS     \
151                 (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
152
153 #define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK             \
154                 (3 << I2S_FIFO1_ATN_LVL_SHIFT)
155 #define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT         \
156                 (I2S_FIFO_ATN_LVL_ONE_SLOT     << I2S_FIFO1_ATN_LVL_SHIFT)
157 #define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS       \
158                 (I2S_FIFO_ATN_LVL_FOUR_SLOTS   << I2S_FIFO1_ATN_LVL_SHIFT)
159 #define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS      \
160                 (I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << I2S_FIFO1_ATN_LVL_SHIFT)
161 #define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS     \
162                 (I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
163 /*
164  * I2S_I2S_PCM_CTRL_0
165  */
166 #define I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ              0
167 #define I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ                 1
168 #define I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ              2
169 #define I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ                 3
170 #define I2S_PCM_TRM_EDGE_CTRL_SHIFT                     9
171
172 #define I2S_I2S_PCM_TRM_EDGE_CTRL_MASK                  \
173                 (3 << I2S_I2S_PCM_TRM_EDGE_CTRL_SHIFT)
174 #define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ          \
175                 (I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ        \
176                 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
177 #define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ             \
178                 (I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ     \
179                 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
180 #define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ          \
181                 (I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ     \
182                 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
183 #define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ             \
184                 (I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ        \
185                 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
186
187 #define I2S_PCM_TRM_MASK_BITS_ZERO                      0
188 #define I2S_PCM_TRM_MASK_BITS_ONE                       1
189 #define I2S_PCM_TRM_MASK_BITS_TWO                       2
190 #define I2S_PCM_TRM_MASK_BITS_THREE                     3
191 #define I2S_PCM_TRM_MASK_BITS_FOUR                      4
192 #define I2S_PCM_TRM_MASK_BITS_FIVE                      5
193 #define I2S_PCM_TRM_MASK_BITS_SIX                       6
194 #define I2S_PCM_TRM_MASK_BITS_SEVEN                     7
195 #define I2S_PCM_TRM_MASK_BITS_SHIFT                     6
196
197 #define I2S_I2S_PCM_TRM_MASK_BITS_MASK                  \
198                 (7 << I2S_PCM_TRM_MASK_BITS_SHIFT)
199 #define I2S_I2S_PCM_TRM_MASK_BITS_ZERO                  \
200                 (I2S_PCM_TRM_MASK_BITS_ZERO             \
201                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
202 #define I2S_I2S_PCM_TRM_MASK_BITS_ONE                   \
203                 (I2S_PCM_TRM_MASK_BITS_ONE              \
204                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
205 #define I2S_I2S_PCM_TRM_MASK_BITS_TWO                   \
206                 (I2S_PCM_TRM_MASK_BITS_TWO              \
207                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
208 #define I2S_I2S_PCM_TRM_MASK_BITS_THREE                 \
209                 (I2S_PCM_TRM_MASK_BITS_THREE            \
210                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
211 #define I2S_I2S_PCM_TRM_MASK_BITS_FOUR                  \
212                 (I2S_PCM_TRM_MASK_BITS_FOUR             \
213                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
214 #define I2S_I2S_PCM_TRM_MASK_BITS_FIVE                  \
215                 (I2S_PCM_TRM_MASK_BITS_FIVE             \
216                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
217 #define I2S_I2S_PCM_TRM_MASK_BITS_SIX                   \
218                 (I2S_PCM_TRM_MASK_BITS_SIX              \
219                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
220 #define I2S_I2S_PCM_TRM_MASK_BITS_SEVEN                 \
221                 (I2S_PCM_TRM_MASK_BITS_SEVEN            \
222                 << I2S_PCM_TRM_MASK_BITS_SHIFT)
223
224 #define I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL                 (1<<5)
225 #define I2S_I2S_PCM_CTRL_TRM_MODE                       (1<<4)
226
227 #define I2S_PCM_RCV_MASK_BITS_ZERO                      0
228 #define I2S_PCM_RCV_MASK_BITS_ONE                       1
229 #define I2S_PCM_RCV_MASK_BITS_TWO                       2
230 #define I2S_PCM_RCV_MASK_BITS_THREE                     3
231 #define I2S_PCM_RCV_MASK_BITS_FOUR                      4
232 #define I2S_PCM_RCV_MASK_BITS_FIVE                      5
233 #define I2S_PCM_RCV_MASK_BITS_SIX                       6
234 #define I2S_PCM_RCV_MASK_BITS_SEVEN                     7
235 #define I2S_PCM_RCV_MASK_BITS_SHIFT                     1
236
237 #define I2S_I2S_PCM_RCV_MASK_BITS_MASK                  \
238                 (7 << I2S_PCM_RCV_MASK_BITS_SHIFT)
239 #define I2S_I2S_PCM_RCV_MASK_BITS_ZERO                  \
240                 (I2S_PCM_RCV_MASK_BITS_ZERO             \
241                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
242 #define I2S_I2S_PCM_RCV_MASK_BITS_ONE                   \
243                 (I2S_PCM_RCV_MASK_BITS_ONE              \
244                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
245 #define I2S_I2S_PCM_RCV_MASK_BITS_TWO                   \
246                 (I2S_PCM_RCV_MASK_BITS_TWO              \
247                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
248 #define I2S_I2S_PCM_RCV_MASK_BITS_THREE                 \
249                 (I2S_PCM_RCV_MASK_BITS_THREE            \
250                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
251 #define I2S_I2S_PCM_RCV_MASK_BITS_FOUR                  \
252                 (I2S_PCM_RCV_MASK_BITS_FOUR             \
253                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
254 #define I2S_I2S_PCM_RCV_MASK_BITS_FIVE                  \
255                 (I2S_PCM_RCV_MASK_BITS_FIVE             \
256                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
257 #define I2S_I2S_PCM_RCV_MASK_BITS_SIX                   \
258                 (I2S_PCM_RCV_MASK_BITS_SIX              \
259                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
260 #define I2S_I2S_PCM_RCV_MASK_BITS_SEVEN                 \
261                 (I2S_PCM_RCV_MASK_BITS_SEVEN            \
262                 << I2S_PCM_RCV_MASK_BITS_SHIFT)
263
264 #define I2S_I2S_PCM_CTRL_RCV_MODE                       (1<<0)
265
266 /*
267  * I2S_I2S_NW_CTRL_0
268  */
269
270 #define I2S_TRM_TLPHY_SLOT_SEL_SLOT1                    0
271 #define I2S_TRM_TLPHY_SLOT_SEL_SLOT2                    1
272 #define I2S_TRM_TLPHY_SLOT_SEL_SLOT3                    2
273 #define I2S_TRM_TLPHY_SLOT_SEL_SLOT4                    3
274 #define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT             4
275
276 #define I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_MASK              \
277                 (3 << I2S_TRM_TLPHY_SLOT_SEL_SHIFT)
278 #define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT1                \
279                 (I2S_TRM_TLPHY_SLOT_SEL_SLOT1           \
280                 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
281 #define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT2                \
282                 (I2S_TRM_TLPHY_SLOT_SEL_SLOT2           \
283                 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
284 #define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT3                \
285                 (I2S_TRM_TLPHY_SLOT_SEL_SLOT3           \
286                 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
287 #define I2S_I2S_TRM_TLPHY_SLOT_SEL_SLOT4                \
288                 (I2S_TRM_TLPHY_SLOT_SEL_SLOT4           \
289                 << I2S_I2S_NW_TRM_TLPHY_SLOT_SEL_SHIFT)
290
291 #define I2S_I2S_NW_CTRL_TRM_TLPHY_MODE                  (1<<3)
292
293 #define I2S_RCV_TLPHY_SLOT_SEL_SLOT1                    0
294 #define I2S_RCV_TLPHY_SLOT_SEL_SLOT2                    1
295 #define I2S_RCV_TLPHY_SLOT_SEL_SLOT3                    2
296 #define I2S_RCV_TLPHY_SLOT_SEL_SLOT4                    3
297 #define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT             1
298
299 #define I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_MASK              \
300                 (3 << I2S_RCV_TLPHY_SLOT_SEL_SHIFT)
301 #define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT1                \
302                 (I2S_RCV_TLPHY_SLOT_SEL_SLOT1           \
303                 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
304 #define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT2                \
305                 (I2S_RCV_TLPHY_SLOT_SEL_SLOT2           \
306                 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
307 #define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT3                \
308                 (I2S_RCV_TLPHY_SLOT_SEL_SLOT3           \
309                 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
310 #define I2S_I2S_RCV_TLPHY_SLOT_SEL_SLOT4                \
311                 (I2S_RCV_TLPHY_SLOT_SEL_SLOT4           \
312                 << I2S_I2S_NW_RCV_TLPHY_SLOT_SEL_SHIFT)
313
314 #define I2S_I2S_NW_CTRL_RCV_TLPHY_MODE                  (1<<0)
315
316 #endif /* __ARCH_ARM_MACH_TEGRA_I2S_H */