73c1176a7b0a66dc31fd33f6dcd4feab9f3c873b
[linux-3.10.git] / arch / arm / mach-tegra / include / mach / dc.h
1 /*
2  * arch/arm/mach-tegra/include/mach/dc.h
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  *      Erik Gilling <konkers@google.com>
8  *
9  * Copyright (C) 2010-2011 NVIDIA Corporation
10  *
11  * This software is licensed under the terms of the GNU General Public
12  * License version 2, as published by the Free Software Foundation, and
13  * may be copied, distributed, and modified under those terms.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  */
21
22 #ifndef __MACH_TEGRA_DC_H
23 #define __MACH_TEGRA_DC_H
24
25 #include <linux/pm.h>
26 #include <linux/types.h>
27 #include <drm/drm_fixed.h>
28
29 #define TEGRA_MAX_DC            2
30 #define DC_N_WINDOWS            3
31 #define DEFAULT_FPGA_FREQ_KHZ   160000
32
33
34 /* DSI pixel data format */
35 enum {
36         TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
37         TEGRA_DSI_PIXEL_FORMAT_18BIT_P,
38         TEGRA_DSI_PIXEL_FORMAT_18BIT_NP,
39         TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
40 };
41
42 /* DSI virtual channel number */
43 enum {
44         TEGRA_DSI_VIRTUAL_CHANNEL_0,
45         TEGRA_DSI_VIRTUAL_CHANNEL_1,
46         TEGRA_DSI_VIRTUAL_CHANNEL_2,
47         TEGRA_DSI_VIRTUAL_CHANNEL_3,
48 };
49
50 /* DSI transmit method for video data */
51 enum {
52         TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
53         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
54 };
55
56 /* DSI HS clock mode */
57 enum {
58         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
59         TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
60 };
61
62 /* DSI burst mode setting in video mode. Each mode is assigned with a
63  * fixed value. The rationale behind this is to avoid change of these
64  * values, since the calculation of dsi clock depends on them. */
65 enum {
66         TEGRA_DSI_VIDEO_NONE_BURST_MODE = 0,
67         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END = 1,
68         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
69         TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
70         TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
71         TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
72         TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
73 };
74
75 enum {
76         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT = 1,
77         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD = 2,
78 };
79
80 enum {
81         TEGRA_DSI_PACKET_CMD,
82         TEGRA_DSI_DELAY_MS,
83 };
84
85 struct tegra_dsi_cmd {
86         u8      cmd_type;
87         u8      data_id;
88         union {
89                 u16 data_len;
90                 u16 delay_ms;
91                 struct {
92                         u8 data0;
93                         u8 data1;
94                 } sp;
95         } sp_len_dly;
96         u8      *pdata;
97 };
98
99 #define DSI_GENERIC_LONG_WRITE                  0x29
100 #define DSI_GENERIC_SHORT_WRITE_2_PARAMS        0x23
101 #define DSI_DCS_WRITE_0_PARAM                   0x05
102 #define DSI_DCS_WRITE_1_PARAM                   0x15
103
104 #define DSI_DCS_SET_ADDR_MODE                   0x36
105 #define DSI_DCS_EXIT_SLEEP_MODE                 0x11
106 #define DSI_DCS_SET_DISPLAY_ON                  0x29
107
108 #define DSI_CMD_SHORT(di, p0, p1)       { \
109                                         .cmd_type = TEGRA_DSI_PACKET_CMD, \
110                                         .data_id = di, \
111                                         .sp_len_dly.sp.data0 = p0, \
112                                         .sp_len_dly.sp.data1 = p1, \
113                                         }
114 #define DSI_DLY_MS(ms)  { \
115                         .cmd_type = TEGRA_DSI_DELAY_MS, \
116                         .sp_len_dly.delay_ms = ms, \
117                         }
118
119 #define DSI_CMD_LONG(di, ptr)   { \
120                                 .cmd_type = TEGRA_DSI_PACKET_CMD, \
121                                 .data_id = di, \
122                                 .sp_len_dly.data_len = ARRAY_SIZE(ptr), \
123                                 .pdata = ptr, \
124                                 }
125
126 struct dsi_phy_timing_ns {
127         u16             t_hsdexit_ns;
128         u16             t_hstrail_ns;
129         u16             t_datzero_ns;
130         u16             t_hsprepare_ns;
131
132         u16             t_clktrail_ns;
133         u16             t_clkpost_ns;
134         u16             t_clkzero_ns;
135         u16             t_tlpx_ns;
136
137         u16             t_clkprepare_ns;
138         u16             t_clkpre_ns;
139         u16             t_wakeup_ns;
140
141         u16             t_taget_ns;
142         u16             t_tasure_ns;
143         u16             t_tago_ns;
144 };
145
146 enum {
147         DSI_VS_0 = 0x0,
148         DSI_VS_1 = 0x1,
149 };
150
151 enum {
152         DSI_INSTANCE_0,
153         DSI_INSTANCE_1,
154 };
155
156 /* Aggressiveness level of DSI suspend. The higher, the more aggressive. */
157 #define DSI_NO_SUSPEND                  0
158 #define DSI_HOST_SUSPEND_LV0            1
159 #define DSI_HOST_SUSPEND_LV1            2
160 #define DSI_HOST_SUSPEND_LV2            3
161 #define DSI_SUSPEND_FULL                4
162
163 struct tegra_dsi_out {
164         u8              n_data_lanes;                   /* required */
165         u8              pixel_format;                   /* required */
166         u8              refresh_rate;                   /* required */
167         u8              rated_refresh_rate;
168         u8              panel_reset;                    /* required */
169         u8              virtual_channel;                /* required */
170         u8              dsi_instance;
171         u8              chip_id;
172         u8              chip_rev;
173         u8              controller_vs;
174
175         bool            panel_has_frame_buffer; /* required*/
176         bool            panel_send_dc_frames;
177
178         struct tegra_dsi_cmd    *dsi_init_cmd;          /* required */
179         u16             n_init_cmd;                     /* required */
180
181         struct tegra_dsi_cmd    *dsi_early_suspend_cmd;
182         u16             n_early_suspend_cmd;
183
184         struct tegra_dsi_cmd    *dsi_late_resume_cmd;
185         u16             n_late_resume_cmd;
186
187         struct tegra_dsi_cmd    *dsi_suspend_cmd;       /* required */
188         u16             n_suspend_cmd;                  /* required */
189
190         u8              video_data_type;                /* required */
191         u8              video_clock_mode;
192         u8              video_burst_mode;
193         u8              ganged_type;
194
195         u8              suspend_aggr;
196
197         u16             panel_buffer_size_byte;
198         u16             panel_reset_timeout_msec;
199
200         bool            hs_cmd_mode_supported;
201         bool            hs_cmd_mode_on_blank_supported;
202         bool            enable_hs_clock_on_lp_cmd_mode;
203         bool            no_pkt_seq_eot; /* 1st generation panel may not
204                                          * support eot. Don't set it for
205                                          * most panels. */
206         bool            te_polarity_low;
207         bool            power_saving_suspend;
208         bool            dsi2lvds_bridge_enable;
209         bool            dsi2edp_bridge_enable;
210
211         u32             max_panel_freq_khz;
212         u32             lp_cmd_mode_freq_khz;
213         u32             lp_read_cmd_mode_freq_khz;
214         u32             hs_clk_in_lp_cmd_mode_freq_khz;
215         u32             burst_mode_freq_khz;
216         u32             fpga_freq_khz;
217
218         struct dsi_phy_timing_ns phy_timing;
219 };
220
221 enum {
222         TEGRA_DC_STEREO_MODE_2D,
223         TEGRA_DC_STEREO_MODE_3D
224 };
225
226 enum {
227         TEGRA_DC_STEREO_LANDSCAPE,
228         TEGRA_DC_STEREO_PORTRAIT
229 };
230
231 struct tegra_stereo_out {
232         int  mode_2d_3d;
233         int  orientation;
234
235         void (*set_mode)(int mode);
236         void (*set_orientation)(int orientation);
237 };
238
239 struct tegra_dc_mode {
240         int     pclk;
241         int     rated_pclk;
242         int     h_ref_to_sync;
243         int     v_ref_to_sync;
244         int     h_sync_width;
245         int     v_sync_width;
246         int     h_back_porch;
247         int     v_back_porch;
248         int     h_active;
249         int     v_active;
250         int     h_front_porch;
251         int     v_front_porch;
252         int     stereo_mode;
253         u32     flags;
254 };
255
256 #define TEGRA_DC_MODE_FLAG_NEG_V_SYNC   (1 << 0)
257 #define TEGRA_DC_MODE_FLAG_NEG_H_SYNC   (1 << 1)
258
259 enum {
260         TEGRA_DC_OUT_RGB,
261         TEGRA_DC_OUT_HDMI,
262         TEGRA_DC_OUT_DSI,
263 };
264
265 struct tegra_dc_out_pin {
266         int     name;
267         int     pol;
268 };
269
270 enum {
271         TEGRA_DC_OUT_PIN_DATA_ENABLE,
272         TEGRA_DC_OUT_PIN_H_SYNC,
273         TEGRA_DC_OUT_PIN_V_SYNC,
274         TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
275 };
276
277 enum {
278         TEGRA_DC_OUT_PIN_POL_LOW,
279         TEGRA_DC_OUT_PIN_POL_HIGH,
280 };
281
282 enum {
283         TEGRA_DC_DISABLE_DITHER = 1,
284         TEGRA_DC_ORDERED_DITHER,
285         TEGRA_DC_ERRDIFF_DITHER,
286 };
287
288 typedef u8 tegra_dc_bl_output[256];
289 typedef u8 *p_tegra_dc_bl_output;
290
291 struct tegra_dc_sd_blp {
292         u16 time_constant;
293         u8 step;
294 };
295
296 struct tegra_dc_sd_fc {
297         u8 time_limit;
298         u8 threshold;
299 };
300
301 struct tegra_dc_sd_rgb {
302         u8 r;
303         u8 g;
304         u8 b;
305 };
306
307 struct tegra_dc_sd_agg_priorities {
308         u8 pri_lvl;
309         u8 agg[4];
310 };
311
312 struct tegra_dc_sd_window {
313         u16 h_position;
314         u16 v_position;
315         u16 h_size;
316         u16 v_size;
317 };
318
319 struct tegra_dc_sd_settings {
320         unsigned enable;
321         bool use_auto_pwm;
322         u8 hw_update_delay;
323         u8 aggressiveness;
324         short bin_width;
325         u8 phase_in_settings;
326         u8 phase_in_adjustments;
327         u8 cmd;
328         u8 final_agg;
329         u16 cur_agg_step;
330         u16 phase_settings_step;
331         u16 phase_adj_step;
332         u16 num_phase_in_steps;
333
334         struct tegra_dc_sd_agg_priorities agg_priorities;
335
336         bool use_vid_luma;
337         struct tegra_dc_sd_rgb coeff;
338
339         bool k_limit_enable;
340         u16 k_limit;
341
342         bool sd_window_enable;
343         struct tegra_dc_sd_window sd_window;
344
345         bool soft_clipping_enable;
346         u8 soft_clipping_threshold;
347
348         bool smooth_k_enable;
349         u16 smooth_k_incr;
350
351         bool sd_proc_control;
352
353         struct tegra_dc_sd_fc fc;
354         struct tegra_dc_sd_blp blp;
355         u8 bltf[4][4][4];
356         struct tegra_dc_sd_rgb lut[4][9];
357
358         atomic_t *sd_brightness;
359         struct platform_device *bl_device;
360 };
361
362 enum {
363         NO_CMD = 0x0,
364         ENABLE = 0x1,
365         DISABLE = 0x2,
366         PHASE_IN = 0x4,
367         AGG_CHG = 0x8,
368 };
369
370 enum {
371         TEGRA_PIN_OUT_CONFIG_SEL_LHP0_LD21,
372         TEGRA_PIN_OUT_CONFIG_SEL_LHP1_LD18,
373         TEGRA_PIN_OUT_CONFIG_SEL_LHP2_LD19,
374         TEGRA_PIN_OUT_CONFIG_SEL_LVP0_LVP0_Out,
375         TEGRA_PIN_OUT_CONFIG_SEL_LVP1_LD20,
376
377         TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1,
378         TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21,
379         TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1,
380
381         TEGRA_PIN_OUT_CONFIG_SEL_LDI_LD22,
382         TEGRA_PIN_OUT_CONFIG_SEL_LPP_LD23,
383         TEGRA_PIN_OUT_CONFIG_SEL_LDC_SDC,
384         TEGRA_PIN_OUT_CONFIG_SEL_LSPI_DE,
385 };
386
387 struct tegra_dc_out {
388         int                             type;
389         unsigned                        flags;
390
391         /* size in mm */
392         unsigned                        h_size;
393         unsigned                        v_size;
394
395         int                             dcc_bus;
396         int                             hotplug_gpio;
397         const char                      *parent_clk;
398         const char                      *parent_clk_backup;
399
400         unsigned                        max_pixclock;
401         unsigned                        order;
402         unsigned                        align;
403         unsigned                        depth;
404         unsigned                        dither;
405
406         struct tegra_dc_mode            *modes;
407         int                             n_modes;
408
409         struct tegra_dsi_out            *dsi;
410         struct tegra_stereo_out         *stereo;
411
412         unsigned                        height; /* mm */
413         unsigned                        width; /* mm */
414
415         struct tegra_dc_out_pin         *out_pins;
416         unsigned                        n_out_pins;
417
418         struct tegra_dc_sd_settings     *sd_settings;
419
420         u8                      *out_sel_configs;
421         unsigned                n_out_sel_configs;
422
423         int     (*enable)(void);
424         int     (*postpoweron)(void);
425         int     (*prepoweroff)(void);
426         int     (*disable)(void);
427
428         int     (*hotplug_init)(void);
429         int     (*postsuspend)(void);
430 };
431
432 /* bits for tegra_dc_out.flags */
433 #define TEGRA_DC_OUT_HOTPLUG_HIGH               (0 << 1)
434 #define TEGRA_DC_OUT_HOTPLUG_LOW                (1 << 1)
435 #define TEGRA_DC_OUT_HOTPLUG_MASK               (1 << 1)
436 #define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON    (0 << 2)
437 #define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND    (1 << 2)
438 #define TEGRA_DC_OUT_NVHDCP_POLICY_MASK         (1 << 2)
439 #define TEGRA_DC_OUT_CONTINUOUS_MODE            (0 << 3)
440 #define TEGRA_DC_OUT_ONE_SHOT_MODE              (1 << 3)
441 #define TEGRA_DC_OUT_N_SHOT_MODE                (1 << 4)
442 #define TEGRA_DC_OUT_ONE_SHOT_LP_MODE           (1 << 5)
443 #define TEGRA_DC_OUT_CMU_DISABLE                (0 << 5)
444 #define TEGRA_DC_OUT_CMU_ENABLE                 (1 << 5)
445
446 #define TEGRA_DC_ALIGN_MSB              0
447 #define TEGRA_DC_ALIGN_LSB              1
448
449 #define TEGRA_DC_ORDER_RED_BLUE         0
450 #define TEGRA_DC_ORDER_BLUE_RED         1
451
452 #define V_BLANK_FLIP            0
453 #define V_BLANK_NVSD            1
454
455 struct tegra_dc;
456 struct nvmap_handle_ref;
457
458 struct tegra_dc_csc {
459         unsigned short yof;
460         unsigned short kyrgb;
461         unsigned short kur;
462         unsigned short kvr;
463         unsigned short kug;
464         unsigned short kvg;
465         unsigned short kub;
466         unsigned short kvb;
467 };
468
469 /* palette lookup table */
470 struct tegra_dc_lut {
471         u8 r[256];
472         u8 g[256];
473         u8 b[256];
474 };
475
476 struct tegra_dc_cmu_csc {
477         u16 krr;
478         u16 kgr;
479         u16 kbr;
480         u16 krg;
481         u16 kgg;
482         u16 kbg;
483         u16 krb;
484         u16 kgb;
485         u16 kbb;
486 };
487
488 struct tegra_dc_cmu {
489         u16 lut1[256];
490         struct tegra_dc_cmu_csc csc;
491         u8 lut2[960];
492 };
493
494 struct tegra_dc_win {
495         u8                      idx;
496         u8                      fmt;
497         u8                      ppflags; /* see TEGRA_WIN_PPFLAG* */
498         u32                     flags;
499
500         void                    *virt_addr;
501         dma_addr_t              phys_addr;
502         dma_addr_t              phys_addr_u;
503         dma_addr_t              phys_addr_v;
504         unsigned                stride;
505         unsigned                stride_uv;
506         fixed20_12              x;
507         fixed20_12              y;
508         fixed20_12              w;
509         fixed20_12              h;
510         unsigned                out_x;
511         unsigned                out_y;
512         unsigned                out_w;
513         unsigned                out_h;
514         unsigned                z;
515         u8                      global_alpha;
516
517         struct tegra_dc_csc     csc;
518
519         int                     dirty;
520         int                     underflows;
521         struct tegra_dc         *dc;
522
523         struct nvmap_handle_ref *cur_handle;
524         unsigned                bandwidth;
525         unsigned                new_bandwidth;
526         struct tegra_dc_lut     lut;
527 };
528
529 #define TEGRA_WIN_PPFLAG_CP_ENABLE      (1 << 0) /* enable RGB color lut */
530 #define TEGRA_WIN_PPFLAG_CP_FBOVERRIDE  (1 << 1) /* override fbdev color lut */
531
532 #define TEGRA_WIN_FLAG_ENABLED          (1 << 0)
533 #define TEGRA_WIN_FLAG_BLEND_PREMULT    (1 << 1)
534 #define TEGRA_WIN_FLAG_BLEND_COVERAGE   (1 << 2)
535 #define TEGRA_WIN_FLAG_INVERT_H         (1 << 3)
536 #define TEGRA_WIN_FLAG_INVERT_V         (1 << 4)
537 #define TEGRA_WIN_FLAG_TILED            (1 << 5)
538 #define TEGRA_WIN_FLAG_H_FILTER         (1 << 6)
539 #define TEGRA_WIN_FLAG_V_FILTER         (1 << 7)
540
541
542 #define TEGRA_WIN_BLEND_FLAGS_MASK \
543         (TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
544
545 /* Note: These are the actual values written to the DC_WIN_COLOR_DEPTH register
546  * and may change in new tegra architectures.
547  */
548 #define TEGRA_WIN_FMT_P1                0
549 #define TEGRA_WIN_FMT_P2                1
550 #define TEGRA_WIN_FMT_P4                2
551 #define TEGRA_WIN_FMT_P8                3
552 #define TEGRA_WIN_FMT_B4G4R4A4          4
553 #define TEGRA_WIN_FMT_B5G5R5A           5
554 #define TEGRA_WIN_FMT_B5G6R5            6
555 #define TEGRA_WIN_FMT_AB5G5R5           7
556 #define TEGRA_WIN_FMT_B8G8R8A8          12
557 #define TEGRA_WIN_FMT_R8G8B8A8          13
558 #define TEGRA_WIN_FMT_B6x2G6x2R6x2A8    14
559 #define TEGRA_WIN_FMT_R6x2G6x2B6x2A8    15
560 #define TEGRA_WIN_FMT_YCbCr422          16
561 #define TEGRA_WIN_FMT_YUV422            17
562 #define TEGRA_WIN_FMT_YCbCr420P         18
563 #define TEGRA_WIN_FMT_YUV420P           19
564 #define TEGRA_WIN_FMT_YCbCr422P         20
565 #define TEGRA_WIN_FMT_YUV422P           21
566 #define TEGRA_WIN_FMT_YCbCr422R         22
567 #define TEGRA_WIN_FMT_YUV422R           23
568 #define TEGRA_WIN_FMT_YCbCr422RA        24
569 #define TEGRA_WIN_FMT_YUV422RA          25
570
571 struct tegra_fb_data {
572         int             win;
573
574         int             xres;
575         int             yres;
576         int             bits_per_pixel; /* -1 means autodetect */
577
578         unsigned long   flags;
579 };
580
581 #define TEGRA_FB_FLIP_ON_PROBE          (1 << 0)
582
583 struct tegra_dc_platform_data {
584         unsigned long           flags;
585         unsigned long           emc_clk_rate;
586         struct tegra_dc_out     *default_out;
587         struct tegra_fb_data    *fb;
588 };
589
590 #define TEGRA_DC_FLAG_ENABLED           (1 << 0)
591
592 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win);
593 struct tegra_dc *tegra_dc_get_dc(unsigned idx);
594 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
595 bool tegra_dc_get_connected(struct tegra_dc *);
596 bool tegra_dc_hpd(struct tegra_dc *dc);
597
598
599 void tegra_dc_blank(struct tegra_dc *dc);
600
601 void tegra_dc_enable(struct tegra_dc *dc);
602 void tegra_dc_disable(struct tegra_dc *dc);
603
604 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i);
605 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i);
606 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val);
607
608 /* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
609  * with differenct dcs in one call
610  */
611 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n);
612 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
613 int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable);
614 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts);
615 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts);
616
617 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
618 struct fb_videomode;
619 int tegra_dc_set_fb_mode(struct tegra_dc *dc, const struct fb_videomode *fbmode,
620         bool stereo_mode);
621
622 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc);
623 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc);
624 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc);
625
626 /* PM0 and PM1 signal control */
627 #define TEGRA_PWM_PM0 0
628 #define TEGRA_PWM_PM1 1
629
630 struct tegra_dc_pwm_params {
631         int which_pwm;
632         int gpio_conf_to_sfio;
633         unsigned int period;
634         unsigned int clk_div;
635         unsigned int clk_select;
636         unsigned int duty_cycle;
637 };
638
639 void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg);
640
641 int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len);
642
643 int tegra_dc_update_csc(struct tegra_dc *dc, int win_index);
644
645 int tegra_dc_update_lut(struct tegra_dc *dc, int win_index, int fboveride);
646
647 /*
648  * In order to get a dc's current EDID, first call tegra_dc_get_edid() from an
649  * interruptible context.  The returned value (if non-NULL) points to a
650  * snapshot of the current state; after copying data from it, call
651  * tegra_dc_put_edid() on that pointer.  Do not dereference anything through
652  * that pointer after calling tegra_dc_put_edid().
653  */
654 struct tegra_dc_edid {
655         size_t          len;
656         u8              buf[0];
657 };
658 struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc);
659 void tegra_dc_put_edid(struct tegra_dc_edid *edid);
660
661 int tegra_dc_set_flip_callback(void (*callback)(void));
662 int tegra_dc_unset_flip_callback(void);
663 int tegra_dc_get_panel_sync_rate(void);
664
665 #endif