video: tegra: host: Fix NULL instead of integer
[linux-3.10.git] / arch / arm / mach-tegra / flowctrl.c
1 /*
2  * arch/arm/mach-tegra/flowctrl.c
3  *
4  * functions and macros to control the flowcontroller
5  *
6  * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24
25 #include <asm/barrier.h>
26
27 #include "flowctrl.h"
28 #include "iomap.h"
29
30 u8 flowctrl_offset_halt_cpu[] = {
31         FLOW_CTRL_HALT_CPU0_EVENTS,
32         FLOW_CTRL_HALT_CPU1_EVENTS,
33         FLOW_CTRL_HALT_CPU1_EVENTS + 8,
34         FLOW_CTRL_HALT_CPU1_EVENTS + 16,
35 };
36
37 u8 flowctrl_offset_cpu_csr[] = {
38         FLOW_CTRL_CPU0_CSR,
39         FLOW_CTRL_CPU1_CSR,
40         FLOW_CTRL_CPU1_CSR + 8,
41         FLOW_CTRL_CPU1_CSR + 16,
42 };
43
44 u8 flowctrl_offset_cc4_ctrl[] = {
45         FLOW_CTRL_CC4_CORE0_CTRL,
46         FLOW_CTRL_CC4_CORE0_CTRL + 4,
47         FLOW_CTRL_CC4_CORE0_CTRL + 8,
48         FLOW_CTRL_CC4_CORE0_CTRL + 12,
49 };
50
51 void flowctrl_update(u8 offset, u32 value)
52 {
53         void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
54
55         writel_relaxed(value, addr);
56
57         /* ensure the update has reached the flow controller */
58         wmb();
59         readl_relaxed(addr);
60 }
61
62 u32 flowctrl_readl(u8 offset)
63 {
64         void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
65         return readl_relaxed(addr);
66 }
67
68 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
69 {
70         return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
71 }
72
73 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
74 {
75         return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
76 }
77
78 void flowctrl_write_cc4_ctrl(unsigned int cpuid, u32 value)
79 {
80         return flowctrl_update(flowctrl_offset_cc4_ctrl[cpuid], value);
81 }