ARM: tegra: power: Fix EDP calculator
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/regulator/consumer.h>
29
30 #include <mach/edp.h>
31
32 #include "fuse.h"
33 #include "dvfs.h"
34 #include "clock.h"
35 #include "cpu-tegra.h"
36
37 #define FREQ_STEP 12750000
38 #define OVERRIDE_DEFAULT 6000
39
40 static struct tegra_edp_limits *edp_limits;
41 static int edp_limits_size;
42 static unsigned int regulator_cur;
43 /* Value to subtract from regulator current limit */
44 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
45
46 static struct tegra_edp_limits *reg_idle_edp_limits;
47 static int reg_idle_cur;
48
49 static const unsigned int *system_edp_limits;
50
51 static struct tegra_system_edp_entry *power_edp_limits;
52 static int power_edp_limits_size;
53
54 /*
55  * "Safe entry" to be used when no match for speedo_id /
56  * regulator_cur is found; must be the last one
57  */
58 static struct tegra_edp_limits edp_default_limits[] = {
59         {85, {1000000, 1000000, 1000000, 1000000} },
60 };
61
62 static struct tegra_system_edp_entry power_edp_default_limits[] = {
63         {0, 20, {1000000, 1000000, 1000000, 1000000} },
64 };
65
66 /* Constants for EDP calculations */
67 static const int temperatures[] = { /* degree celcius (C) */
68         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
69 };
70
71 static const int power_cap_levels[] = { /* milliwatts (mW) */
72           500,  1000,  1500,  2000,  2500,  3000,  3500,
73          4000,  4500,  5000,  5500,  6000,  6500,  7000,
74          7500,  8000,  8500,  9000,  9500, 10000, 10500,
75         11000, 11500, 12000, 12500, 13000, 13500, 14000,
76         14500, 15000, 15500, 16000, 16500, 17000
77 };
78
79 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
80 static unsigned int freq_voltage_lut_size_saved;
81 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
82 static unsigned int freq_voltage_lut_size;
83
84 static inline s64 edp_pow(s64 val, int pwr)
85 {
86         s64 retval = 1;
87
88         while (val && pwr) {
89                 if (pwr & 1)
90                         retval *= val;
91                 pwr >>= 1;
92                 if (pwr)
93                         val *= val;
94         }
95
96         return retval;
97 }
98
99
100 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
101 static inline unsigned int edp_apply_fixed_limits(
102                                 unsigned int in_freq_KHz,
103                                 struct tegra_edp_cpu_leakage_params *params,
104                                 unsigned int cur_effective,
105                                 int temp_C, int n_cores_idx)
106 {
107         unsigned int out_freq_KHz = in_freq_KHz;
108         unsigned int max_cur, max_temp, max_freq;
109         int i;
110
111         /* Apply any additional fixed limits */
112         for (i = 0; i < 8; i++) {
113                 max_cur = params->max_current_cap[i].max_cur;
114                 if (max_cur != 0 && cur_effective <= max_cur) {
115                         max_temp = params->max_current_cap[i].max_temp;
116                         if (max_temp != 0 && temp_C > max_temp) {
117                                 max_freq = params->max_current_cap[i].
118                                         max_freq[n_cores_idx];
119                                 if (max_freq && max_freq < out_freq_KHz)
120                                         out_freq_KHz = max_freq;
121                         }
122                 }
123         }
124
125         return out_freq_KHz;
126 }
127 #else
128 #define edp_apply_fixed_limits(freq, unused...) (freq)
129 #endif
130
131 /*
132  * Find the maximum frequency that results in dynamic and leakage current that
133  * is less than the regulator current limit.
134  * temp_C - valid or -EINVAL
135  * power_mW - valid or -1 (infinite) or -EINVAL
136  */
137 static unsigned int edp_calculate_maxf(
138                                 struct tegra_edp_cpu_leakage_params *params,
139                                 int temp_C, int power_mW, unsigned int cur_mA,
140                                 int iddq_mA,
141                                 int n_cores_idx)
142 {
143         unsigned int voltage_mV, freq_KHz = 0;
144         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
145         int f, i, j, k;
146         s64 leakage_mA, dyn_mA, leakage_calc_step;
147         s64 leakage_mW, dyn_mW;
148
149         /* If current limit is not specified, use max by default */
150         cur_mA = cur_mA ? : cur_effective;
151
152         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
153                 freq_KHz = freq_voltage_lut[f].freq / 1000;
154                 voltage_mV = freq_voltage_lut[f].voltage_mV;
155
156                 /* Constrain Volt-Temp */
157                 if (params->volt_temp_cap.temperature &&
158                     temp_C > params->volt_temp_cap.temperature &&
159                     params->volt_temp_cap.voltage_limit_mV &&
160                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
161                         continue;
162
163                 /* Calculate leakage current */
164                 leakage_mA = 0;
165                 for (i = 0; i <= 3; i++) {
166                         for (j = 0; j <= 3; j++) {
167                                 for (k = 0; k <= 3; k++) {
168                                         leakage_calc_step =
169                                                 params->leakage_consts_ijk
170                                                 [i][j][k] * edp_pow(iddq_mA, i);
171                                         /* Convert (mA)^i to (A)^i */
172                                         leakage_calc_step =
173                                                 div64_s64(leakage_calc_step,
174                                                           edp_pow(1000, i));
175                                         leakage_calc_step *=
176                                                 edp_pow(voltage_mV, j);
177                                         /* Convert (mV)^j to (V)^j */
178                                         leakage_calc_step =
179                                                 div64_s64(leakage_calc_step,
180                                                           edp_pow(1000, j));
181                                         leakage_calc_step *=
182                                                 edp_pow(temp_C, k);
183                                         /* Convert (C)^k to (scaled_C)^k */
184                                         leakage_calc_step =
185                                                 div64_s64(leakage_calc_step,
186                                                 edp_pow(params->temp_scaled,
187                                                         k));
188                                         /* leakage_consts_ijk was scaled */
189                                         leakage_calc_step =
190                                                 div64_s64(leakage_calc_step,
191                                                           params->ijk_scaled);
192                                         leakage_mA += leakage_calc_step;
193                                 }
194                         }
195                 }
196
197                 /* set floor for leakage current */
198                 if (leakage_mA <= params->leakage_min)
199                         leakage_mA = params->leakage_min;
200
201                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
202
203                 /* leakage_const_n was scaled */
204                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
205
206                 /* Calculate dynamic current */
207                 dyn_mA = voltage_mV * freq_KHz / 1000;
208                 /* Convert mV to V */
209                 dyn_mA = div64_s64(dyn_mA, 1000);
210                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
211                 /* dyn_const_n was scaled */
212                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
213
214                 if (power_mW != -1) {
215                         leakage_mW = leakage_mA * voltage_mV;
216                         dyn_mW = dyn_mA * voltage_mV;
217                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
218                                 goto end;
219                 } else if ((leakage_mA + dyn_mA) <= cur_mA) {
220                         goto end;
221                 }
222                 freq_KHz = 0;
223         }
224
225  end:
226         return edp_apply_fixed_limits(freq_KHz, params,
227                                         cur_effective, temp_C, n_cores_idx);
228 }
229
230 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
231                         unsigned int cpu_speedo_idx,
232                         unsigned int freq_volt_lut_size,
233                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
234 {
235         unsigned int i, j, freq;
236         int voltage_mV;
237
238         for (i = 0, j = 0, freq = 0;
239                  i < freq_volt_lut_size;
240                  i++, freq += FREQ_STEP) {
241
242                 /* Predict voltages */
243                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
244                         clk_cpu_g, freq);
245                 if (voltage_mV < 0) {
246                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
247                                __func__, freq, voltage_mV);
248                         return -EINVAL;
249                 }
250
251                 /* Cache frequency / voltage / voltage constant relationship */
252                 freq_volt_lut[i].freq = freq;
253                 freq_volt_lut[i].voltage_mV = voltage_mV;
254         }
255         return 0;
256 }
257
258 unsigned int tegra_edp_find_maxf(int volt)
259 {
260         unsigned int i;
261
262         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
263                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
264                         break;
265         }
266         return freq_voltage_lut[i - 1].freq;
267 }
268
269
270 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
271 {
272         int i, array_size;
273         struct tegra_edp_cpu_leakage_params *params;
274
275         switch (tegra_get_chip_id()) {
276         case TEGRA_CHIPID_TEGRA11:
277                 params = tegra11x_get_leakage_params(0, &array_size);
278                 break;
279         case TEGRA_CHIPID_TEGRA14:
280                 params = tegra14x_get_leakage_params(0, &array_size);
281                 break;
282         case TEGRA_CHIPID_TEGRA12:
283                 params = tegra12x_get_leakage_params(0, &array_size);
284                 break;
285         case TEGRA_CHIPID_TEGRA3:
286         case TEGRA_CHIPID_TEGRA2:
287         default:
288                 array_size = 0;
289                 break;
290         }
291
292         for (i = 0; i < array_size; i++)
293                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
294                         *cpu_speedo_idx = i;
295                         return 0;
296                 }
297
298         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
299                __func__, cpu_speedo_id);
300         return -EINVAL;
301 }
302
303 static int init_cpu_edp_limits_calculated(void)
304 {
305         unsigned int max_nr_cpus = num_possible_cpus();
306         unsigned int temp_idx, n_cores_idx, pwr_idx;
307         unsigned int cpu_g_minf, cpu_g_maxf;
308         unsigned int iddq_mA;
309         unsigned int cpu_speedo_idx;
310         unsigned int cap, limit;
311         struct tegra_edp_limits *edp_calculated_limits;
312         struct tegra_edp_limits *reg_idle_calc_limits;
313         struct tegra_system_edp_entry *power_edp_calc_limits;
314         struct tegra_edp_cpu_leakage_params *params;
315         int ret;
316         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
317         int cpu_speedo_id = tegra_cpu_speedo_id();
318         int idle_cur = reg_idle_cur;
319
320         /* Determine all inputs to EDP formula */
321         iddq_mA = tegra_get_cpu_iddq_value();
322         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
323         if (ret)
324                 return ret;
325
326         switch (tegra_get_chip_id()) {
327         case TEGRA_CHIPID_TEGRA11:
328                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
329                 break;
330         case TEGRA_CHIPID_TEGRA14:
331                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
332                 break;
333         case TEGRA_CHIPID_TEGRA12:
334                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
335                 break;
336         case TEGRA_CHIPID_TEGRA3:
337         case TEGRA_CHIPID_TEGRA2:
338         default:
339                 return -EINVAL;
340         }
341
342         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
343                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
344         BUG_ON(!edp_calculated_limits);
345
346         reg_idle_calc_limits = kmalloc(sizeof(struct tegra_edp_limits)
347                                        * ARRAY_SIZE(temperatures), GFP_KERNEL);
348         BUG_ON(!reg_idle_calc_limits);
349
350         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
351                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
352         BUG_ON(!power_edp_calc_limits);
353
354         cpu_g_minf = 0;
355         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
356         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
357         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
358                                    * freq_voltage_lut_size, GFP_KERNEL);
359         if (!freq_voltage_lut) {
360                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
361                 kfree(power_edp_calc_limits);
362                 kfree(reg_idle_calc_limits);
363                 kfree(edp_calculated_limits);
364                 return -ENOMEM;
365         }
366
367         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
368                                 freq_voltage_lut_size, freq_voltage_lut);
369         if (ret) {
370                 kfree(power_edp_calc_limits);
371                 kfree(reg_idle_calc_limits);
372                 kfree(edp_calculated_limits);
373                 kfree(freq_voltage_lut);
374                 return ret;
375         }
376
377         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
378                 /* release previous table if present */
379                 kfree(freq_voltage_lut_saved);
380                 /* create table to save */
381                 freq_voltage_lut_saved =
382                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
383                         freq_voltage_lut_size, GFP_KERNEL);
384                 if (!freq_voltage_lut_saved) {
385                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
386                                 __func__);
387                         kfree(freq_voltage_lut);
388                         return -ENOMEM;
389                 }
390                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
391         }
392         memcpy(freq_voltage_lut_saved,
393                 freq_voltage_lut,
394                 sizeof(struct tegra_edp_freq_voltage_table) *
395                         freq_voltage_lut_size);
396
397         /* Calculate EDP table */
398         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
399                 for (temp_idx = 0;
400                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
401                         edp_calculated_limits[temp_idx].temperature =
402                                 temperatures[temp_idx];
403                         limit = edp_calculate_maxf(params,
404                                                    temperatures[temp_idx],
405                                                    -1,
406                                                    0,
407                                                    iddq_mA,
408                                                    n_cores_idx);
409                         if (limit == -EINVAL)
410                                 return -EINVAL;
411                         /* apply safety cap if it is specified */
412                         if (n_cores_idx < 4) {
413                                 cap = params->safety_cap[n_cores_idx];
414                                 if (cap && cap < limit)
415                                         limit = cap;
416                         }
417                         edp_calculated_limits[temp_idx].
418                                 freq_limits[n_cores_idx] = limit;
419
420                         /* regulator mode threshold */
421                         if (!idle_cur)
422                                 continue;
423                         reg_idle_calc_limits[temp_idx].temperature =
424                                 temperatures[temp_idx];
425                         limit = edp_calculate_maxf(params,
426                                                    temperatures[temp_idx],
427                                                    -1,
428                                                    idle_cur,
429                                                    iddq_mA,
430                                                    n_cores_idx);
431
432                         /* remove idle table if any threshold is invalid */
433                         if (limit == -EINVAL) {
434                                 pr_warn("%s: Invalid idle limit for %dmA\n",
435                                         __func__, idle_cur);
436                                 idle_cur = 0;
437                                 continue;
438                         }
439
440                         /* No mode change below G CPU minimum rate */
441                         if (limit < clk_get_min_rate(clk_cpu_g) / 1000)
442                                 limit = 0;
443                         reg_idle_calc_limits[temp_idx].
444                                 freq_limits[n_cores_idx] = limit;
445                 }
446
447                 for (pwr_idx = 0;
448                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
449                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
450                                 power_cap_levels[pwr_idx] / 100;
451                         limit = edp_calculate_maxf(params,
452                                                    90,
453                                                    power_cap_levels[pwr_idx],
454                                                    0,
455                                                    iddq_mA,
456                                                    n_cores_idx);
457                         if (limit == -EINVAL)
458                                 return -EINVAL;
459                         power_edp_calc_limits[pwr_idx].
460                                 freq_limits[n_cores_idx] = limit;
461                 }
462         }
463
464         /*
465          * If this is an EDP table update, need to overwrite old table.
466          * The old table's address must remain valid.
467          */
468         if (edp_limits != edp_default_limits) {
469                 memcpy(edp_limits, edp_calculated_limits,
470                        sizeof(struct tegra_edp_limits)
471                        * ARRAY_SIZE(temperatures));
472                 kfree(edp_calculated_limits);
473         }
474         else {
475                 edp_limits = edp_calculated_limits;
476                 edp_limits_size = ARRAY_SIZE(temperatures);
477         }
478
479         if (idle_cur && reg_idle_edp_limits) {
480                 memcpy(reg_idle_edp_limits, reg_idle_calc_limits,
481                        sizeof(struct tegra_edp_limits)
482                        * ARRAY_SIZE(temperatures));
483                 kfree(reg_idle_calc_limits);
484         } else if (idle_cur) {
485                 reg_idle_edp_limits = reg_idle_calc_limits;
486         } else {
487                 kfree(reg_idle_edp_limits);
488                 kfree(reg_idle_calc_limits);
489                 reg_idle_edp_limits = NULL;
490         }
491
492         if (power_edp_limits != power_edp_default_limits) {
493                 memcpy(power_edp_limits, power_edp_calc_limits,
494                        sizeof(struct tegra_system_edp_entry)
495                        * ARRAY_SIZE(power_cap_levels));
496                 kfree(power_edp_calc_limits);
497         } else {
498                 power_edp_limits = power_edp_calc_limits;
499                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
500         }
501
502         kfree(freq_voltage_lut);
503         return 0;
504 }
505
506 void tegra_recalculate_cpu_edp_limits(void)
507 {
508         u32 tegra_chip_id;
509
510         tegra_chip_id = tegra_get_chip_id();
511         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
512             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
513             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
514                 return;
515
516         if (init_cpu_edp_limits_calculated() == 0)
517                 return;
518
519         /* Revert to default EDP table on error */
520         edp_limits = edp_default_limits;
521         edp_limits_size = ARRAY_SIZE(edp_default_limits);
522
523         power_edp_limits = power_edp_default_limits;
524         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
525
526         kfree(reg_idle_edp_limits);
527         reg_idle_edp_limits = NULL;
528         pr_err("%s: Failed to recalculate EDP limits\n", __func__);
529 }
530
531 /*
532  * Specify regulator current in mA, e.g. 5000mA
533  * Use 0 for default
534  */
535 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
536 {
537         if (!regulator_mA)
538                 goto end;
539         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
540
541         switch (tegra_get_chip_id()) {
542         case TEGRA_CHIPID_TEGRA11:
543         case TEGRA_CHIPID_TEGRA14:
544         case TEGRA_CHIPID_TEGRA12:
545                 if (init_cpu_edp_limits_calculated() == 0)
546                         return;
547                 break;
548         case TEGRA_CHIPID_TEGRA2:
549         case TEGRA_CHIPID_TEGRA3:
550         default:
551                 BUG();
552                 break;
553         }
554
555  end:
556         edp_limits = edp_default_limits;
557         edp_limits_size = ARRAY_SIZE(edp_default_limits);
558
559         power_edp_limits = power_edp_default_limits;
560         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
561 }
562
563 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
564 {
565         *limits = edp_limits;
566         *size = edp_limits_size;
567 }
568
569 void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
570                                            unsigned int mode)
571 {
572         if (mode == REGULATOR_MODE_IDLE) {
573                 reg_idle_cur = regulator_mA;
574                 return;
575         }
576         pr_err("%s: Not supported regulator mode 0x%x\n", __func__, mode);
577 }
578
579 void tegra_get_cpu_reg_mode_limits(const struct tegra_edp_limits **limits,
580                                    int *size, unsigned int mode)
581 {
582         if (mode == REGULATOR_MODE_IDLE) {
583                 *limits = reg_idle_edp_limits;
584                 *size = edp_limits_size;
585         } else {
586                 *limits = NULL;
587                 *size = 0;
588         }
589 }
590
591 void tegra_get_system_edp_limits(const unsigned int **limits)
592 {
593         *limits = system_edp_limits;
594 }
595
596 void tegra_platform_edp_init(struct thermal_trip_info *trips,
597                                 int *num_trips, int margin)
598 {
599         const struct tegra_edp_limits *cpu_edp_limits;
600         struct thermal_trip_info *trip_state;
601         int i, cpu_edp_limits_size;
602
603         if (!trips || !num_trips)
604                 return;
605
606         /* edp capping */
607         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
608
609         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
610                 BUG();
611
612         for (i = 0; i < cpu_edp_limits_size-1; i++) {
613                 trip_state = &trips[*num_trips];
614
615                 trip_state->cdev_type = "cpu_edp";
616                 trip_state->trip_temp =
617                         (cpu_edp_limits[i].temperature * 1000) - margin;
618                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
619                 trip_state->upper = trip_state->lower = i + 1;
620
621                 (*num_trips)++;
622
623                 if (*num_trips >= THERMAL_MAX_TRIPS)
624                         BUG();
625         }
626 }
627
628 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
629 {
630         *size = power_edp_limits_size;
631         return power_edp_limits;
632 }
633
634 #ifdef CONFIG_DEBUG_FS
635
636 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
637 {
638 #ifdef CONFIG_CPU_FREQ
639         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
640 #endif
641         return 0;
642 }
643
644 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
645 {
646         int i;
647
648         seq_printf(s, "%6s %10s %10s %10s %10s\n",
649                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
650         for (i = 0; i < edp_limits_size; i++) {
651                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
652                            i == th_idx ? '>' : ' ',
653                            edp_limits[i].temperature,
654                            edp_limits[i].freq_limits[0],
655                            edp_limits[i].freq_limits[1],
656                            edp_limits[i].freq_limits[2],
657                            edp_limits[i].freq_limits[3]);
658         }
659 }
660
661 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
662 {
663         int i;
664
665         seq_printf(s, "%6s %10s %10s\n",
666                    " Temp.", "1-core", "2-cores");
667         for (i = 0; i < edp_limits_size; i++) {
668                 seq_printf(s, "%c%3dC: %10u %10u\n",
669                            i == th_idx ? '>' : ' ',
670                            edp_limits[i].temperature,
671                            edp_limits[i].freq_limits[0],
672                            edp_limits[i].freq_limits[1]);
673         }
674 }
675
676 static inline void edp_show_4core_reg_mode_table(struct seq_file *s, int th_idx)
677 {
678         int i;
679
680         seq_printf(s, "%6s %10s %10s %10s %10s\n",
681                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
682         for (i = 0; i < edp_limits_size; i++) {
683                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
684                            i == th_idx ? '>' : ' ',
685                            reg_idle_edp_limits[i].temperature,
686                            reg_idle_edp_limits[i].freq_limits[0],
687                            reg_idle_edp_limits[i].freq_limits[1],
688                            reg_idle_edp_limits[i].freq_limits[2],
689                            reg_idle_edp_limits[i].freq_limits[3]);
690         }
691 }
692
693 static inline void edp_show_2core_reg_mode_table(struct seq_file *s, int th_idx)
694 {
695         int i;
696
697         seq_printf(s, "%6s %10s %10s\n",
698                    " Temp.", "1-core", "2-cores");
699         for (i = 0; i < edp_limits_size; i++) {
700                 seq_printf(s, "%c%3dC: %10u %10u\n",
701                            i == th_idx ? '>' : ' ',
702                            reg_idle_edp_limits[i].temperature,
703                            reg_idle_edp_limits[i].freq_limits[0],
704                            reg_idle_edp_limits[i].freq_limits[1]);
705         }
706 }
707
708 static inline void edp_show_2core_system_table(struct seq_file *s)
709 {
710         seq_printf(s, "%10u %10u\n",
711                    system_edp_limits[0],
712                    system_edp_limits[1]);
713 }
714
715 static inline void edp_show_4core_system_table(struct seq_file *s)
716 {
717         seq_printf(s, "%10u %10u %10u %10u\n",
718                    system_edp_limits[0],
719                    system_edp_limits[1],
720                    system_edp_limits[2],
721                    system_edp_limits[3]);
722 }
723
724 static int edp_debugfs_show(struct seq_file *s, void *data)
725 {
726         unsigned int max_nr_cpus = num_possible_cpus();
727         int th_idx;
728
729         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
730                 seq_printf(s, "Unsupported number of CPUs\n");
731                 return 0;
732         }
733
734 #ifdef CONFIG_CPU_FREQ
735         tegra_get_edp_limit(&th_idx);
736 #else
737         th_idx = 0;
738 #endif
739
740         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
741                    edp_limits == edp_default_limits ? "**default** " : "",
742                    regulator_cur - edp_reg_override_mA,
743                    regulator_cur, edp_reg_override_mA);
744
745         if (max_nr_cpus == 2)
746                 edp_show_2core_edp_table(s, th_idx);
747         else if (max_nr_cpus == 4)
748                 edp_show_4core_edp_table(s, th_idx);
749
750         if (reg_idle_edp_limits) {
751                 seq_printf(s, "\n-- Regulator mode thresholds @ %dmA --\n",
752                            reg_idle_cur);
753                 if (max_nr_cpus == 2)
754                         edp_show_2core_reg_mode_table(s, th_idx);
755                 else if (max_nr_cpus == 4)
756                         edp_show_4core_reg_mode_table(s, th_idx);
757         }
758
759         if (system_edp_limits) {
760                 seq_printf(s, "\n-- System EDP table --\n");
761                 if (max_nr_cpus == 2)
762                         edp_show_2core_system_table(s);
763                 else if (max_nr_cpus == 4)
764                         edp_show_4core_system_table(s);
765         }
766
767         return 0;
768 }
769
770 static int edp_reg_override_show(struct seq_file *s, void *data)
771 {
772         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
773                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
774         return 0;
775 }
776
777 static int edp_reg_override_write(struct file *file,
778         const char __user *userbuf, size_t count, loff_t *ppos)
779 {
780         char buf[32], *end;
781         unsigned int edp_reg_override_mA_temp;
782         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
783         u32 tegra_chip_id;
784
785         tegra_chip_id = tegra_get_chip_id();
786         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
787                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
788                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
789                 goto override_err;
790
791         if (sizeof(buf) <= count)
792                 goto override_err;
793
794         if (copy_from_user(buf, userbuf, count))
795                 goto override_err;
796
797         /* terminate buffer and trim - white spaces may be appended
798          *  at the end when invoked from shell command line */
799         buf[count]='\0';
800         strim(buf);
801
802         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
803         if (*end != '\0')
804                 goto override_err;
805
806         if (edp_reg_override_mA_temp >= regulator_cur)
807                 goto override_err;
808
809         if (edp_reg_override_mA == edp_reg_override_mA_temp)
810                 return count;
811
812         edp_reg_override_mA = edp_reg_override_mA_temp;
813         if (init_cpu_edp_limits_calculated()) {
814                 /* Revert to previous override value if new value fails */
815                 edp_reg_override_mA = edp_reg_override_mA_prev;
816                 goto override_err;
817         }
818
819 #ifdef CONFIG_CPU_FREQ
820         if (tegra_cpu_set_speed_cap(NULL)) {
821                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
822                 goto override_out;
823         }
824
825         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
826                         " %u mA\n", regulator_cur - edp_reg_override_mA);
827 #else
828         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
829 #endif
830
831         return count;
832
833 override_err:
834         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
835                buf);
836 #ifdef CONFIG_CPU_FREQ
837 override_out:
838 #endif
839         return -EINVAL;
840 }
841
842 static int edp_debugfs_open(struct inode *inode, struct file *file)
843 {
844         return single_open(file, edp_debugfs_show, inode->i_private);
845 }
846
847 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
848 {
849         return single_open(file, edp_limit_debugfs_show, inode->i_private);
850 }
851
852 static int edp_reg_override_open(struct inode *inode, struct file *file)
853 {
854         return single_open(file, edp_reg_override_show, inode->i_private);
855 }
856
857 static const struct file_operations edp_debugfs_fops = {
858         .open           = edp_debugfs_open,
859         .read           = seq_read,
860         .llseek         = seq_lseek,
861         .release        = single_release,
862 };
863
864 static const struct file_operations edp_limit_debugfs_fops = {
865         .open           = edp_limit_debugfs_open,
866         .read           = seq_read,
867         .llseek         = seq_lseek,
868         .release        = single_release,
869 };
870
871 static const struct file_operations edp_reg_override_debugfs_fops = {
872         .open           = edp_reg_override_open,
873         .read           = seq_read,
874         .write          = edp_reg_override_write,
875         .llseek         = seq_lseek,
876         .release        = single_release,
877 };
878
879 static int reg_idle_cur_get(void *data, u64 *val)
880 {
881         *val = reg_idle_cur;
882         return 0;
883 }
884 static int reg_idle_cur_set(void *data, u64 val)
885 {
886         int ret;
887
888         ret = tegra_cpu_reg_mode_force_normal(true);
889         if (ret) {
890                 pr_err("%s: Failed to force regulator normal mode\n", __func__);
891                 return ret;
892         }
893
894         reg_idle_cur = (int)val;
895         tegra_update_cpu_edp_limits();
896         return 0;
897 }
898 DEFINE_SIMPLE_ATTRIBUTE(reg_idle_cur_debugfs_fops,
899                         reg_idle_cur_get, reg_idle_cur_set, "%llu\n");
900
901 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
902 static __init struct dentry *tegra_edp_debugfs_dir(void)
903 {
904         if (edp_debugfs_dir)
905                 return edp_debugfs_dir;
906         else
907                 return debugfs_create_dir("edp", NULL);
908 }
909 #else
910 static __init struct dentry *tegra_edp_debugfs_dir(void)
911 {
912         return debugfs_create_dir("edp", NULL);
913 }
914 #endif
915
916 static int __init tegra_edp_debugfs_init(void)
917 {
918         struct dentry *d_reg_idle_cur;
919         struct dentry *d_edp;
920         struct dentry *d_edp_limit;
921         struct dentry *d_edp_reg_override;
922         struct dentry *edp_dir;
923         struct dentry *vdd_cpu_dir;
924
925         if (!tegra_platform_is_silicon())
926                 return -ENOSYS;
927
928         edp_dir = tegra_edp_debugfs_dir();
929
930         if (!edp_dir)
931                 goto edp_dir_err;
932
933         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
934
935         if (!vdd_cpu_dir)
936                 goto vdd_cpu_dir_err;
937
938         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
939                                 &edp_debugfs_fops);
940
941         if (!d_edp)
942                 goto edp_err;
943
944         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
945                                 NULL, &edp_limit_debugfs_fops);
946
947         if (!d_edp_limit)
948                 goto edp_limit_err;
949
950         d_edp_reg_override = debugfs_create_file("edp_reg_override",
951                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
952                                 &edp_reg_override_debugfs_fops);
953
954         if (!d_edp_reg_override)
955                 goto edp_reg_override_err;
956
957         d_reg_idle_cur = debugfs_create_file("reg_idle_mA",
958                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
959                                 &reg_idle_cur_debugfs_fops);
960         if (!d_reg_idle_cur)
961                 goto reg_idle_cur_err;
962
963         if (tegra_core_edp_debugfs_init(edp_dir))
964                 return -ENOMEM;
965
966         return 0;
967
968 reg_idle_cur_err:
969         debugfs_remove(d_edp_reg_override);
970 edp_reg_override_err:
971         debugfs_remove(d_edp_limit);
972 edp_limit_err:
973         debugfs_remove(d_edp);
974 edp_err:
975         debugfs_remove(vdd_cpu_dir);
976 vdd_cpu_dir_err:
977         debugfs_remove(edp_dir);
978 edp_dir_err:
979         return -ENOMEM;
980 }
981
982 late_initcall(tegra_edp_debugfs_init);
983 #endif /* CONFIG_DEBUG_FS */