ARM: tegra: remove CPU power lim from EDP debugfs
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26
27 #include <mach/edp.h>
28 #include <mach/hardware.h>
29
30 #include "fuse.h"
31 #include "dvfs.h"
32 #include "clock.h"
33 #include "cpu-tegra.h"
34
35 #define FREQ_STEP 12750000
36 #define OVERRIDE_DEFAULT 6000
37
38 static struct tegra_edp_limits *edp_limits;
39 static int edp_limits_size;
40 static unsigned int regulator_cur;
41 /* Value to subtract from regulator current limit */
42 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
43
44 static const unsigned int *system_edp_limits;
45
46 static struct tegra_system_edp_entry *power_edp_limits;
47 static int power_edp_limits_size;
48
49 /*
50  * "Safe entry" to be used when no match for speedo_id /
51  * regulator_cur is found; must be the last one
52  */
53 static struct tegra_edp_limits edp_default_limits[] = {
54         {85, {1000000, 1000000, 1000000, 1000000} },
55 };
56
57 static struct tegra_system_edp_entry power_edp_default_limits[] = {
58         {0, 20, {1000000, 1000000, 1000000, 1000000} },
59 };
60
61 /* Constants for EDP calculations */
62 static const int temperatures[] = { /* degree celcius (C) */
63         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
64 };
65
66 static const int power_cap_levels[] = { /* milliwatts (mW) */
67           500,  1000,  1500,  2000,  2500,  3000,  3500,
68          4000,  4500,  5000,  5500,  6000,  6500,  7000,
69          7500,  8000,  8500,  9000,  9500, 10000, 10500,
70         11000, 11500, 12000, 12500, 13000, 13500, 14000,
71         14500, 15000, 15500, 16000, 16500, 17000
72 };
73
74 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
75 static unsigned int freq_voltage_lut_size_saved;
76 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
77 static unsigned int freq_voltage_lut_size;
78
79 static inline s64 edp_pow(s64 val, int pwr)
80 {
81         s64 retval = 1;
82
83         while (val && pwr) {
84                 if (pwr & 1)
85                         retval *= val;
86                 pwr >>= 1;
87                 if (pwr)
88                         val *= val;
89         }
90
91         return retval;
92 }
93
94 /*
95  * Find the maximum frequency that results in dynamic and leakage current that
96  * is less than the regulator current limit.
97  * temp_C - always valid
98  * power_mW - valid or -1 (infinite)
99  */
100 static unsigned int edp_calculate_maxf(
101                                 struct tegra_edp_cpu_leakage_params *params,
102                                 int temp_C, int power_mW,
103                                 int iddq_mA,
104                                 int n_cores_idx)
105 {
106         unsigned int voltage_mV, freq_KHz;
107         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
108         int f, i, j, k;
109         s64 leakage_mA, dyn_mA, leakage_calc_step;
110         s64 leakage_mW, dyn_mW;
111
112         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
113                 freq_KHz = freq_voltage_lut[f].freq / 1000;
114                 voltage_mV = freq_voltage_lut[f].voltage_mV;
115
116                 /* Constrain Volt-Temp */
117                 if (params->volt_temp_cap.temperature &&
118                     temp_C > params->volt_temp_cap.temperature &&
119                     params->volt_temp_cap.voltage_limit_mV &&
120                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
121                         continue;
122
123                 /* Calculate leakage current */
124                 leakage_mA = 0;
125                 for (i = 0; i <= 3; i++) {
126                         for (j = 0; j <= 3; j++) {
127                                 for (k = 0; k <= 3; k++) {
128                                         leakage_calc_step =
129                                                 params->leakage_consts_ijk
130                                                 [i][j][k] * edp_pow(iddq_mA, i);
131                                         /* Convert (mA)^i to (A)^i */
132                                         leakage_calc_step =
133                                                 div64_s64(leakage_calc_step,
134                                                           edp_pow(1000, i));
135                                         leakage_calc_step *=
136                                                 edp_pow(voltage_mV, j);
137                                         /* Convert (mV)^j to (V)^j */
138                                         leakage_calc_step =
139                                                 div64_s64(leakage_calc_step,
140                                                           edp_pow(1000, j));
141                                         leakage_calc_step *=
142                                                 edp_pow(temp_C, k);
143                                         /* Convert (C)^k to (scaled_C)^k */
144                                         leakage_calc_step =
145                                                 div64_s64(leakage_calc_step,
146                                                 edp_pow(params->temp_scaled,
147                                                         k));
148                                         /* leakage_consts_ijk was scaled */
149                                         leakage_calc_step =
150                                                 div64_s64(leakage_calc_step,
151                                                           params->ijk_scaled);
152                                         leakage_mA += leakage_calc_step;
153                                 }
154                         }
155                 }
156
157                 /* if specified, set floor for leakage current */
158                 if (params->leakage_min && leakage_mA <= params->leakage_min)
159                         leakage_mA = params->leakage_min;
160
161                 /* leakage cannot be negative => leakage model has error */
162                 if (leakage_mA <= 0) {
163                         pr_err("VDD_CPU EDP failed: IDDQ too high (%d mA)\n",
164                                iddq_mA);
165                         return -EINVAL;
166                 }
167
168                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
169
170                 /* leakage_const_n was scaled */
171                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
172
173                 /* Calculate dynamic current */
174                 dyn_mA = voltage_mV * freq_KHz / 1000;
175                 /* Convert mV to V */
176                 dyn_mA = div64_s64(dyn_mA, 1000);
177                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
178                 /* dyn_const_n was scaled */
179                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
180
181                 if (power_mW != -1) {
182                         leakage_mW = leakage_mA * voltage_mV;
183                         dyn_mW = dyn_mA * voltage_mV;
184                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
185                                 return freq_KHz;
186                 } else if ((leakage_mA + dyn_mA) <= cur_effective) {
187                         return freq_KHz;
188                 }
189         }
190         return 0;
191 }
192
193 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
194                         unsigned int cpu_speedo_idx,
195                         unsigned int freq_volt_lut_size,
196                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
197 {
198         unsigned int i, j, freq;
199         int voltage_mV;
200
201         for (i = 0, j = 0, freq = 0;
202                  i < freq_volt_lut_size;
203                  i++, freq += FREQ_STEP) {
204
205                 /* Predict voltages */
206                 voltage_mV = tegra_dvfs_predict_millivolts(clk_cpu_g, freq);
207                 if (voltage_mV < 0) {
208                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
209                                __func__, freq, voltage_mV);
210                         return -EINVAL;
211                 }
212
213                 /* Cache frequency / voltage / voltage constant relationship */
214                 freq_volt_lut[i].freq = freq;
215                 freq_volt_lut[i].voltage_mV = voltage_mV;
216         }
217         return 0;
218 }
219
220 unsigned int tegra_edp_find_maxf(int volt)
221 {
222         unsigned int i;
223
224         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
225                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
226                         break;
227         }
228         return freq_voltage_lut[i - 1].freq;
229 }
230
231
232 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
233 {
234         int i, array_size;
235         struct tegra_edp_cpu_leakage_params *params;
236
237         switch (tegra_chip_id) {
238         case TEGRA_CHIPID_TEGRA11:
239                 params = tegra11x_get_leakage_params(0, &array_size);
240                 break;
241         case TEGRA_CHIPID_TEGRA14:
242                 params = tegra14x_get_leakage_params(0, &array_size);
243                 break;
244         case TEGRA_CHIPID_TEGRA3:
245         case TEGRA_CHIPID_TEGRA2:
246         default:
247                 array_size = 0;
248                 break;
249         }
250
251         for (i = 0; i < array_size; i++)
252                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
253                         *cpu_speedo_idx = i;
254                         return 0;
255                 }
256
257         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
258                __func__, cpu_speedo_id);
259         return -EINVAL;
260 }
261
262 static int init_cpu_edp_limits_calculated(void)
263 {
264         unsigned int temp_idx, n_cores_idx, pwr_idx;
265         unsigned int cpu_g_minf, cpu_g_maxf;
266         unsigned int iddq_mA;
267         unsigned int cpu_speedo_idx;
268         unsigned int cap, limit;
269         struct tegra_edp_limits *edp_calculated_limits;
270         struct tegra_system_edp_entry *power_edp_calc_limits;
271         struct tegra_edp_cpu_leakage_params *params;
272         int ret;
273         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
274         int cpu_speedo_id = tegra_cpu_speedo_id();
275
276         /* Determine all inputs to EDP formula */
277         iddq_mA = tegra_get_cpu_iddq_value();
278         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
279         if (ret)
280                 return ret;
281
282         switch (tegra_chip_id) {
283         case TEGRA_CHIPID_TEGRA11:
284                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
285                 break;
286         case TEGRA_CHIPID_TEGRA14:
287                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
288                 break;
289         case TEGRA_CHIPID_TEGRA3:
290         case TEGRA_CHIPID_TEGRA2:
291         default:
292                 return -EINVAL;
293         }
294
295         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
296                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
297         BUG_ON(!edp_calculated_limits);
298
299         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
300                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
301         BUG_ON(!power_edp_calc_limits);
302
303         cpu_g_minf = 0;
304         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
305         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
306         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
307                                    * freq_voltage_lut_size, GFP_KERNEL);
308         if (!freq_voltage_lut) {
309                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
310                 kfree(power_edp_calc_limits);
311                 kfree(edp_calculated_limits);
312                 return -ENOMEM;
313         }
314
315         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
316                                 freq_voltage_lut_size, freq_voltage_lut);
317         if (ret) {
318                 kfree(power_edp_calc_limits);
319                 kfree(edp_calculated_limits);
320                 kfree(freq_voltage_lut);
321                 return ret;
322         }
323
324         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
325                 /* release previous table if present */
326                 kfree(freq_voltage_lut_saved);
327                 /* create table to save */
328                 freq_voltage_lut_saved =
329                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
330                         freq_voltage_lut_size, GFP_KERNEL);
331                 if (!freq_voltage_lut_saved) {
332                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
333                                 __func__);
334                         kfree(freq_voltage_lut);
335                         return -ENOMEM;
336                 }
337                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
338         }
339         memcpy(freq_voltage_lut_saved,
340                 freq_voltage_lut,
341                 sizeof(struct tegra_edp_freq_voltage_table) *
342                         freq_voltage_lut_size);
343
344         /* Calculate EDP table */
345         for (n_cores_idx = 0; n_cores_idx < NR_CPUS; n_cores_idx++) {
346                 for (temp_idx = 0;
347                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
348                         edp_calculated_limits[temp_idx].temperature =
349                                 temperatures[temp_idx];
350                         limit = edp_calculate_maxf(params,
351                                                    temperatures[temp_idx],
352                                                    -1,
353                                                    iddq_mA,
354                                                    n_cores_idx);
355                         /* apply safety cap if it is specified */
356                         if (n_cores_idx < 4) {
357                                 cap = params->safety_cap[n_cores_idx];
358                                 if (cap && cap < limit)
359                                         limit = cap;
360                         }
361                         edp_calculated_limits[temp_idx].
362                                 freq_limits[n_cores_idx] = limit;
363                 }
364
365                 for (pwr_idx = 0;
366                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
367                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
368                                 power_cap_levels[pwr_idx] / 100;
369                         limit = edp_calculate_maxf(params,
370                                                    90,
371                                                    power_cap_levels[pwr_idx],
372                                                    iddq_mA,
373                                                    n_cores_idx);
374                         power_edp_calc_limits[pwr_idx].
375                                 freq_limits[n_cores_idx] = limit;
376                 }
377         }
378
379         /*
380          * If this is an EDP table update, need to overwrite old table.
381          * The old table's address must remain valid.
382          */
383         if (edp_limits != edp_default_limits) {
384                 memcpy(edp_limits, edp_calculated_limits,
385                        sizeof(struct tegra_edp_limits)
386                        * ARRAY_SIZE(temperatures));
387                 kfree(edp_calculated_limits);
388         }
389         else {
390                 edp_limits = edp_calculated_limits;
391                 edp_limits_size = ARRAY_SIZE(temperatures);
392         }
393
394         if (power_edp_limits != power_edp_default_limits) {
395                 memcpy(power_edp_limits, power_edp_calc_limits,
396                        sizeof(struct tegra_system_edp_entry)
397                        * ARRAY_SIZE(power_cap_levels));
398                 kfree(power_edp_calc_limits);
399         } else {
400                 power_edp_limits = power_edp_calc_limits;
401                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
402         }
403
404         kfree(freq_voltage_lut);
405         return 0;
406 }
407
408 static int __init init_cpu_edp_limits_lookup(void)
409 {
410         int i, j;
411         struct tegra_edp_limits *e;
412         struct tegra_edp_vdd_cpu_entry *t;
413         int tsize = 0;
414         int cpu_speedo_id = tegra_cpu_speedo_id();
415
416         if (tegra_chip_id != TEGRA_CHIPID_TEGRA3)
417                 return -EINVAL;
418
419         t = tegra3x_get_vdd_cpu_map(&tsize);
420
421         for (i = 0; i < tsize; i++) {
422                 if (t[i].speedo_id == cpu_speedo_id &&
423                     t[i].regulator_100mA <= regulator_cur / 100)
424                         break;
425         }
426
427         /* No entry found in tegra_edp_vdd_cpu_map */
428         if (i >= tsize)
429                 return -EINVAL;
430
431         /* Find all rows for this entry */
432         for (j = i + 1; j < tsize; j++) {
433                 if (t[i].speedo_id != t[j].speedo_id ||
434                     t[i].regulator_100mA != t[j].regulator_100mA)
435                         break;
436         }
437
438         edp_limits_size = j - i;
439         e = kmalloc(sizeof(struct tegra_edp_limits) * edp_limits_size,
440                     GFP_KERNEL);
441         BUG_ON(!e);
442
443         for (j = 0; j < edp_limits_size; j++) {
444                 e[j].temperature = (int)t[i+j].temperature;
445                 e[j].freq_limits[0] = (unsigned int)t[i+j].freq_limits[0]*10000;
446                 e[j].freq_limits[1] = (unsigned int)t[i+j].freq_limits[1]*10000;
447                 e[j].freq_limits[2] = (unsigned int)t[i+j].freq_limits[2]*10000;
448                 e[j].freq_limits[3] = (unsigned int)t[i+j].freq_limits[3]*10000;
449         }
450
451         if (edp_limits != edp_default_limits)
452                 kfree(edp_limits);
453
454         edp_limits = e;
455         return 0;
456 }
457
458 void tegra_recalculate_cpu_edp_limits(void)
459 {
460         if (tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
461             tegra_chip_id == TEGRA_CHIPID_TEGRA14)
462                 init_cpu_edp_limits_calculated();
463 }
464
465 /*
466  * Specify regulator current in mA, e.g. 5000mA
467  * Use 0 for default
468  */
469 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
470 {
471         if (!regulator_mA)
472                 goto end;
473         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
474
475         switch (tegra_chip_id) {
476         case TEGRA_CHIPID_TEGRA3:
477                 if (init_cpu_edp_limits_lookup() == 0)
478                         return;
479                 break;
480         case TEGRA_CHIPID_TEGRA11:
481         case TEGRA_CHIPID_TEGRA14:
482                 if (init_cpu_edp_limits_calculated() == 0)
483                         return;
484                 break;
485         case TEGRA_CHIPID_TEGRA2:
486         default:
487                 BUG();
488                 break;
489         }
490
491  end:
492         edp_limits = edp_default_limits;
493         edp_limits_size = ARRAY_SIZE(edp_default_limits);
494
495         power_edp_limits = power_edp_default_limits;
496         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
497 }
498
499 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
500 {
501         *limits = edp_limits;
502         *size = edp_limits_size;
503 }
504
505 void __init tegra_init_system_edp_limits(unsigned int power_limit_mW)
506 {
507         int cpu_speedo_id = tegra_cpu_speedo_id();
508         int i;
509         unsigned int *e;
510         struct tegra_system_edp_entry *t;
511         int tsize = 0;
512
513         if (tegra_chip_id != TEGRA_CHIPID_TEGRA3) {
514                 e = NULL;
515                 goto out;
516         }
517
518         t = tegra3x_get_system_edp_map(&tsize);
519
520         if (!power_limit_mW) {
521                 e = NULL;
522                 goto out;
523         }
524
525         for (i = 0; i < tsize; i++)
526                 if (t[i].speedo_id == cpu_speedo_id)
527                         break;
528
529         if (i >= tsize) {
530                 e = NULL;
531                 goto out;
532         }
533
534         do {
535                 if (t[i].power_limit_100mW <= power_limit_mW / 100)
536                         break;
537                 i++;
538         } while (i < tsize && t[i].speedo_id == cpu_speedo_id);
539
540         if (i >= tsize || t[i].speedo_id != cpu_speedo_id)
541                 i--; /* No low enough entry in the table, use best possible */
542
543         e = kmalloc(sizeof(unsigned int) * 4, GFP_KERNEL);
544         BUG_ON(!e);
545
546         e[0] = (unsigned int)t[i].freq_limits[0] * 10000;
547         e[1] = (unsigned int)t[i].freq_limits[1] * 10000;
548         e[2] = (unsigned int)t[i].freq_limits[2] * 10000;
549         e[3] = (unsigned int)t[i].freq_limits[3] * 10000;
550
551 out:
552         kfree(system_edp_limits);
553
554         system_edp_limits = e;
555 }
556
557 void tegra_get_system_edp_limits(const unsigned int **limits)
558 {
559         *limits = system_edp_limits;
560 }
561
562 void tegra_platform_edp_init(struct thermal_trip_info *trips,
563                                 int *num_trips, int margin)
564 {
565         const struct tegra_edp_limits *cpu_edp_limits;
566         struct thermal_trip_info *trip_state;
567         int i, cpu_edp_limits_size;
568
569         if (!trips || !num_trips)
570                 return;
571
572         /* edp capping */
573         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
574
575         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
576                 BUG();
577
578         for (i = 0; i < cpu_edp_limits_size-1; i++) {
579                 trip_state = &trips[*num_trips];
580
581                 trip_state->cdev_type = "cpu_edp";
582                 trip_state->trip_temp =
583                         (cpu_edp_limits[i].temperature * 1000) - margin;
584                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
585                 trip_state->upper = trip_state->lower = i + 1;
586
587                 (*num_trips)++;
588
589                 if (*num_trips >= THERMAL_MAX_TRIPS)
590                         BUG();
591         }
592 }
593
594 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
595 {
596         *size = power_edp_limits_size;
597         return power_edp_limits;
598 }
599
600 #ifdef CONFIG_DEBUG_FS
601
602 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
603 {
604 #ifdef CONFIG_CPU_FREQ
605         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
606 #endif
607         return 0;
608 }
609
610 static int edp_debugfs_show(struct seq_file *s, void *data)
611 {
612         int i, th_idx;
613
614 #ifdef CONFIG_CPU_FREQ
615         tegra_get_edp_limit(&th_idx);
616 #else
617         th_idx = 0;
618 #endif
619         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
620                    edp_limits == edp_default_limits ? "default " : "",
621                    regulator_cur - edp_reg_override_mA,
622                    regulator_cur, edp_reg_override_mA);
623         seq_printf(s, "%6s %10s %10s %10s %10s\n",
624                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
625         for (i = 0; i < edp_limits_size; i++) {
626                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
627                            i == th_idx ? '>' : ' ',
628                            edp_limits[i].temperature,
629                            edp_limits[i].freq_limits[0],
630                            edp_limits[i].freq_limits[1],
631                            edp_limits[i].freq_limits[2],
632                            edp_limits[i].freq_limits[3]);
633         }
634
635         if (system_edp_limits) {
636                 seq_printf(s, "\n-- System EDP table --\n");
637                 seq_printf(s, "%10u %10u %10u %10u\n",
638                            system_edp_limits[0],
639                            system_edp_limits[1],
640                            system_edp_limits[2],
641                            system_edp_limits[3]);
642         }
643
644         return 0;
645 }
646
647 static int edp_reg_override_show(struct seq_file *s, void *data)
648 {
649         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
650                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
651         return 0;
652 }
653
654 static int edp_reg_override_write(struct file *file,
655         const char __user *userbuf, size_t count, loff_t *ppos)
656 {
657         char buf[32], *end;
658         unsigned int edp_reg_override_mA_temp;
659         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
660
661         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
662                 tegra_chip_id == TEGRA_CHIPID_TEGRA14))
663                 goto override_err;
664
665         if (sizeof(buf) <= count)
666                 goto override_err;
667
668         if (copy_from_user(buf, userbuf, count))
669                 goto override_err;
670
671         /* terminate buffer and trim - white spaces may be appended
672          *  at the end when invoked from shell command line */
673         buf[count]='\0';
674         strim(buf);
675
676         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
677         if (*end != '\0')
678                 goto override_err;
679
680         if (edp_reg_override_mA_temp >= regulator_cur)
681                 goto override_err;
682
683         if (edp_reg_override_mA == edp_reg_override_mA_temp)
684                 return count;
685
686         edp_reg_override_mA = edp_reg_override_mA_temp;
687         if (init_cpu_edp_limits_calculated()) {
688                 /* Revert to previous override value if new value fails */
689                 edp_reg_override_mA = edp_reg_override_mA_prev;
690                 goto override_err;
691         }
692
693 #ifdef CONFIG_CPU_FREQ
694         if (tegra_cpu_set_speed_cap(NULL)) {
695                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
696                 goto override_out;
697         }
698
699         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
700                         " %u mA\n", regulator_cur - edp_reg_override_mA);
701 #else
702         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
703 #endif
704
705         return count;
706
707 override_err:
708         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
709                buf);
710 #ifdef CONFIG_CPU_FREQ
711 override_out:
712 #endif
713         return -EINVAL;
714 }
715
716 static int edp_debugfs_open(struct inode *inode, struct file *file)
717 {
718         return single_open(file, edp_debugfs_show, inode->i_private);
719 }
720
721 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
722 {
723         return single_open(file, edp_limit_debugfs_show, inode->i_private);
724 }
725
726 static int edp_reg_override_open(struct inode *inode, struct file *file)
727 {
728         return single_open(file, edp_reg_override_show, inode->i_private);
729 }
730
731 static const struct file_operations edp_debugfs_fops = {
732         .open           = edp_debugfs_open,
733         .read           = seq_read,
734         .llseek         = seq_lseek,
735         .release        = single_release,
736 };
737
738 static const struct file_operations edp_limit_debugfs_fops = {
739         .open           = edp_limit_debugfs_open,
740         .read           = seq_read,
741         .llseek         = seq_lseek,
742         .release        = single_release,
743 };
744
745 static const struct file_operations edp_reg_override_debugfs_fops = {
746         .open           = edp_reg_override_open,
747         .read           = seq_read,
748         .write          = edp_reg_override_write,
749         .llseek         = seq_lseek,
750         .release        = single_release,
751 };
752
753 #ifdef CONFIG_EDP_FRAMEWORK
754 static __init struct dentry *tegra_edp_debugfs_dir(void)
755 {
756         return edp_debugfs_dir;
757 }
758 #else
759 static __init struct dentry *tegra_edp_debugfs_dir(void)
760 {
761         return debugfs_create_dir("edp", NULL);
762 }
763 #endif
764
765 static int __init tegra_edp_debugfs_init(void)
766 {
767         struct dentry *d_edp;
768         struct dentry *d_edp_limit;
769         struct dentry *d_edp_reg_override;
770         struct dentry *edp_dir;
771         struct dentry *vdd_cpu_dir;
772
773         edp_dir = tegra_edp_debugfs_dir();
774
775         if (!edp_dir)
776                 goto edp_dir_err;
777
778         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
779
780         if (!vdd_cpu_dir)
781                 goto vdd_cpu_dir_err;
782
783         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
784                                 &edp_debugfs_fops);
785
786         if (!d_edp)
787                 goto edp_err;
788
789         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
790                                 NULL, &edp_limit_debugfs_fops);
791
792         if (!d_edp_limit)
793                 goto edp_limit_err;
794
795         d_edp_reg_override = debugfs_create_file("edp_reg_override",
796                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
797                                 &edp_reg_override_debugfs_fops);
798
799         if (!d_edp_reg_override)
800                 goto edp_reg_override_err;
801
802         if (tegra_core_edp_debugfs_init(edp_dir))
803                 goto edp_reg_override_err;
804
805         return 0;
806
807 edp_reg_override_err:
808         debugfs_remove(d_edp_limit);
809 edp_limit_err:
810         debugfs_remove(d_edp);
811 edp_err:
812         debugfs_remove(vdd_cpu_dir);
813 vdd_cpu_dir_err:
814         debugfs_remove(edp_dir);
815 edp_dir_err:
816         return -ENOMEM;
817 }
818
819 late_initcall(tegra_edp_debugfs_init);
820 #endif /* CONFIG_DEBUG_FS */