ARM: tegra: Move platform detect from <mach/hardware.h> to <linux/tegra-soc.h>
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/tegra-soc.h>
27
28 #include <mach/edp.h>
29
30 #include "fuse.h"
31 #include "dvfs.h"
32 #include "clock.h"
33 #include "cpu-tegra.h"
34
35 #define FREQ_STEP 12750000
36 #define OVERRIDE_DEFAULT 6000
37
38 static struct tegra_edp_limits *edp_limits;
39 static int edp_limits_size;
40 static unsigned int regulator_cur;
41 /* Value to subtract from regulator current limit */
42 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
43
44 static const unsigned int *system_edp_limits;
45
46 static struct tegra_system_edp_entry *power_edp_limits;
47 static int power_edp_limits_size;
48
49 /*
50  * "Safe entry" to be used when no match for speedo_id /
51  * regulator_cur is found; must be the last one
52  */
53 static struct tegra_edp_limits edp_default_limits[] = {
54         {85, {1000000, 1000000, 1000000, 1000000} },
55 };
56
57 static struct tegra_system_edp_entry power_edp_default_limits[] = {
58         {0, 20, {1000000, 1000000, 1000000, 1000000} },
59 };
60
61 /* Constants for EDP calculations */
62 static const int temperatures[] = { /* degree celcius (C) */
63         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
64 };
65
66 static const int power_cap_levels[] = { /* milliwatts (mW) */
67           500,  1000,  1500,  2000,  2500,  3000,  3500,
68          4000,  4500,  5000,  5500,  6000,  6500,  7000,
69          7500,  8000,  8500,  9000,  9500, 10000, 10500,
70         11000, 11500, 12000, 12500, 13000, 13500, 14000,
71         14500, 15000, 15500, 16000, 16500, 17000
72 };
73
74 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
75 static unsigned int freq_voltage_lut_size_saved;
76 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
77 static unsigned int freq_voltage_lut_size;
78
79 static inline s64 edp_pow(s64 val, int pwr)
80 {
81         s64 retval = 1;
82
83         while (val && pwr) {
84                 if (pwr & 1)
85                         retval *= val;
86                 pwr >>= 1;
87                 if (pwr)
88                         val *= val;
89         }
90
91         return retval;
92 }
93
94
95 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
96 static inline unsigned int edp_apply_fixed_limits(
97                                 unsigned int in_freq_KHz,
98                                 struct tegra_edp_cpu_leakage_params *params,
99                                 unsigned int cur_effective,
100                                 int temp_C, int n_cores_idx)
101 {
102         unsigned int out_freq_KHz = in_freq_KHz;
103         unsigned int max_cur, max_temp, max_freq;
104         int i;
105
106         /* Apply any additional fixed limits */
107         for (i = 0; i < 8; i++) {
108                 max_cur = params->max_current_cap[i].max_cur;
109                 if (max_cur != 0 && cur_effective <= max_cur) {
110                         max_temp = params->max_current_cap[i].max_temp;
111                         if (max_temp != 0 && temp_C > max_temp) {
112                                 max_freq = params->max_current_cap[i].
113                                         max_freq[n_cores_idx];
114                                 if (max_freq && max_freq < out_freq_KHz)
115                                         out_freq_KHz = max_freq;
116                         }
117                 }
118         }
119
120         return out_freq_KHz;
121 }
122 #else
123 #define edp_apply_fixed_limits(freq, unused...) (freq)
124 #endif
125
126 /*
127  * Find the maximum frequency that results in dynamic and leakage current that
128  * is less than the regulator current limit.
129  * temp_C - valid or -EINVAL
130  * power_mW - valid or -1 (infinite) or -EINVAL
131  */
132 static unsigned int edp_calculate_maxf(
133                                 struct tegra_edp_cpu_leakage_params *params,
134                                 int temp_C, int power_mW,
135                                 int iddq_mA,
136                                 int n_cores_idx)
137 {
138         unsigned int voltage_mV, freq_KHz = 0;
139         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
140         int f, i, j, k;
141         s64 leakage_mA, dyn_mA, leakage_calc_step;
142         s64 leakage_mW, dyn_mW;
143
144         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
145                 freq_KHz = freq_voltage_lut[f].freq / 1000;
146                 voltage_mV = freq_voltage_lut[f].voltage_mV;
147
148                 /* Constrain Volt-Temp */
149                 if (params->volt_temp_cap.temperature &&
150                     temp_C > params->volt_temp_cap.temperature &&
151                     params->volt_temp_cap.voltage_limit_mV &&
152                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
153                         continue;
154
155                 /* Calculate leakage current */
156                 leakage_mA = 0;
157                 for (i = 0; i <= 3; i++) {
158                         for (j = 0; j <= 3; j++) {
159                                 for (k = 0; k <= 3; k++) {
160                                         leakage_calc_step =
161                                                 params->leakage_consts_ijk
162                                                 [i][j][k] * edp_pow(iddq_mA, i);
163                                         /* Convert (mA)^i to (A)^i */
164                                         leakage_calc_step =
165                                                 div64_s64(leakage_calc_step,
166                                                           edp_pow(1000, i));
167                                         leakage_calc_step *=
168                                                 edp_pow(voltage_mV, j);
169                                         /* Convert (mV)^j to (V)^j */
170                                         leakage_calc_step =
171                                                 div64_s64(leakage_calc_step,
172                                                           edp_pow(1000, j));
173                                         leakage_calc_step *=
174                                                 edp_pow(temp_C, k);
175                                         /* Convert (C)^k to (scaled_C)^k */
176                                         leakage_calc_step =
177                                                 div64_s64(leakage_calc_step,
178                                                 edp_pow(params->temp_scaled,
179                                                         k));
180                                         /* leakage_consts_ijk was scaled */
181                                         leakage_calc_step =
182                                                 div64_s64(leakage_calc_step,
183                                                           params->ijk_scaled);
184                                         leakage_mA += leakage_calc_step;
185                                 }
186                         }
187                 }
188
189                 /* set floor for leakage current */
190                 if (leakage_mA <= params->leakage_min)
191                         leakage_mA = params->leakage_min;
192
193                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
194
195                 /* leakage_const_n was scaled */
196                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
197
198                 /* Calculate dynamic current */
199                 dyn_mA = voltage_mV * freq_KHz / 1000;
200                 /* Convert mV to V */
201                 dyn_mA = div64_s64(dyn_mA, 1000);
202                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
203                 /* dyn_const_n was scaled */
204                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
205
206                 if (power_mW != -1) {
207                         leakage_mW = leakage_mA * voltage_mV;
208                         dyn_mW = dyn_mA * voltage_mV;
209                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
210                                 goto end;
211                 } else if ((leakage_mA + dyn_mA) <= cur_effective) {
212                         goto end;
213                 }
214                 freq_KHz = 0;
215         }
216
217  end:
218         return edp_apply_fixed_limits(freq_KHz, params,
219                                         cur_effective, temp_C, n_cores_idx);
220 }
221
222 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
223                         unsigned int cpu_speedo_idx,
224                         unsigned int freq_volt_lut_size,
225                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
226 {
227         unsigned int i, j, freq;
228         int voltage_mV;
229
230         for (i = 0, j = 0, freq = 0;
231                  i < freq_volt_lut_size;
232                  i++, freq += FREQ_STEP) {
233
234                 /* Predict voltages */
235                 voltage_mV = tegra_dvfs_predict_millivolts(clk_cpu_g, freq);
236                 if (voltage_mV < 0) {
237                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
238                                __func__, freq, voltage_mV);
239                         return -EINVAL;
240                 }
241
242                 /* Cache frequency / voltage / voltage constant relationship */
243                 freq_volt_lut[i].freq = freq;
244                 freq_volt_lut[i].voltage_mV = voltage_mV;
245         }
246         return 0;
247 }
248
249 unsigned int tegra_edp_find_maxf(int volt)
250 {
251         unsigned int i;
252
253         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
254                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
255                         break;
256         }
257         return freq_voltage_lut[i - 1].freq;
258 }
259
260
261 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
262 {
263         int i, array_size;
264         struct tegra_edp_cpu_leakage_params *params;
265
266         switch (tegra_chip_id) {
267         case TEGRA_CHIPID_TEGRA11:
268                 params = tegra11x_get_leakage_params(0, &array_size);
269                 break;
270         case TEGRA_CHIPID_TEGRA14:
271                 params = tegra14x_get_leakage_params(0, &array_size);
272                 break;
273         case TEGRA_CHIPID_TEGRA12:
274                 params = tegra12x_get_leakage_params(0, &array_size);
275                 break;
276         case TEGRA_CHIPID_TEGRA3:
277         case TEGRA_CHIPID_TEGRA2:
278         default:
279                 array_size = 0;
280                 break;
281         }
282
283         for (i = 0; i < array_size; i++)
284                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
285                         *cpu_speedo_idx = i;
286                         return 0;
287                 }
288
289         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
290                __func__, cpu_speedo_id);
291         return -EINVAL;
292 }
293
294 static int init_cpu_edp_limits_calculated(void)
295 {
296         unsigned int max_nr_cpus = num_possible_cpus();
297         unsigned int temp_idx, n_cores_idx, pwr_idx;
298         unsigned int cpu_g_minf, cpu_g_maxf;
299         unsigned int iddq_mA;
300         unsigned int cpu_speedo_idx;
301         unsigned int cap, limit;
302         struct tegra_edp_limits *edp_calculated_limits;
303         struct tegra_system_edp_entry *power_edp_calc_limits;
304         struct tegra_edp_cpu_leakage_params *params;
305         int ret;
306         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
307         int cpu_speedo_id = tegra_cpu_speedo_id();
308
309         /* Determine all inputs to EDP formula */
310         iddq_mA = tegra_get_cpu_iddq_value();
311         iddq_mA = 1281; /* hard code for testing */
312         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
313         if (ret)
314                 return ret;
315
316         switch (tegra_chip_id) {
317         case TEGRA_CHIPID_TEGRA11:
318                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
319                 break;
320         case TEGRA_CHIPID_TEGRA14:
321                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
322                 break;
323         case TEGRA_CHIPID_TEGRA12:
324                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
325                 break;
326         case TEGRA_CHIPID_TEGRA3:
327         case TEGRA_CHIPID_TEGRA2:
328         default:
329                 return -EINVAL;
330         }
331
332         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
333                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
334         BUG_ON(!edp_calculated_limits);
335
336         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
337                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
338         BUG_ON(!power_edp_calc_limits);
339
340         cpu_g_minf = 0;
341         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
342         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
343         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
344                                    * freq_voltage_lut_size, GFP_KERNEL);
345         if (!freq_voltage_lut) {
346                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
347                 kfree(power_edp_calc_limits);
348                 kfree(edp_calculated_limits);
349                 return -ENOMEM;
350         }
351
352         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
353                                 freq_voltage_lut_size, freq_voltage_lut);
354         if (ret) {
355                 kfree(power_edp_calc_limits);
356                 kfree(edp_calculated_limits);
357                 kfree(freq_voltage_lut);
358                 return ret;
359         }
360
361         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
362                 /* release previous table if present */
363                 kfree(freq_voltage_lut_saved);
364                 /* create table to save */
365                 freq_voltage_lut_saved =
366                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
367                         freq_voltage_lut_size, GFP_KERNEL);
368                 if (!freq_voltage_lut_saved) {
369                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
370                                 __func__);
371                         kfree(freq_voltage_lut);
372                         return -ENOMEM;
373                 }
374                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
375         }
376         memcpy(freq_voltage_lut_saved,
377                 freq_voltage_lut,
378                 sizeof(struct tegra_edp_freq_voltage_table) *
379                         freq_voltage_lut_size);
380
381         /* Calculate EDP table */
382         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
383                 for (temp_idx = 0;
384                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
385                         edp_calculated_limits[temp_idx].temperature =
386                                 temperatures[temp_idx];
387                         limit = edp_calculate_maxf(params,
388                                                    temperatures[temp_idx],
389                                                    -1,
390                                                    iddq_mA,
391                                                    n_cores_idx);
392                         if (limit == -EINVAL)
393                                 return -EINVAL;
394                         /* apply safety cap if it is specified */
395                         if (n_cores_idx < 4) {
396                                 cap = params->safety_cap[n_cores_idx];
397                                 if (cap && cap < limit)
398                                         limit = cap;
399                         }
400                         edp_calculated_limits[temp_idx].
401                                 freq_limits[n_cores_idx] = limit;
402                 }
403
404                 for (pwr_idx = 0;
405                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
406                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
407                                 power_cap_levels[pwr_idx] / 100;
408                         limit = edp_calculate_maxf(params,
409                                                    90,
410                                                    power_cap_levels[pwr_idx],
411                                                    iddq_mA,
412                                                    n_cores_idx);
413                         if (limit == -EINVAL)
414                                 return -EINVAL;
415                         power_edp_calc_limits[pwr_idx].
416                                 freq_limits[n_cores_idx] = limit;
417                 }
418         }
419
420         /*
421          * If this is an EDP table update, need to overwrite old table.
422          * The old table's address must remain valid.
423          */
424         if (edp_limits != edp_default_limits) {
425                 memcpy(edp_limits, edp_calculated_limits,
426                        sizeof(struct tegra_edp_limits)
427                        * ARRAY_SIZE(temperatures));
428                 kfree(edp_calculated_limits);
429         }
430         else {
431                 edp_limits = edp_calculated_limits;
432                 edp_limits_size = ARRAY_SIZE(temperatures);
433         }
434
435         if (power_edp_limits != power_edp_default_limits) {
436                 memcpy(power_edp_limits, power_edp_calc_limits,
437                        sizeof(struct tegra_system_edp_entry)
438                        * ARRAY_SIZE(power_cap_levels));
439                 kfree(power_edp_calc_limits);
440         } else {
441                 power_edp_limits = power_edp_calc_limits;
442                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
443         }
444
445         kfree(freq_voltage_lut);
446         return 0;
447 }
448
449 void tegra_recalculate_cpu_edp_limits(void)
450 {
451         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
452             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
453             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
454                 return;
455
456         if (init_cpu_edp_limits_calculated() == 0)
457                 return;
458
459         /* Revert to default EDP table on error */
460         edp_limits = edp_default_limits;
461         edp_limits_size = ARRAY_SIZE(edp_default_limits);
462
463         power_edp_limits = power_edp_default_limits;
464         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
465 }
466
467 /*
468  * Specify regulator current in mA, e.g. 5000mA
469  * Use 0 for default
470  */
471 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
472 {
473         if (!regulator_mA)
474                 goto end;
475         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
476
477         switch (tegra_chip_id) {
478         case TEGRA_CHIPID_TEGRA11:
479         case TEGRA_CHIPID_TEGRA14:
480         case TEGRA_CHIPID_TEGRA12:
481                 if (init_cpu_edp_limits_calculated() == 0)
482                         return;
483                 break;
484         case TEGRA_CHIPID_TEGRA2:
485         case TEGRA_CHIPID_TEGRA3:
486         default:
487                 BUG();
488                 break;
489         }
490
491  end:
492         edp_limits = edp_default_limits;
493         edp_limits_size = ARRAY_SIZE(edp_default_limits);
494
495         power_edp_limits = power_edp_default_limits;
496         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
497 }
498
499 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
500 {
501         *limits = edp_limits;
502         *size = edp_limits_size;
503 }
504
505 void tegra_get_system_edp_limits(const unsigned int **limits)
506 {
507         *limits = system_edp_limits;
508 }
509
510 void tegra_platform_edp_init(struct thermal_trip_info *trips,
511                                 int *num_trips, int margin)
512 {
513         const struct tegra_edp_limits *cpu_edp_limits;
514         struct thermal_trip_info *trip_state;
515         int i, cpu_edp_limits_size;
516
517         if (!trips || !num_trips)
518                 return;
519
520         /* edp capping */
521         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
522
523         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
524                 BUG();
525
526         for (i = 0; i < cpu_edp_limits_size-1; i++) {
527                 trip_state = &trips[*num_trips];
528
529                 trip_state->cdev_type = "cpu_edp";
530                 trip_state->trip_temp =
531                         (cpu_edp_limits[i].temperature * 1000) - margin;
532                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
533                 trip_state->upper = trip_state->lower = i + 1;
534
535                 (*num_trips)++;
536
537                 if (*num_trips >= THERMAL_MAX_TRIPS)
538                         BUG();
539         }
540 }
541
542 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
543 {
544         *size = power_edp_limits_size;
545         return power_edp_limits;
546 }
547
548 #ifdef CONFIG_DEBUG_FS
549
550 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
551 {
552 #ifdef CONFIG_CPU_FREQ
553         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
554 #endif
555         return 0;
556 }
557
558 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
559 {
560         int i;
561
562         seq_printf(s, "%6s %10s %10s %10s %10s\n",
563                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
564         for (i = 0; i < edp_limits_size; i++) {
565                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
566                            i == th_idx ? '>' : ' ',
567                            edp_limits[i].temperature,
568                            edp_limits[i].freq_limits[0],
569                            edp_limits[i].freq_limits[1],
570                            edp_limits[i].freq_limits[2],
571                            edp_limits[i].freq_limits[3]);
572         }
573 }
574
575 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
576 {
577         int i;
578
579         seq_printf(s, "%6s %10s %10s\n",
580                    " Temp.", "1-core", "2-cores");
581         for (i = 0; i < edp_limits_size; i++) {
582                 seq_printf(s, "%c%3dC: %10u %10u\n",
583                            i == th_idx ? '>' : ' ',
584                            edp_limits[i].temperature,
585                            edp_limits[i].freq_limits[0],
586                            edp_limits[i].freq_limits[1]);
587         }
588 }
589
590 static inline void edp_show_2core_system_table(struct seq_file *s)
591 {
592         seq_printf(s, "%10u %10u\n",
593                    system_edp_limits[0],
594                    system_edp_limits[1]);
595 }
596
597 static inline void edp_show_4core_system_table(struct seq_file *s)
598 {
599         seq_printf(s, "%10u %10u %10u %10u\n",
600                    system_edp_limits[0],
601                    system_edp_limits[1],
602                    system_edp_limits[2],
603                    system_edp_limits[3]);
604 }
605
606 static int edp_debugfs_show(struct seq_file *s, void *data)
607 {
608         unsigned int max_nr_cpus = num_possible_cpus();
609         int th_idx;
610
611         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
612                 seq_printf(s, "Unsupported number of CPUs\n");
613                 return 0;
614         }
615
616 #ifdef CONFIG_CPU_FREQ
617         tegra_get_edp_limit(&th_idx);
618 #else
619         th_idx = 0;
620 #endif
621
622         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
623                    edp_limits == edp_default_limits ? "**default** " : "",
624                    regulator_cur - edp_reg_override_mA,
625                    regulator_cur, edp_reg_override_mA);
626
627         if (max_nr_cpus == 2)
628                 edp_show_2core_edp_table(s, th_idx);
629         else if (max_nr_cpus == 4)
630                 edp_show_4core_edp_table(s, th_idx);
631
632         if (system_edp_limits) {
633                 seq_printf(s, "\n-- System EDP table --\n");
634                 if (max_nr_cpus == 2)
635                         edp_show_2core_system_table(s);
636                 else if (max_nr_cpus == 4)
637                         edp_show_4core_system_table(s);
638         }
639
640         return 0;
641 }
642
643 static int edp_reg_override_show(struct seq_file *s, void *data)
644 {
645         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
646                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
647         return 0;
648 }
649
650 static int edp_reg_override_write(struct file *file,
651         const char __user *userbuf, size_t count, loff_t *ppos)
652 {
653         char buf[32], *end;
654         unsigned int edp_reg_override_mA_temp;
655         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
656
657         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
658                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
659                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
660                 goto override_err;
661
662         if (sizeof(buf) <= count)
663                 goto override_err;
664
665         if (copy_from_user(buf, userbuf, count))
666                 goto override_err;
667
668         /* terminate buffer and trim - white spaces may be appended
669          *  at the end when invoked from shell command line */
670         buf[count]='\0';
671         strim(buf);
672
673         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
674         if (*end != '\0')
675                 goto override_err;
676
677         if (edp_reg_override_mA_temp >= regulator_cur)
678                 goto override_err;
679
680         if (edp_reg_override_mA == edp_reg_override_mA_temp)
681                 return count;
682
683         edp_reg_override_mA = edp_reg_override_mA_temp;
684         if (init_cpu_edp_limits_calculated()) {
685                 /* Revert to previous override value if new value fails */
686                 edp_reg_override_mA = edp_reg_override_mA_prev;
687                 goto override_err;
688         }
689
690 #ifdef CONFIG_CPU_FREQ
691         if (tegra_cpu_set_speed_cap(NULL)) {
692                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
693                 goto override_out;
694         }
695
696         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
697                         " %u mA\n", regulator_cur - edp_reg_override_mA);
698 #else
699         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
700 #endif
701
702         return count;
703
704 override_err:
705         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
706                buf);
707 #ifdef CONFIG_CPU_FREQ
708 override_out:
709 #endif
710         return -EINVAL;
711 }
712
713 static int edp_debugfs_open(struct inode *inode, struct file *file)
714 {
715         return single_open(file, edp_debugfs_show, inode->i_private);
716 }
717
718 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
719 {
720         return single_open(file, edp_limit_debugfs_show, inode->i_private);
721 }
722
723 static int edp_reg_override_open(struct inode *inode, struct file *file)
724 {
725         return single_open(file, edp_reg_override_show, inode->i_private);
726 }
727
728 static const struct file_operations edp_debugfs_fops = {
729         .open           = edp_debugfs_open,
730         .read           = seq_read,
731         .llseek         = seq_lseek,
732         .release        = single_release,
733 };
734
735 static const struct file_operations edp_limit_debugfs_fops = {
736         .open           = edp_limit_debugfs_open,
737         .read           = seq_read,
738         .llseek         = seq_lseek,
739         .release        = single_release,
740 };
741
742 static const struct file_operations edp_reg_override_debugfs_fops = {
743         .open           = edp_reg_override_open,
744         .read           = seq_read,
745         .write          = edp_reg_override_write,
746         .llseek         = seq_lseek,
747         .release        = single_release,
748 };
749
750 #ifdef CONFIG_EDP_FRAMEWORK
751 static __init struct dentry *tegra_edp_debugfs_dir(void)
752 {
753         return edp_debugfs_dir;
754 }
755 #else
756 static __init struct dentry *tegra_edp_debugfs_dir(void)
757 {
758         return debugfs_create_dir("edp", NULL);
759 }
760 #endif
761
762 static int __init tegra_edp_debugfs_init(void)
763 {
764         struct dentry *d_edp;
765         struct dentry *d_edp_limit;
766         struct dentry *d_edp_reg_override;
767         struct dentry *edp_dir;
768         struct dentry *vdd_cpu_dir;
769
770         if (!tegra_platform_is_silicon())
771                 return -ENOSYS;
772
773         edp_dir = tegra_edp_debugfs_dir();
774
775         if (!edp_dir)
776                 goto edp_dir_err;
777
778         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
779
780         if (!vdd_cpu_dir)
781                 goto vdd_cpu_dir_err;
782
783         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
784                                 &edp_debugfs_fops);
785
786         if (!d_edp)
787                 goto edp_err;
788
789         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
790                                 NULL, &edp_limit_debugfs_fops);
791
792         if (!d_edp_limit)
793                 goto edp_limit_err;
794
795         d_edp_reg_override = debugfs_create_file("edp_reg_override",
796                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
797                                 &edp_reg_override_debugfs_fops);
798
799         if (!d_edp_reg_override)
800                 goto edp_reg_override_err;
801
802         if (tegra_core_edp_debugfs_init(edp_dir))
803                 goto edp_reg_override_err;
804
805         return 0;
806
807 edp_reg_override_err:
808         debugfs_remove(d_edp_limit);
809 edp_limit_err:
810         debugfs_remove(d_edp);
811 edp_err:
812         debugfs_remove(vdd_cpu_dir);
813 vdd_cpu_dir_err:
814         debugfs_remove(edp_dir);
815 edp_dir_err:
816         return -ENOMEM;
817 }
818
819 late_initcall(tegra_edp_debugfs_init);
820 #endif /* CONFIG_DEBUG_FS */