arm: tegra: EDP: add compatibility to new EDP
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28
29 #include <mach/edp.h>
30
31 #include "fuse.h"
32 #include "dvfs.h"
33 #include "clock.h"
34 #include "cpu-tegra.h"
35
36 #define FREQ_STEP 12750000
37 #define OVERRIDE_DEFAULT 6000
38
39 static struct tegra_edp_limits *edp_limits;
40 static int edp_limits_size;
41 static unsigned int regulator_cur;
42 /* Value to subtract from regulator current limit */
43 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
44
45 static const unsigned int *system_edp_limits;
46
47 static struct tegra_system_edp_entry *power_edp_limits;
48 static int power_edp_limits_size;
49
50 /*
51  * "Safe entry" to be used when no match for speedo_id /
52  * regulator_cur is found; must be the last one
53  */
54 static struct tegra_edp_limits edp_default_limits[] = {
55         {85, {1000000, 1000000, 1000000, 1000000} },
56 };
57
58 static struct tegra_system_edp_entry power_edp_default_limits[] = {
59         {0, 20, {1000000, 1000000, 1000000, 1000000} },
60 };
61
62 /* Constants for EDP calculations */
63 static const int temperatures[] = { /* degree celcius (C) */
64         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
65 };
66
67 static const int power_cap_levels[] = { /* milliwatts (mW) */
68           500,  1000,  1500,  2000,  2500,  3000,  3500,
69          4000,  4500,  5000,  5500,  6000,  6500,  7000,
70          7500,  8000,  8500,  9000,  9500, 10000, 10500,
71         11000, 11500, 12000, 12500, 13000, 13500, 14000,
72         14500, 15000, 15500, 16000, 16500, 17000
73 };
74
75 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
76 static unsigned int freq_voltage_lut_size_saved;
77 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
78 static unsigned int freq_voltage_lut_size;
79
80 static inline s64 edp_pow(s64 val, int pwr)
81 {
82         s64 retval = 1;
83
84         while (val && pwr) {
85                 if (pwr & 1)
86                         retval *= val;
87                 pwr >>= 1;
88                 if (pwr)
89                         val *= val;
90         }
91
92         return retval;
93 }
94
95
96 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
97 static inline unsigned int edp_apply_fixed_limits(
98                                 unsigned int in_freq_KHz,
99                                 struct tegra_edp_cpu_leakage_params *params,
100                                 unsigned int cur_effective,
101                                 int temp_C, int n_cores_idx)
102 {
103         unsigned int out_freq_KHz = in_freq_KHz;
104         unsigned int max_cur, max_temp, max_freq;
105         int i;
106
107         /* Apply any additional fixed limits */
108         for (i = 0; i < 8; i++) {
109                 max_cur = params->max_current_cap[i].max_cur;
110                 if (max_cur != 0 && cur_effective <= max_cur) {
111                         max_temp = params->max_current_cap[i].max_temp;
112                         if (max_temp != 0 && temp_C > max_temp) {
113                                 max_freq = params->max_current_cap[i].
114                                         max_freq[n_cores_idx];
115                                 if (max_freq && max_freq < out_freq_KHz)
116                                         out_freq_KHz = max_freq;
117                         }
118                 }
119         }
120
121         return out_freq_KHz;
122 }
123 #else
124 #define edp_apply_fixed_limits(freq, unused...) (freq)
125 #endif
126
127 /*
128  * Find the maximum frequency that results in dynamic and leakage current that
129  * is less than the regulator current limit.
130  * temp_C - valid or -EINVAL
131  * power_mW - valid or -1 (infinite) or -EINVAL
132  */
133 static unsigned int edp_calculate_maxf(
134                                 struct tegra_edp_cpu_leakage_params *params,
135                                 int temp_C, int power_mW,
136                                 int iddq_mA,
137                                 int n_cores_idx)
138 {
139         unsigned int voltage_mV, freq_KHz = 0;
140         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
141         int f, i, j, k;
142         s64 leakage_mA, dyn_mA, leakage_calc_step;
143         s64 leakage_mW, dyn_mW;
144
145         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
146                 freq_KHz = freq_voltage_lut[f].freq / 1000;
147                 voltage_mV = freq_voltage_lut[f].voltage_mV;
148
149                 /* Constrain Volt-Temp */
150                 if (params->volt_temp_cap.temperature &&
151                     temp_C > params->volt_temp_cap.temperature &&
152                     params->volt_temp_cap.voltage_limit_mV &&
153                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
154                         continue;
155
156                 /* Calculate leakage current */
157                 leakage_mA = 0;
158                 for (i = 0; i <= 3; i++) {
159                         for (j = 0; j <= 3; j++) {
160                                 for (k = 0; k <= 3; k++) {
161                                         leakage_calc_step =
162                                                 params->leakage_consts_ijk
163                                                 [i][j][k] * edp_pow(iddq_mA, i);
164                                         /* Convert (mA)^i to (A)^i */
165                                         leakage_calc_step =
166                                                 div64_s64(leakage_calc_step,
167                                                           edp_pow(1000, i));
168                                         leakage_calc_step *=
169                                                 edp_pow(voltage_mV, j);
170                                         /* Convert (mV)^j to (V)^j */
171                                         leakage_calc_step =
172                                                 div64_s64(leakage_calc_step,
173                                                           edp_pow(1000, j));
174                                         leakage_calc_step *=
175                                                 edp_pow(temp_C, k);
176                                         /* Convert (C)^k to (scaled_C)^k */
177                                         leakage_calc_step =
178                                                 div64_s64(leakage_calc_step,
179                                                 edp_pow(params->temp_scaled,
180                                                         k));
181                                         /* leakage_consts_ijk was scaled */
182                                         leakage_calc_step =
183                                                 div64_s64(leakage_calc_step,
184                                                           params->ijk_scaled);
185                                         leakage_mA += leakage_calc_step;
186                                 }
187                         }
188                 }
189
190                 /* set floor for leakage current */
191                 if (leakage_mA <= params->leakage_min)
192                         leakage_mA = params->leakage_min;
193
194                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
195
196                 /* leakage_const_n was scaled */
197                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
198
199                 /* Calculate dynamic current */
200                 dyn_mA = voltage_mV * freq_KHz / 1000;
201                 /* Convert mV to V */
202                 dyn_mA = div64_s64(dyn_mA, 1000);
203                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
204                 /* dyn_const_n was scaled */
205                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
206
207                 if (power_mW != -1) {
208                         leakage_mW = leakage_mA * voltage_mV;
209                         dyn_mW = dyn_mA * voltage_mV;
210                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
211                                 goto end;
212                 } else if ((leakage_mA + dyn_mA) <= cur_effective) {
213                         goto end;
214                 }
215                 freq_KHz = 0;
216         }
217
218  end:
219         return edp_apply_fixed_limits(freq_KHz, params,
220                                         cur_effective, temp_C, n_cores_idx);
221 }
222
223 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
224                         unsigned int cpu_speedo_idx,
225                         unsigned int freq_volt_lut_size,
226                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
227 {
228         unsigned int i, j, freq;
229         int voltage_mV;
230
231         for (i = 0, j = 0, freq = 0;
232                  i < freq_volt_lut_size;
233                  i++, freq += FREQ_STEP) {
234
235                 /* Predict voltages */
236                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
237                         clk_cpu_g, freq);
238                 if (voltage_mV < 0) {
239                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
240                                __func__, freq, voltage_mV);
241                         return -EINVAL;
242                 }
243
244                 /* Cache frequency / voltage / voltage constant relationship */
245                 freq_volt_lut[i].freq = freq;
246                 freq_volt_lut[i].voltage_mV = voltage_mV;
247         }
248         return 0;
249 }
250
251 unsigned int tegra_edp_find_maxf(int volt)
252 {
253         unsigned int i;
254
255         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
256                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
257                         break;
258         }
259         return freq_voltage_lut[i - 1].freq;
260 }
261
262
263 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
264 {
265         int i, array_size;
266         struct tegra_edp_cpu_leakage_params *params;
267
268         switch (tegra_get_chip_id()) {
269         case TEGRA_CHIPID_TEGRA11:
270                 params = tegra11x_get_leakage_params(0, &array_size);
271                 break;
272         case TEGRA_CHIPID_TEGRA14:
273                 params = tegra14x_get_leakage_params(0, &array_size);
274                 break;
275         case TEGRA_CHIPID_TEGRA12:
276                 params = tegra12x_get_leakage_params(0, &array_size);
277                 break;
278         case TEGRA_CHIPID_TEGRA3:
279         case TEGRA_CHIPID_TEGRA2:
280         default:
281                 array_size = 0;
282                 break;
283         }
284
285         for (i = 0; i < array_size; i++)
286                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
287                         *cpu_speedo_idx = i;
288                         return 0;
289                 }
290
291         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
292                __func__, cpu_speedo_id);
293         return -EINVAL;
294 }
295
296 static int init_cpu_edp_limits_calculated(void)
297 {
298         unsigned int max_nr_cpus = num_possible_cpus();
299         unsigned int temp_idx, n_cores_idx, pwr_idx;
300         unsigned int cpu_g_minf, cpu_g_maxf;
301         unsigned int iddq_mA;
302         unsigned int cpu_speedo_idx;
303         unsigned int cap, limit;
304         struct tegra_edp_limits *edp_calculated_limits;
305         struct tegra_system_edp_entry *power_edp_calc_limits;
306         struct tegra_edp_cpu_leakage_params *params;
307         int ret;
308         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
309         int cpu_speedo_id = tegra_cpu_speedo_id();
310
311         /* Determine all inputs to EDP formula */
312         iddq_mA = tegra_get_cpu_iddq_value();
313         iddq_mA = 1281; /* hard code for testing */
314         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
315         if (ret)
316                 return ret;
317
318         switch (tegra_get_chip_id()) {
319         case TEGRA_CHIPID_TEGRA11:
320                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
321                 break;
322         case TEGRA_CHIPID_TEGRA14:
323                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
324                 break;
325         case TEGRA_CHIPID_TEGRA12:
326                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
327                 break;
328         case TEGRA_CHIPID_TEGRA3:
329         case TEGRA_CHIPID_TEGRA2:
330         default:
331                 return -EINVAL;
332         }
333
334         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
335                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
336         BUG_ON(!edp_calculated_limits);
337
338         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
339                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
340         BUG_ON(!power_edp_calc_limits);
341
342         cpu_g_minf = 0;
343         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
344         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
345         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
346                                    * freq_voltage_lut_size, GFP_KERNEL);
347         if (!freq_voltage_lut) {
348                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
349                 kfree(power_edp_calc_limits);
350                 kfree(edp_calculated_limits);
351                 return -ENOMEM;
352         }
353
354         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
355                                 freq_voltage_lut_size, freq_voltage_lut);
356         if (ret) {
357                 kfree(power_edp_calc_limits);
358                 kfree(edp_calculated_limits);
359                 kfree(freq_voltage_lut);
360                 return ret;
361         }
362
363         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
364                 /* release previous table if present */
365                 kfree(freq_voltage_lut_saved);
366                 /* create table to save */
367                 freq_voltage_lut_saved =
368                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
369                         freq_voltage_lut_size, GFP_KERNEL);
370                 if (!freq_voltage_lut_saved) {
371                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
372                                 __func__);
373                         kfree(freq_voltage_lut);
374                         return -ENOMEM;
375                 }
376                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
377         }
378         memcpy(freq_voltage_lut_saved,
379                 freq_voltage_lut,
380                 sizeof(struct tegra_edp_freq_voltage_table) *
381                         freq_voltage_lut_size);
382
383         /* Calculate EDP table */
384         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
385                 for (temp_idx = 0;
386                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
387                         edp_calculated_limits[temp_idx].temperature =
388                                 temperatures[temp_idx];
389                         limit = edp_calculate_maxf(params,
390                                                    temperatures[temp_idx],
391                                                    -1,
392                                                    iddq_mA,
393                                                    n_cores_idx);
394                         if (limit == -EINVAL)
395                                 return -EINVAL;
396                         /* apply safety cap if it is specified */
397                         if (n_cores_idx < 4) {
398                                 cap = params->safety_cap[n_cores_idx];
399                                 if (cap && cap < limit)
400                                         limit = cap;
401                         }
402                         edp_calculated_limits[temp_idx].
403                                 freq_limits[n_cores_idx] = limit;
404                 }
405
406                 for (pwr_idx = 0;
407                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
408                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
409                                 power_cap_levels[pwr_idx] / 100;
410                         limit = edp_calculate_maxf(params,
411                                                    90,
412                                                    power_cap_levels[pwr_idx],
413                                                    iddq_mA,
414                                                    n_cores_idx);
415                         if (limit == -EINVAL)
416                                 return -EINVAL;
417                         power_edp_calc_limits[pwr_idx].
418                                 freq_limits[n_cores_idx] = limit;
419                 }
420         }
421
422         /*
423          * If this is an EDP table update, need to overwrite old table.
424          * The old table's address must remain valid.
425          */
426         if (edp_limits != edp_default_limits) {
427                 memcpy(edp_limits, edp_calculated_limits,
428                        sizeof(struct tegra_edp_limits)
429                        * ARRAY_SIZE(temperatures));
430                 kfree(edp_calculated_limits);
431         }
432         else {
433                 edp_limits = edp_calculated_limits;
434                 edp_limits_size = ARRAY_SIZE(temperatures);
435         }
436
437         if (power_edp_limits != power_edp_default_limits) {
438                 memcpy(power_edp_limits, power_edp_calc_limits,
439                        sizeof(struct tegra_system_edp_entry)
440                        * ARRAY_SIZE(power_cap_levels));
441                 kfree(power_edp_calc_limits);
442         } else {
443                 power_edp_limits = power_edp_calc_limits;
444                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
445         }
446
447         kfree(freq_voltage_lut);
448         return 0;
449 }
450
451 void tegra_recalculate_cpu_edp_limits(void)
452 {
453         u32 tegra_chip_id;
454
455         tegra_chip_id = tegra_get_chip_id();
456         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
457             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
458             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
459                 return;
460
461         if (init_cpu_edp_limits_calculated() == 0)
462                 return;
463
464         /* Revert to default EDP table on error */
465         edp_limits = edp_default_limits;
466         edp_limits_size = ARRAY_SIZE(edp_default_limits);
467
468         power_edp_limits = power_edp_default_limits;
469         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
470 }
471
472 /*
473  * Specify regulator current in mA, e.g. 5000mA
474  * Use 0 for default
475  */
476 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
477 {
478         if (!regulator_mA)
479                 goto end;
480         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
481
482         switch (tegra_get_chip_id()) {
483         case TEGRA_CHIPID_TEGRA11:
484         case TEGRA_CHIPID_TEGRA14:
485         case TEGRA_CHIPID_TEGRA12:
486                 if (init_cpu_edp_limits_calculated() == 0)
487                         return;
488                 break;
489         case TEGRA_CHIPID_TEGRA2:
490         case TEGRA_CHIPID_TEGRA3:
491         default:
492                 BUG();
493                 break;
494         }
495
496  end:
497         edp_limits = edp_default_limits;
498         edp_limits_size = ARRAY_SIZE(edp_default_limits);
499
500         power_edp_limits = power_edp_default_limits;
501         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
502 }
503
504 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
505 {
506         *limits = edp_limits;
507         *size = edp_limits_size;
508 }
509
510 void tegra_get_system_edp_limits(const unsigned int **limits)
511 {
512         *limits = system_edp_limits;
513 }
514
515 void tegra_platform_edp_init(struct thermal_trip_info *trips,
516                                 int *num_trips, int margin)
517 {
518         const struct tegra_edp_limits *cpu_edp_limits;
519         struct thermal_trip_info *trip_state;
520         int i, cpu_edp_limits_size;
521
522         if (!trips || !num_trips)
523                 return;
524
525         /* edp capping */
526         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
527
528         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
529                 BUG();
530
531         for (i = 0; i < cpu_edp_limits_size-1; i++) {
532                 trip_state = &trips[*num_trips];
533
534                 trip_state->cdev_type = "cpu_edp";
535                 trip_state->trip_temp =
536                         (cpu_edp_limits[i].temperature * 1000) - margin;
537                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
538                 trip_state->upper = trip_state->lower = i + 1;
539
540                 (*num_trips)++;
541
542                 if (*num_trips >= THERMAL_MAX_TRIPS)
543                         BUG();
544         }
545 }
546
547 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
548 {
549         *size = power_edp_limits_size;
550         return power_edp_limits;
551 }
552
553 #ifdef CONFIG_DEBUG_FS
554
555 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
556 {
557 #ifdef CONFIG_CPU_FREQ
558         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
559 #endif
560         return 0;
561 }
562
563 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
564 {
565         int i;
566
567         seq_printf(s, "%6s %10s %10s %10s %10s\n",
568                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
569         for (i = 0; i < edp_limits_size; i++) {
570                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
571                            i == th_idx ? '>' : ' ',
572                            edp_limits[i].temperature,
573                            edp_limits[i].freq_limits[0],
574                            edp_limits[i].freq_limits[1],
575                            edp_limits[i].freq_limits[2],
576                            edp_limits[i].freq_limits[3]);
577         }
578 }
579
580 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
581 {
582         int i;
583
584         seq_printf(s, "%6s %10s %10s\n",
585                    " Temp.", "1-core", "2-cores");
586         for (i = 0; i < edp_limits_size; i++) {
587                 seq_printf(s, "%c%3dC: %10u %10u\n",
588                            i == th_idx ? '>' : ' ',
589                            edp_limits[i].temperature,
590                            edp_limits[i].freq_limits[0],
591                            edp_limits[i].freq_limits[1]);
592         }
593 }
594
595 static inline void edp_show_2core_system_table(struct seq_file *s)
596 {
597         seq_printf(s, "%10u %10u\n",
598                    system_edp_limits[0],
599                    system_edp_limits[1]);
600 }
601
602 static inline void edp_show_4core_system_table(struct seq_file *s)
603 {
604         seq_printf(s, "%10u %10u %10u %10u\n",
605                    system_edp_limits[0],
606                    system_edp_limits[1],
607                    system_edp_limits[2],
608                    system_edp_limits[3]);
609 }
610
611 static int edp_debugfs_show(struct seq_file *s, void *data)
612 {
613         unsigned int max_nr_cpus = num_possible_cpus();
614         int th_idx;
615
616         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
617                 seq_printf(s, "Unsupported number of CPUs\n");
618                 return 0;
619         }
620
621 #ifdef CONFIG_CPU_FREQ
622         tegra_get_edp_limit(&th_idx);
623 #else
624         th_idx = 0;
625 #endif
626
627         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
628                    edp_limits == edp_default_limits ? "**default** " : "",
629                    regulator_cur - edp_reg_override_mA,
630                    regulator_cur, edp_reg_override_mA);
631
632         if (max_nr_cpus == 2)
633                 edp_show_2core_edp_table(s, th_idx);
634         else if (max_nr_cpus == 4)
635                 edp_show_4core_edp_table(s, th_idx);
636
637         if (system_edp_limits) {
638                 seq_printf(s, "\n-- System EDP table --\n");
639                 if (max_nr_cpus == 2)
640                         edp_show_2core_system_table(s);
641                 else if (max_nr_cpus == 4)
642                         edp_show_4core_system_table(s);
643         }
644
645         return 0;
646 }
647
648 static int edp_reg_override_show(struct seq_file *s, void *data)
649 {
650         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
651                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
652         return 0;
653 }
654
655 static int edp_reg_override_write(struct file *file,
656         const char __user *userbuf, size_t count, loff_t *ppos)
657 {
658         char buf[32], *end;
659         unsigned int edp_reg_override_mA_temp;
660         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
661         u32 tegra_chip_id;
662
663         tegra_chip_id = tegra_get_chip_id();
664         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
665                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
666                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
667                 goto override_err;
668
669         if (sizeof(buf) <= count)
670                 goto override_err;
671
672         if (copy_from_user(buf, userbuf, count))
673                 goto override_err;
674
675         /* terminate buffer and trim - white spaces may be appended
676          *  at the end when invoked from shell command line */
677         buf[count]='\0';
678         strim(buf);
679
680         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
681         if (*end != '\0')
682                 goto override_err;
683
684         if (edp_reg_override_mA_temp >= regulator_cur)
685                 goto override_err;
686
687         if (edp_reg_override_mA == edp_reg_override_mA_temp)
688                 return count;
689
690         edp_reg_override_mA = edp_reg_override_mA_temp;
691         if (init_cpu_edp_limits_calculated()) {
692                 /* Revert to previous override value if new value fails */
693                 edp_reg_override_mA = edp_reg_override_mA_prev;
694                 goto override_err;
695         }
696
697 #ifdef CONFIG_CPU_FREQ
698         if (tegra_cpu_set_speed_cap(NULL)) {
699                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
700                 goto override_out;
701         }
702
703         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
704                         " %u mA\n", regulator_cur - edp_reg_override_mA);
705 #else
706         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
707 #endif
708
709         return count;
710
711 override_err:
712         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
713                buf);
714 #ifdef CONFIG_CPU_FREQ
715 override_out:
716 #endif
717         return -EINVAL;
718 }
719
720 static int edp_debugfs_open(struct inode *inode, struct file *file)
721 {
722         return single_open(file, edp_debugfs_show, inode->i_private);
723 }
724
725 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
726 {
727         return single_open(file, edp_limit_debugfs_show, inode->i_private);
728 }
729
730 static int edp_reg_override_open(struct inode *inode, struct file *file)
731 {
732         return single_open(file, edp_reg_override_show, inode->i_private);
733 }
734
735 static const struct file_operations edp_debugfs_fops = {
736         .open           = edp_debugfs_open,
737         .read           = seq_read,
738         .llseek         = seq_lseek,
739         .release        = single_release,
740 };
741
742 static const struct file_operations edp_limit_debugfs_fops = {
743         .open           = edp_limit_debugfs_open,
744         .read           = seq_read,
745         .llseek         = seq_lseek,
746         .release        = single_release,
747 };
748
749 static const struct file_operations edp_reg_override_debugfs_fops = {
750         .open           = edp_reg_override_open,
751         .read           = seq_read,
752         .write          = edp_reg_override_write,
753         .llseek         = seq_lseek,
754         .release        = single_release,
755 };
756
757 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
758 static __init struct dentry *tegra_edp_debugfs_dir(void)
759 {
760         if (edp_debugfs_dir)
761                 return edp_debugfs_dir;
762         else
763                 return debugfs_create_dir("edp", NULL);
764 }
765 #else
766 static __init struct dentry *tegra_edp_debugfs_dir(void)
767 {
768         return debugfs_create_dir("edp", NULL);
769 }
770 #endif
771
772 static int __init tegra_edp_debugfs_init(void)
773 {
774         struct dentry *d_edp;
775         struct dentry *d_edp_limit;
776         struct dentry *d_edp_reg_override;
777         struct dentry *edp_dir;
778         struct dentry *vdd_cpu_dir;
779
780         if (!tegra_platform_is_silicon())
781                 return -ENOSYS;
782
783         edp_dir = tegra_edp_debugfs_dir();
784
785         if (!edp_dir)
786                 goto edp_dir_err;
787
788         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
789
790         if (!vdd_cpu_dir)
791                 goto vdd_cpu_dir_err;
792
793         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
794                                 &edp_debugfs_fops);
795
796         if (!d_edp)
797                 goto edp_err;
798
799         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
800                                 NULL, &edp_limit_debugfs_fops);
801
802         if (!d_edp_limit)
803                 goto edp_limit_err;
804
805         d_edp_reg_override = debugfs_create_file("edp_reg_override",
806                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
807                                 &edp_reg_override_debugfs_fops);
808
809         if (!d_edp_reg_override)
810                 goto edp_reg_override_err;
811
812         if (tegra_core_edp_debugfs_init(edp_dir))
813                 goto edp_reg_override_err;
814
815         return 0;
816
817 edp_reg_override_err:
818         debugfs_remove(d_edp_limit);
819 edp_limit_err:
820         debugfs_remove(d_edp);
821 edp_err:
822         debugfs_remove(vdd_cpu_dir);
823 vdd_cpu_dir_err:
824         debugfs_remove(edp_dir);
825 edp_dir_err:
826         return -ENOMEM;
827 }
828
829 late_initcall(tegra_edp_debugfs_init);
830 #endif /* CONFIG_DEBUG_FS */