ARM: Tegra: Floor the calculated CPU leakage current
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26
27 #include <mach/edp.h>
28 #include <mach/hardware.h>
29
30 #include "fuse.h"
31 #include "dvfs.h"
32 #include "clock.h"
33 #include "cpu-tegra.h"
34
35 #define FREQ_STEP 12750000
36 #define OVERRIDE_DEFAULT 6000
37
38 static struct tegra_edp_limits *edp_limits;
39 static int edp_limits_size;
40 static unsigned int regulator_cur;
41 /* Value to subtract from regulator current limit */
42 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
43
44 static const unsigned int *system_edp_limits;
45
46 static struct tegra_system_edp_entry *power_edp_limits;
47 static int power_edp_limits_size;
48
49 /*
50  * "Safe entry" to be used when no match for speedo_id /
51  * regulator_cur is found; must be the last one
52  */
53 static struct tegra_edp_limits edp_default_limits[] = {
54         {85, {1000000, 1000000, 1000000, 1000000} },
55 };
56
57 static struct tegra_system_edp_entry power_edp_default_limits[] = {
58         {0, 20, {1000000, 1000000, 1000000, 1000000} },
59 };
60
61 /* Constants for EDP calculations */
62 static const int temperatures[] = { /* degree celcius (C) */
63         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
64 };
65
66 static const int power_cap_levels[] = { /* milliwatts (mW) */
67           500,  1000,  1500,  2000,  2500,  3000,  3500,
68          4000,  4500,  5000,  5500,  6000,  6500,  7000,
69          7500,  8000,  8500,  9000,  9500, 10000, 10500,
70         11000, 11500, 12000, 12500, 13000, 13500, 14000,
71         14500, 15000, 15500, 16000, 16500, 17000
72 };
73
74 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
75 static unsigned int freq_voltage_lut_size_saved;
76 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
77 static unsigned int freq_voltage_lut_size;
78
79 static inline s64 edp_pow(s64 val, int pwr)
80 {
81         s64 retval = 1;
82
83         while (val && pwr) {
84                 if (pwr & 1)
85                         retval *= val;
86                 pwr >>= 1;
87                 if (pwr)
88                         val *= val;
89         }
90
91         return retval;
92 }
93
94 /*
95  * Find the maximum frequency that results in dynamic and leakage current that
96  * is less than the regulator current limit.
97  * temp_C - valid or -EINVAL
98  * power_mW - valid or -1 (infinite) or -EINVAL
99  */
100 static unsigned int edp_calculate_maxf(
101                                 struct tegra_edp_cpu_leakage_params *params,
102                                 int temp_C, int power_mW,
103                                 int iddq_mA,
104                                 int n_cores_idx)
105 {
106         unsigned int voltage_mV, freq_KHz;
107         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
108         int f, i, j, k;
109         s64 leakage_mA, dyn_mA, leakage_calc_step;
110         s64 leakage_mW, dyn_mW;
111
112         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
113                 freq_KHz = freq_voltage_lut[f].freq / 1000;
114                 voltage_mV = freq_voltage_lut[f].voltage_mV;
115
116                 /* Constrain Volt-Temp */
117                 if (params->volt_temp_cap.temperature &&
118                     temp_C > params->volt_temp_cap.temperature &&
119                     params->volt_temp_cap.voltage_limit_mV &&
120                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
121                         continue;
122
123                 /* Calculate leakage current */
124                 leakage_mA = 0;
125                 for (i = 0; i <= 3; i++) {
126                         for (j = 0; j <= 3; j++) {
127                                 for (k = 0; k <= 3; k++) {
128                                         leakage_calc_step =
129                                                 params->leakage_consts_ijk
130                                                 [i][j][k] * edp_pow(iddq_mA, i);
131                                         /* Convert (mA)^i to (A)^i */
132                                         leakage_calc_step =
133                                                 div64_s64(leakage_calc_step,
134                                                           edp_pow(1000, i));
135                                         leakage_calc_step *=
136                                                 edp_pow(voltage_mV, j);
137                                         /* Convert (mV)^j to (V)^j */
138                                         leakage_calc_step =
139                                                 div64_s64(leakage_calc_step,
140                                                           edp_pow(1000, j));
141                                         leakage_calc_step *=
142                                                 edp_pow(temp_C, k);
143                                         /* Convert (C)^k to (scaled_C)^k */
144                                         leakage_calc_step =
145                                                 div64_s64(leakage_calc_step,
146                                                 edp_pow(params->temp_scaled,
147                                                         k));
148                                         /* leakage_consts_ijk was scaled */
149                                         leakage_calc_step =
150                                                 div64_s64(leakage_calc_step,
151                                                           params->ijk_scaled);
152                                         leakage_mA += leakage_calc_step;
153                                 }
154                         }
155                 }
156
157                 /* set floor for leakage current */
158                 if (leakage_mA <= params->leakage_min)
159                         leakage_mA = params->leakage_min;
160
161                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
162
163                 /* leakage_const_n was scaled */
164                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
165
166                 /* Calculate dynamic current */
167                 dyn_mA = voltage_mV * freq_KHz / 1000;
168                 /* Convert mV to V */
169                 dyn_mA = div64_s64(dyn_mA, 1000);
170                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
171                 /* dyn_const_n was scaled */
172                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
173
174                 if (power_mW != -1) {
175                         leakage_mW = leakage_mA * voltage_mV;
176                         dyn_mW = dyn_mA * voltage_mV;
177                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
178                                 return freq_KHz;
179                 } else if ((leakage_mA + dyn_mA) <= cur_effective) {
180                         return freq_KHz;
181                 }
182         }
183         return -EINVAL;
184 }
185
186 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
187                         unsigned int cpu_speedo_idx,
188                         unsigned int freq_volt_lut_size,
189                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
190 {
191         unsigned int i, j, freq;
192         int voltage_mV;
193
194         for (i = 0, j = 0, freq = 0;
195                  i < freq_volt_lut_size;
196                  i++, freq += FREQ_STEP) {
197
198                 /* Predict voltages */
199                 voltage_mV = tegra_dvfs_predict_millivolts(clk_cpu_g, freq);
200                 if (voltage_mV < 0) {
201                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
202                                __func__, freq, voltage_mV);
203                         return -EINVAL;
204                 }
205
206                 /* Cache frequency / voltage / voltage constant relationship */
207                 freq_volt_lut[i].freq = freq;
208                 freq_volt_lut[i].voltage_mV = voltage_mV;
209         }
210         return 0;
211 }
212
213 unsigned int tegra_edp_find_maxf(int volt)
214 {
215         unsigned int i;
216
217         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
218                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
219                         break;
220         }
221         return freq_voltage_lut[i - 1].freq;
222 }
223
224
225 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
226 {
227         int i, array_size;
228         struct tegra_edp_cpu_leakage_params *params;
229
230         switch (tegra_chip_id) {
231         case TEGRA_CHIPID_TEGRA11:
232                 params = tegra11x_get_leakage_params(0, &array_size);
233                 break;
234         case TEGRA_CHIPID_TEGRA14:
235                 params = tegra14x_get_leakage_params(0, &array_size);
236                 break;
237         case TEGRA_CHIPID_TEGRA3:
238         case TEGRA_CHIPID_TEGRA2:
239         default:
240                 array_size = 0;
241                 break;
242         }
243
244         for (i = 0; i < array_size; i++)
245                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
246                         *cpu_speedo_idx = i;
247                         return 0;
248                 }
249
250         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
251                __func__, cpu_speedo_id);
252         return -EINVAL;
253 }
254
255 static int init_cpu_edp_limits_calculated(void)
256 {
257         unsigned int max_nr_cpus = num_possible_cpus();
258         unsigned int temp_idx, n_cores_idx, pwr_idx;
259         unsigned int cpu_g_minf, cpu_g_maxf;
260         unsigned int iddq_mA;
261         unsigned int cpu_speedo_idx;
262         unsigned int cap, limit;
263         struct tegra_edp_limits *edp_calculated_limits;
264         struct tegra_system_edp_entry *power_edp_calc_limits;
265         struct tegra_edp_cpu_leakage_params *params;
266         int ret;
267         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
268         int cpu_speedo_id = tegra_cpu_speedo_id();
269
270         /* Determine all inputs to EDP formula */
271         iddq_mA = tegra_get_cpu_iddq_value();
272         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
273         if (ret)
274                 return ret;
275
276         switch (tegra_chip_id) {
277         case TEGRA_CHIPID_TEGRA11:
278                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
279                 break;
280         case TEGRA_CHIPID_TEGRA14:
281                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
282                 break;
283         case TEGRA_CHIPID_TEGRA3:
284         case TEGRA_CHIPID_TEGRA2:
285         default:
286                 return -EINVAL;
287         }
288
289         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
290                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
291         BUG_ON(!edp_calculated_limits);
292
293         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
294                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
295         BUG_ON(!power_edp_calc_limits);
296
297         cpu_g_minf = 0;
298         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
299         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
300         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
301                                    * freq_voltage_lut_size, GFP_KERNEL);
302         if (!freq_voltage_lut) {
303                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
304                 kfree(power_edp_calc_limits);
305                 kfree(edp_calculated_limits);
306                 return -ENOMEM;
307         }
308
309         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
310                                 freq_voltage_lut_size, freq_voltage_lut);
311         if (ret) {
312                 kfree(power_edp_calc_limits);
313                 kfree(edp_calculated_limits);
314                 kfree(freq_voltage_lut);
315                 return ret;
316         }
317
318         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
319                 /* release previous table if present */
320                 kfree(freq_voltage_lut_saved);
321                 /* create table to save */
322                 freq_voltage_lut_saved =
323                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
324                         freq_voltage_lut_size, GFP_KERNEL);
325                 if (!freq_voltage_lut_saved) {
326                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
327                                 __func__);
328                         kfree(freq_voltage_lut);
329                         return -ENOMEM;
330                 }
331                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
332         }
333         memcpy(freq_voltage_lut_saved,
334                 freq_voltage_lut,
335                 sizeof(struct tegra_edp_freq_voltage_table) *
336                         freq_voltage_lut_size);
337
338         /* Calculate EDP table */
339         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
340                 for (temp_idx = 0;
341                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
342                         edp_calculated_limits[temp_idx].temperature =
343                                 temperatures[temp_idx];
344                         limit = edp_calculate_maxf(params,
345                                                    temperatures[temp_idx],
346                                                    -1,
347                                                    iddq_mA,
348                                                    n_cores_idx);
349                         if (limit == -EINVAL)
350                                 return -EINVAL;
351                         /* apply safety cap if it is specified */
352                         if (n_cores_idx < 4) {
353                                 cap = params->safety_cap[n_cores_idx];
354                                 if (cap && cap < limit)
355                                         limit = cap;
356                         }
357                         edp_calculated_limits[temp_idx].
358                                 freq_limits[n_cores_idx] = limit;
359                 }
360
361                 for (pwr_idx = 0;
362                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
363                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
364                                 power_cap_levels[pwr_idx] / 100;
365                         limit = edp_calculate_maxf(params,
366                                                    90,
367                                                    power_cap_levels[pwr_idx],
368                                                    iddq_mA,
369                                                    n_cores_idx);
370                         if (limit == -EINVAL)
371                                 return -EINVAL;
372                         power_edp_calc_limits[pwr_idx].
373                                 freq_limits[n_cores_idx] = limit;
374                 }
375         }
376
377         /*
378          * If this is an EDP table update, need to overwrite old table.
379          * The old table's address must remain valid.
380          */
381         if (edp_limits != edp_default_limits) {
382                 memcpy(edp_limits, edp_calculated_limits,
383                        sizeof(struct tegra_edp_limits)
384                        * ARRAY_SIZE(temperatures));
385                 kfree(edp_calculated_limits);
386         }
387         else {
388                 edp_limits = edp_calculated_limits;
389                 edp_limits_size = ARRAY_SIZE(temperatures);
390         }
391
392         if (power_edp_limits != power_edp_default_limits) {
393                 memcpy(power_edp_limits, power_edp_calc_limits,
394                        sizeof(struct tegra_system_edp_entry)
395                        * ARRAY_SIZE(power_cap_levels));
396                 kfree(power_edp_calc_limits);
397         } else {
398                 power_edp_limits = power_edp_calc_limits;
399                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
400         }
401
402         kfree(freq_voltage_lut);
403         return 0;
404 }
405
406 void tegra_recalculate_cpu_edp_limits(void)
407 {
408         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
409             tegra_chip_id != TEGRA_CHIPID_TEGRA14)
410                 return;
411
412         if (init_cpu_edp_limits_calculated() == 0)
413                 return;
414
415         /* Revert to default EDP table on error */
416         edp_limits = edp_default_limits;
417         edp_limits_size = ARRAY_SIZE(edp_default_limits);
418
419         power_edp_limits = power_edp_default_limits;
420         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
421 }
422
423 /*
424  * Specify regulator current in mA, e.g. 5000mA
425  * Use 0 for default
426  */
427 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
428 {
429         if (!regulator_mA)
430                 goto end;
431         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
432
433         switch (tegra_chip_id) {
434         case TEGRA_CHIPID_TEGRA11:
435         case TEGRA_CHIPID_TEGRA14:
436                 if (init_cpu_edp_limits_calculated() == 0)
437                         return;
438                 break;
439         case TEGRA_CHIPID_TEGRA2:
440         case TEGRA_CHIPID_TEGRA3:
441         default:
442                 BUG();
443                 break;
444         }
445
446  end:
447         edp_limits = edp_default_limits;
448         edp_limits_size = ARRAY_SIZE(edp_default_limits);
449
450         power_edp_limits = power_edp_default_limits;
451         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
452 }
453
454 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
455 {
456         *limits = edp_limits;
457         *size = edp_limits_size;
458 }
459
460 void tegra_get_system_edp_limits(const unsigned int **limits)
461 {
462         *limits = system_edp_limits;
463 }
464
465 void tegra_platform_edp_init(struct thermal_trip_info *trips,
466                                 int *num_trips, int margin)
467 {
468         const struct tegra_edp_limits *cpu_edp_limits;
469         struct thermal_trip_info *trip_state;
470         int i, cpu_edp_limits_size;
471
472         if (!trips || !num_trips)
473                 return;
474
475         /* edp capping */
476         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
477
478         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
479                 BUG();
480
481         for (i = 0; i < cpu_edp_limits_size-1; i++) {
482                 trip_state = &trips[*num_trips];
483
484                 trip_state->cdev_type = "cpu_edp";
485                 trip_state->trip_temp =
486                         (cpu_edp_limits[i].temperature * 1000) - margin;
487                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
488                 trip_state->upper = trip_state->lower = i + 1;
489
490                 (*num_trips)++;
491
492                 if (*num_trips >= THERMAL_MAX_TRIPS)
493                         BUG();
494         }
495 }
496
497 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
498 {
499         *size = power_edp_limits_size;
500         return power_edp_limits;
501 }
502
503 #ifdef CONFIG_DEBUG_FS
504
505 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
506 {
507 #ifdef CONFIG_CPU_FREQ
508         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
509 #endif
510         return 0;
511 }
512
513 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
514 {
515         int i;
516
517         seq_printf(s, "%6s %10s %10s %10s %10s\n",
518                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
519         for (i = 0; i < edp_limits_size; i++) {
520                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
521                            i == th_idx ? '>' : ' ',
522                            edp_limits[i].temperature,
523                            edp_limits[i].freq_limits[0],
524                            edp_limits[i].freq_limits[1],
525                            edp_limits[i].freq_limits[2],
526                            edp_limits[i].freq_limits[3]);
527         }
528 }
529
530 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
531 {
532         int i;
533
534         seq_printf(s, "%6s %10s %10s\n",
535                    " Temp.", "1-core", "2-cores");
536         for (i = 0; i < edp_limits_size; i++) {
537                 seq_printf(s, "%c%3dC: %10u %10u\n",
538                            i == th_idx ? '>' : ' ',
539                            edp_limits[i].temperature,
540                            edp_limits[i].freq_limits[0],
541                            edp_limits[i].freq_limits[1]);
542         }
543 }
544
545 static inline void edp_show_2core_system_table(struct seq_file *s)
546 {
547         seq_printf(s, "%10u %10u\n",
548                    system_edp_limits[0],
549                    system_edp_limits[1]);
550 }
551
552 static inline void edp_show_4core_system_table(struct seq_file *s)
553 {
554         seq_printf(s, "%10u %10u %10u %10u\n",
555                    system_edp_limits[0],
556                    system_edp_limits[1],
557                    system_edp_limits[2],
558                    system_edp_limits[3]);
559 }
560
561 static int edp_debugfs_show(struct seq_file *s, void *data)
562 {
563         unsigned int max_nr_cpus = num_possible_cpus();
564         int th_idx;
565
566         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
567                 seq_printf(s, "Unsupported number of CPUs\n");
568                 return 0;
569         }
570
571 #ifdef CONFIG_CPU_FREQ
572         tegra_get_edp_limit(&th_idx);
573 #else
574         th_idx = 0;
575 #endif
576
577         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
578                    edp_limits == edp_default_limits ? "**default** " : "",
579                    regulator_cur - edp_reg_override_mA,
580                    regulator_cur, edp_reg_override_mA);
581
582         if (max_nr_cpus == 2)
583                 edp_show_2core_edp_table(s, th_idx);
584         else if (max_nr_cpus == 4)
585                 edp_show_4core_edp_table(s, th_idx);
586
587         if (system_edp_limits) {
588                 seq_printf(s, "\n-- System EDP table --\n");
589                 if (max_nr_cpus == 2)
590                         edp_show_2core_system_table(s);
591                 else if (max_nr_cpus == 4)
592                         edp_show_4core_system_table(s);
593         }
594
595         return 0;
596 }
597
598 static int edp_reg_override_show(struct seq_file *s, void *data)
599 {
600         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
601                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
602         return 0;
603 }
604
605 static int edp_reg_override_write(struct file *file,
606         const char __user *userbuf, size_t count, loff_t *ppos)
607 {
608         char buf[32], *end;
609         unsigned int edp_reg_override_mA_temp;
610         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
611
612         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
613                 tegra_chip_id == TEGRA_CHIPID_TEGRA14))
614                 goto override_err;
615
616         if (sizeof(buf) <= count)
617                 goto override_err;
618
619         if (copy_from_user(buf, userbuf, count))
620                 goto override_err;
621
622         /* terminate buffer and trim - white spaces may be appended
623          *  at the end when invoked from shell command line */
624         buf[count]='\0';
625         strim(buf);
626
627         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
628         if (*end != '\0')
629                 goto override_err;
630
631         if (edp_reg_override_mA_temp >= regulator_cur)
632                 goto override_err;
633
634         if (edp_reg_override_mA == edp_reg_override_mA_temp)
635                 return count;
636
637         edp_reg_override_mA = edp_reg_override_mA_temp;
638         if (init_cpu_edp_limits_calculated()) {
639                 /* Revert to previous override value if new value fails */
640                 edp_reg_override_mA = edp_reg_override_mA_prev;
641                 goto override_err;
642         }
643
644 #ifdef CONFIG_CPU_FREQ
645         if (tegra_cpu_set_speed_cap(NULL)) {
646                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
647                 goto override_out;
648         }
649
650         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
651                         " %u mA\n", regulator_cur - edp_reg_override_mA);
652 #else
653         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
654 #endif
655
656         return count;
657
658 override_err:
659         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
660                buf);
661 #ifdef CONFIG_CPU_FREQ
662 override_out:
663 #endif
664         return -EINVAL;
665 }
666
667 static int edp_debugfs_open(struct inode *inode, struct file *file)
668 {
669         return single_open(file, edp_debugfs_show, inode->i_private);
670 }
671
672 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
673 {
674         return single_open(file, edp_limit_debugfs_show, inode->i_private);
675 }
676
677 static int edp_reg_override_open(struct inode *inode, struct file *file)
678 {
679         return single_open(file, edp_reg_override_show, inode->i_private);
680 }
681
682 static const struct file_operations edp_debugfs_fops = {
683         .open           = edp_debugfs_open,
684         .read           = seq_read,
685         .llseek         = seq_lseek,
686         .release        = single_release,
687 };
688
689 static const struct file_operations edp_limit_debugfs_fops = {
690         .open           = edp_limit_debugfs_open,
691         .read           = seq_read,
692         .llseek         = seq_lseek,
693         .release        = single_release,
694 };
695
696 static const struct file_operations edp_reg_override_debugfs_fops = {
697         .open           = edp_reg_override_open,
698         .read           = seq_read,
699         .write          = edp_reg_override_write,
700         .llseek         = seq_lseek,
701         .release        = single_release,
702 };
703
704 #ifdef CONFIG_EDP_FRAMEWORK
705 static __init struct dentry *tegra_edp_debugfs_dir(void)
706 {
707         return edp_debugfs_dir;
708 }
709 #else
710 static __init struct dentry *tegra_edp_debugfs_dir(void)
711 {
712         return debugfs_create_dir("edp", NULL);
713 }
714 #endif
715
716 static int __init tegra_edp_debugfs_init(void)
717 {
718         struct dentry *d_edp;
719         struct dentry *d_edp_limit;
720         struct dentry *d_edp_reg_override;
721         struct dentry *edp_dir;
722         struct dentry *vdd_cpu_dir;
723
724         edp_dir = tegra_edp_debugfs_dir();
725
726         if (!edp_dir)
727                 goto edp_dir_err;
728
729         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
730
731         if (!vdd_cpu_dir)
732                 goto vdd_cpu_dir_err;
733
734         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
735                                 &edp_debugfs_fops);
736
737         if (!d_edp)
738                 goto edp_err;
739
740         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
741                                 NULL, &edp_limit_debugfs_fops);
742
743         if (!d_edp_limit)
744                 goto edp_limit_err;
745
746         d_edp_reg_override = debugfs_create_file("edp_reg_override",
747                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
748                                 &edp_reg_override_debugfs_fops);
749
750         if (!d_edp_reg_override)
751                 goto edp_reg_override_err;
752
753         if (tegra_core_edp_debugfs_init(edp_dir))
754                 goto edp_reg_override_err;
755
756         return 0;
757
758 edp_reg_override_err:
759         debugfs_remove(d_edp_limit);
760 edp_limit_err:
761         debugfs_remove(d_edp);
762 edp_err:
763         debugfs_remove(vdd_cpu_dir);
764 vdd_cpu_dir_err:
765         debugfs_remove(edp_dir);
766 edp_dir_err:
767         return -ENOMEM;
768 }
769
770 late_initcall(tegra_edp_debugfs_init);
771 #endif /* CONFIG_DEBUG_FS */