ARM: tegra: edp: Fix resource leak
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/tegra-fuse.h>
30
31 #include <mach/edp.h>
32
33 #include "dvfs.h"
34 #include "clock.h"
35 #include "cpu-tegra.h"
36 #include "common.h"
37
38 #define FREQ_STEP 12750000
39 #define OVERRIDE_DEFAULT 6000
40
41 #define GPU_FREQ_STEP 12000000
42
43 static struct tegra_edp_limits *edp_limits;
44 static int edp_limits_size;
45 static unsigned int regulator_cur;
46 /* Value to subtract from regulator current limit */
47 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
48
49 static struct tegra_edp_limits *reg_idle_edp_limits;
50 static int reg_idle_cur;
51
52 static const unsigned int *system_edp_limits;
53
54 static struct tegra_system_edp_entry *power_edp_limits;
55 static int power_edp_limits_size;
56
57 /*
58  * "Safe entry" to be used when no match for speedo_id /
59  * regulator_cur is found; must be the last one
60  */
61 static struct tegra_edp_limits edp_default_limits[] = {
62         {85, {1000000, 1000000, 1000000, 1000000} },
63 };
64
65 static struct tegra_system_edp_entry power_edp_default_limits[] = {
66         {0, 20, {1000000, 1000000, 1000000, 1000000} },
67 };
68
69 /* Constants for EDP calculations */
70 static const int temperatures[] = { /* degree celcius (C) */
71         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
72 };
73
74 static const int power_cap_levels[] = { /* milliwatts (mW) */
75           500,  1000,  1500,  2000,  2500,  3000,  3500,
76          4000,  4500,  5000,  5500,  6000,  6500,  7000,
77          7500,  8000,  8500,  9000,  9500, 10000, 10500,
78         11000, 11500, 12000, 12500, 13000, 13500, 14000,
79         14500, 15000, 15500, 16000, 16500, 17000
80 };
81
82 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
83 static unsigned int freq_voltage_lut_size_saved;
84 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
85 static unsigned int freq_voltage_lut_size;
86
87 #ifdef CONFIG_TEGRA_GPU_EDP
88 static struct tegra_edp_gpu_limits *edp_gpu_limits;
89 static int edp_gpu_limits_size;
90 static int edp_gpu_thermal_idx;
91 static struct clk *gpu_cap_clk;
92 static DEFINE_MUTEX(gpu_edp_lock);
93
94 static struct tegra_edp_freq_voltage_table *freq_voltage_gpu_lut;
95 static unsigned int freq_voltage_gpu_lut_size;
96
97 static unsigned int gpu_regulator_cur;
98
99 static struct tegra_edp_gpu_limits edp_gpu_default_limits[] = {
100         {85, 350000},
101 };
102
103 static const int gpu_temperatures[] = { /* degree celcius (C) */
104         20, 50, 70, 75, 80, 85, 90, 95, 100, 105,
105 };
106 #endif
107
108 static inline s64 edp_pow(s64 val, int pwr)
109 {
110         s64 retval = 1;
111
112         while (val && pwr) {
113                 if (pwr & 1)
114                         retval *= val;
115                 pwr >>= 1;
116                 if (pwr)
117                         val *= val;
118         }
119
120         return retval;
121 }
122
123
124 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
125 static inline unsigned int edp_apply_fixed_limits(
126                                 unsigned int in_freq_KHz,
127                                 struct tegra_edp_cpu_leakage_params *params,
128                                 unsigned int cur_effective,
129                                 int temp_C, int n_cores_idx)
130 {
131         unsigned int out_freq_KHz = in_freq_KHz;
132         unsigned int max_cur, max_temp, max_freq;
133         int i;
134
135         /* Apply any additional fixed limits */
136         for (i = 0; i < 8; i++) {
137                 max_cur = params->max_current_cap[i].max_cur;
138                 if (max_cur != 0 && cur_effective <= max_cur) {
139                         max_temp = params->max_current_cap[i].max_temp;
140                         if (max_temp != 0 && temp_C > max_temp) {
141                                 max_freq = params->max_current_cap[i].
142                                         max_freq[n_cores_idx];
143                                 if (max_freq && max_freq < out_freq_KHz)
144                                         out_freq_KHz = max_freq;
145                         }
146                 }
147         }
148
149         return out_freq_KHz;
150 }
151 #else
152 #define edp_apply_fixed_limits(freq, unused...) (freq)
153 #endif
154
155 /*
156  * Find the maximum frequency that results in dynamic and leakage current that
157  * is less than the regulator current limit.
158  * temp_C - valid or -EINVAL
159  * power_mW - valid or -1 (infinite) or -EINVAL
160  */
161 static unsigned int edp_calculate_maxf(
162                                 struct tegra_edp_cpu_leakage_params *params,
163                                 int temp_C, int power_mW, unsigned int cur_mA,
164                                 int iddq_mA,
165                                 int n_cores_idx)
166 {
167         unsigned int voltage_mV, freq_KHz = 0;
168         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
169         int f, i, j, k;
170         s64 leakage_mA, dyn_mA, leakage_calc_step;
171         s64 leakage_mW, dyn_mW;
172
173         /* If current limit is not specified, use max by default */
174         cur_mA = cur_mA ? : cur_effective;
175
176         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
177                 freq_KHz = freq_voltage_lut[f].freq / 1000;
178                 voltage_mV = freq_voltage_lut[f].voltage_mV;
179
180                 /* Constrain Volt-Temp */
181                 if (params->volt_temp_cap.temperature &&
182                     temp_C > params->volt_temp_cap.temperature &&
183                     params->volt_temp_cap.voltage_limit_mV &&
184                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
185                         continue;
186
187                 /* Calculate leakage current */
188                 leakage_mA = 0;
189                 for (i = 0; i <= 3; i++) {
190                         for (j = 0; j <= 3; j++) {
191                                 for (k = 0; k <= 3; k++) {
192                                         leakage_calc_step =
193                                                 params->leakage_consts_ijk
194                                                 [i][j][k] * edp_pow(iddq_mA, i);
195                                         /* Convert (mA)^i to (A)^i */
196                                         leakage_calc_step =
197                                                 div64_s64(leakage_calc_step,
198                                                           edp_pow(1000, i));
199                                         leakage_calc_step *=
200                                                 edp_pow(voltage_mV, j);
201                                         /* Convert (mV)^j to (V)^j */
202                                         leakage_calc_step =
203                                                 div64_s64(leakage_calc_step,
204                                                           edp_pow(1000, j));
205                                         leakage_calc_step *=
206                                                 edp_pow(temp_C, k);
207                                         /* Convert (C)^k to (scaled_C)^k */
208                                         leakage_calc_step =
209                                                 div64_s64(leakage_calc_step,
210                                                 edp_pow(params->temp_scaled,
211                                                         k));
212                                         /* leakage_consts_ijk was scaled */
213                                         leakage_calc_step =
214                                                 div64_s64(leakage_calc_step,
215                                                           params->ijk_scaled);
216                                         leakage_mA += leakage_calc_step;
217                                 }
218                         }
219                 }
220
221                 /* set floor for leakage current */
222                 if (leakage_mA <= params->leakage_min)
223                         leakage_mA = params->leakage_min;
224
225                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
226
227                 /* leakage_const_n was scaled */
228                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
229
230                 /* Calculate dynamic current */
231                 dyn_mA = voltage_mV * freq_KHz / 1000;
232                 /* Convert mV to V */
233                 dyn_mA = div64_s64(dyn_mA, 1000);
234                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
235                 /* dyn_const_n was scaled */
236                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
237
238                 if (power_mW != -1) {
239                         leakage_mW = leakage_mA * voltage_mV;
240                         dyn_mW = dyn_mA * voltage_mV;
241                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
242                                 goto end;
243                 } else if ((leakage_mA + dyn_mA) <= cur_mA) {
244                         goto end;
245                 }
246                 freq_KHz = 0;
247         }
248
249  end:
250         return edp_apply_fixed_limits(freq_KHz, params,
251                                         cur_effective, temp_C, n_cores_idx);
252 }
253
254 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
255                         unsigned int cpu_speedo_idx,
256                         unsigned int freq_volt_lut_size,
257                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
258 {
259         unsigned int i, j, freq;
260         int voltage_mV;
261
262         for (i = 0, j = 0, freq = 0;
263                  i < freq_volt_lut_size;
264                  i++, freq += FREQ_STEP) {
265
266                 /* Predict voltages */
267                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
268                         clk_cpu_g, freq);
269                 if (voltage_mV < 0) {
270                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
271                                __func__, freq, voltage_mV);
272                         return -EINVAL;
273                 }
274
275                 /* Cache frequency / voltage / voltage constant relationship */
276                 freq_volt_lut[i].freq = freq;
277                 freq_volt_lut[i].voltage_mV = voltage_mV;
278         }
279         return 0;
280 }
281
282 /*
283  * Finds the maximum frequency whose corresponding voltage is <= volt
284  * If no such frequency is found, the least possible frequency is returned
285  */
286 unsigned int tegra_edp_find_maxf(int volt)
287 {
288         unsigned int i;
289
290         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
291                 if (freq_voltage_lut_saved[i].voltage_mV > volt) {
292                         if (!i)
293                                 return freq_voltage_lut_saved[i].freq;
294                         break;
295                 }
296         }
297         return freq_voltage_lut_saved[i - 1].freq;
298 }
299
300
301 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
302 {
303         int i, array_size;
304         struct tegra_edp_cpu_leakage_params *params;
305
306         switch (tegra_get_chip_id()) {
307         case TEGRA_CHIPID_TEGRA11:
308                 params = tegra11x_get_leakage_params(0, &array_size);
309                 break;
310         case TEGRA_CHIPID_TEGRA14:
311                 params = tegra14x_get_leakage_params(0, &array_size);
312                 break;
313         case TEGRA_CHIPID_TEGRA12:
314                 params = tegra12x_get_leakage_params(0, &array_size);
315                 break;
316         case TEGRA_CHIPID_TEGRA3:
317         case TEGRA_CHIPID_TEGRA2:
318         default:
319                 array_size = 0;
320                 break;
321         }
322
323         for (i = 0; i < array_size; i++)
324                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
325                         *cpu_speedo_idx = i;
326                         return 0;
327                 }
328
329         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
330                __func__, cpu_speedo_id);
331         return -EINVAL;
332 }
333
334 static int init_cpu_edp_limits_calculated(void)
335 {
336         unsigned int max_nr_cpus = num_possible_cpus();
337         unsigned int temp_idx, n_cores_idx, pwr_idx;
338         unsigned int cpu_g_minf, cpu_g_maxf;
339         unsigned int iddq_mA;
340         unsigned int cpu_speedo_idx;
341         unsigned int cap, limit;
342         struct tegra_edp_limits *edp_calculated_limits;
343         struct tegra_edp_limits *reg_idle_calc_limits;
344         struct tegra_system_edp_entry *power_edp_calc_limits;
345         struct tegra_edp_cpu_leakage_params *params;
346         int ret;
347         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
348         int cpu_speedo_id = tegra_cpu_speedo_id();
349         int idle_cur = reg_idle_cur;
350
351         /* Determine all inputs to EDP formula */
352         iddq_mA = tegra_get_cpu_iddq_value();
353         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
354         if (ret)
355                 return ret;
356
357         switch (tegra_get_chip_id()) {
358         case TEGRA_CHIPID_TEGRA11:
359                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
360                 break;
361         case TEGRA_CHIPID_TEGRA14:
362                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
363                 break;
364         case TEGRA_CHIPID_TEGRA12:
365                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
366                 break;
367         case TEGRA_CHIPID_TEGRA3:
368         case TEGRA_CHIPID_TEGRA2:
369         default:
370                 return -EINVAL;
371         }
372
373         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
374                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
375         BUG_ON(!edp_calculated_limits);
376
377         reg_idle_calc_limits = kmalloc(sizeof(struct tegra_edp_limits)
378                                        * ARRAY_SIZE(temperatures), GFP_KERNEL);
379         BUG_ON(!reg_idle_calc_limits);
380
381         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
382                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
383         BUG_ON(!power_edp_calc_limits);
384
385         cpu_g_minf = 0;
386         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
387         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
388         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
389                                    * freq_voltage_lut_size, GFP_KERNEL);
390         if (!freq_voltage_lut) {
391                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
392                 kfree(power_edp_calc_limits);
393                 kfree(reg_idle_calc_limits);
394                 kfree(edp_calculated_limits);
395                 return -ENOMEM;
396         }
397
398         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
399                                 freq_voltage_lut_size, freq_voltage_lut);
400         if (ret) {
401                 kfree(power_edp_calc_limits);
402                 kfree(reg_idle_calc_limits);
403                 kfree(edp_calculated_limits);
404                 kfree(freq_voltage_lut);
405                 return ret;
406         }
407
408         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
409                 /* release previous table if present */
410                 kfree(freq_voltage_lut_saved);
411                 /* create table to save */
412                 freq_voltage_lut_saved =
413                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
414                         freq_voltage_lut_size, GFP_KERNEL);
415                 if (!freq_voltage_lut_saved) {
416                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
417                                 __func__);
418                         kfree(freq_voltage_lut);
419                         kfree(edp_calculated_limits);
420                         kfree(reg_idle_calc_limits);
421                         kfree(power_edp_calc_limits);
422                         return -ENOMEM;
423                 }
424                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
425         }
426         memcpy(freq_voltage_lut_saved,
427                 freq_voltage_lut,
428                 sizeof(struct tegra_edp_freq_voltage_table) *
429                         freq_voltage_lut_size);
430
431         /* Calculate EDP table */
432         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
433                 for (temp_idx = 0;
434                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
435                         edp_calculated_limits[temp_idx].temperature =
436                                 temperatures[temp_idx];
437                         limit = edp_calculate_maxf(params,
438                                                    temperatures[temp_idx],
439                                                    -1,
440                                                    0,
441                                                    iddq_mA,
442                                                    n_cores_idx);
443                         if (limit == -EINVAL)
444                                 return -EINVAL;
445                         /* apply safety cap if it is specified */
446                         if (n_cores_idx < 4) {
447                                 cap = params->safety_cap[n_cores_idx];
448                                 if (cap && cap < limit)
449                                         limit = cap;
450                         }
451                         edp_calculated_limits[temp_idx].
452                                 freq_limits[n_cores_idx] = limit;
453
454                         /* regulator mode threshold */
455                         if (!idle_cur)
456                                 continue;
457                         reg_idle_calc_limits[temp_idx].temperature =
458                                 temperatures[temp_idx];
459                         limit = edp_calculate_maxf(params,
460                                                    temperatures[temp_idx],
461                                                    -1,
462                                                    idle_cur,
463                                                    iddq_mA,
464                                                    n_cores_idx);
465
466                         /* remove idle table if any threshold is invalid */
467                         if (limit == -EINVAL) {
468                                 pr_warn("%s: Invalid idle limit for %dmA\n",
469                                         __func__, idle_cur);
470                                 idle_cur = 0;
471                                 continue;
472                         }
473
474                         /* No mode change below G CPU minimum rate */
475                         if (limit < clk_get_min_rate(clk_cpu_g) / 1000)
476                                 limit = 0;
477                         reg_idle_calc_limits[temp_idx].
478                                 freq_limits[n_cores_idx] = limit;
479                 }
480
481                 for (pwr_idx = 0;
482                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
483                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
484                                 power_cap_levels[pwr_idx] / 100;
485                         limit = edp_calculate_maxf(params,
486                                                    50,
487                                                    power_cap_levels[pwr_idx],
488                                                    0,
489                                                    iddq_mA,
490                                                    n_cores_idx);
491                         if (limit == -EINVAL)
492                                 return -EINVAL;
493                         power_edp_calc_limits[pwr_idx].
494                                 freq_limits[n_cores_idx] = limit;
495                 }
496         }
497
498         /*
499          * If this is an EDP table update, need to overwrite old table.
500          * The old table's address must remain valid.
501          */
502         if (edp_limits != edp_default_limits) {
503                 memcpy(edp_limits, edp_calculated_limits,
504                        sizeof(struct tegra_edp_limits)
505                        * ARRAY_SIZE(temperatures));
506                 kfree(edp_calculated_limits);
507         } else {
508                 edp_limits = edp_calculated_limits;
509                 edp_limits_size = ARRAY_SIZE(temperatures);
510         }
511
512         if (idle_cur && reg_idle_edp_limits) {
513                 memcpy(reg_idle_edp_limits, reg_idle_calc_limits,
514                        sizeof(struct tegra_edp_limits)
515                        * ARRAY_SIZE(temperatures));
516                 kfree(reg_idle_calc_limits);
517         } else if (idle_cur) {
518                 reg_idle_edp_limits = reg_idle_calc_limits;
519         } else {
520                 kfree(reg_idle_edp_limits);
521                 kfree(reg_idle_calc_limits);
522                 reg_idle_edp_limits = NULL;
523         }
524
525         if (power_edp_limits != power_edp_default_limits) {
526                 memcpy(power_edp_limits, power_edp_calc_limits,
527                        sizeof(struct tegra_system_edp_entry)
528                        * ARRAY_SIZE(power_cap_levels));
529                 kfree(power_edp_calc_limits);
530         } else {
531                 power_edp_limits = power_edp_calc_limits;
532                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
533         }
534
535         kfree(freq_voltage_lut);
536         return 0;
537 }
538
539 void tegra_recalculate_cpu_edp_limits(void)
540 {
541         u32 tegra_chip_id;
542
543         tegra_chip_id = tegra_get_chip_id();
544         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
545             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
546             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
547                 return;
548
549         if (init_cpu_edp_limits_calculated() == 0)
550                 return;
551
552         /* Revert to default EDP table on error */
553         edp_limits = edp_default_limits;
554         edp_limits_size = ARRAY_SIZE(edp_default_limits);
555
556         power_edp_limits = power_edp_default_limits;
557         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
558
559         kfree(reg_idle_edp_limits);
560         reg_idle_edp_limits = NULL;
561         pr_err("%s: Failed to recalculate EDP limits\n", __func__);
562 }
563
564 /*
565  * Specify regulator current in mA, e.g. 5000mA
566  * Use 0 for default
567  */
568 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
569 {
570         if (!regulator_mA)
571                 goto end;
572         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
573
574         switch (tegra_get_chip_id()) {
575         case TEGRA_CHIPID_TEGRA11:
576         case TEGRA_CHIPID_TEGRA14:
577         case TEGRA_CHIPID_TEGRA12:
578                 if (init_cpu_edp_limits_calculated() == 0)
579                         return;
580                 break;
581         case TEGRA_CHIPID_TEGRA2:
582         case TEGRA_CHIPID_TEGRA3:
583         default:
584                 BUG();
585                 break;
586         }
587
588  end:
589         edp_limits = edp_default_limits;
590         edp_limits_size = ARRAY_SIZE(edp_default_limits);
591
592         power_edp_limits = power_edp_default_limits;
593         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
594 }
595
596 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
597 {
598         *limits = edp_limits;
599         *size = edp_limits_size;
600 }
601
602 void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
603                                            unsigned int mode)
604 {
605         if (mode == REGULATOR_MODE_IDLE) {
606                 reg_idle_cur = regulator_mA;
607                 return;
608         }
609         pr_err("%s: Not supported regulator mode 0x%x\n", __func__, mode);
610 }
611
612 void tegra_get_cpu_reg_mode_limits(const struct tegra_edp_limits **limits,
613                                    int *size, unsigned int mode)
614 {
615         if (mode == REGULATOR_MODE_IDLE) {
616                 *limits = reg_idle_edp_limits;
617                 *size = edp_limits_size;
618         } else {
619                 *limits = NULL;
620                 *size = 0;
621         }
622 }
623
624 void tegra_get_system_edp_limits(const unsigned int **limits)
625 {
626         *limits = system_edp_limits;
627 }
628
629 void tegra_platform_edp_init(struct thermal_trip_info *trips,
630                                 int *num_trips, int margin)
631 {
632         const struct tegra_edp_limits *cpu_edp_limits;
633         struct thermal_trip_info *trip_state;
634         int i, cpu_edp_limits_size;
635
636         if (!trips || !num_trips)
637                 return;
638
639         /* edp capping */
640         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
641
642         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
643                 BUG();
644
645         for (i = 0; i < cpu_edp_limits_size-1; i++) {
646                 trip_state = &trips[*num_trips];
647
648                 trip_state->cdev_type = "cpu_edp";
649                 trip_state->trip_temp =
650                         (cpu_edp_limits[i].temperature * 1000) - margin;
651                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
652                 trip_state->upper = trip_state->lower = i + 1;
653
654                 (*num_trips)++;
655
656                 if (*num_trips >= THERMAL_MAX_TRIPS)
657                         BUG();
658         }
659 }
660
661 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
662 {
663         *size = power_edp_limits_size;
664         return power_edp_limits;
665 }
666
667
668 #ifdef CONFIG_TEGRA_GPU_EDP
669 void tegra_get_gpu_edp_limits(const struct tegra_edp_gpu_limits **limits,
670                                                         int *size)
671 {
672         *limits = edp_gpu_limits;
673         *size = edp_gpu_limits_size;
674 }
675
676 void tegra_platform_gpu_edp_init(struct thermal_trip_info *trips,
677                                 int *num_trips, int margin)
678 {
679         const struct tegra_edp_gpu_limits *gpu_edp_limits;
680         struct thermal_trip_info *trip_state;
681         int i, gpu_edp_limits_size;
682
683         if (!trips || !num_trips)
684                 return;
685
686         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
687
688         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
689                 BUG();
690
691         for (i = 0; i < gpu_edp_limits_size-1; i++) {
692                 trip_state = &trips[*num_trips];
693
694                 trip_state->cdev_type = "gpu_edp";
695                 trip_state->trip_temp =
696                         (gpu_edp_limits[i].temperature * 1000) - margin;
697                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
698                 trip_state->upper = trip_state->lower = i + 1;
699
700                 (*num_trips)++;
701
702                 if (*num_trips >= THERMAL_MAX_TRIPS)
703                         BUG();
704         }
705 }
706
707 static unsigned int edp_gpu_calculate_maxf(
708                                 struct tegra_edp_gpu_leakage_params *params,
709                                 int temp_C, int iddq_mA)
710 {
711         unsigned int voltage_mV, freq_KHz = 0;
712         unsigned int cur_effective = gpu_regulator_cur;
713         int f, i, j, k;
714         s64 leakage_mA, dyn_mA, leakage_calc_step;
715
716         for (f = freq_voltage_gpu_lut_size - 1; f >= 0; f--) {
717                 freq_KHz = freq_voltage_gpu_lut[f].freq / 1000;
718                 voltage_mV = freq_voltage_gpu_lut[f].voltage_mV;
719
720                 /* Calculate leakage current */
721                 leakage_mA = 0;
722                 for (i = 0; i <= 3; i++) {
723                         for (j = 0; j <= 3; j++) {
724                                 for (k = 0; k <= 3; k++) {
725                                         leakage_calc_step =
726                                                 params->leakage_consts_ijk
727                                                 [i][j][k] * edp_pow(iddq_mA, i);
728
729                                         /* Convert (mA)^i to (A)^i */
730                                         leakage_calc_step =
731                                                 div64_s64(leakage_calc_step,
732                                                           edp_pow(1000, i));
733                                         leakage_calc_step *=
734                                                 edp_pow(voltage_mV, j);
735
736                                         /* Convert (mV)^j to (V)^j */
737                                         leakage_calc_step =
738                                                 div64_s64(leakage_calc_step,
739                                                           edp_pow(1000, j));
740                                         leakage_calc_step *=
741                                                 edp_pow(temp_C, k);
742
743                                         /* Convert (C)^k to (scaled_C)^k */
744                                         leakage_calc_step =
745                                                 div64_s64(leakage_calc_step,
746                                                 edp_pow(params->temp_scaled,
747                                                         k));
748
749                                         /* leakage_consts_ijk was scaled */
750                                         leakage_calc_step =
751                                                 div64_s64(leakage_calc_step,
752                                                           params->ijk_scaled);
753
754                                         leakage_mA += leakage_calc_step;
755                                 }
756                         }
757                 }
758                 /* set floor for leakage current */
759                 if (leakage_mA <= params->leakage_min)
760                         leakage_mA = params->leakage_min;
761
762                 /* Calculate dynamic current */
763
764                 dyn_mA = voltage_mV * freq_KHz / 1000;
765                 /* Convert mV to V */
766                 dyn_mA = div64_s64(dyn_mA, 1000);
767                 dyn_mA *= params->dyn_consts_n;
768                 /* dyn_const_n was scaled */
769                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
770
771                 if ((leakage_mA + dyn_mA) <= cur_effective)
772                         goto end;
773
774                 freq_KHz = 0;
775         }
776
777  end:
778         return freq_KHz;
779 }
780
781 static int __init start_gpu_edp(void)
782 {
783         const char *cap_name = "edp.gbus";
784
785         gpu_cap_clk = tegra_get_clock_by_name(cap_name);
786         if (!gpu_cap_clk) {
787                 pr_err("gpu_edp_set_cdev_state: cannot get clock:%s\n",
788                                 cap_name);
789                 return -EINVAL;
790         }
791         edp_gpu_thermal_idx = 0;
792
793         return 0;
794 }
795
796
797 static int edp_gpu_relate_freq_voltage(struct clk *clk_gpu,
798                         unsigned int freq_volt_lut_size,
799                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
800 {
801         unsigned int i, j, freq;
802         int voltage_mV;
803
804         for (i = 0, j = 0, freq = 0;
805                  i < freq_volt_lut_size;
806                  i++, freq += GPU_FREQ_STEP) {
807
808                 /* Predict voltages */
809                 voltage_mV = tegra_dvfs_predict_peak_millivolts(clk_gpu, freq);
810                 if (voltage_mV < 0) {
811                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
812                                __func__, freq, voltage_mV);
813                         return -EINVAL;
814                 }
815
816                 /* Cache frequency / voltage / voltage constant relationship */
817                 freq_volt_lut[i].freq = freq;
818                 freq_volt_lut[i].voltage_mV = voltage_mV;
819         }
820         return 0;
821 }
822
823 static int init_gpu_edp_limits_calculated(void)
824 {
825         unsigned int temp_idx;
826         unsigned int gpu_minf, gpu_maxf;
827         unsigned int limit;
828         struct tegra_edp_gpu_limits *edp_gpu_calculated_limits;
829         struct tegra_edp_gpu_limits *temp;
830         struct tegra_edp_gpu_leakage_params *params;
831         int ret;
832         unsigned int gpu_iddq_mA;
833         u32 tegra_chip_id;
834         struct clk *gpu_clk = clk_get_parent(gpu_cap_clk);
835         tegra_chip_id = tegra_get_chip_id();
836
837         if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
838                 gpu_iddq_mA = tegra_get_gpu_iddq_value();
839                 params = tegra12x_get_gpu_leakage_params();
840         } else
841                 return -EINVAL;
842
843         edp_gpu_calculated_limits = kmalloc(sizeof(struct tegra_edp_gpu_limits)
844                                 * ARRAY_SIZE(gpu_temperatures), GFP_KERNEL);
845         BUG_ON(!edp_gpu_calculated_limits);
846
847         gpu_minf = 0;
848         gpu_maxf = clk_get_max_rate(gpu_clk);
849
850         freq_voltage_gpu_lut_size = (gpu_maxf - gpu_minf) / GPU_FREQ_STEP + 1;
851         freq_voltage_gpu_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
852                                    * freq_voltage_gpu_lut_size, GFP_KERNEL);
853         if (!freq_voltage_gpu_lut) {
854                 pr_err("%s: failed alloc mem for gpu freq/voltage LUT\n",
855                          __func__);
856                 kfree(edp_gpu_calculated_limits);
857                 return -ENOMEM;
858         }
859
860         ret = edp_gpu_relate_freq_voltage(gpu_clk,
861                         freq_voltage_gpu_lut_size, freq_voltage_gpu_lut);
862
863         if (ret) {
864                 kfree(edp_gpu_calculated_limits);
865                 kfree(freq_voltage_gpu_lut);
866                 return ret;
867         }
868
869         for (temp_idx = 0;
870                      temp_idx < ARRAY_SIZE(gpu_temperatures); temp_idx++) {
871                         edp_gpu_calculated_limits[temp_idx].temperature =
872                                 gpu_temperatures[temp_idx];
873                         limit = edp_gpu_calculate_maxf(params,
874                                                    gpu_temperatures[temp_idx],
875                                                    gpu_iddq_mA);
876                         if (limit == -EINVAL) {
877                                 kfree(edp_gpu_calculated_limits);
878                                 kfree(freq_voltage_gpu_lut);
879                                 return -EINVAL;
880                         }
881
882                         edp_gpu_calculated_limits[temp_idx].freq_limits = limit;
883         }
884
885         /*
886          * If this is an EDP table update, need to overwrite old table.
887          * The old table's address must remain valid.
888          */
889         if (edp_gpu_limits != edp_gpu_default_limits &&
890                         edp_gpu_limits != edp_gpu_calculated_limits) {
891                 temp = edp_gpu_limits;
892                 edp_gpu_limits = edp_gpu_calculated_limits;
893                 edp_gpu_limits_size = ARRAY_SIZE(gpu_temperatures);
894                 kfree(temp);
895         } else {
896                 edp_gpu_limits = edp_gpu_calculated_limits;
897                 edp_gpu_limits_size = ARRAY_SIZE(gpu_temperatures);
898         }
899
900         kfree(freq_voltage_gpu_lut);
901
902         return 0;
903 }
904
905 void tegra_platform_edp_gpu_init(struct thermal_trip_info *trips,
906                                 int *num_trips, int margin)
907 {
908         const struct tegra_edp_gpu_limits *gpu_edp_limits;
909         struct thermal_trip_info *trip_state;
910         int i, gpu_edp_limits_size;
911
912         if (!trips || !num_trips)
913                 return;
914
915         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
916
917         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
918                 BUG();
919
920         for (i = 0; i < gpu_edp_limits_size-1; i++) {
921                 trip_state = &trips[*num_trips];
922
923                 trip_state->cdev_type = "gpu_edp";
924                 trip_state->trip_temp =
925                         (gpu_edp_limits[i].temperature * 1000) - margin;
926                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
927                 trip_state->upper = trip_state->lower = i + 1;
928
929                 (*num_trips)++;
930
931                 if (*num_trips >= THERMAL_MAX_TRIPS)
932                         BUG();
933         }
934 }
935
936 void __init tegra_init_gpu_edp_limits(unsigned int regulator_mA)
937 {
938         u32 tegra_chip_id;
939         tegra_chip_id = tegra_get_chip_id();
940
941         if (!regulator_mA)
942                 goto end;
943         gpu_regulator_cur = regulator_mA;
944
945         if (start_gpu_edp()) {
946                 WARN(1, "GPU EDP failed to set initialial limits");
947                 return;
948         }
949
950         switch (tegra_chip_id) {
951         case TEGRA_CHIPID_TEGRA12:
952                 if (init_gpu_edp_limits_calculated() == 0)
953                         return;
954                 break;
955
956         default:
957                 BUG();
958                 break;
959         }
960
961  end:
962         edp_gpu_limits = edp_gpu_default_limits;
963         edp_gpu_limits_size = ARRAY_SIZE(edp_gpu_default_limits);
964 }
965
966 static int gpu_edp_get_cdev_max_state(struct thermal_cooling_device *cdev,
967                                        unsigned long *max_state)
968 {
969         *max_state = edp_gpu_limits_size - 1;
970         return 0;
971 }
972
973 static int gpu_edp_get_cdev_cur_state(struct thermal_cooling_device *cdev,
974                                        unsigned long *cur_state)
975 {
976         *cur_state = edp_gpu_thermal_idx;
977         return 0;
978 }
979
980 static int gpu_edp_set_cdev_state(struct thermal_cooling_device *cdev,
981                                    unsigned long cur_state)
982 {
983         unsigned long clk_rate;
984         BUG_ON(cur_state >= edp_gpu_limits_size);
985         clk_rate = edp_gpu_limits[cur_state].freq_limits;
986         mutex_lock(&gpu_edp_lock);
987         edp_gpu_thermal_idx = cur_state;
988         clk_set_rate(gpu_cap_clk, clk_rate * 1000);
989         mutex_unlock(&gpu_edp_lock);
990         return 0;
991 }
992
993 static struct thermal_cooling_device_ops gpu_edp_cooling_ops = {
994         .get_max_state = gpu_edp_get_cdev_max_state,
995         .get_cur_state = gpu_edp_get_cdev_cur_state,
996         .set_cur_state = gpu_edp_set_cdev_state,
997 };
998
999 static int __init tegra_gpu_edp_late_init(void)
1000 {
1001         if (IS_ERR_OR_NULL(thermal_cooling_device_register(
1002                 "gpu_edp", NULL, &gpu_edp_cooling_ops)))
1003                 pr_err("%s: failed to register edp cooling device\n", __func__);
1004
1005         return 0;
1006 }
1007 late_initcall(tegra_gpu_edp_late_init);
1008
1009 #endif
1010
1011 #ifdef CONFIG_DEBUG_FS
1012
1013 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
1014 {
1015 #ifdef CONFIG_CPU_FREQ
1016         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
1017 #endif
1018         return 0;
1019 }
1020
1021 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
1022 {
1023         int i;
1024
1025         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1026                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1027         for (i = 0; i < edp_limits_size; i++) {
1028                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1029                            i == th_idx ? '>' : ' ',
1030                            edp_limits[i].temperature,
1031                            edp_limits[i].freq_limits[0],
1032                            edp_limits[i].freq_limits[1],
1033                            edp_limits[i].freq_limits[2],
1034                            edp_limits[i].freq_limits[3]);
1035         }
1036 }
1037
1038 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
1039 {
1040         int i;
1041
1042         seq_printf(s, "%6s %10s %10s\n",
1043                    " Temp.", "1-core", "2-cores");
1044         for (i = 0; i < edp_limits_size; i++) {
1045                 seq_printf(s, "%c%3dC: %10u %10u\n",
1046                            i == th_idx ? '>' : ' ',
1047                            edp_limits[i].temperature,
1048                            edp_limits[i].freq_limits[0],
1049                            edp_limits[i].freq_limits[1]);
1050         }
1051 }
1052
1053 static inline void edp_show_4core_reg_mode_table(struct seq_file *s, int th_idx)
1054 {
1055         int i;
1056
1057         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1058                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1059         for (i = 0; i < edp_limits_size; i++) {
1060                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1061                            i == th_idx ? '>' : ' ',
1062                            reg_idle_edp_limits[i].temperature,
1063                            reg_idle_edp_limits[i].freq_limits[0],
1064                            reg_idle_edp_limits[i].freq_limits[1],
1065                            reg_idle_edp_limits[i].freq_limits[2],
1066                            reg_idle_edp_limits[i].freq_limits[3]);
1067         }
1068 }
1069
1070 static inline void edp_show_2core_reg_mode_table(struct seq_file *s, int th_idx)
1071 {
1072         int i;
1073
1074         seq_printf(s, "%6s %10s %10s\n",
1075                    " Temp.", "1-core", "2-cores");
1076         for (i = 0; i < edp_limits_size; i++) {
1077                 seq_printf(s, "%c%3dC: %10u %10u\n",
1078                            i == th_idx ? '>' : ' ',
1079                            reg_idle_edp_limits[i].temperature,
1080                            reg_idle_edp_limits[i].freq_limits[0],
1081                            reg_idle_edp_limits[i].freq_limits[1]);
1082         }
1083 }
1084
1085 static inline void edp_show_2core_system_table(struct seq_file *s)
1086 {
1087         seq_printf(s, "%10u %10u\n",
1088                    system_edp_limits[0],
1089                    system_edp_limits[1]);
1090 }
1091
1092 static inline void edp_show_4core_system_table(struct seq_file *s)
1093 {
1094         seq_printf(s, "%10u %10u %10u %10u\n",
1095                    system_edp_limits[0],
1096                    system_edp_limits[1],
1097                    system_edp_limits[2],
1098                    system_edp_limits[3]);
1099 }
1100
1101 static int edp_debugfs_show(struct seq_file *s, void *data)
1102 {
1103         unsigned int max_nr_cpus = num_possible_cpus();
1104         int th_idx;
1105
1106         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
1107                 seq_printf(s, "Unsupported number of CPUs\n");
1108                 return 0;
1109         }
1110
1111 #ifdef CONFIG_CPU_FREQ
1112         tegra_get_edp_limit(&th_idx);
1113 #else
1114         th_idx = 0;
1115 #endif
1116
1117         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
1118                    edp_limits == edp_default_limits ? "**default** " : "",
1119                    regulator_cur - edp_reg_override_mA,
1120                    regulator_cur, edp_reg_override_mA);
1121
1122         if (max_nr_cpus == 2)
1123                 edp_show_2core_edp_table(s, th_idx);
1124         else if (max_nr_cpus == 4)
1125                 edp_show_4core_edp_table(s, th_idx);
1126
1127         if (reg_idle_edp_limits) {
1128                 seq_printf(s, "\n-- Regulator mode thresholds @ %dmA --\n",
1129                            reg_idle_cur);
1130                 if (max_nr_cpus == 2)
1131                         edp_show_2core_reg_mode_table(s, th_idx);
1132                 else if (max_nr_cpus == 4)
1133                         edp_show_4core_reg_mode_table(s, th_idx);
1134         }
1135
1136         if (system_edp_limits) {
1137                 seq_printf(s, "\n-- System EDP table --\n");
1138                 if (max_nr_cpus == 2)
1139                         edp_show_2core_system_table(s);
1140                 else if (max_nr_cpus == 4)
1141                         edp_show_4core_system_table(s);
1142         }
1143
1144         return 0;
1145 }
1146
1147 #ifdef CONFIG_TEGRA_GPU_EDP
1148 static inline void gpu_edp_show_table(struct seq_file *s)
1149 {
1150         int i;
1151
1152         seq_printf(s, "%6s %10s\n",
1153                    " Temp.", "Freq_limit");
1154         for (i = 0; i < edp_gpu_limits_size; i++) {
1155                 seq_printf(s, "%3dC: %10u \n",
1156                            edp_gpu_limits[i].temperature,
1157                            edp_gpu_limits[i].freq_limits);
1158         }
1159 }
1160
1161
1162 static int gpu_edp_debugfs_show(struct seq_file *s, void *data)
1163 {
1164         seq_printf(s, "-- VDD_GPU EDP table --\n");
1165
1166         gpu_edp_show_table(s);
1167
1168         return 0;
1169 }
1170 #endif
1171
1172 static int edp_reg_override_show(struct seq_file *s, void *data)
1173 {
1174         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
1175                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
1176         return 0;
1177 }
1178
1179 static int edp_reg_override_write(struct file *file,
1180         const char __user *userbuf, size_t count, loff_t *ppos)
1181 {
1182         char buf[32], *end;
1183         unsigned int edp_reg_override_mA_temp;
1184         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
1185         u32 tegra_chip_id;
1186
1187         tegra_chip_id = tegra_get_chip_id();
1188         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
1189                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
1190                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
1191                 goto override_err;
1192
1193         if (sizeof(buf) <= count)
1194                 goto override_err;
1195
1196         if (copy_from_user(buf, userbuf, count))
1197                 goto override_err;
1198
1199         /* terminate buffer and trim - white spaces may be appended
1200          *  at the end when invoked from shell command line */
1201         buf[count]='\0';
1202         strim(buf);
1203
1204         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
1205         if (*end != '\0')
1206                 goto override_err;
1207
1208         if (edp_reg_override_mA_temp >= regulator_cur)
1209                 goto override_err;
1210
1211         if (edp_reg_override_mA == edp_reg_override_mA_temp)
1212                 return count;
1213
1214         edp_reg_override_mA = edp_reg_override_mA_temp;
1215         if (init_cpu_edp_limits_calculated()) {
1216                 /* Revert to previous override value if new value fails */
1217                 edp_reg_override_mA = edp_reg_override_mA_prev;
1218                 goto override_err;
1219         }
1220
1221 #ifdef CONFIG_CPU_FREQ
1222         if (tegra_cpu_set_speed_cap(NULL)) {
1223                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
1224                 goto override_out;
1225         }
1226
1227         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
1228                         " %u mA\n", regulator_cur - edp_reg_override_mA);
1229 #else
1230         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
1231 #endif
1232
1233         return count;
1234
1235 override_err:
1236         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
1237                buf);
1238 #ifdef CONFIG_CPU_FREQ
1239 override_out:
1240 #endif
1241         return -EINVAL;
1242 }
1243
1244 static int edp_debugfs_open(struct inode *inode, struct file *file)
1245 {
1246         return single_open(file, edp_debugfs_show, inode->i_private);
1247 }
1248
1249 #ifdef CONFIG_TEGRA_GPU_EDP
1250 static int gpu_edp_debugfs_open(struct inode *inode, struct file *file)
1251 {
1252         return single_open(file, gpu_edp_debugfs_show, inode->i_private);
1253 }
1254 #endif
1255
1256 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
1257 {
1258         return single_open(file, edp_limit_debugfs_show, inode->i_private);
1259 }
1260
1261 static int edp_reg_override_open(struct inode *inode, struct file *file)
1262 {
1263         return single_open(file, edp_reg_override_show, inode->i_private);
1264 }
1265
1266 static const struct file_operations edp_debugfs_fops = {
1267         .open           = edp_debugfs_open,
1268         .read           = seq_read,
1269         .llseek         = seq_lseek,
1270         .release        = single_release,
1271 };
1272
1273 #ifdef CONFIG_TEGRA_GPU_EDP
1274 static const struct file_operations gpu_edp_debugfs_fops = {
1275         .open           = gpu_edp_debugfs_open,
1276         .read           = seq_read,
1277         .llseek         = seq_lseek,
1278         .release        = single_release,
1279 };
1280 #endif
1281
1282 static const struct file_operations edp_limit_debugfs_fops = {
1283         .open           = edp_limit_debugfs_open,
1284         .read           = seq_read,
1285         .llseek         = seq_lseek,
1286         .release        = single_release,
1287 };
1288
1289 static const struct file_operations edp_reg_override_debugfs_fops = {
1290         .open           = edp_reg_override_open,
1291         .read           = seq_read,
1292         .write          = edp_reg_override_write,
1293         .llseek         = seq_lseek,
1294         .release        = single_release,
1295 };
1296
1297 static int reg_idle_cur_get(void *data, u64 *val)
1298 {
1299         *val = reg_idle_cur;
1300         return 0;
1301 }
1302 static int reg_idle_cur_set(void *data, u64 val)
1303 {
1304         int ret;
1305
1306         ret = tegra_cpu_reg_mode_force_normal(true);
1307         if (ret) {
1308                 pr_err("%s: Failed to force regulator normal mode\n", __func__);
1309                 return ret;
1310         }
1311
1312         reg_idle_cur = (int)val;
1313         tegra_update_cpu_edp_limits();
1314         return 0;
1315 }
1316 DEFINE_SIMPLE_ATTRIBUTE(reg_idle_cur_debugfs_fops,
1317                         reg_idle_cur_get, reg_idle_cur_set, "%llu\n");
1318
1319 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
1320 static __init struct dentry *tegra_edp_debugfs_dir(void)
1321 {
1322         if (edp_debugfs_dir)
1323                 return edp_debugfs_dir;
1324         else
1325                 return debugfs_create_dir("edp", NULL);
1326 }
1327 #else
1328 static __init struct dentry *tegra_edp_debugfs_dir(void)
1329 {
1330         return debugfs_create_dir("edp", NULL);
1331 }
1332 #endif
1333
1334 static int __init tegra_edp_debugfs_init(void)
1335 {
1336         struct dentry *d_reg_idle_cur;
1337         struct dentry *d_edp;
1338         struct dentry *d_edp_limit;
1339         struct dentry *d_edp_reg_override;
1340         struct dentry *edp_dir;
1341         struct dentry *vdd_cpu_dir;
1342 #ifdef CONFIG_TEGRA_GPU_EDP
1343         struct dentry *gpu_edp;
1344         struct dentry *vdd_gpu_dir;
1345 #endif
1346
1347         if (!tegra_platform_is_silicon())
1348                 return -ENOSYS;
1349
1350         edp_dir = tegra_edp_debugfs_dir();
1351
1352         if (!edp_dir)
1353                 goto edp_dir_err;
1354
1355         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
1356
1357         if (!vdd_cpu_dir)
1358                 goto vdd_cpu_dir_err;
1359
1360 #ifdef CONFIG_TEGRA_GPU_EDP
1361         vdd_gpu_dir = debugfs_create_dir("vdd_gpu", edp_dir);
1362
1363         if (!vdd_gpu_dir)
1364                 goto vdd_gpu_dir_err;
1365 #endif
1366
1367         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
1368                                 &edp_debugfs_fops);
1369
1370         if (!d_edp)
1371                 goto edp_err;
1372 #ifdef CONFIG_TEGRA_GPU_EDP
1373         gpu_edp = debugfs_create_file("gpu_edp",  S_IRUGO, vdd_gpu_dir, NULL,
1374                          &gpu_edp_debugfs_fops);
1375         if (!gpu_edp)
1376                 goto gpu_edp_err;
1377 #endif
1378
1379         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
1380                                 NULL, &edp_limit_debugfs_fops);
1381
1382         if (!d_edp_limit)
1383                 goto edp_limit_err;
1384
1385         d_edp_reg_override = debugfs_create_file("edp_reg_override",
1386                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1387                                 &edp_reg_override_debugfs_fops);
1388
1389         if (!d_edp_reg_override)
1390                 goto edp_reg_override_err;
1391
1392         d_reg_idle_cur = debugfs_create_file("reg_idle_mA",
1393                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1394                                 &reg_idle_cur_debugfs_fops);
1395         if (!d_reg_idle_cur)
1396                 goto reg_idle_cur_err;
1397
1398         if (tegra_core_edp_debugfs_init(edp_dir))
1399                 return -ENOMEM;
1400
1401         return 0;
1402
1403 reg_idle_cur_err:
1404         debugfs_remove(d_edp_reg_override);
1405 edp_reg_override_err:
1406         debugfs_remove(d_edp_limit);
1407 edp_limit_err:
1408 #ifdef CONFIG_TEGRA_GPU_EDP
1409         debugfs_remove(gpu_edp);
1410 gpu_edp_err:
1411 #endif
1412         debugfs_remove(d_edp);
1413 edp_err:
1414 #ifdef CONFIG_TEGRA_GPU_EDP
1415         debugfs_remove(vdd_gpu_dir);
1416 vdd_gpu_dir_err:
1417 #endif
1418         debugfs_remove(vdd_cpu_dir);
1419 vdd_cpu_dir_err:
1420         debugfs_remove(edp_dir);
1421 edp_dir_err:
1422         return -ENOMEM;
1423 }
1424
1425 late_initcall(tegra_edp_debugfs_init);
1426 #endif /* CONFIG_DEBUG_FS */