arm: tegra: adding CPU EDP support for T124
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26
27 #include <mach/edp.h>
28 #include <mach/hardware.h>
29
30 #include "fuse.h"
31 #include "dvfs.h"
32 #include "clock.h"
33 #include "cpu-tegra.h"
34
35 #define FREQ_STEP 12750000
36 #define OVERRIDE_DEFAULT 6000
37
38 static struct tegra_edp_limits *edp_limits;
39 static int edp_limits_size;
40 static unsigned int regulator_cur;
41 /* Value to subtract from regulator current limit */
42 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
43
44 static const unsigned int *system_edp_limits;
45
46 static struct tegra_system_edp_entry *power_edp_limits;
47 static int power_edp_limits_size;
48
49 /*
50  * "Safe entry" to be used when no match for speedo_id /
51  * regulator_cur is found; must be the last one
52  */
53 static struct tegra_edp_limits edp_default_limits[] = {
54         {85, {1000000, 1000000, 1000000, 1000000} },
55 };
56
57 static struct tegra_system_edp_entry power_edp_default_limits[] = {
58         {0, 20, {1000000, 1000000, 1000000, 1000000} },
59 };
60
61 /* Constants for EDP calculations */
62 static const int temperatures[] = { /* degree celcius (C) */
63         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
64 };
65
66 static const int power_cap_levels[] = { /* milliwatts (mW) */
67           500,  1000,  1500,  2000,  2500,  3000,  3500,
68          4000,  4500,  5000,  5500,  6000,  6500,  7000,
69          7500,  8000,  8500,  9000,  9500, 10000, 10500,
70         11000, 11500, 12000, 12500, 13000, 13500, 14000,
71         14500, 15000, 15500, 16000, 16500, 17000
72 };
73
74 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
75 static unsigned int freq_voltage_lut_size_saved;
76 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
77 static unsigned int freq_voltage_lut_size;
78
79 static inline s64 edp_pow(s64 val, int pwr)
80 {
81         s64 retval = 1;
82
83         while (val && pwr) {
84                 if (pwr & 1)
85                         retval *= val;
86                 pwr >>= 1;
87                 if (pwr)
88                         val *= val;
89         }
90
91         return retval;
92 }
93
94
95 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
96 static inline unsigned int edp_apply_fixed_limits(
97                                 unsigned int in_freq_KHz,
98                                 struct tegra_edp_cpu_leakage_params *params,
99                                 unsigned int cur_effective,
100                                 int temp_C, int n_cores_idx)
101 {
102         unsigned int out_freq_KHz = in_freq_KHz;
103         unsigned int max_cur, max_temp, max_freq;
104         int i;
105
106         /* Apply any additional fixed limits */
107         for (i = 0; i < 8; i++) {
108                 max_cur = params->max_current_cap[i].max_cur;
109                 if (max_cur != 0 && cur_effective <= max_cur) {
110                         max_temp = params->max_current_cap[i].max_temp;
111                         if (max_temp != 0 && temp_C > max_temp) {
112                                 max_freq = params->max_current_cap[i].
113                                         max_freq[n_cores_idx];
114                                 if (max_freq && max_freq < out_freq_KHz)
115                                         out_freq_KHz = max_freq;
116                         }
117                 }
118         }
119
120         return out_freq_KHz;
121 }
122 #else
123 #define edp_apply_fixed_limits(freq, unused...) (freq)
124 #endif
125
126 /*
127  * Find the maximum frequency that results in dynamic and leakage current that
128  * is less than the regulator current limit.
129  * temp_C - valid or -EINVAL
130  * power_mW - valid or -1 (infinite) or -EINVAL
131  */
132 static unsigned int edp_calculate_maxf(
133                                 struct tegra_edp_cpu_leakage_params *params,
134                                 int temp_C, int power_mW,
135                                 int iddq_mA,
136                                 int n_cores_idx)
137 {
138         unsigned int voltage_mV, freq_KHz = 0;
139         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
140         int f, i, j, k, r = 0;
141         s64 leakage_mA, dyn_mA, leakage_calc_step;
142         s64 leakage_mW, dyn_mW;
143
144         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
145                 freq_KHz = freq_voltage_lut[f].freq / 1000;
146                 voltage_mV = freq_voltage_lut[f].voltage_mV;
147
148                 /* Constrain Volt-Temp */
149                 if (params->volt_temp_cap.temperature &&
150                     temp_C > params->volt_temp_cap.temperature &&
151                     params->volt_temp_cap.voltage_limit_mV &&
152                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
153                         continue;
154
155                 /* Calculate leakage current */
156                 leakage_mA = 0;
157                 for (i = 0; i <= 3; i++) {
158                         for (j = 0; j <= 3; j++) {
159                                 for (k = 0; k <= 3; k++) {
160                                         leakage_calc_step =
161                                                 params->leakage_consts_ijk
162                                                 [i][j][k] * edp_pow(iddq_mA, i);
163                                         /* Convert (mA)^i to (A)^i */
164                                         leakage_calc_step =
165                                                 div64_s64(leakage_calc_step,
166                                                           edp_pow(1000, i));
167                                         leakage_calc_step *=
168                                                 edp_pow(voltage_mV, j);
169                                         /* Convert (mV)^j to (V)^j */
170                                         leakage_calc_step =
171                                                 div64_s64(leakage_calc_step,
172                                                           edp_pow(1000, j));
173                                         leakage_calc_step *=
174                                                 edp_pow(temp_C, k);
175                                         /* Convert (C)^k to (scaled_C)^k */
176                                         leakage_calc_step =
177                                                 div64_s64(leakage_calc_step,
178                                                 edp_pow(params->temp_scaled,
179                                                         k));
180                                         /* leakage_consts_ijk was scaled */
181                                         leakage_calc_step =
182                                                 div64_s64(leakage_calc_step,
183                                                           params->ijk_scaled);
184                                         leakage_mA += leakage_calc_step;
185                                 }
186                         }
187                 }
188
189                 /* set floor for leakage current */
190                 if (leakage_mA <= params->leakage_min)
191                         leakage_mA = params->leakage_min;
192
193                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
194
195                 /* leakage_const_n was scaled */
196                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
197
198                 /* Calculate dynamic current */
199                 dyn_mA = voltage_mV * freq_KHz / 1000;
200                 /* Convert mV to V */
201                 dyn_mA = div64_s64(dyn_mA, 1000);
202                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
203                 /* dyn_const_n was scaled */
204                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
205
206                 if (power_mW != -1) {
207                         leakage_mW = leakage_mA * voltage_mV;
208                         dyn_mW = dyn_mA * voltage_mV;
209                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
210                                 goto end;
211                 } else if ((leakage_mA + dyn_mA) <= cur_effective) {
212                         goto end;
213                 }
214                 freq_KHz = 0;
215         }
216
217  end:
218         if (r != 0)
219                 return r;
220
221         return edp_apply_fixed_limits(freq_KHz, params,
222                                         cur_effective, temp_C, n_cores_idx);
223 }
224
225 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
226                         unsigned int cpu_speedo_idx,
227                         unsigned int freq_volt_lut_size,
228                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
229 {
230         unsigned int i, j, freq;
231         int voltage_mV;
232
233         for (i = 0, j = 0, freq = 0;
234                  i < freq_volt_lut_size;
235                  i++, freq += FREQ_STEP) {
236
237                 /* Predict voltages */
238                 voltage_mV = tegra_dvfs_predict_millivolts(clk_cpu_g, freq);
239                 if (voltage_mV < 0) {
240                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
241                                __func__, freq, voltage_mV);
242                         return -EINVAL;
243                 }
244
245                 /* Cache frequency / voltage / voltage constant relationship */
246                 freq_volt_lut[i].freq = freq;
247                 freq_volt_lut[i].voltage_mV = voltage_mV;
248         }
249         return 0;
250 }
251
252 unsigned int tegra_edp_find_maxf(int volt)
253 {
254         unsigned int i;
255
256         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
257                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
258                         break;
259         }
260         return freq_voltage_lut[i - 1].freq;
261 }
262
263
264 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
265 {
266         int i, array_size;
267         struct tegra_edp_cpu_leakage_params *params;
268
269         switch (tegra_chip_id) {
270         case TEGRA_CHIPID_TEGRA11:
271                 params = tegra11x_get_leakage_params(0, &array_size);
272                 break;
273         case TEGRA_CHIPID_TEGRA14:
274                 params = tegra14x_get_leakage_params(0, &array_size);
275                 break;
276         case TEGRA_CHIPID_TEGRA12:
277                 params = tegra12x_get_leakage_params(0, &array_size);
278                 break;
279         case TEGRA_CHIPID_TEGRA3:
280         case TEGRA_CHIPID_TEGRA2:
281         default:
282                 array_size = 0;
283                 break;
284         }
285
286         for (i = 0; i < array_size; i++)
287                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
288                         *cpu_speedo_idx = i;
289                         return 0;
290                 }
291
292         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
293                __func__, cpu_speedo_id);
294         return -EINVAL;
295 }
296
297 static int init_cpu_edp_limits_calculated(void)
298 {
299         unsigned int max_nr_cpus = num_possible_cpus();
300         unsigned int temp_idx, n_cores_idx, pwr_idx;
301         unsigned int cpu_g_minf, cpu_g_maxf;
302         unsigned int iddq_mA;
303         unsigned int cpu_speedo_idx;
304         unsigned int cap, limit;
305         struct tegra_edp_limits *edp_calculated_limits;
306         struct tegra_system_edp_entry *power_edp_calc_limits;
307         struct tegra_edp_cpu_leakage_params *params;
308         int ret;
309         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
310         int cpu_speedo_id = tegra_cpu_speedo_id();
311
312         /* Determine all inputs to EDP formula */
313         iddq_mA = tegra_get_cpu_iddq_value();
314         iddq_mA = 1281; /* hard code for testing */
315         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
316         if (ret)
317                 return ret;
318
319         switch (tegra_chip_id) {
320         case TEGRA_CHIPID_TEGRA11:
321                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
322                 break;
323         case TEGRA_CHIPID_TEGRA14:
324                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
325                 break;
326         case TEGRA_CHIPID_TEGRA12:
327                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
328                 break;
329         case TEGRA_CHIPID_TEGRA3:
330         case TEGRA_CHIPID_TEGRA2:
331         default:
332                 return -EINVAL;
333         }
334
335         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
336                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
337         BUG_ON(!edp_calculated_limits);
338
339         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
340                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
341         BUG_ON(!power_edp_calc_limits);
342
343         cpu_g_minf = 0;
344         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
345         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
346         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
347                                    * freq_voltage_lut_size, GFP_KERNEL);
348         if (!freq_voltage_lut) {
349                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
350                 kfree(power_edp_calc_limits);
351                 kfree(edp_calculated_limits);
352                 return -ENOMEM;
353         }
354
355         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
356                                 freq_voltage_lut_size, freq_voltage_lut);
357         if (ret) {
358                 kfree(power_edp_calc_limits);
359                 kfree(edp_calculated_limits);
360                 kfree(freq_voltage_lut);
361                 return ret;
362         }
363
364         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
365                 /* release previous table if present */
366                 kfree(freq_voltage_lut_saved);
367                 /* create table to save */
368                 freq_voltage_lut_saved =
369                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
370                         freq_voltage_lut_size, GFP_KERNEL);
371                 if (!freq_voltage_lut_saved) {
372                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
373                                 __func__);
374                         kfree(freq_voltage_lut);
375                         return -ENOMEM;
376                 }
377                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
378         }
379         memcpy(freq_voltage_lut_saved,
380                 freq_voltage_lut,
381                 sizeof(struct tegra_edp_freq_voltage_table) *
382                         freq_voltage_lut_size);
383
384         /* Calculate EDP table */
385         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
386                 for (temp_idx = 0;
387                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
388                         edp_calculated_limits[temp_idx].temperature =
389                                 temperatures[temp_idx];
390                         limit = edp_calculate_maxf(params,
391                                                    temperatures[temp_idx],
392                                                    -1,
393                                                    iddq_mA,
394                                                    n_cores_idx);
395                         if (limit == -EINVAL)
396                                 return -EINVAL;
397                         /* apply safety cap if it is specified */
398                         if (n_cores_idx < 4) {
399                                 cap = params->safety_cap[n_cores_idx];
400                                 if (cap && cap < limit)
401                                         limit = cap;
402                         }
403                         edp_calculated_limits[temp_idx].
404                                 freq_limits[n_cores_idx] = limit;
405                 }
406
407                 for (pwr_idx = 0;
408                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
409                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
410                                 power_cap_levels[pwr_idx] / 100;
411                         limit = edp_calculate_maxf(params,
412                                                    90,
413                                                    power_cap_levels[pwr_idx],
414                                                    iddq_mA,
415                                                    n_cores_idx);
416                         if (limit == -EINVAL)
417                                 return -EINVAL;
418                         power_edp_calc_limits[pwr_idx].
419                                 freq_limits[n_cores_idx] = limit;
420                 }
421         }
422
423         /*
424          * If this is an EDP table update, need to overwrite old table.
425          * The old table's address must remain valid.
426          */
427         if (edp_limits != edp_default_limits) {
428                 memcpy(edp_limits, edp_calculated_limits,
429                        sizeof(struct tegra_edp_limits)
430                        * ARRAY_SIZE(temperatures));
431                 kfree(edp_calculated_limits);
432         }
433         else {
434                 edp_limits = edp_calculated_limits;
435                 edp_limits_size = ARRAY_SIZE(temperatures);
436         }
437
438         if (power_edp_limits != power_edp_default_limits) {
439                 memcpy(power_edp_limits, power_edp_calc_limits,
440                        sizeof(struct tegra_system_edp_entry)
441                        * ARRAY_SIZE(power_cap_levels));
442                 kfree(power_edp_calc_limits);
443         } else {
444                 power_edp_limits = power_edp_calc_limits;
445                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
446         }
447
448         kfree(freq_voltage_lut);
449         return 0;
450 }
451
452 void tegra_recalculate_cpu_edp_limits(void)
453 {
454         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
455             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
456             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
457                 return;
458
459         if (init_cpu_edp_limits_calculated() == 0)
460                 return;
461
462         /* Revert to default EDP table on error */
463         edp_limits = edp_default_limits;
464         edp_limits_size = ARRAY_SIZE(edp_default_limits);
465
466         power_edp_limits = power_edp_default_limits;
467         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
468 }
469
470 /*
471  * Specify regulator current in mA, e.g. 5000mA
472  * Use 0 for default
473  */
474 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
475 {
476         if (!regulator_mA)
477                 goto end;
478         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
479
480         switch (tegra_chip_id) {
481         case TEGRA_CHIPID_TEGRA11:
482         case TEGRA_CHIPID_TEGRA14:
483         case TEGRA_CHIPID_TEGRA12:
484                 if (init_cpu_edp_limits_calculated() == 0)
485                         return;
486                 break;
487         case TEGRA_CHIPID_TEGRA2:
488         case TEGRA_CHIPID_TEGRA3:
489         default:
490                 BUG();
491                 break;
492         }
493
494  end:
495         edp_limits = edp_default_limits;
496         edp_limits_size = ARRAY_SIZE(edp_default_limits);
497
498         power_edp_limits = power_edp_default_limits;
499         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
500 }
501
502 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
503 {
504         *limits = edp_limits;
505         *size = edp_limits_size;
506 }
507
508 void tegra_get_system_edp_limits(const unsigned int **limits)
509 {
510         *limits = system_edp_limits;
511 }
512
513 void tegra_platform_edp_init(struct thermal_trip_info *trips,
514                                 int *num_trips, int margin)
515 {
516         const struct tegra_edp_limits *cpu_edp_limits;
517         struct thermal_trip_info *trip_state;
518         int i, cpu_edp_limits_size;
519
520         if (!trips || !num_trips)
521                 return;
522
523         /* edp capping */
524         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
525
526         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
527                 BUG();
528
529         for (i = 0; i < cpu_edp_limits_size-1; i++) {
530                 trip_state = &trips[*num_trips];
531
532                 trip_state->cdev_type = "cpu_edp";
533                 trip_state->trip_temp =
534                         (cpu_edp_limits[i].temperature * 1000) - margin;
535                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
536                 trip_state->upper = trip_state->lower = i + 1;
537
538                 (*num_trips)++;
539
540                 if (*num_trips >= THERMAL_MAX_TRIPS)
541                         BUG();
542         }
543 }
544
545 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
546 {
547         *size = power_edp_limits_size;
548         return power_edp_limits;
549 }
550
551 #ifdef CONFIG_DEBUG_FS
552
553 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
554 {
555 #ifdef CONFIG_CPU_FREQ
556         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
557 #endif
558         return 0;
559 }
560
561 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
562 {
563         int i;
564
565         seq_printf(s, "%6s %10s %10s %10s %10s\n",
566                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
567         for (i = 0; i < edp_limits_size; i++) {
568                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
569                            i == th_idx ? '>' : ' ',
570                            edp_limits[i].temperature,
571                            edp_limits[i].freq_limits[0],
572                            edp_limits[i].freq_limits[1],
573                            edp_limits[i].freq_limits[2],
574                            edp_limits[i].freq_limits[3]);
575         }
576 }
577
578 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
579 {
580         int i;
581
582         seq_printf(s, "%6s %10s %10s\n",
583                    " Temp.", "1-core", "2-cores");
584         for (i = 0; i < edp_limits_size; i++) {
585                 seq_printf(s, "%c%3dC: %10u %10u\n",
586                            i == th_idx ? '>' : ' ',
587                            edp_limits[i].temperature,
588                            edp_limits[i].freq_limits[0],
589                            edp_limits[i].freq_limits[1]);
590         }
591 }
592
593 static inline void edp_show_2core_system_table(struct seq_file *s)
594 {
595         seq_printf(s, "%10u %10u\n",
596                    system_edp_limits[0],
597                    system_edp_limits[1]);
598 }
599
600 static inline void edp_show_4core_system_table(struct seq_file *s)
601 {
602         seq_printf(s, "%10u %10u %10u %10u\n",
603                    system_edp_limits[0],
604                    system_edp_limits[1],
605                    system_edp_limits[2],
606                    system_edp_limits[3]);
607 }
608
609 static int edp_debugfs_show(struct seq_file *s, void *data)
610 {
611         unsigned int max_nr_cpus = num_possible_cpus();
612         int th_idx;
613
614         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
615                 seq_printf(s, "Unsupported number of CPUs\n");
616                 return 0;
617         }
618
619 #ifdef CONFIG_CPU_FREQ
620         tegra_get_edp_limit(&th_idx);
621 #else
622         th_idx = 0;
623 #endif
624
625         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
626                    edp_limits == edp_default_limits ? "**default** " : "",
627                    regulator_cur - edp_reg_override_mA,
628                    regulator_cur, edp_reg_override_mA);
629
630         if (max_nr_cpus == 2)
631                 edp_show_2core_edp_table(s, th_idx);
632         else if (max_nr_cpus == 4)
633                 edp_show_4core_edp_table(s, th_idx);
634
635         if (system_edp_limits) {
636                 seq_printf(s, "\n-- System EDP table --\n");
637                 if (max_nr_cpus == 2)
638                         edp_show_2core_system_table(s);
639                 else if (max_nr_cpus == 4)
640                         edp_show_4core_system_table(s);
641         }
642
643         return 0;
644 }
645
646 static int edp_reg_override_show(struct seq_file *s, void *data)
647 {
648         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
649                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
650         return 0;
651 }
652
653 static int edp_reg_override_write(struct file *file,
654         const char __user *userbuf, size_t count, loff_t *ppos)
655 {
656         char buf[32], *end;
657         unsigned int edp_reg_override_mA_temp;
658         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
659
660         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
661                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
662                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
663                 goto override_err;
664
665         if (sizeof(buf) <= count)
666                 goto override_err;
667
668         if (copy_from_user(buf, userbuf, count))
669                 goto override_err;
670
671         /* terminate buffer and trim - white spaces may be appended
672          *  at the end when invoked from shell command line */
673         buf[count]='\0';
674         strim(buf);
675
676         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
677         if (*end != '\0')
678                 goto override_err;
679
680         if (edp_reg_override_mA_temp >= regulator_cur)
681                 goto override_err;
682
683         if (edp_reg_override_mA == edp_reg_override_mA_temp)
684                 return count;
685
686         edp_reg_override_mA = edp_reg_override_mA_temp;
687         if (init_cpu_edp_limits_calculated()) {
688                 /* Revert to previous override value if new value fails */
689                 edp_reg_override_mA = edp_reg_override_mA_prev;
690                 goto override_err;
691         }
692
693 #ifdef CONFIG_CPU_FREQ
694         if (tegra_cpu_set_speed_cap(NULL)) {
695                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
696                 goto override_out;
697         }
698
699         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
700                         " %u mA\n", regulator_cur - edp_reg_override_mA);
701 #else
702         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
703 #endif
704
705         return count;
706
707 override_err:
708         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
709                buf);
710 #ifdef CONFIG_CPU_FREQ
711 override_out:
712 #endif
713         return -EINVAL;
714 }
715
716 static int edp_debugfs_open(struct inode *inode, struct file *file)
717 {
718         return single_open(file, edp_debugfs_show, inode->i_private);
719 }
720
721 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
722 {
723         return single_open(file, edp_limit_debugfs_show, inode->i_private);
724 }
725
726 static int edp_reg_override_open(struct inode *inode, struct file *file)
727 {
728         return single_open(file, edp_reg_override_show, inode->i_private);
729 }
730
731 static const struct file_operations edp_debugfs_fops = {
732         .open           = edp_debugfs_open,
733         .read           = seq_read,
734         .llseek         = seq_lseek,
735         .release        = single_release,
736 };
737
738 static const struct file_operations edp_limit_debugfs_fops = {
739         .open           = edp_limit_debugfs_open,
740         .read           = seq_read,
741         .llseek         = seq_lseek,
742         .release        = single_release,
743 };
744
745 static const struct file_operations edp_reg_override_debugfs_fops = {
746         .open           = edp_reg_override_open,
747         .read           = seq_read,
748         .write          = edp_reg_override_write,
749         .llseek         = seq_lseek,
750         .release        = single_release,
751 };
752
753 #ifdef CONFIG_EDP_FRAMEWORK
754 static __init struct dentry *tegra_edp_debugfs_dir(void)
755 {
756         return edp_debugfs_dir;
757 }
758 #else
759 static __init struct dentry *tegra_edp_debugfs_dir(void)
760 {
761         return debugfs_create_dir("edp", NULL);
762 }
763 #endif
764
765 static int __init tegra_edp_debugfs_init(void)
766 {
767         struct dentry *d_edp;
768         struct dentry *d_edp_limit;
769         struct dentry *d_edp_reg_override;
770         struct dentry *edp_dir;
771         struct dentry *vdd_cpu_dir;
772
773         if (!tegra_platform_is_silicon())
774                 return -ENOSYS;
775
776         edp_dir = tegra_edp_debugfs_dir();
777
778         if (!edp_dir)
779                 goto edp_dir_err;
780
781         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
782
783         if (!vdd_cpu_dir)
784                 goto vdd_cpu_dir_err;
785
786         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
787                                 &edp_debugfs_fops);
788
789         if (!d_edp)
790                 goto edp_err;
791
792         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
793                                 NULL, &edp_limit_debugfs_fops);
794
795         if (!d_edp_limit)
796                 goto edp_limit_err;
797
798         d_edp_reg_override = debugfs_create_file("edp_reg_override",
799                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
800                                 &edp_reg_override_debugfs_fops);
801
802         if (!d_edp_reg_override)
803                 goto edp_reg_override_err;
804
805         if (tegra_core_edp_debugfs_init(edp_dir))
806                 goto edp_reg_override_err;
807
808         return 0;
809
810 edp_reg_override_err:
811         debugfs_remove(d_edp_limit);
812 edp_limit_err:
813         debugfs_remove(d_edp);
814 edp_err:
815         debugfs_remove(vdd_cpu_dir);
816 vdd_cpu_dir_err:
817         debugfs_remove(edp_dir);
818 edp_dir_err:
819         return -ENOMEM;
820 }
821
822 late_initcall(tegra_edp_debugfs_init);
823 #endif /* CONFIG_DEBUG_FS */