arm: tegra: edp: table show support for T40DC
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26
27 #include <mach/edp.h>
28 #include <mach/hardware.h>
29
30 #include "fuse.h"
31 #include "dvfs.h"
32 #include "clock.h"
33 #include "cpu-tegra.h"
34
35 #define FREQ_STEP 12750000
36 #define OVERRIDE_DEFAULT 6000
37
38 static struct tegra_edp_limits *edp_limits;
39 static int edp_limits_size;
40 static unsigned int regulator_cur;
41 /* Value to subtract from regulator current limit */
42 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
43
44 static const unsigned int *system_edp_limits;
45
46 static struct tegra_system_edp_entry *power_edp_limits;
47 static int power_edp_limits_size;
48
49 /*
50  * "Safe entry" to be used when no match for speedo_id /
51  * regulator_cur is found; must be the last one
52  */
53 static struct tegra_edp_limits edp_default_limits[] = {
54         {85, {1000000, 1000000, 1000000, 1000000} },
55 };
56
57 static struct tegra_system_edp_entry power_edp_default_limits[] = {
58         {0, 20, {1000000, 1000000, 1000000, 1000000} },
59 };
60
61 /* Constants for EDP calculations */
62 static const int temperatures[] = { /* degree celcius (C) */
63         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
64 };
65
66 static const int power_cap_levels[] = { /* milliwatts (mW) */
67           500,  1000,  1500,  2000,  2500,  3000,  3500,
68          4000,  4500,  5000,  5500,  6000,  6500,  7000,
69          7500,  8000,  8500,  9000,  9500, 10000, 10500,
70         11000, 11500, 12000, 12500, 13000, 13500, 14000,
71         14500, 15000, 15500, 16000, 16500, 17000
72 };
73
74 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
75 static unsigned int freq_voltage_lut_size_saved;
76 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
77 static unsigned int freq_voltage_lut_size;
78
79 static inline s64 edp_pow(s64 val, int pwr)
80 {
81         s64 retval = 1;
82
83         while (val && pwr) {
84                 if (pwr & 1)
85                         retval *= val;
86                 pwr >>= 1;
87                 if (pwr)
88                         val *= val;
89         }
90
91         return retval;
92 }
93
94 /*
95  * Find the maximum frequency that results in dynamic and leakage current that
96  * is less than the regulator current limit.
97  * temp_C - always valid
98  * power_mW - valid or -1 (infinite)
99  */
100 static unsigned int edp_calculate_maxf(
101                                 struct tegra_edp_cpu_leakage_params *params,
102                                 int temp_C, int power_mW,
103                                 int iddq_mA,
104                                 int n_cores_idx)
105 {
106         unsigned int voltage_mV, freq_KHz;
107         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
108         int f, i, j, k;
109         s64 leakage_mA, dyn_mA, leakage_calc_step;
110         s64 leakage_mW, dyn_mW;
111
112         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
113                 freq_KHz = freq_voltage_lut[f].freq / 1000;
114                 voltage_mV = freq_voltage_lut[f].voltage_mV;
115
116                 /* Constrain Volt-Temp */
117                 if (params->volt_temp_cap.temperature &&
118                     temp_C > params->volt_temp_cap.temperature &&
119                     params->volt_temp_cap.voltage_limit_mV &&
120                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
121                         continue;
122
123                 /* Calculate leakage current */
124                 leakage_mA = 0;
125                 for (i = 0; i <= 3; i++) {
126                         for (j = 0; j <= 3; j++) {
127                                 for (k = 0; k <= 3; k++) {
128                                         leakage_calc_step =
129                                                 params->leakage_consts_ijk
130                                                 [i][j][k] * edp_pow(iddq_mA, i);
131                                         /* Convert (mA)^i to (A)^i */
132                                         leakage_calc_step =
133                                                 div64_s64(leakage_calc_step,
134                                                           edp_pow(1000, i));
135                                         leakage_calc_step *=
136                                                 edp_pow(voltage_mV, j);
137                                         /* Convert (mV)^j to (V)^j */
138                                         leakage_calc_step =
139                                                 div64_s64(leakage_calc_step,
140                                                           edp_pow(1000, j));
141                                         leakage_calc_step *=
142                                                 edp_pow(temp_C, k);
143                                         /* Convert (C)^k to (scaled_C)^k */
144                                         leakage_calc_step =
145                                                 div64_s64(leakage_calc_step,
146                                                 edp_pow(params->temp_scaled,
147                                                         k));
148                                         /* leakage_consts_ijk was scaled */
149                                         leakage_calc_step =
150                                                 div64_s64(leakage_calc_step,
151                                                           params->ijk_scaled);
152                                         leakage_mA += leakage_calc_step;
153                                 }
154                         }
155                 }
156
157                 /* if specified, set floor for leakage current */
158                 if (params->leakage_min && leakage_mA <= params->leakage_min)
159                         leakage_mA = params->leakage_min;
160
161                 /* leakage cannot be negative => leakage model has error */
162                 if (leakage_mA <= 0) {
163                         pr_err("VDD_CPU EDP failed: IDDQ too high (%d mA)\n",
164                                iddq_mA);
165                         return -EINVAL;
166                 }
167
168                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
169
170                 /* leakage_const_n was scaled */
171                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
172
173                 /* Calculate dynamic current */
174                 dyn_mA = voltage_mV * freq_KHz / 1000;
175                 /* Convert mV to V */
176                 dyn_mA = div64_s64(dyn_mA, 1000);
177                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
178                 /* dyn_const_n was scaled */
179                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
180
181                 if (power_mW != -1) {
182                         leakage_mW = leakage_mA * voltage_mV;
183                         dyn_mW = dyn_mA * voltage_mV;
184                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
185                                 return freq_KHz;
186                 } else if ((leakage_mA + dyn_mA) <= cur_effective) {
187                         return freq_KHz;
188                 }
189         }
190         return 0;
191 }
192
193 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
194                         unsigned int cpu_speedo_idx,
195                         unsigned int freq_volt_lut_size,
196                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
197 {
198         unsigned int i, j, freq;
199         int voltage_mV;
200
201         for (i = 0, j = 0, freq = 0;
202                  i < freq_volt_lut_size;
203                  i++, freq += FREQ_STEP) {
204
205                 /* Predict voltages */
206                 voltage_mV = tegra_dvfs_predict_millivolts(clk_cpu_g, freq);
207                 if (voltage_mV < 0) {
208                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
209                                __func__, freq, voltage_mV);
210                         return -EINVAL;
211                 }
212
213                 /* Cache frequency / voltage / voltage constant relationship */
214                 freq_volt_lut[i].freq = freq;
215                 freq_volt_lut[i].voltage_mV = voltage_mV;
216         }
217         return 0;
218 }
219
220 unsigned int tegra_edp_find_maxf(int volt)
221 {
222         unsigned int i;
223
224         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
225                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
226                         break;
227         }
228         return freq_voltage_lut[i - 1].freq;
229 }
230
231
232 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
233 {
234         int i, array_size;
235         struct tegra_edp_cpu_leakage_params *params;
236
237         switch (tegra_chip_id) {
238         case TEGRA_CHIPID_TEGRA11:
239                 params = tegra11x_get_leakage_params(0, &array_size);
240                 break;
241         case TEGRA_CHIPID_TEGRA14:
242                 params = tegra14x_get_leakage_params(0, &array_size);
243                 break;
244         case TEGRA_CHIPID_TEGRA3:
245         case TEGRA_CHIPID_TEGRA2:
246         default:
247                 array_size = 0;
248                 break;
249         }
250
251         for (i = 0; i < array_size; i++)
252                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
253                         *cpu_speedo_idx = i;
254                         return 0;
255                 }
256
257         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
258                __func__, cpu_speedo_id);
259         return -EINVAL;
260 }
261
262 static int init_cpu_edp_limits_calculated(void)
263 {
264         unsigned int max_nr_cpus = num_possible_cpus();
265         unsigned int temp_idx, n_cores_idx, pwr_idx;
266         unsigned int cpu_g_minf, cpu_g_maxf;
267         unsigned int iddq_mA;
268         unsigned int cpu_speedo_idx;
269         unsigned int cap, limit;
270         struct tegra_edp_limits *edp_calculated_limits;
271         struct tegra_system_edp_entry *power_edp_calc_limits;
272         struct tegra_edp_cpu_leakage_params *params;
273         int ret;
274         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
275         int cpu_speedo_id = tegra_cpu_speedo_id();
276
277         /* Determine all inputs to EDP formula */
278         iddq_mA = tegra_get_cpu_iddq_value();
279         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
280         if (ret)
281                 return ret;
282
283         switch (tegra_chip_id) {
284         case TEGRA_CHIPID_TEGRA11:
285                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
286                 break;
287         case TEGRA_CHIPID_TEGRA14:
288                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
289                 break;
290         case TEGRA_CHIPID_TEGRA3:
291         case TEGRA_CHIPID_TEGRA2:
292         default:
293                 return -EINVAL;
294         }
295
296         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
297                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
298         BUG_ON(!edp_calculated_limits);
299
300         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
301                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
302         BUG_ON(!power_edp_calc_limits);
303
304         cpu_g_minf = 0;
305         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
306         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
307         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
308                                    * freq_voltage_lut_size, GFP_KERNEL);
309         if (!freq_voltage_lut) {
310                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
311                 kfree(power_edp_calc_limits);
312                 kfree(edp_calculated_limits);
313                 return -ENOMEM;
314         }
315
316         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
317                                 freq_voltage_lut_size, freq_voltage_lut);
318         if (ret) {
319                 kfree(power_edp_calc_limits);
320                 kfree(edp_calculated_limits);
321                 kfree(freq_voltage_lut);
322                 return ret;
323         }
324
325         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
326                 /* release previous table if present */
327                 kfree(freq_voltage_lut_saved);
328                 /* create table to save */
329                 freq_voltage_lut_saved =
330                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
331                         freq_voltage_lut_size, GFP_KERNEL);
332                 if (!freq_voltage_lut_saved) {
333                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
334                                 __func__);
335                         kfree(freq_voltage_lut);
336                         return -ENOMEM;
337                 }
338                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
339         }
340         memcpy(freq_voltage_lut_saved,
341                 freq_voltage_lut,
342                 sizeof(struct tegra_edp_freq_voltage_table) *
343                         freq_voltage_lut_size);
344
345         /* Calculate EDP table */
346         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
347                 for (temp_idx = 0;
348                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
349                         edp_calculated_limits[temp_idx].temperature =
350                                 temperatures[temp_idx];
351                         limit = edp_calculate_maxf(params,
352                                                    temperatures[temp_idx],
353                                                    -1,
354                                                    iddq_mA,
355                                                    n_cores_idx);
356                         /* apply safety cap if it is specified */
357                         if (n_cores_idx < 4) {
358                                 cap = params->safety_cap[n_cores_idx];
359                                 if (cap && cap < limit)
360                                         limit = cap;
361                         }
362                         edp_calculated_limits[temp_idx].
363                                 freq_limits[n_cores_idx] = limit;
364                 }
365
366                 for (pwr_idx = 0;
367                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
368                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
369                                 power_cap_levels[pwr_idx] / 100;
370                         limit = edp_calculate_maxf(params,
371                                                    90,
372                                                    power_cap_levels[pwr_idx],
373                                                    iddq_mA,
374                                                    n_cores_idx);
375                         power_edp_calc_limits[pwr_idx].
376                                 freq_limits[n_cores_idx] = limit;
377                 }
378         }
379
380         /*
381          * If this is an EDP table update, need to overwrite old table.
382          * The old table's address must remain valid.
383          */
384         if (edp_limits != edp_default_limits) {
385                 memcpy(edp_limits, edp_calculated_limits,
386                        sizeof(struct tegra_edp_limits)
387                        * ARRAY_SIZE(temperatures));
388                 kfree(edp_calculated_limits);
389         }
390         else {
391                 edp_limits = edp_calculated_limits;
392                 edp_limits_size = ARRAY_SIZE(temperatures);
393         }
394
395         if (power_edp_limits != power_edp_default_limits) {
396                 memcpy(power_edp_limits, power_edp_calc_limits,
397                        sizeof(struct tegra_system_edp_entry)
398                        * ARRAY_SIZE(power_cap_levels));
399                 kfree(power_edp_calc_limits);
400         } else {
401                 power_edp_limits = power_edp_calc_limits;
402                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
403         }
404
405         kfree(freq_voltage_lut);
406         return 0;
407 }
408
409 void tegra_recalculate_cpu_edp_limits(void)
410 {
411         if (tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
412             tegra_chip_id == TEGRA_CHIPID_TEGRA14)
413                 init_cpu_edp_limits_calculated();
414 }
415
416 /*
417  * Specify regulator current in mA, e.g. 5000mA
418  * Use 0 for default
419  */
420 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
421 {
422         if (!regulator_mA)
423                 goto end;
424         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
425
426         switch (tegra_chip_id) {
427         case TEGRA_CHIPID_TEGRA11:
428         case TEGRA_CHIPID_TEGRA14:
429                 if (init_cpu_edp_limits_calculated() == 0)
430                         return;
431                 break;
432         case TEGRA_CHIPID_TEGRA2:
433         case TEGRA_CHIPID_TEGRA3:
434         default:
435                 BUG();
436                 break;
437         }
438
439  end:
440         edp_limits = edp_default_limits;
441         edp_limits_size = ARRAY_SIZE(edp_default_limits);
442
443         power_edp_limits = power_edp_default_limits;
444         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
445 }
446
447 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
448 {
449         *limits = edp_limits;
450         *size = edp_limits_size;
451 }
452
453 void tegra_get_system_edp_limits(const unsigned int **limits)
454 {
455         *limits = system_edp_limits;
456 }
457
458 void tegra_platform_edp_init(struct thermal_trip_info *trips,
459                                 int *num_trips, int margin)
460 {
461         const struct tegra_edp_limits *cpu_edp_limits;
462         struct thermal_trip_info *trip_state;
463         int i, cpu_edp_limits_size;
464
465         if (!trips || !num_trips)
466                 return;
467
468         /* edp capping */
469         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
470
471         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
472                 BUG();
473
474         for (i = 0; i < cpu_edp_limits_size-1; i++) {
475                 trip_state = &trips[*num_trips];
476
477                 trip_state->cdev_type = "cpu_edp";
478                 trip_state->trip_temp =
479                         (cpu_edp_limits[i].temperature * 1000) - margin;
480                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
481                 trip_state->upper = trip_state->lower = i + 1;
482
483                 (*num_trips)++;
484
485                 if (*num_trips >= THERMAL_MAX_TRIPS)
486                         BUG();
487         }
488 }
489
490 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
491 {
492         *size = power_edp_limits_size;
493         return power_edp_limits;
494 }
495
496 #ifdef CONFIG_DEBUG_FS
497
498 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
499 {
500 #ifdef CONFIG_CPU_FREQ
501         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
502 #endif
503         return 0;
504 }
505
506 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
507 {
508         int i;
509
510         seq_printf(s, "%6s %10s %10s %10s %10s\n",
511                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
512         for (i = 0; i < edp_limits_size; i++) {
513                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
514                            i == th_idx ? '>' : ' ',
515                            edp_limits[i].temperature,
516                            edp_limits[i].freq_limits[0],
517                            edp_limits[i].freq_limits[1],
518                            edp_limits[i].freq_limits[2],
519                            edp_limits[i].freq_limits[3]);
520         }
521 }
522
523 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
524 {
525         int i;
526
527         seq_printf(s, "%6s %10s %10s\n",
528                    " Temp.", "1-core", "2-cores");
529         for (i = 0; i < edp_limits_size; i++) {
530                 seq_printf(s, "%c%3dC: %10u %10u\n",
531                            i == th_idx ? '>' : ' ',
532                            edp_limits[i].temperature,
533                            edp_limits[i].freq_limits[0],
534                            edp_limits[i].freq_limits[1]);
535         }
536 }
537
538 static inline void edp_show_2core_system_table(struct seq_file *s)
539 {
540         seq_printf(s, "%10u %10u\n",
541                    system_edp_limits[0],
542                    system_edp_limits[1]);
543 }
544
545 static inline void edp_show_4core_system_table(struct seq_file *s)
546 {
547         seq_printf(s, "%10u %10u %10u %10u\n",
548                    system_edp_limits[0],
549                    system_edp_limits[1],
550                    system_edp_limits[2],
551                    system_edp_limits[3]);
552 }
553
554 static int edp_debugfs_show(struct seq_file *s, void *data)
555 {
556         unsigned int max_nr_cpus = num_possible_cpus();
557         int th_idx;
558
559         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
560                 seq_printf(s, "Unsupported number of CPUs\n");
561                 return 0;
562         }
563
564 #ifdef CONFIG_CPU_FREQ
565         tegra_get_edp_limit(&th_idx);
566 #else
567         th_idx = 0;
568 #endif
569
570         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
571                    edp_limits == edp_default_limits ? "**default** " : "",
572                    regulator_cur - edp_reg_override_mA,
573                    regulator_cur, edp_reg_override_mA);
574
575         if (max_nr_cpus == 2)
576                 edp_show_2core_edp_table(s, th_idx);
577         else if (max_nr_cpus == 4)
578                 edp_show_4core_edp_table(s, th_idx);
579
580         if (system_edp_limits) {
581                 seq_printf(s, "\n-- System EDP table --\n");
582                 if (max_nr_cpus == 2)
583                         edp_show_2core_system_table(s);
584                 else if (max_nr_cpus == 4)
585                         edp_show_4core_system_table(s);
586         }
587
588         return 0;
589 }
590
591 static int edp_reg_override_show(struct seq_file *s, void *data)
592 {
593         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
594                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
595         return 0;
596 }
597
598 static int edp_reg_override_write(struct file *file,
599         const char __user *userbuf, size_t count, loff_t *ppos)
600 {
601         char buf[32], *end;
602         unsigned int edp_reg_override_mA_temp;
603         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
604
605         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
606                 tegra_chip_id == TEGRA_CHIPID_TEGRA14))
607                 goto override_err;
608
609         if (sizeof(buf) <= count)
610                 goto override_err;
611
612         if (copy_from_user(buf, userbuf, count))
613                 goto override_err;
614
615         /* terminate buffer and trim - white spaces may be appended
616          *  at the end when invoked from shell command line */
617         buf[count]='\0';
618         strim(buf);
619
620         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
621         if (*end != '\0')
622                 goto override_err;
623
624         if (edp_reg_override_mA_temp >= regulator_cur)
625                 goto override_err;
626
627         if (edp_reg_override_mA == edp_reg_override_mA_temp)
628                 return count;
629
630         edp_reg_override_mA = edp_reg_override_mA_temp;
631         if (init_cpu_edp_limits_calculated()) {
632                 /* Revert to previous override value if new value fails */
633                 edp_reg_override_mA = edp_reg_override_mA_prev;
634                 goto override_err;
635         }
636
637 #ifdef CONFIG_CPU_FREQ
638         if (tegra_cpu_set_speed_cap(NULL)) {
639                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
640                 goto override_out;
641         }
642
643         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
644                         " %u mA\n", regulator_cur - edp_reg_override_mA);
645 #else
646         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
647 #endif
648
649         return count;
650
651 override_err:
652         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
653                buf);
654 #ifdef CONFIG_CPU_FREQ
655 override_out:
656 #endif
657         return -EINVAL;
658 }
659
660 static int edp_debugfs_open(struct inode *inode, struct file *file)
661 {
662         return single_open(file, edp_debugfs_show, inode->i_private);
663 }
664
665 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
666 {
667         return single_open(file, edp_limit_debugfs_show, inode->i_private);
668 }
669
670 static int edp_reg_override_open(struct inode *inode, struct file *file)
671 {
672         return single_open(file, edp_reg_override_show, inode->i_private);
673 }
674
675 static const struct file_operations edp_debugfs_fops = {
676         .open           = edp_debugfs_open,
677         .read           = seq_read,
678         .llseek         = seq_lseek,
679         .release        = single_release,
680 };
681
682 static const struct file_operations edp_limit_debugfs_fops = {
683         .open           = edp_limit_debugfs_open,
684         .read           = seq_read,
685         .llseek         = seq_lseek,
686         .release        = single_release,
687 };
688
689 static const struct file_operations edp_reg_override_debugfs_fops = {
690         .open           = edp_reg_override_open,
691         .read           = seq_read,
692         .write          = edp_reg_override_write,
693         .llseek         = seq_lseek,
694         .release        = single_release,
695 };
696
697 #ifdef CONFIG_EDP_FRAMEWORK
698 static __init struct dentry *tegra_edp_debugfs_dir(void)
699 {
700         return edp_debugfs_dir;
701 }
702 #else
703 static __init struct dentry *tegra_edp_debugfs_dir(void)
704 {
705         return debugfs_create_dir("edp", NULL);
706 }
707 #endif
708
709 static int __init tegra_edp_debugfs_init(void)
710 {
711         struct dentry *d_edp;
712         struct dentry *d_edp_limit;
713         struct dentry *d_edp_reg_override;
714         struct dentry *edp_dir;
715         struct dentry *vdd_cpu_dir;
716
717         edp_dir = tegra_edp_debugfs_dir();
718
719         if (!edp_dir)
720                 goto edp_dir_err;
721
722         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
723
724         if (!vdd_cpu_dir)
725                 goto vdd_cpu_dir_err;
726
727         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
728                                 &edp_debugfs_fops);
729
730         if (!d_edp)
731                 goto edp_err;
732
733         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
734                                 NULL, &edp_limit_debugfs_fops);
735
736         if (!d_edp_limit)
737                 goto edp_limit_err;
738
739         d_edp_reg_override = debugfs_create_file("edp_reg_override",
740                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
741                                 &edp_reg_override_debugfs_fops);
742
743         if (!d_edp_reg_override)
744                 goto edp_reg_override_err;
745
746         if (tegra_core_edp_debugfs_init(edp_dir))
747                 goto edp_reg_override_err;
748
749         return 0;
750
751 edp_reg_override_err:
752         debugfs_remove(d_edp_limit);
753 edp_limit_err:
754         debugfs_remove(d_edp);
755 edp_err:
756         debugfs_remove(vdd_cpu_dir);
757 vdd_cpu_dir_err:
758         debugfs_remove(edp_dir);
759 edp_dir_err:
760         return -ENOMEM;
761 }
762
763 late_initcall(tegra_edp_debugfs_init);
764 #endif /* CONFIG_DEBUG_FS */