arm: tegra: add support for GPU EDP
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/tegra-fuse.h>
30
31 #include <mach/edp.h>
32
33 #include "dvfs.h"
34 #include "clock.h"
35 #include "cpu-tegra.h"
36 #include "common.h"
37
38 #define FREQ_STEP 12750000
39 #define OVERRIDE_DEFAULT 6000
40
41 #define GPU_FREQ_STEP 12000000
42
43 static struct tegra_edp_limits *edp_limits;
44 static int edp_limits_size;
45 static unsigned int regulator_cur;
46 /* Value to subtract from regulator current limit */
47 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
48
49 static struct tegra_edp_limits *reg_idle_edp_limits;
50 static int reg_idle_cur;
51
52 static const unsigned int *system_edp_limits;
53
54 static struct tegra_system_edp_entry *power_edp_limits;
55 static int power_edp_limits_size;
56
57 /*
58  * "Safe entry" to be used when no match for speedo_id /
59  * regulator_cur is found; must be the last one
60  */
61 static struct tegra_edp_limits edp_default_limits[] = {
62         {85, {1000000, 1000000, 1000000, 1000000} },
63 };
64
65 static struct tegra_system_edp_entry power_edp_default_limits[] = {
66         {0, 20, {1000000, 1000000, 1000000, 1000000} },
67 };
68
69 /* Constants for EDP calculations */
70 static const int temperatures[] = { /* degree celcius (C) */
71         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
72 };
73
74 static const int power_cap_levels[] = { /* milliwatts (mW) */
75           500,  1000,  1500,  2000,  2500,  3000,  3500,
76          4000,  4500,  5000,  5500,  6000,  6500,  7000,
77          7500,  8000,  8500,  9000,  9500, 10000, 10500,
78         11000, 11500, 12000, 12500, 13000, 13500, 14000,
79         14500, 15000, 15500, 16000, 16500, 17000
80 };
81
82 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
83 static unsigned int freq_voltage_lut_size_saved;
84 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
85 static unsigned int freq_voltage_lut_size;
86
87 #ifdef CONFIG_TEGRA_GPU_EDP
88 static struct tegra_edp_gpu_limits *edp_gpu_limits;
89 static int edp_gpu_limits_size;
90 static int edp_gpu_thermal_idx;
91 static struct clk *gpu_cap_clk;
92 static DEFINE_MUTEX(gpu_edp_lock);
93
94 static struct tegra_edp_freq_voltage_table *freq_voltage_gpu_lut;
95 static unsigned int freq_voltage_gpu_lut_size;
96
97 static unsigned int gpu_regulator_cur;
98
99 static struct tegra_edp_gpu_limits edp_gpu_default_limits[] = {
100         {85, 350000},
101 };
102
103 static const int gpu_temperatures[] = { /* degree celcius (C) */
104         20, 50, 70, 75, 80, 85, 90, 95, 100, 105,
105 };
106 #endif
107
108 static inline s64 edp_pow(s64 val, int pwr)
109 {
110         s64 retval = 1;
111
112         while (val && pwr) {
113                 if (pwr & 1)
114                         retval *= val;
115                 pwr >>= 1;
116                 if (pwr)
117                         val *= val;
118         }
119
120         return retval;
121 }
122
123
124 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
125 static inline unsigned int edp_apply_fixed_limits(
126                                 unsigned int in_freq_KHz,
127                                 struct tegra_edp_cpu_leakage_params *params,
128                                 unsigned int cur_effective,
129                                 int temp_C, int n_cores_idx)
130 {
131         unsigned int out_freq_KHz = in_freq_KHz;
132         unsigned int max_cur, max_temp, max_freq;
133         int i;
134
135         /* Apply any additional fixed limits */
136         for (i = 0; i < 8; i++) {
137                 max_cur = params->max_current_cap[i].max_cur;
138                 if (max_cur != 0 && cur_effective <= max_cur) {
139                         max_temp = params->max_current_cap[i].max_temp;
140                         if (max_temp != 0 && temp_C > max_temp) {
141                                 max_freq = params->max_current_cap[i].
142                                         max_freq[n_cores_idx];
143                                 if (max_freq && max_freq < out_freq_KHz)
144                                         out_freq_KHz = max_freq;
145                         }
146                 }
147         }
148
149         return out_freq_KHz;
150 }
151 #else
152 #define edp_apply_fixed_limits(freq, unused...) (freq)
153 #endif
154
155 /*
156  * Find the maximum frequency that results in dynamic and leakage current that
157  * is less than the regulator current limit.
158  * temp_C - valid or -EINVAL
159  * power_mW - valid or -1 (infinite) or -EINVAL
160  */
161 static unsigned int edp_calculate_maxf(
162                                 struct tegra_edp_cpu_leakage_params *params,
163                                 int temp_C, int power_mW, unsigned int cur_mA,
164                                 int iddq_mA,
165                                 int n_cores_idx)
166 {
167         unsigned int voltage_mV, freq_KHz = 0;
168         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
169         int f, i, j, k;
170         s64 leakage_mA, dyn_mA, leakage_calc_step;
171         s64 leakage_mW, dyn_mW;
172
173         /* If current limit is not specified, use max by default */
174         cur_mA = cur_mA ? : cur_effective;
175
176         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
177                 freq_KHz = freq_voltage_lut[f].freq / 1000;
178                 voltage_mV = freq_voltage_lut[f].voltage_mV;
179
180                 /* Constrain Volt-Temp */
181                 if (params->volt_temp_cap.temperature &&
182                     temp_C > params->volt_temp_cap.temperature &&
183                     params->volt_temp_cap.voltage_limit_mV &&
184                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
185                         continue;
186
187                 /* Calculate leakage current */
188                 leakage_mA = 0;
189                 for (i = 0; i <= 3; i++) {
190                         for (j = 0; j <= 3; j++) {
191                                 for (k = 0; k <= 3; k++) {
192                                         leakage_calc_step =
193                                                 params->leakage_consts_ijk
194                                                 [i][j][k] * edp_pow(iddq_mA, i);
195                                         /* Convert (mA)^i to (A)^i */
196                                         leakage_calc_step =
197                                                 div64_s64(leakage_calc_step,
198                                                           edp_pow(1000, i));
199                                         leakage_calc_step *=
200                                                 edp_pow(voltage_mV, j);
201                                         /* Convert (mV)^j to (V)^j */
202                                         leakage_calc_step =
203                                                 div64_s64(leakage_calc_step,
204                                                           edp_pow(1000, j));
205                                         leakage_calc_step *=
206                                                 edp_pow(temp_C, k);
207                                         /* Convert (C)^k to (scaled_C)^k */
208                                         leakage_calc_step =
209                                                 div64_s64(leakage_calc_step,
210                                                 edp_pow(params->temp_scaled,
211                                                         k));
212                                         /* leakage_consts_ijk was scaled */
213                                         leakage_calc_step =
214                                                 div64_s64(leakage_calc_step,
215                                                           params->ijk_scaled);
216                                         leakage_mA += leakage_calc_step;
217                                 }
218                         }
219                 }
220
221                 /* set floor for leakage current */
222                 if (leakage_mA <= params->leakage_min)
223                         leakage_mA = params->leakage_min;
224
225                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
226
227                 /* leakage_const_n was scaled */
228                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
229
230                 /* Calculate dynamic current */
231                 dyn_mA = voltage_mV * freq_KHz / 1000;
232                 /* Convert mV to V */
233                 dyn_mA = div64_s64(dyn_mA, 1000);
234                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
235                 /* dyn_const_n was scaled */
236                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
237
238                 if (power_mW != -1) {
239                         leakage_mW = leakage_mA * voltage_mV;
240                         dyn_mW = dyn_mA * voltage_mV;
241                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
242                                 goto end;
243                 } else if ((leakage_mA + dyn_mA) <= cur_mA) {
244                         goto end;
245                 }
246                 freq_KHz = 0;
247         }
248
249  end:
250         return edp_apply_fixed_limits(freq_KHz, params,
251                                         cur_effective, temp_C, n_cores_idx);
252 }
253
254 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
255                         unsigned int cpu_speedo_idx,
256                         unsigned int freq_volt_lut_size,
257                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
258 {
259         unsigned int i, j, freq;
260         int voltage_mV;
261
262         for (i = 0, j = 0, freq = 0;
263                  i < freq_volt_lut_size;
264                  i++, freq += FREQ_STEP) {
265
266                 /* Predict voltages */
267                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
268                         clk_cpu_g, freq);
269                 if (voltage_mV < 0) {
270                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
271                                __func__, freq, voltage_mV);
272                         return -EINVAL;
273                 }
274
275                 /* Cache frequency / voltage / voltage constant relationship */
276                 freq_volt_lut[i].freq = freq;
277                 freq_volt_lut[i].voltage_mV = voltage_mV;
278         }
279         return 0;
280 }
281
282 unsigned int tegra_edp_find_maxf(int volt)
283 {
284         unsigned int i;
285
286         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
287                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
288                         break;
289         }
290         return freq_voltage_lut[i - 1].freq;
291 }
292
293
294 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
295 {
296         int i, array_size;
297         struct tegra_edp_cpu_leakage_params *params;
298
299         switch (tegra_get_chip_id()) {
300         case TEGRA_CHIPID_TEGRA11:
301                 params = tegra11x_get_leakage_params(0, &array_size);
302                 break;
303         case TEGRA_CHIPID_TEGRA14:
304                 params = tegra14x_get_leakage_params(0, &array_size);
305                 break;
306         case TEGRA_CHIPID_TEGRA12:
307                 params = tegra12x_get_leakage_params(0, &array_size);
308                 break;
309         case TEGRA_CHIPID_TEGRA3:
310         case TEGRA_CHIPID_TEGRA2:
311         default:
312                 array_size = 0;
313                 break;
314         }
315
316         for (i = 0; i < array_size; i++)
317                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
318                         *cpu_speedo_idx = i;
319                         return 0;
320                 }
321
322         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
323                __func__, cpu_speedo_id);
324         return -EINVAL;
325 }
326
327 static int init_cpu_edp_limits_calculated(void)
328 {
329         unsigned int max_nr_cpus = num_possible_cpus();
330         unsigned int temp_idx, n_cores_idx, pwr_idx;
331         unsigned int cpu_g_minf, cpu_g_maxf;
332         unsigned int iddq_mA;
333         unsigned int cpu_speedo_idx;
334         unsigned int cap, limit;
335         struct tegra_edp_limits *edp_calculated_limits;
336         struct tegra_edp_limits *reg_idle_calc_limits;
337         struct tegra_system_edp_entry *power_edp_calc_limits;
338         struct tegra_edp_cpu_leakage_params *params;
339         int ret;
340         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
341         int cpu_speedo_id = tegra_cpu_speedo_id();
342         int idle_cur = reg_idle_cur;
343
344         /* Determine all inputs to EDP formula */
345         iddq_mA = tegra_get_cpu_iddq_value();
346         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
347         if (ret)
348                 return ret;
349
350         switch (tegra_get_chip_id()) {
351         case TEGRA_CHIPID_TEGRA11:
352                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
353                 break;
354         case TEGRA_CHIPID_TEGRA14:
355                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
356                 break;
357         case TEGRA_CHIPID_TEGRA12:
358                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
359                 break;
360         case TEGRA_CHIPID_TEGRA3:
361         case TEGRA_CHIPID_TEGRA2:
362         default:
363                 return -EINVAL;
364         }
365
366         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
367                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
368         BUG_ON(!edp_calculated_limits);
369
370         reg_idle_calc_limits = kmalloc(sizeof(struct tegra_edp_limits)
371                                        * ARRAY_SIZE(temperatures), GFP_KERNEL);
372         BUG_ON(!reg_idle_calc_limits);
373
374         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
375                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
376         BUG_ON(!power_edp_calc_limits);
377
378         cpu_g_minf = 0;
379         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
380         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
381         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
382                                    * freq_voltage_lut_size, GFP_KERNEL);
383         if (!freq_voltage_lut) {
384                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
385                 kfree(power_edp_calc_limits);
386                 kfree(reg_idle_calc_limits);
387                 kfree(edp_calculated_limits);
388                 return -ENOMEM;
389         }
390
391         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
392                                 freq_voltage_lut_size, freq_voltage_lut);
393         if (ret) {
394                 kfree(power_edp_calc_limits);
395                 kfree(reg_idle_calc_limits);
396                 kfree(edp_calculated_limits);
397                 kfree(freq_voltage_lut);
398                 return ret;
399         }
400
401         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
402                 /* release previous table if present */
403                 kfree(freq_voltage_lut_saved);
404                 /* create table to save */
405                 freq_voltage_lut_saved =
406                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
407                         freq_voltage_lut_size, GFP_KERNEL);
408                 if (!freq_voltage_lut_saved) {
409                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
410                                 __func__);
411                         kfree(freq_voltage_lut);
412                         return -ENOMEM;
413                 }
414                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
415         }
416         memcpy(freq_voltage_lut_saved,
417                 freq_voltage_lut,
418                 sizeof(struct tegra_edp_freq_voltage_table) *
419                         freq_voltage_lut_size);
420
421         /* Calculate EDP table */
422         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
423                 for (temp_idx = 0;
424                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
425                         edp_calculated_limits[temp_idx].temperature =
426                                 temperatures[temp_idx];
427                         limit = edp_calculate_maxf(params,
428                                                    temperatures[temp_idx],
429                                                    -1,
430                                                    0,
431                                                    iddq_mA,
432                                                    n_cores_idx);
433                         if (limit == -EINVAL)
434                                 return -EINVAL;
435                         /* apply safety cap if it is specified */
436                         if (n_cores_idx < 4) {
437                                 cap = params->safety_cap[n_cores_idx];
438                                 if (cap && cap < limit)
439                                         limit = cap;
440                         }
441                         edp_calculated_limits[temp_idx].
442                                 freq_limits[n_cores_idx] = limit;
443
444                         /* regulator mode threshold */
445                         if (!idle_cur)
446                                 continue;
447                         reg_idle_calc_limits[temp_idx].temperature =
448                                 temperatures[temp_idx];
449                         limit = edp_calculate_maxf(params,
450                                                    temperatures[temp_idx],
451                                                    -1,
452                                                    idle_cur,
453                                                    iddq_mA,
454                                                    n_cores_idx);
455
456                         /* remove idle table if any threshold is invalid */
457                         if (limit == -EINVAL) {
458                                 pr_warn("%s: Invalid idle limit for %dmA\n",
459                                         __func__, idle_cur);
460                                 idle_cur = 0;
461                                 continue;
462                         }
463
464                         /* No mode change below G CPU minimum rate */
465                         if (limit < clk_get_min_rate(clk_cpu_g) / 1000)
466                                 limit = 0;
467                         reg_idle_calc_limits[temp_idx].
468                                 freq_limits[n_cores_idx] = limit;
469                 }
470
471                 for (pwr_idx = 0;
472                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
473                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
474                                 power_cap_levels[pwr_idx] / 100;
475                         limit = edp_calculate_maxf(params,
476                                                    90,
477                                                    power_cap_levels[pwr_idx],
478                                                    0,
479                                                    iddq_mA,
480                                                    n_cores_idx);
481                         if (limit == -EINVAL)
482                                 return -EINVAL;
483                         power_edp_calc_limits[pwr_idx].
484                                 freq_limits[n_cores_idx] = limit;
485                 }
486         }
487
488         /*
489          * If this is an EDP table update, need to overwrite old table.
490          * The old table's address must remain valid.
491          */
492         if (edp_limits != edp_default_limits) {
493                 memcpy(edp_limits, edp_calculated_limits,
494                        sizeof(struct tegra_edp_limits)
495                        * ARRAY_SIZE(temperatures));
496                 kfree(edp_calculated_limits);
497         } else {
498                 edp_limits = edp_calculated_limits;
499                 edp_limits_size = ARRAY_SIZE(temperatures);
500         }
501
502         if (idle_cur && reg_idle_edp_limits) {
503                 memcpy(reg_idle_edp_limits, reg_idle_calc_limits,
504                        sizeof(struct tegra_edp_limits)
505                        * ARRAY_SIZE(temperatures));
506                 kfree(reg_idle_calc_limits);
507         } else if (idle_cur) {
508                 reg_idle_edp_limits = reg_idle_calc_limits;
509         } else {
510                 kfree(reg_idle_edp_limits);
511                 kfree(reg_idle_calc_limits);
512                 reg_idle_edp_limits = NULL;
513         }
514
515         if (power_edp_limits != power_edp_default_limits) {
516                 memcpy(power_edp_limits, power_edp_calc_limits,
517                        sizeof(struct tegra_system_edp_entry)
518                        * ARRAY_SIZE(power_cap_levels));
519                 kfree(power_edp_calc_limits);
520         } else {
521                 power_edp_limits = power_edp_calc_limits;
522                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
523         }
524
525         kfree(freq_voltage_lut);
526         return 0;
527 }
528
529 void tegra_recalculate_cpu_edp_limits(void)
530 {
531         u32 tegra_chip_id;
532
533         tegra_chip_id = tegra_get_chip_id();
534         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
535             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
536             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
537                 return;
538
539         if (init_cpu_edp_limits_calculated() == 0)
540                 return;
541
542         /* Revert to default EDP table on error */
543         edp_limits = edp_default_limits;
544         edp_limits_size = ARRAY_SIZE(edp_default_limits);
545
546         power_edp_limits = power_edp_default_limits;
547         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
548
549         kfree(reg_idle_edp_limits);
550         reg_idle_edp_limits = NULL;
551         pr_err("%s: Failed to recalculate EDP limits\n", __func__);
552 }
553
554 /*
555  * Specify regulator current in mA, e.g. 5000mA
556  * Use 0 for default
557  */
558 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
559 {
560         if (!regulator_mA)
561                 goto end;
562         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
563
564         switch (tegra_get_chip_id()) {
565         case TEGRA_CHIPID_TEGRA11:
566         case TEGRA_CHIPID_TEGRA14:
567         case TEGRA_CHIPID_TEGRA12:
568                 if (init_cpu_edp_limits_calculated() == 0)
569                         return;
570                 break;
571         case TEGRA_CHIPID_TEGRA2:
572         case TEGRA_CHIPID_TEGRA3:
573         default:
574                 BUG();
575                 break;
576         }
577
578  end:
579         edp_limits = edp_default_limits;
580         edp_limits_size = ARRAY_SIZE(edp_default_limits);
581
582         power_edp_limits = power_edp_default_limits;
583         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
584 }
585
586 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
587 {
588         *limits = edp_limits;
589         *size = edp_limits_size;
590 }
591
592 void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
593                                            unsigned int mode)
594 {
595         if (mode == REGULATOR_MODE_IDLE) {
596                 reg_idle_cur = regulator_mA;
597                 return;
598         }
599         pr_err("%s: Not supported regulator mode 0x%x\n", __func__, mode);
600 }
601
602 void tegra_get_cpu_reg_mode_limits(const struct tegra_edp_limits **limits,
603                                    int *size, unsigned int mode)
604 {
605         if (mode == REGULATOR_MODE_IDLE) {
606                 *limits = reg_idle_edp_limits;
607                 *size = edp_limits_size;
608         } else {
609                 *limits = NULL;
610                 *size = 0;
611         }
612 }
613
614 void tegra_get_system_edp_limits(const unsigned int **limits)
615 {
616         *limits = system_edp_limits;
617 }
618
619 void tegra_platform_edp_init(struct thermal_trip_info *trips,
620                                 int *num_trips, int margin)
621 {
622         const struct tegra_edp_limits *cpu_edp_limits;
623         struct thermal_trip_info *trip_state;
624         int i, cpu_edp_limits_size;
625
626         if (!trips || !num_trips)
627                 return;
628
629         /* edp capping */
630         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
631
632         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
633                 BUG();
634
635         for (i = 0; i < cpu_edp_limits_size-1; i++) {
636                 trip_state = &trips[*num_trips];
637
638                 trip_state->cdev_type = "cpu_edp";
639                 trip_state->trip_temp =
640                         (cpu_edp_limits[i].temperature * 1000) - margin;
641                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
642                 trip_state->upper = trip_state->lower = i + 1;
643
644                 (*num_trips)++;
645
646                 if (*num_trips >= THERMAL_MAX_TRIPS)
647                         BUG();
648         }
649 }
650
651 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
652 {
653         *size = power_edp_limits_size;
654         return power_edp_limits;
655 }
656
657
658 #ifdef CONFIG_TEGRA_GPU_EDP
659 void tegra_get_gpu_edp_limits(const struct tegra_edp_gpu_limits **limits,
660                                                         int *size)
661 {
662         *limits = edp_gpu_limits;
663         *size = edp_gpu_limits_size;
664 }
665
666 void tegra_platform_gpu_edp_init(struct thermal_trip_info *trips,
667                                 int *num_trips, int margin)
668 {
669         const struct tegra_edp_gpu_limits *gpu_edp_limits;
670         struct thermal_trip_info *trip_state;
671         int i, gpu_edp_limits_size;
672
673         if (!trips || !num_trips)
674                 return;
675
676         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
677
678         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
679                 BUG();
680
681         for (i = 0; i < gpu_edp_limits_size-1; i++) {
682                 trip_state = &trips[*num_trips];
683
684                 trip_state->cdev_type = "gpu_edp";
685                 trip_state->trip_temp =
686                         (gpu_edp_limits[i].temperature * 1000) - margin;
687                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
688                 trip_state->upper = trip_state->lower = i + 1;
689
690                 (*num_trips)++;
691
692                 if (*num_trips >= THERMAL_MAX_TRIPS)
693                         BUG();
694         }
695 }
696
697 static unsigned int edp_gpu_calculate_maxf(
698                                 struct tegra_edp_gpu_leakage_params *params,
699                                 int temp_C, int iddq_mA)
700 {
701         unsigned int voltage_mV, freq_KHz = 0;
702         unsigned int cur_effective = gpu_regulator_cur;
703         int f, i, j, k;
704         s64 leakage_mA, dyn_mA, leakage_calc_step;
705
706         for (f = freq_voltage_gpu_lut_size - 1; f >= 0; f--) {
707                 freq_KHz = freq_voltage_gpu_lut[f].freq / 1000;
708                 voltage_mV = freq_voltage_gpu_lut[f].voltage_mV;
709
710                 /* Calculate leakage current */
711                 leakage_mA = 0;
712                 for (i = 0; i <= 3; i++) {
713                         for (j = 0; j <= 3; j++) {
714                                 for (k = 0; k <= 3; k++) {
715                                         leakage_calc_step =
716                                                 params->leakage_consts_ijk
717                                                 [i][j][k] * edp_pow(iddq_mA, i);
718
719                                         /* Convert (mA)^i to (A)^i */
720                                         leakage_calc_step =
721                                                 div64_s64(leakage_calc_step,
722                                                           edp_pow(1000, i));
723                                         leakage_calc_step *=
724                                                 edp_pow(voltage_mV, j);
725
726                                         /* Convert (mV)^j to (V)^j */
727                                         leakage_calc_step =
728                                                 div64_s64(leakage_calc_step,
729                                                           edp_pow(1000, j));
730                                         leakage_calc_step *=
731                                                 edp_pow(temp_C, k);
732
733                                         /* Convert (C)^k to (scaled_C)^k */
734                                         leakage_calc_step =
735                                                 div64_s64(leakage_calc_step,
736                                                 edp_pow(params->temp_scaled,
737                                                         k));
738
739                                         /* leakage_consts_ijk was scaled */
740                                         leakage_calc_step =
741                                                 div64_s64(leakage_calc_step,
742                                                           params->ijk_scaled);
743
744                                         leakage_mA += leakage_calc_step;
745                                 }
746                         }
747                 }
748                 /* set floor for leakage current */
749                 if (leakage_mA <= params->leakage_min)
750                         leakage_mA = params->leakage_min;
751
752                 /* Calculate dynamic current */
753
754                 dyn_mA = voltage_mV * freq_KHz / 1000;
755                 /* Convert mV to V */
756                 dyn_mA = div64_s64(dyn_mA, 1000);
757                 dyn_mA *= params->dyn_consts_n;
758                 /* dyn_const_n was scaled */
759                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
760
761                 if ((leakage_mA + dyn_mA) <= cur_effective)
762                         goto end;
763
764                 freq_KHz = 0;
765         }
766
767  end:
768         return freq_KHz;
769 }
770
771 static int __init start_gpu_edp(void)
772 {
773         const char *cap_name = "edp.gbus";
774
775         gpu_cap_clk = tegra_get_clock_by_name(cap_name);
776         if (!gpu_cap_clk) {
777                 pr_err("gpu_edp_set_cdev_state: cannot get clock:%s\n",
778                                 cap_name);
779                 return -EINVAL;
780         }
781         edp_gpu_thermal_idx = 0;
782
783         return 0;
784 }
785
786
787 static int edp_gpu_relate_freq_voltage(struct clk *clk_gpu,
788                         unsigned int freq_volt_lut_size,
789                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
790 {
791         unsigned int i, j, freq;
792         int voltage_mV;
793
794         for (i = 0, j = 0, freq = 0;
795                  i < freq_volt_lut_size;
796                  i++, freq += GPU_FREQ_STEP) {
797
798                 /* Predict voltages */
799                 voltage_mV = tegra_dvfs_predict_peak_millivolts(clk_gpu, freq);
800                 if (voltage_mV < 0) {
801                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
802                                __func__, freq, voltage_mV);
803                         return -EINVAL;
804                 }
805
806                 /* Cache frequency / voltage / voltage constant relationship */
807                 freq_volt_lut[i].freq = freq;
808                 freq_volt_lut[i].voltage_mV = voltage_mV;
809         }
810         return 0;
811 }
812
813 static int init_gpu_edp_limits_calculated(void)
814 {
815         unsigned int temp_idx;
816         unsigned int gpu_minf, gpu_maxf;
817         unsigned int limit;
818         struct tegra_edp_gpu_limits *edp_gpu_calculated_limits;
819         struct tegra_edp_gpu_limits *temp;
820         struct tegra_edp_gpu_leakage_params *params;
821         int ret;
822         unsigned int gpu_iddq_mA;
823         u32 tegra_chip_id;
824         struct clk *gpu_clk = clk_get_parent(gpu_cap_clk);
825         tegra_chip_id = tegra_get_chip_id();
826
827         if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
828                 gpu_iddq_mA = tegra_get_gpu_iddq_value();
829                 params = tegra12x_get_gpu_leakage_params();
830         } else
831                 return -EINVAL;
832
833         edp_gpu_calculated_limits = kmalloc(sizeof(struct tegra_edp_gpu_limits)
834                                 * ARRAY_SIZE(gpu_temperatures), GFP_KERNEL);
835         BUG_ON(!edp_gpu_calculated_limits);
836
837         gpu_minf = 0;
838         gpu_maxf = clk_get_max_rate(gpu_clk);
839
840         freq_voltage_gpu_lut_size = (gpu_maxf - gpu_minf) / GPU_FREQ_STEP + 1;
841         freq_voltage_gpu_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
842                                    * freq_voltage_gpu_lut_size, GFP_KERNEL);
843         if (!freq_voltage_gpu_lut) {
844                 pr_err("%s: failed alloc mem for gpu freq/voltage LUT\n",
845                          __func__);
846                 kfree(edp_gpu_calculated_limits);
847                 return -ENOMEM;
848         }
849
850         ret = edp_gpu_relate_freq_voltage(gpu_clk,
851                         freq_voltage_gpu_lut_size, freq_voltage_gpu_lut);
852
853         if (ret) {
854                 kfree(edp_gpu_calculated_limits);
855                 kfree(freq_voltage_gpu_lut);
856                 return ret;
857         }
858
859         for (temp_idx = 0;
860                      temp_idx < ARRAY_SIZE(gpu_temperatures); temp_idx++) {
861                         edp_gpu_calculated_limits[temp_idx].temperature =
862                                 gpu_temperatures[temp_idx];
863                         limit = edp_gpu_calculate_maxf(params,
864                                                    gpu_temperatures[temp_idx],
865                                                    gpu_iddq_mA);
866                         if (limit == -EINVAL)
867                                 return -EINVAL;
868                         edp_gpu_calculated_limits[temp_idx].freq_limits = limit;
869         }
870
871         /*
872          * If this is an EDP table update, need to overwrite old table.
873          * The old table's address must remain valid.
874          */
875         if (edp_gpu_limits != edp_gpu_default_limits &&
876                         edp_gpu_limits != edp_gpu_calculated_limits) {
877                 temp = edp_gpu_limits;
878                 edp_gpu_limits = edp_gpu_calculated_limits;
879                 edp_gpu_limits_size = ARRAY_SIZE(gpu_temperatures);
880                 kfree(temp);
881         } else {
882                 edp_gpu_limits = edp_gpu_calculated_limits;
883                 edp_gpu_limits_size = ARRAY_SIZE(gpu_temperatures);
884         }
885
886         kfree(freq_voltage_gpu_lut);
887
888         return 0;
889 }
890
891 void tegra_platform_edp_gpu_init(struct thermal_trip_info *trips,
892                                 int *num_trips, int margin)
893 {
894         const struct tegra_edp_gpu_limits *gpu_edp_limits;
895         struct thermal_trip_info *trip_state;
896         int i, gpu_edp_limits_size;
897
898         if (!trips || !num_trips)
899                 return;
900
901         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
902
903         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
904                 BUG();
905
906         for (i = 0; i < gpu_edp_limits_size-1; i++) {
907                 trip_state = &trips[*num_trips];
908
909                 trip_state->cdev_type = "gpu_edp";
910                 trip_state->trip_temp =
911                         (gpu_edp_limits[i].temperature * 1000) - margin;
912                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
913                 trip_state->upper = trip_state->lower = i + 1;
914
915                 (*num_trips)++;
916
917                 if (*num_trips >= THERMAL_MAX_TRIPS)
918                         BUG();
919         }
920 }
921
922 void __init tegra_init_gpu_edp_limits(unsigned int regulator_mA)
923 {
924         u32 tegra_chip_id;
925         tegra_chip_id = tegra_get_chip_id();
926
927         if (!regulator_mA)
928                 goto end;
929         gpu_regulator_cur = regulator_mA;
930
931         if (start_gpu_edp()) {
932                 WARN(1, "GPU EDP failed to set initialial limits");
933                 return;
934         }
935
936         switch (tegra_chip_id) {
937         case TEGRA_CHIPID_TEGRA12:
938                 if (init_gpu_edp_limits_calculated() == 0)
939                         return;
940                 break;
941
942         default:
943                 BUG();
944                 break;
945         }
946
947  end:
948         edp_gpu_limits = edp_gpu_default_limits;
949         edp_gpu_limits_size = ARRAY_SIZE(edp_gpu_default_limits);
950 }
951
952 static int gpu_edp_get_cdev_max_state(struct thermal_cooling_device *cdev,
953                                        unsigned long *max_state)
954 {
955         *max_state = edp_gpu_limits_size - 1;
956         return 0;
957 }
958
959 static int gpu_edp_get_cdev_cur_state(struct thermal_cooling_device *cdev,
960                                        unsigned long *cur_state)
961 {
962         *cur_state = edp_gpu_thermal_idx;
963         return 0;
964 }
965
966 static int gpu_edp_set_cdev_state(struct thermal_cooling_device *cdev,
967                                    unsigned long cur_state)
968 {
969         unsigned long clk_rate;
970         BUG_ON(cur_state >= edp_gpu_limits_size);
971         clk_rate = edp_gpu_limits[cur_state].freq_limits;
972         mutex_lock(&gpu_edp_lock);
973         edp_gpu_thermal_idx = cur_state;
974         clk_set_rate(gpu_cap_clk, clk_rate * 1000);
975         mutex_unlock(&gpu_edp_lock);
976         return 0;
977 }
978
979 static struct thermal_cooling_device_ops gpu_edp_cooling_ops = {
980         .get_max_state = gpu_edp_get_cdev_max_state,
981         .get_cur_state = gpu_edp_get_cdev_cur_state,
982         .set_cur_state = gpu_edp_set_cdev_state,
983 };
984
985 static int __init tegra_gpu_edp_late_init(void)
986 {
987         if (IS_ERR_OR_NULL(thermal_cooling_device_register(
988                 "gpu_edp", NULL, &gpu_edp_cooling_ops)))
989                 pr_err("%s: failed to register edp cooling device\n", __func__);
990
991         return 0;
992 }
993 late_initcall(tegra_gpu_edp_late_init);
994
995 #endif
996
997 #ifdef CONFIG_DEBUG_FS
998
999 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
1000 {
1001 #ifdef CONFIG_CPU_FREQ
1002         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
1003 #endif
1004         return 0;
1005 }
1006
1007 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
1008 {
1009         int i;
1010
1011         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1012                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1013         for (i = 0; i < edp_limits_size; i++) {
1014                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1015                            i == th_idx ? '>' : ' ',
1016                            edp_limits[i].temperature,
1017                            edp_limits[i].freq_limits[0],
1018                            edp_limits[i].freq_limits[1],
1019                            edp_limits[i].freq_limits[2],
1020                            edp_limits[i].freq_limits[3]);
1021         }
1022 }
1023
1024 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
1025 {
1026         int i;
1027
1028         seq_printf(s, "%6s %10s %10s\n",
1029                    " Temp.", "1-core", "2-cores");
1030         for (i = 0; i < edp_limits_size; i++) {
1031                 seq_printf(s, "%c%3dC: %10u %10u\n",
1032                            i == th_idx ? '>' : ' ',
1033                            edp_limits[i].temperature,
1034                            edp_limits[i].freq_limits[0],
1035                            edp_limits[i].freq_limits[1]);
1036         }
1037 }
1038
1039 static inline void edp_show_4core_reg_mode_table(struct seq_file *s, int th_idx)
1040 {
1041         int i;
1042
1043         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1044                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1045         for (i = 0; i < edp_limits_size; i++) {
1046                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1047                            i == th_idx ? '>' : ' ',
1048                            reg_idle_edp_limits[i].temperature,
1049                            reg_idle_edp_limits[i].freq_limits[0],
1050                            reg_idle_edp_limits[i].freq_limits[1],
1051                            reg_idle_edp_limits[i].freq_limits[2],
1052                            reg_idle_edp_limits[i].freq_limits[3]);
1053         }
1054 }
1055
1056 static inline void edp_show_2core_reg_mode_table(struct seq_file *s, int th_idx)
1057 {
1058         int i;
1059
1060         seq_printf(s, "%6s %10s %10s\n",
1061                    " Temp.", "1-core", "2-cores");
1062         for (i = 0; i < edp_limits_size; i++) {
1063                 seq_printf(s, "%c%3dC: %10u %10u\n",
1064                            i == th_idx ? '>' : ' ',
1065                            reg_idle_edp_limits[i].temperature,
1066                            reg_idle_edp_limits[i].freq_limits[0],
1067                            reg_idle_edp_limits[i].freq_limits[1]);
1068         }
1069 }
1070
1071 static inline void edp_show_2core_system_table(struct seq_file *s)
1072 {
1073         seq_printf(s, "%10u %10u\n",
1074                    system_edp_limits[0],
1075                    system_edp_limits[1]);
1076 }
1077
1078 static inline void edp_show_4core_system_table(struct seq_file *s)
1079 {
1080         seq_printf(s, "%10u %10u %10u %10u\n",
1081                    system_edp_limits[0],
1082                    system_edp_limits[1],
1083                    system_edp_limits[2],
1084                    system_edp_limits[3]);
1085 }
1086
1087 static int edp_debugfs_show(struct seq_file *s, void *data)
1088 {
1089         unsigned int max_nr_cpus = num_possible_cpus();
1090         int th_idx;
1091
1092         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
1093                 seq_printf(s, "Unsupported number of CPUs\n");
1094                 return 0;
1095         }
1096
1097 #ifdef CONFIG_CPU_FREQ
1098         tegra_get_edp_limit(&th_idx);
1099 #else
1100         th_idx = 0;
1101 #endif
1102
1103         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
1104                    edp_limits == edp_default_limits ? "**default** " : "",
1105                    regulator_cur - edp_reg_override_mA,
1106                    regulator_cur, edp_reg_override_mA);
1107
1108         if (max_nr_cpus == 2)
1109                 edp_show_2core_edp_table(s, th_idx);
1110         else if (max_nr_cpus == 4)
1111                 edp_show_4core_edp_table(s, th_idx);
1112
1113         if (reg_idle_edp_limits) {
1114                 seq_printf(s, "\n-- Regulator mode thresholds @ %dmA --\n",
1115                            reg_idle_cur);
1116                 if (max_nr_cpus == 2)
1117                         edp_show_2core_reg_mode_table(s, th_idx);
1118                 else if (max_nr_cpus == 4)
1119                         edp_show_4core_reg_mode_table(s, th_idx);
1120         }
1121
1122         if (system_edp_limits) {
1123                 seq_printf(s, "\n-- System EDP table --\n");
1124                 if (max_nr_cpus == 2)
1125                         edp_show_2core_system_table(s);
1126                 else if (max_nr_cpus == 4)
1127                         edp_show_4core_system_table(s);
1128         }
1129
1130         return 0;
1131 }
1132
1133 #ifdef CONFIG_TEGRA_GPU_EDP
1134 static inline void gpu_edp_show_table(struct seq_file *s)
1135 {
1136         int i;
1137
1138         seq_printf(s, "%6s %10s\n",
1139                    " Temp.", "Freq_limit");
1140         for (i = 0; i < edp_gpu_limits_size; i++) {
1141                 seq_printf(s, "%3dC: %10u \n",
1142                            edp_gpu_limits[i].temperature,
1143                            edp_gpu_limits[i].freq_limits);
1144         }
1145 }
1146
1147
1148 static int gpu_edp_debugfs_show(struct seq_file *s, void *data)
1149 {
1150         seq_printf(s, "-- VDD_GPU EDP table --\n");
1151
1152         gpu_edp_show_table(s);
1153
1154         return 0;
1155 }
1156 #endif
1157
1158 static int edp_reg_override_show(struct seq_file *s, void *data)
1159 {
1160         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
1161                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
1162         return 0;
1163 }
1164
1165 static int edp_reg_override_write(struct file *file,
1166         const char __user *userbuf, size_t count, loff_t *ppos)
1167 {
1168         char buf[32], *end;
1169         unsigned int edp_reg_override_mA_temp;
1170         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
1171         u32 tegra_chip_id;
1172
1173         tegra_chip_id = tegra_get_chip_id();
1174         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
1175                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
1176                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
1177                 goto override_err;
1178
1179         if (sizeof(buf) <= count)
1180                 goto override_err;
1181
1182         if (copy_from_user(buf, userbuf, count))
1183                 goto override_err;
1184
1185         /* terminate buffer and trim - white spaces may be appended
1186          *  at the end when invoked from shell command line */
1187         buf[count]='\0';
1188         strim(buf);
1189
1190         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
1191         if (*end != '\0')
1192                 goto override_err;
1193
1194         if (edp_reg_override_mA_temp >= regulator_cur)
1195                 goto override_err;
1196
1197         if (edp_reg_override_mA == edp_reg_override_mA_temp)
1198                 return count;
1199
1200         edp_reg_override_mA = edp_reg_override_mA_temp;
1201         if (init_cpu_edp_limits_calculated()) {
1202                 /* Revert to previous override value if new value fails */
1203                 edp_reg_override_mA = edp_reg_override_mA_prev;
1204                 goto override_err;
1205         }
1206
1207 #ifdef CONFIG_CPU_FREQ
1208         if (tegra_cpu_set_speed_cap(NULL)) {
1209                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
1210                 goto override_out;
1211         }
1212
1213         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
1214                         " %u mA\n", regulator_cur - edp_reg_override_mA);
1215 #else
1216         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
1217 #endif
1218
1219         return count;
1220
1221 override_err:
1222         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
1223                buf);
1224 #ifdef CONFIG_CPU_FREQ
1225 override_out:
1226 #endif
1227         return -EINVAL;
1228 }
1229
1230 static int edp_debugfs_open(struct inode *inode, struct file *file)
1231 {
1232         return single_open(file, edp_debugfs_show, inode->i_private);
1233 }
1234
1235 #ifdef CONFIG_TEGRA_GPU_EDP
1236 static int gpu_edp_debugfs_open(struct inode *inode, struct file *file)
1237 {
1238         return single_open(file, gpu_edp_debugfs_show, inode->i_private);
1239 }
1240 #endif
1241
1242 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
1243 {
1244         return single_open(file, edp_limit_debugfs_show, inode->i_private);
1245 }
1246
1247 static int edp_reg_override_open(struct inode *inode, struct file *file)
1248 {
1249         return single_open(file, edp_reg_override_show, inode->i_private);
1250 }
1251
1252 static const struct file_operations edp_debugfs_fops = {
1253         .open           = edp_debugfs_open,
1254         .read           = seq_read,
1255         .llseek         = seq_lseek,
1256         .release        = single_release,
1257 };
1258
1259 #ifdef CONFIG_TEGRA_GPU_EDP
1260 static const struct file_operations gpu_edp_debugfs_fops = {
1261         .open           = gpu_edp_debugfs_open,
1262         .read           = seq_read,
1263         .llseek         = seq_lseek,
1264         .release        = single_release,
1265 };
1266 #endif
1267
1268 static const struct file_operations edp_limit_debugfs_fops = {
1269         .open           = edp_limit_debugfs_open,
1270         .read           = seq_read,
1271         .llseek         = seq_lseek,
1272         .release        = single_release,
1273 };
1274
1275 static const struct file_operations edp_reg_override_debugfs_fops = {
1276         .open           = edp_reg_override_open,
1277         .read           = seq_read,
1278         .write          = edp_reg_override_write,
1279         .llseek         = seq_lseek,
1280         .release        = single_release,
1281 };
1282
1283 static int reg_idle_cur_get(void *data, u64 *val)
1284 {
1285         *val = reg_idle_cur;
1286         return 0;
1287 }
1288 static int reg_idle_cur_set(void *data, u64 val)
1289 {
1290         int ret;
1291
1292         ret = tegra_cpu_reg_mode_force_normal(true);
1293         if (ret) {
1294                 pr_err("%s: Failed to force regulator normal mode\n", __func__);
1295                 return ret;
1296         }
1297
1298         reg_idle_cur = (int)val;
1299         tegra_update_cpu_edp_limits();
1300         return 0;
1301 }
1302 DEFINE_SIMPLE_ATTRIBUTE(reg_idle_cur_debugfs_fops,
1303                         reg_idle_cur_get, reg_idle_cur_set, "%llu\n");
1304
1305 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
1306 static __init struct dentry *tegra_edp_debugfs_dir(void)
1307 {
1308         if (edp_debugfs_dir)
1309                 return edp_debugfs_dir;
1310         else
1311                 return debugfs_create_dir("edp", NULL);
1312 }
1313 #else
1314 static __init struct dentry *tegra_edp_debugfs_dir(void)
1315 {
1316         return debugfs_create_dir("edp", NULL);
1317 }
1318 #endif
1319
1320 static int __init tegra_edp_debugfs_init(void)
1321 {
1322         struct dentry *d_reg_idle_cur;
1323         struct dentry *d_edp;
1324         struct dentry *d_edp_limit;
1325         struct dentry *d_edp_reg_override;
1326         struct dentry *edp_dir;
1327         struct dentry *vdd_cpu_dir;
1328 #ifdef CONFIG_TEGRA_GPU_EDP
1329         struct dentry *gpu_edp;
1330         struct dentry *vdd_gpu_dir;
1331 #endif
1332
1333         if (!tegra_platform_is_silicon())
1334                 return -ENOSYS;
1335
1336         edp_dir = tegra_edp_debugfs_dir();
1337
1338         if (!edp_dir)
1339                 goto edp_dir_err;
1340
1341         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
1342
1343         if (!vdd_cpu_dir)
1344                 goto vdd_cpu_dir_err;
1345
1346 #ifdef CONFIG_TEGRA_GPU_EDP
1347         vdd_gpu_dir = debugfs_create_dir("vdd_gpu", edp_dir);
1348
1349         if (!vdd_gpu_dir)
1350                 goto vdd_gpu_dir_err;
1351 #endif
1352
1353         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
1354                                 &edp_debugfs_fops);
1355
1356         if (!d_edp)
1357                 goto edp_err;
1358 #ifdef CONFIG_TEGRA_GPU_EDP
1359         gpu_edp = debugfs_create_file("gpu_edp",  S_IRUGO, vdd_gpu_dir, NULL,
1360                          &gpu_edp_debugfs_fops);
1361         if (!gpu_edp)
1362                 goto gpu_edp_err;
1363 #endif
1364
1365         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
1366                                 NULL, &edp_limit_debugfs_fops);
1367
1368         if (!d_edp_limit)
1369                 goto edp_limit_err;
1370
1371         d_edp_reg_override = debugfs_create_file("edp_reg_override",
1372                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1373                                 &edp_reg_override_debugfs_fops);
1374
1375         if (!d_edp_reg_override)
1376                 goto edp_reg_override_err;
1377
1378         d_reg_idle_cur = debugfs_create_file("reg_idle_mA",
1379                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1380                                 &reg_idle_cur_debugfs_fops);
1381         if (!d_reg_idle_cur)
1382                 goto reg_idle_cur_err;
1383
1384         if (tegra_core_edp_debugfs_init(edp_dir))
1385                 return -ENOMEM;
1386
1387         return 0;
1388
1389 reg_idle_cur_err:
1390         debugfs_remove(d_edp_reg_override);
1391 edp_reg_override_err:
1392         debugfs_remove(d_edp_limit);
1393 edp_limit_err:
1394 #ifdef CONFIG_TEGRA_GPU_EDP
1395         debugfs_remove(gpu_edp);
1396 gpu_edp_err:
1397 #endif
1398         debugfs_remove(d_edp);
1399 edp_err:
1400 #ifdef CONFIG_TEGRA_GPU_EDP
1401         debugfs_remove(vdd_gpu_dir);
1402 vdd_gpu_dir_err:
1403 #endif
1404         debugfs_remove(vdd_cpu_dir);
1405 vdd_cpu_dir_err:
1406         debugfs_remove(edp_dir);
1407 edp_dir_err:
1408         return -ENOMEM;
1409 }
1410
1411 late_initcall(tegra_edp_debugfs_init);
1412 #endif /* CONFIG_DEBUG_FS */