Revert "arm: tegra: loose cpu edp power table calculation."
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/tegra-fuse.h>
30
31 #include <mach/edp.h>
32
33 #include "dvfs.h"
34 #include "clock.h"
35 #include "cpu-tegra.h"
36 #include "common.h"
37
38 #define FREQ_STEP 12750000
39 #define OVERRIDE_DEFAULT 6000
40
41 static struct tegra_edp_limits *edp_limits;
42 static int edp_limits_size;
43 static unsigned int regulator_cur;
44 /* Value to subtract from regulator current limit */
45 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
46
47 static struct tegra_edp_limits *reg_idle_edp_limits;
48 static int reg_idle_cur;
49
50 static const unsigned int *system_edp_limits;
51
52 static struct tegra_system_edp_entry *power_edp_limits;
53 static int power_edp_limits_size;
54
55 /*
56  * "Safe entry" to be used when no match for speedo_id /
57  * regulator_cur is found; must be the last one
58  */
59 static struct tegra_edp_limits edp_default_limits[] = {
60         {85, {1000000, 1000000, 1000000, 1000000} },
61 };
62
63 static struct tegra_system_edp_entry power_edp_default_limits[] = {
64         {0, 20, {1000000, 1000000, 1000000, 1000000} },
65 };
66
67 /* Constants for EDP calculations */
68 static const int temperatures[] = { /* degree celcius (C) */
69         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
70 };
71
72 static const int power_cap_levels[] = { /* milliwatts (mW) */
73           500,  1000,  1500,  2000,  2500,  3000,  3500,
74          4000,  4500,  5000,  5500,  6000,  6500,  7000,
75          7500,  8000,  8500,  9000,  9500, 10000, 10500,
76         11000, 11500, 12000, 12500, 13000, 13500, 14000,
77         14500, 15000, 15500, 16000, 16500, 17000
78 };
79
80 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
81 static unsigned int freq_voltage_lut_size_saved;
82 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
83 static unsigned int freq_voltage_lut_size;
84
85 static inline s64 edp_pow(s64 val, int pwr)
86 {
87         s64 retval = 1;
88
89         while (val && pwr) {
90                 if (pwr & 1)
91                         retval *= val;
92                 pwr >>= 1;
93                 if (pwr)
94                         val *= val;
95         }
96
97         return retval;
98 }
99
100
101 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
102 static inline unsigned int edp_apply_fixed_limits(
103                                 unsigned int in_freq_KHz,
104                                 struct tegra_edp_cpu_leakage_params *params,
105                                 unsigned int cur_effective,
106                                 int temp_C, int n_cores_idx)
107 {
108         unsigned int out_freq_KHz = in_freq_KHz;
109         unsigned int max_cur, max_temp, max_freq;
110         int i;
111
112         /* Apply any additional fixed limits */
113         for (i = 0; i < 8; i++) {
114                 max_cur = params->max_current_cap[i].max_cur;
115                 if (max_cur != 0 && cur_effective <= max_cur) {
116                         max_temp = params->max_current_cap[i].max_temp;
117                         if (max_temp != 0 && temp_C > max_temp) {
118                                 max_freq = params->max_current_cap[i].
119                                         max_freq[n_cores_idx];
120                                 if (max_freq && max_freq < out_freq_KHz)
121                                         out_freq_KHz = max_freq;
122                         }
123                 }
124         }
125
126         return out_freq_KHz;
127 }
128 #else
129 #define edp_apply_fixed_limits(freq, unused...) (freq)
130 #endif
131
132 /*
133  * Find the maximum frequency that results in dynamic and leakage current that
134  * is less than the regulator current limit.
135  * temp_C - valid or -EINVAL
136  * power_mW - valid or -1 (infinite) or -EINVAL
137  */
138 static unsigned int edp_calculate_maxf(
139                                 struct tegra_edp_cpu_leakage_params *params,
140                                 int temp_C, int power_mW, unsigned int cur_mA,
141                                 int iddq_mA,
142                                 int n_cores_idx)
143 {
144         unsigned int voltage_mV, freq_KHz = 0;
145         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
146         int f, i, j, k;
147         s64 leakage_mA, dyn_mA, leakage_calc_step;
148         s64 leakage_mW, dyn_mW;
149
150         /* If current limit is not specified, use max by default */
151         cur_mA = cur_mA ? : cur_effective;
152
153         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
154                 freq_KHz = freq_voltage_lut[f].freq / 1000;
155                 voltage_mV = freq_voltage_lut[f].voltage_mV;
156
157                 /* Constrain Volt-Temp */
158                 if (params->volt_temp_cap.temperature &&
159                     temp_C > params->volt_temp_cap.temperature &&
160                     params->volt_temp_cap.voltage_limit_mV &&
161                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
162                         continue;
163
164                 /* Calculate leakage current */
165                 leakage_mA = 0;
166                 for (i = 0; i <= 3; i++) {
167                         for (j = 0; j <= 3; j++) {
168                                 for (k = 0; k <= 3; k++) {
169                                         leakage_calc_step =
170                                                 params->leakage_consts_ijk
171                                                 [i][j][k] * edp_pow(iddq_mA, i);
172                                         /* Convert (mA)^i to (A)^i */
173                                         leakage_calc_step =
174                                                 div64_s64(leakage_calc_step,
175                                                           edp_pow(1000, i));
176                                         leakage_calc_step *=
177                                                 edp_pow(voltage_mV, j);
178                                         /* Convert (mV)^j to (V)^j */
179                                         leakage_calc_step =
180                                                 div64_s64(leakage_calc_step,
181                                                           edp_pow(1000, j));
182                                         leakage_calc_step *=
183                                                 edp_pow(temp_C, k);
184                                         /* Convert (C)^k to (scaled_C)^k */
185                                         leakage_calc_step =
186                                                 div64_s64(leakage_calc_step,
187                                                 edp_pow(params->temp_scaled,
188                                                         k));
189                                         /* leakage_consts_ijk was scaled */
190                                         leakage_calc_step =
191                                                 div64_s64(leakage_calc_step,
192                                                           params->ijk_scaled);
193                                         leakage_mA += leakage_calc_step;
194                                 }
195                         }
196                 }
197
198                 /* set floor for leakage current */
199                 if (leakage_mA <= params->leakage_min)
200                         leakage_mA = params->leakage_min;
201
202                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
203
204                 /* leakage_const_n was scaled */
205                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
206
207                 /* Calculate dynamic current */
208                 dyn_mA = voltage_mV * freq_KHz / 1000;
209                 /* Convert mV to V */
210                 dyn_mA = div64_s64(dyn_mA, 1000);
211                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
212                 /* dyn_const_n was scaled */
213                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
214
215                 if (power_mW != -1) {
216                         leakage_mW = leakage_mA * voltage_mV;
217                         dyn_mW = dyn_mA * voltage_mV;
218                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
219                                 goto end;
220                 } else if ((leakage_mA + dyn_mA) <= cur_mA) {
221                         goto end;
222                 }
223                 freq_KHz = 0;
224         }
225
226  end:
227         return edp_apply_fixed_limits(freq_KHz, params,
228                                         cur_effective, temp_C, n_cores_idx);
229 }
230
231 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
232                         unsigned int cpu_speedo_idx,
233                         unsigned int freq_volt_lut_size,
234                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
235 {
236         unsigned int i, j, freq;
237         int voltage_mV;
238
239         for (i = 0, j = 0, freq = 0;
240                  i < freq_volt_lut_size;
241                  i++, freq += FREQ_STEP) {
242
243                 /* Predict voltages */
244                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
245                         clk_cpu_g, freq);
246                 if (voltage_mV < 0) {
247                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
248                                __func__, freq, voltage_mV);
249                         return -EINVAL;
250                 }
251
252                 /* Cache frequency / voltage / voltage constant relationship */
253                 freq_volt_lut[i].freq = freq;
254                 freq_volt_lut[i].voltage_mV = voltage_mV;
255         }
256         return 0;
257 }
258
259 unsigned int tegra_edp_find_maxf(int volt)
260 {
261         unsigned int i;
262
263         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
264                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
265                         break;
266         }
267         return freq_voltage_lut[i - 1].freq;
268 }
269
270
271 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
272 {
273         int i, array_size;
274         struct tegra_edp_cpu_leakage_params *params;
275
276         switch (tegra_get_chip_id()) {
277         case TEGRA_CHIPID_TEGRA11:
278                 params = tegra11x_get_leakage_params(0, &array_size);
279                 break;
280         case TEGRA_CHIPID_TEGRA14:
281                 params = tegra14x_get_leakage_params(0, &array_size);
282                 break;
283         case TEGRA_CHIPID_TEGRA12:
284                 params = tegra12x_get_leakage_params(0, &array_size);
285                 break;
286         case TEGRA_CHIPID_TEGRA3:
287         case TEGRA_CHIPID_TEGRA2:
288         default:
289                 array_size = 0;
290                 break;
291         }
292
293         for (i = 0; i < array_size; i++)
294                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
295                         *cpu_speedo_idx = i;
296                         return 0;
297                 }
298
299         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
300                __func__, cpu_speedo_id);
301         return -EINVAL;
302 }
303
304 static int init_cpu_edp_limits_calculated(void)
305 {
306         unsigned int max_nr_cpus = num_possible_cpus();
307         unsigned int temp_idx, n_cores_idx, pwr_idx;
308         unsigned int cpu_g_minf, cpu_g_maxf;
309         unsigned int iddq_mA;
310         unsigned int cpu_speedo_idx;
311         unsigned int cap, limit;
312         struct tegra_edp_limits *edp_calculated_limits;
313         struct tegra_edp_limits *reg_idle_calc_limits;
314         struct tegra_system_edp_entry *power_edp_calc_limits;
315         struct tegra_edp_cpu_leakage_params *params;
316         int ret;
317         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
318         int cpu_speedo_id = tegra_cpu_speedo_id();
319         int idle_cur = reg_idle_cur;
320
321         /* Determine all inputs to EDP formula */
322         iddq_mA = tegra_get_cpu_iddq_value();
323         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
324         if (ret)
325                 return ret;
326
327         switch (tegra_get_chip_id()) {
328         case TEGRA_CHIPID_TEGRA11:
329                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
330                 break;
331         case TEGRA_CHIPID_TEGRA14:
332                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
333                 break;
334         case TEGRA_CHIPID_TEGRA12:
335                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
336                 break;
337         case TEGRA_CHIPID_TEGRA3:
338         case TEGRA_CHIPID_TEGRA2:
339         default:
340                 return -EINVAL;
341         }
342
343         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
344                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
345         BUG_ON(!edp_calculated_limits);
346
347         reg_idle_calc_limits = kmalloc(sizeof(struct tegra_edp_limits)
348                                        * ARRAY_SIZE(temperatures), GFP_KERNEL);
349         BUG_ON(!reg_idle_calc_limits);
350
351         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
352                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
353         BUG_ON(!power_edp_calc_limits);
354
355         cpu_g_minf = 0;
356         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
357         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
358         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
359                                    * freq_voltage_lut_size, GFP_KERNEL);
360         if (!freq_voltage_lut) {
361                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
362                 kfree(power_edp_calc_limits);
363                 kfree(reg_idle_calc_limits);
364                 kfree(edp_calculated_limits);
365                 return -ENOMEM;
366         }
367
368         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
369                                 freq_voltage_lut_size, freq_voltage_lut);
370         if (ret) {
371                 kfree(power_edp_calc_limits);
372                 kfree(reg_idle_calc_limits);
373                 kfree(edp_calculated_limits);
374                 kfree(freq_voltage_lut);
375                 return ret;
376         }
377
378         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
379                 /* release previous table if present */
380                 kfree(freq_voltage_lut_saved);
381                 /* create table to save */
382                 freq_voltage_lut_saved =
383                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
384                         freq_voltage_lut_size, GFP_KERNEL);
385                 if (!freq_voltage_lut_saved) {
386                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
387                                 __func__);
388                         kfree(freq_voltage_lut);
389                         return -ENOMEM;
390                 }
391                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
392         }
393         memcpy(freq_voltage_lut_saved,
394                 freq_voltage_lut,
395                 sizeof(struct tegra_edp_freq_voltage_table) *
396                         freq_voltage_lut_size);
397
398         /* Calculate EDP table */
399         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
400                 for (temp_idx = 0;
401                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
402                         edp_calculated_limits[temp_idx].temperature =
403                                 temperatures[temp_idx];
404                         limit = edp_calculate_maxf(params,
405                                                    temperatures[temp_idx],
406                                                    -1,
407                                                    0,
408                                                    iddq_mA,
409                                                    n_cores_idx);
410                         if (limit == -EINVAL)
411                                 return -EINVAL;
412                         /* apply safety cap if it is specified */
413                         if (n_cores_idx < 4) {
414                                 cap = params->safety_cap[n_cores_idx];
415                                 if (cap && cap < limit)
416                                         limit = cap;
417                         }
418                         edp_calculated_limits[temp_idx].
419                                 freq_limits[n_cores_idx] = limit;
420
421                         /* regulator mode threshold */
422                         if (!idle_cur)
423                                 continue;
424                         reg_idle_calc_limits[temp_idx].temperature =
425                                 temperatures[temp_idx];
426                         limit = edp_calculate_maxf(params,
427                                                    temperatures[temp_idx],
428                                                    -1,
429                                                    idle_cur,
430                                                    iddq_mA,
431                                                    n_cores_idx);
432
433                         /* remove idle table if any threshold is invalid */
434                         if (limit == -EINVAL) {
435                                 pr_warn("%s: Invalid idle limit for %dmA\n",
436                                         __func__, idle_cur);
437                                 idle_cur = 0;
438                                 continue;
439                         }
440
441                         /* No mode change below G CPU minimum rate */
442                         if (limit < clk_get_min_rate(clk_cpu_g) / 1000)
443                                 limit = 0;
444                         reg_idle_calc_limits[temp_idx].
445                                 freq_limits[n_cores_idx] = limit;
446                 }
447
448                 for (pwr_idx = 0;
449                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
450                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
451                                 power_cap_levels[pwr_idx] / 100;
452                         limit = edp_calculate_maxf(params,
453                                                    90,
454                                                    power_cap_levels[pwr_idx],
455                                                    0,
456                                                    iddq_mA,
457                                                    n_cores_idx);
458                         if (limit == -EINVAL)
459                                 return -EINVAL;
460                         power_edp_calc_limits[pwr_idx].
461                                 freq_limits[n_cores_idx] = limit;
462                 }
463         }
464
465         /*
466          * If this is an EDP table update, need to overwrite old table.
467          * The old table's address must remain valid.
468          */
469         if (edp_limits != edp_default_limits) {
470                 memcpy(edp_limits, edp_calculated_limits,
471                        sizeof(struct tegra_edp_limits)
472                        * ARRAY_SIZE(temperatures));
473                 kfree(edp_calculated_limits);
474         }
475         else {
476                 edp_limits = edp_calculated_limits;
477                 edp_limits_size = ARRAY_SIZE(temperatures);
478         }
479
480         if (idle_cur && reg_idle_edp_limits) {
481                 memcpy(reg_idle_edp_limits, reg_idle_calc_limits,
482                        sizeof(struct tegra_edp_limits)
483                        * ARRAY_SIZE(temperatures));
484                 kfree(reg_idle_calc_limits);
485         } else if (idle_cur) {
486                 reg_idle_edp_limits = reg_idle_calc_limits;
487         } else {
488                 kfree(reg_idle_edp_limits);
489                 kfree(reg_idle_calc_limits);
490                 reg_idle_edp_limits = NULL;
491         }
492
493         if (power_edp_limits != power_edp_default_limits) {
494                 memcpy(power_edp_limits, power_edp_calc_limits,
495                        sizeof(struct tegra_system_edp_entry)
496                        * ARRAY_SIZE(power_cap_levels));
497                 kfree(power_edp_calc_limits);
498         } else {
499                 power_edp_limits = power_edp_calc_limits;
500                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
501         }
502
503         kfree(freq_voltage_lut);
504         return 0;
505 }
506
507 void tegra_recalculate_cpu_edp_limits(void)
508 {
509         u32 tegra_chip_id;
510
511         tegra_chip_id = tegra_get_chip_id();
512         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
513             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
514             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
515                 return;
516
517         if (init_cpu_edp_limits_calculated() == 0)
518                 return;
519
520         /* Revert to default EDP table on error */
521         edp_limits = edp_default_limits;
522         edp_limits_size = ARRAY_SIZE(edp_default_limits);
523
524         power_edp_limits = power_edp_default_limits;
525         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
526
527         kfree(reg_idle_edp_limits);
528         reg_idle_edp_limits = NULL;
529         pr_err("%s: Failed to recalculate EDP limits\n", __func__);
530 }
531
532 /*
533  * Specify regulator current in mA, e.g. 5000mA
534  * Use 0 for default
535  */
536 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
537 {
538         if (!regulator_mA)
539                 goto end;
540         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
541
542         switch (tegra_get_chip_id()) {
543         case TEGRA_CHIPID_TEGRA11:
544         case TEGRA_CHIPID_TEGRA14:
545         case TEGRA_CHIPID_TEGRA12:
546                 if (init_cpu_edp_limits_calculated() == 0)
547                         return;
548                 break;
549         case TEGRA_CHIPID_TEGRA2:
550         case TEGRA_CHIPID_TEGRA3:
551         default:
552                 BUG();
553                 break;
554         }
555
556  end:
557         edp_limits = edp_default_limits;
558         edp_limits_size = ARRAY_SIZE(edp_default_limits);
559
560         power_edp_limits = power_edp_default_limits;
561         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
562 }
563
564 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
565 {
566         *limits = edp_limits;
567         *size = edp_limits_size;
568 }
569
570 void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
571                                            unsigned int mode)
572 {
573         if (mode == REGULATOR_MODE_IDLE) {
574                 reg_idle_cur = regulator_mA;
575                 return;
576         }
577         pr_err("%s: Not supported regulator mode 0x%x\n", __func__, mode);
578 }
579
580 void tegra_get_cpu_reg_mode_limits(const struct tegra_edp_limits **limits,
581                                    int *size, unsigned int mode)
582 {
583         if (mode == REGULATOR_MODE_IDLE) {
584                 *limits = reg_idle_edp_limits;
585                 *size = edp_limits_size;
586         } else {
587                 *limits = NULL;
588                 *size = 0;
589         }
590 }
591
592 void tegra_get_system_edp_limits(const unsigned int **limits)
593 {
594         *limits = system_edp_limits;
595 }
596
597 void tegra_platform_edp_init(struct thermal_trip_info *trips,
598                                 int *num_trips, int margin)
599 {
600         const struct tegra_edp_limits *cpu_edp_limits;
601         struct thermal_trip_info *trip_state;
602         int i, cpu_edp_limits_size;
603
604         if (!trips || !num_trips)
605                 return;
606
607         /* edp capping */
608         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
609
610         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
611                 BUG();
612
613         for (i = 0; i < cpu_edp_limits_size-1; i++) {
614                 trip_state = &trips[*num_trips];
615
616                 trip_state->cdev_type = "cpu_edp";
617                 trip_state->trip_temp =
618                         (cpu_edp_limits[i].temperature * 1000) - margin;
619                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
620                 trip_state->upper = trip_state->lower = i + 1;
621
622                 (*num_trips)++;
623
624                 if (*num_trips >= THERMAL_MAX_TRIPS)
625                         BUG();
626         }
627 }
628
629 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
630 {
631         *size = power_edp_limits_size;
632         return power_edp_limits;
633 }
634
635 #ifdef CONFIG_DEBUG_FS
636
637 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
638 {
639 #ifdef CONFIG_CPU_FREQ
640         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
641 #endif
642         return 0;
643 }
644
645 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
646 {
647         int i;
648
649         seq_printf(s, "%6s %10s %10s %10s %10s\n",
650                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
651         for (i = 0; i < edp_limits_size; i++) {
652                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
653                            i == th_idx ? '>' : ' ',
654                            edp_limits[i].temperature,
655                            edp_limits[i].freq_limits[0],
656                            edp_limits[i].freq_limits[1],
657                            edp_limits[i].freq_limits[2],
658                            edp_limits[i].freq_limits[3]);
659         }
660 }
661
662 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
663 {
664         int i;
665
666         seq_printf(s, "%6s %10s %10s\n",
667                    " Temp.", "1-core", "2-cores");
668         for (i = 0; i < edp_limits_size; i++) {
669                 seq_printf(s, "%c%3dC: %10u %10u\n",
670                            i == th_idx ? '>' : ' ',
671                            edp_limits[i].temperature,
672                            edp_limits[i].freq_limits[0],
673                            edp_limits[i].freq_limits[1]);
674         }
675 }
676
677 static inline void edp_show_4core_reg_mode_table(struct seq_file *s, int th_idx)
678 {
679         int i;
680
681         seq_printf(s, "%6s %10s %10s %10s %10s\n",
682                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
683         for (i = 0; i < edp_limits_size; i++) {
684                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
685                            i == th_idx ? '>' : ' ',
686                            reg_idle_edp_limits[i].temperature,
687                            reg_idle_edp_limits[i].freq_limits[0],
688                            reg_idle_edp_limits[i].freq_limits[1],
689                            reg_idle_edp_limits[i].freq_limits[2],
690                            reg_idle_edp_limits[i].freq_limits[3]);
691         }
692 }
693
694 static inline void edp_show_2core_reg_mode_table(struct seq_file *s, int th_idx)
695 {
696         int i;
697
698         seq_printf(s, "%6s %10s %10s\n",
699                    " Temp.", "1-core", "2-cores");
700         for (i = 0; i < edp_limits_size; i++) {
701                 seq_printf(s, "%c%3dC: %10u %10u\n",
702                            i == th_idx ? '>' : ' ',
703                            reg_idle_edp_limits[i].temperature,
704                            reg_idle_edp_limits[i].freq_limits[0],
705                            reg_idle_edp_limits[i].freq_limits[1]);
706         }
707 }
708
709 static inline void edp_show_2core_system_table(struct seq_file *s)
710 {
711         seq_printf(s, "%10u %10u\n",
712                    system_edp_limits[0],
713                    system_edp_limits[1]);
714 }
715
716 static inline void edp_show_4core_system_table(struct seq_file *s)
717 {
718         seq_printf(s, "%10u %10u %10u %10u\n",
719                    system_edp_limits[0],
720                    system_edp_limits[1],
721                    system_edp_limits[2],
722                    system_edp_limits[3]);
723 }
724
725 static int edp_debugfs_show(struct seq_file *s, void *data)
726 {
727         unsigned int max_nr_cpus = num_possible_cpus();
728         int th_idx;
729
730         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
731                 seq_printf(s, "Unsupported number of CPUs\n");
732                 return 0;
733         }
734
735 #ifdef CONFIG_CPU_FREQ
736         tegra_get_edp_limit(&th_idx);
737 #else
738         th_idx = 0;
739 #endif
740
741         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
742                    edp_limits == edp_default_limits ? "**default** " : "",
743                    regulator_cur - edp_reg_override_mA,
744                    regulator_cur, edp_reg_override_mA);
745
746         if (max_nr_cpus == 2)
747                 edp_show_2core_edp_table(s, th_idx);
748         else if (max_nr_cpus == 4)
749                 edp_show_4core_edp_table(s, th_idx);
750
751         if (reg_idle_edp_limits) {
752                 seq_printf(s, "\n-- Regulator mode thresholds @ %dmA --\n",
753                            reg_idle_cur);
754                 if (max_nr_cpus == 2)
755                         edp_show_2core_reg_mode_table(s, th_idx);
756                 else if (max_nr_cpus == 4)
757                         edp_show_4core_reg_mode_table(s, th_idx);
758         }
759
760         if (system_edp_limits) {
761                 seq_printf(s, "\n-- System EDP table --\n");
762                 if (max_nr_cpus == 2)
763                         edp_show_2core_system_table(s);
764                 else if (max_nr_cpus == 4)
765                         edp_show_4core_system_table(s);
766         }
767
768         return 0;
769 }
770
771 static int edp_reg_override_show(struct seq_file *s, void *data)
772 {
773         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
774                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
775         return 0;
776 }
777
778 static int edp_reg_override_write(struct file *file,
779         const char __user *userbuf, size_t count, loff_t *ppos)
780 {
781         char buf[32], *end;
782         unsigned int edp_reg_override_mA_temp;
783         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
784         u32 tegra_chip_id;
785
786         tegra_chip_id = tegra_get_chip_id();
787         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
788                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
789                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
790                 goto override_err;
791
792         if (sizeof(buf) <= count)
793                 goto override_err;
794
795         if (copy_from_user(buf, userbuf, count))
796                 goto override_err;
797
798         /* terminate buffer and trim - white spaces may be appended
799          *  at the end when invoked from shell command line */
800         buf[count]='\0';
801         strim(buf);
802
803         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
804         if (*end != '\0')
805                 goto override_err;
806
807         if (edp_reg_override_mA_temp >= regulator_cur)
808                 goto override_err;
809
810         if (edp_reg_override_mA == edp_reg_override_mA_temp)
811                 return count;
812
813         edp_reg_override_mA = edp_reg_override_mA_temp;
814         if (init_cpu_edp_limits_calculated()) {
815                 /* Revert to previous override value if new value fails */
816                 edp_reg_override_mA = edp_reg_override_mA_prev;
817                 goto override_err;
818         }
819
820 #ifdef CONFIG_CPU_FREQ
821         if (tegra_cpu_set_speed_cap(NULL)) {
822                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
823                 goto override_out;
824         }
825
826         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
827                         " %u mA\n", regulator_cur - edp_reg_override_mA);
828 #else
829         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
830 #endif
831
832         return count;
833
834 override_err:
835         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
836                buf);
837 #ifdef CONFIG_CPU_FREQ
838 override_out:
839 #endif
840         return -EINVAL;
841 }
842
843 static int edp_debugfs_open(struct inode *inode, struct file *file)
844 {
845         return single_open(file, edp_debugfs_show, inode->i_private);
846 }
847
848 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
849 {
850         return single_open(file, edp_limit_debugfs_show, inode->i_private);
851 }
852
853 static int edp_reg_override_open(struct inode *inode, struct file *file)
854 {
855         return single_open(file, edp_reg_override_show, inode->i_private);
856 }
857
858 static const struct file_operations edp_debugfs_fops = {
859         .open           = edp_debugfs_open,
860         .read           = seq_read,
861         .llseek         = seq_lseek,
862         .release        = single_release,
863 };
864
865 static const struct file_operations edp_limit_debugfs_fops = {
866         .open           = edp_limit_debugfs_open,
867         .read           = seq_read,
868         .llseek         = seq_lseek,
869         .release        = single_release,
870 };
871
872 static const struct file_operations edp_reg_override_debugfs_fops = {
873         .open           = edp_reg_override_open,
874         .read           = seq_read,
875         .write          = edp_reg_override_write,
876         .llseek         = seq_lseek,
877         .release        = single_release,
878 };
879
880 static int reg_idle_cur_get(void *data, u64 *val)
881 {
882         *val = reg_idle_cur;
883         return 0;
884 }
885 static int reg_idle_cur_set(void *data, u64 val)
886 {
887         int ret;
888
889         ret = tegra_cpu_reg_mode_force_normal(true);
890         if (ret) {
891                 pr_err("%s: Failed to force regulator normal mode\n", __func__);
892                 return ret;
893         }
894
895         reg_idle_cur = (int)val;
896         tegra_update_cpu_edp_limits();
897         return 0;
898 }
899 DEFINE_SIMPLE_ATTRIBUTE(reg_idle_cur_debugfs_fops,
900                         reg_idle_cur_get, reg_idle_cur_set, "%llu\n");
901
902 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
903 static __init struct dentry *tegra_edp_debugfs_dir(void)
904 {
905         if (edp_debugfs_dir)
906                 return edp_debugfs_dir;
907         else
908                 return debugfs_create_dir("edp", NULL);
909 }
910 #else
911 static __init struct dentry *tegra_edp_debugfs_dir(void)
912 {
913         return debugfs_create_dir("edp", NULL);
914 }
915 #endif
916
917 static int __init tegra_edp_debugfs_init(void)
918 {
919         struct dentry *d_reg_idle_cur;
920         struct dentry *d_edp;
921         struct dentry *d_edp_limit;
922         struct dentry *d_edp_reg_override;
923         struct dentry *edp_dir;
924         struct dentry *vdd_cpu_dir;
925
926         if (!tegra_platform_is_silicon())
927                 return -ENOSYS;
928
929         edp_dir = tegra_edp_debugfs_dir();
930
931         if (!edp_dir)
932                 goto edp_dir_err;
933
934         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
935
936         if (!vdd_cpu_dir)
937                 goto vdd_cpu_dir_err;
938
939         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
940                                 &edp_debugfs_fops);
941
942         if (!d_edp)
943                 goto edp_err;
944
945         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
946                                 NULL, &edp_limit_debugfs_fops);
947
948         if (!d_edp_limit)
949                 goto edp_limit_err;
950
951         d_edp_reg_override = debugfs_create_file("edp_reg_override",
952                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
953                                 &edp_reg_override_debugfs_fops);
954
955         if (!d_edp_reg_override)
956                 goto edp_reg_override_err;
957
958         d_reg_idle_cur = debugfs_create_file("reg_idle_mA",
959                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
960                                 &reg_idle_cur_debugfs_fops);
961         if (!d_reg_idle_cur)
962                 goto reg_idle_cur_err;
963
964         if (tegra_core_edp_debugfs_init(edp_dir))
965                 return -ENOMEM;
966
967         return 0;
968
969 reg_idle_cur_err:
970         debugfs_remove(d_edp_reg_override);
971 edp_reg_override_err:
972         debugfs_remove(d_edp_limit);
973 edp_limit_err:
974         debugfs_remove(d_edp);
975 edp_err:
976         debugfs_remove(vdd_cpu_dir);
977 vdd_cpu_dir_err:
978         debugfs_remove(edp_dir);
979 edp_dir_err:
980         return -ENOMEM;
981 }
982
983 late_initcall(tegra_edp_debugfs_init);
984 #endif /* CONFIG_DEBUG_FS */