arm: tegra: edp: Add GPU EDP override debugfs
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/tegra-fuse.h>
30
31 #include <mach/edp.h>
32
33 #include "dvfs.h"
34 #include "clock.h"
35 #include "cpu-tegra.h"
36 #include "common.h"
37
38 #define FREQ_STEP 12750000
39 #define OVERRIDE_DEFAULT 6000
40
41 #define GPU_FREQ_STEP 12000000
42
43 static struct tegra_edp_limits *edp_limits;
44 static int edp_limits_size;
45 static unsigned int regulator_cur;
46 /* Value to subtract from regulator current limit */
47 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
48
49 static struct tegra_edp_limits *reg_idle_edp_limits;
50 static int reg_idle_cur;
51
52 static const unsigned int *system_edp_limits;
53
54 static struct tegra_system_edp_entry *power_edp_limits;
55 static int power_edp_limits_size;
56
57 /*
58  * "Safe entry" to be used when no match for speedo_id /
59  * regulator_cur is found; must be the last one
60  */
61 static struct tegra_edp_limits edp_default_limits[] = {
62         {85, {1000000, 1000000, 1000000, 1000000} },
63 };
64
65 static struct tegra_system_edp_entry power_edp_default_limits[] = {
66         {0, 20, {1000000, 1000000, 1000000, 1000000} },
67 };
68
69 /* Constants for EDP calculations */
70 static const int temperatures[] = { /* degree celcius (C) */
71         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
72 };
73
74 static const int power_cap_levels[] = { /* milliwatts (mW) */
75           500,  1000,  1500,  2000,  2500,  3000,  3500,
76          4000,  4500,  5000,  5500,  6000,  6500,  7000,
77          7500,  8000,  8500,  9000,  9500, 10000, 10500,
78         11000, 11500, 12000, 12500, 13000, 13500, 14000,
79         14500, 15000, 15500, 16000, 16500, 17000
80 };
81
82 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
83 static unsigned int freq_voltage_lut_size_saved;
84 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
85 static unsigned int freq_voltage_lut_size;
86
87 #ifdef CONFIG_TEGRA_GPU_EDP
88 static struct tegra_edp_gpu_limits *gpu_edp_limits;
89 static int gpu_edp_limits_size;
90 static int gpu_edp_thermal_idx;
91 static struct clk *gpu_cap_clk;
92 static DEFINE_MUTEX(gpu_edp_lock);
93
94 static struct tegra_edp_freq_voltage_table *freq_voltage_gpu_lut;
95 static unsigned int freq_voltage_gpu_lut_size;
96
97 static unsigned int gpu_regulator_cur;
98 /* Value to subtract from regulator current limit */
99 static unsigned int gpu_edp_reg_override_mA = OVERRIDE_DEFAULT;
100
101 static struct tegra_edp_gpu_limits gpu_edp_default_limits[] = {
102         {85, 350000},
103 };
104
105 static const int gpu_temperatures[] = { /* degree celcius (C) */
106         20, 50, 70, 75, 80, 85, 90, 95, 100, 105,
107 };
108 #endif
109
110 static inline s64 edp_pow(s64 val, int pwr)
111 {
112         s64 retval = 1;
113
114         while (val && pwr) {
115                 if (pwr & 1)
116                         retval *= val;
117                 pwr >>= 1;
118                 if (pwr)
119                         val *= val;
120         }
121
122         return retval;
123 }
124
125
126 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
127 static inline unsigned int edp_apply_fixed_limits(
128                                 unsigned int in_freq_KHz,
129                                 struct tegra_edp_cpu_leakage_params *params,
130                                 unsigned int cur_effective,
131                                 int temp_C, int n_cores_idx)
132 {
133         unsigned int out_freq_KHz = in_freq_KHz;
134         unsigned int max_cur, max_temp, max_freq;
135         int i;
136
137         /* Apply any additional fixed limits */
138         for (i = 0; i < 8; i++) {
139                 max_cur = params->max_current_cap[i].max_cur;
140                 if (max_cur != 0 && cur_effective <= max_cur) {
141                         max_temp = params->max_current_cap[i].max_temp;
142                         if (max_temp != 0 && temp_C > max_temp) {
143                                 max_freq = params->max_current_cap[i].
144                                         max_freq[n_cores_idx];
145                                 if (max_freq && max_freq < out_freq_KHz)
146                                         out_freq_KHz = max_freq;
147                         }
148                 }
149         }
150
151         return out_freq_KHz;
152 }
153 #else
154 #define edp_apply_fixed_limits(freq, unused...) (freq)
155 #endif
156
157 /*
158  * Find the maximum frequency that results in dynamic and leakage current that
159  * is less than the regulator current limit.
160  * temp_C - valid or -EINVAL
161  * power_mW - valid or -1 (infinite) or -EINVAL
162  */
163 static unsigned int edp_calculate_maxf(
164                                 struct tegra_edp_cpu_leakage_params *params,
165                                 int temp_C, int power_mW, unsigned int cur_mA,
166                                 int iddq_mA,
167                                 int n_cores_idx)
168 {
169         unsigned int voltage_mV, freq_KHz = 0;
170         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
171         int f, i, j, k;
172         s64 leakage_mA, dyn_mA, leakage_calc_step;
173         s64 leakage_mW, dyn_mW;
174
175         /* If current limit is not specified, use max by default */
176         cur_mA = cur_mA ? : cur_effective;
177
178         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
179                 freq_KHz = freq_voltage_lut[f].freq / 1000;
180                 voltage_mV = freq_voltage_lut[f].voltage_mV;
181
182                 /* Constrain Volt-Temp */
183                 if (params->volt_temp_cap.temperature &&
184                     temp_C > params->volt_temp_cap.temperature &&
185                     params->volt_temp_cap.voltage_limit_mV &&
186                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
187                         continue;
188
189                 /* Calculate leakage current */
190                 leakage_mA = 0;
191                 for (i = 0; i <= 3; i++) {
192                         for (j = 0; j <= 3; j++) {
193                                 for (k = 0; k <= 3; k++) {
194                                         leakage_calc_step =
195                                                 params->leakage_consts_ijk
196                                                 [i][j][k] * edp_pow(iddq_mA, i);
197                                         /* Convert (mA)^i to (A)^i */
198                                         leakage_calc_step =
199                                                 div64_s64(leakage_calc_step,
200                                                           edp_pow(1000, i));
201                                         leakage_calc_step *=
202                                                 edp_pow(voltage_mV, j);
203                                         /* Convert (mV)^j to (V)^j */
204                                         leakage_calc_step =
205                                                 div64_s64(leakage_calc_step,
206                                                           edp_pow(1000, j));
207                                         leakage_calc_step *=
208                                                 edp_pow(temp_C, k);
209                                         /* Convert (C)^k to (scaled_C)^k */
210                                         leakage_calc_step =
211                                                 div64_s64(leakage_calc_step,
212                                                 edp_pow(params->temp_scaled,
213                                                         k));
214                                         /* leakage_consts_ijk was scaled */
215                                         leakage_calc_step =
216                                                 div64_s64(leakage_calc_step,
217                                                           params->ijk_scaled);
218                                         leakage_mA += leakage_calc_step;
219                                 }
220                         }
221                 }
222
223                 /* set floor for leakage current */
224                 if (leakage_mA <= params->leakage_min)
225                         leakage_mA = params->leakage_min;
226
227                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
228
229                 /* leakage_const_n was scaled */
230                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
231
232                 /* Calculate dynamic current */
233                 dyn_mA = voltage_mV * freq_KHz / 1000;
234                 /* Convert mV to V */
235                 dyn_mA = div64_s64(dyn_mA, 1000);
236                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
237                 /* dyn_const_n was scaled */
238                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
239
240                 if (power_mW != -1) {
241                         leakage_mW = leakage_mA * voltage_mV;
242                         dyn_mW = dyn_mA * voltage_mV;
243                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
244                                 goto end;
245                 } else if ((leakage_mA + dyn_mA) <= cur_mA) {
246                         goto end;
247                 }
248                 freq_KHz = 0;
249         }
250
251  end:
252         return edp_apply_fixed_limits(freq_KHz, params,
253                                         cur_effective, temp_C, n_cores_idx);
254 }
255
256 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
257                         unsigned int cpu_speedo_idx,
258                         unsigned int freq_volt_lut_size,
259                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
260 {
261         unsigned int i, j, freq;
262         int voltage_mV;
263
264         for (i = 0, j = 0, freq = 0;
265                  i < freq_volt_lut_size;
266                  i++, freq += FREQ_STEP) {
267
268                 /* Predict voltages */
269                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
270                         clk_cpu_g, freq);
271                 if (voltage_mV < 0) {
272                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
273                                __func__, freq, voltage_mV);
274                         return -EINVAL;
275                 }
276
277                 /* Cache frequency / voltage / voltage constant relationship */
278                 freq_volt_lut[i].freq = freq;
279                 freq_volt_lut[i].voltage_mV = voltage_mV;
280         }
281         return 0;
282 }
283
284 /*
285  * Finds the maximum frequency whose corresponding voltage is <= volt
286  * If no such frequency is found, the least possible frequency is returned
287  */
288 unsigned int tegra_edp_find_maxf(int volt)
289 {
290         unsigned int i;
291
292         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
293                 if (freq_voltage_lut_saved[i].voltage_mV > volt) {
294                         if (!i)
295                                 return freq_voltage_lut_saved[i].freq;
296                         break;
297                 }
298         }
299         return freq_voltage_lut_saved[i - 1].freq;
300 }
301
302
303 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
304 {
305         int i, array_size;
306         struct tegra_edp_cpu_leakage_params *params;
307
308         switch (tegra_get_chip_id()) {
309         case TEGRA_CHIPID_TEGRA11:
310                 params = tegra11x_get_leakage_params(0, &array_size);
311                 break;
312         case TEGRA_CHIPID_TEGRA14:
313                 params = tegra14x_get_leakage_params(0, &array_size);
314                 break;
315         case TEGRA_CHIPID_TEGRA12:
316                 params = tegra12x_get_leakage_params(0, &array_size);
317                 break;
318         case TEGRA_CHIPID_TEGRA3:
319         case TEGRA_CHIPID_TEGRA2:
320         default:
321                 array_size = 0;
322                 break;
323         }
324
325         for (i = 0; i < array_size; i++)
326                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
327                         *cpu_speedo_idx = i;
328                         return 0;
329                 }
330
331         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
332                __func__, cpu_speedo_id);
333         return -EINVAL;
334 }
335
336 static int init_cpu_edp_limits_calculated(void)
337 {
338         unsigned int max_nr_cpus = num_possible_cpus();
339         unsigned int temp_idx, n_cores_idx, pwr_idx;
340         unsigned int cpu_g_minf, cpu_g_maxf;
341         unsigned int iddq_mA;
342         unsigned int cpu_speedo_idx;
343         unsigned int cap, limit;
344         struct tegra_edp_limits *edp_calculated_limits;
345         struct tegra_edp_limits *reg_idle_calc_limits;
346         struct tegra_system_edp_entry *power_edp_calc_limits;
347         struct tegra_edp_cpu_leakage_params *params;
348         int ret;
349         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
350         int cpu_speedo_id = tegra_cpu_speedo_id();
351         int idle_cur = reg_idle_cur;
352
353         /* Determine all inputs to EDP formula */
354         iddq_mA = tegra_get_cpu_iddq_value();
355         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
356         if (ret)
357                 return ret;
358
359         switch (tegra_get_chip_id()) {
360         case TEGRA_CHIPID_TEGRA11:
361                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
362                 break;
363         case TEGRA_CHIPID_TEGRA14:
364                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
365                 break;
366         case TEGRA_CHIPID_TEGRA12:
367                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
368                 break;
369         case TEGRA_CHIPID_TEGRA3:
370         case TEGRA_CHIPID_TEGRA2:
371         default:
372                 return -EINVAL;
373         }
374
375         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
376                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
377         BUG_ON(!edp_calculated_limits);
378
379         reg_idle_calc_limits = kmalloc(sizeof(struct tegra_edp_limits)
380                                        * ARRAY_SIZE(temperatures), GFP_KERNEL);
381         BUG_ON(!reg_idle_calc_limits);
382
383         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
384                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
385         BUG_ON(!power_edp_calc_limits);
386
387         cpu_g_minf = 0;
388         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
389         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
390         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
391                                    * freq_voltage_lut_size, GFP_KERNEL);
392         if (!freq_voltage_lut) {
393                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
394                 kfree(power_edp_calc_limits);
395                 kfree(reg_idle_calc_limits);
396                 kfree(edp_calculated_limits);
397                 return -ENOMEM;
398         }
399
400         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
401                                 freq_voltage_lut_size, freq_voltage_lut);
402         if (ret) {
403                 kfree(power_edp_calc_limits);
404                 kfree(reg_idle_calc_limits);
405                 kfree(edp_calculated_limits);
406                 kfree(freq_voltage_lut);
407                 return ret;
408         }
409
410         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
411                 /* release previous table if present */
412                 kfree(freq_voltage_lut_saved);
413                 /* create table to save */
414                 freq_voltage_lut_saved =
415                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
416                         freq_voltage_lut_size, GFP_KERNEL);
417                 if (!freq_voltage_lut_saved) {
418                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
419                                 __func__);
420                         kfree(freq_voltage_lut);
421                         kfree(edp_calculated_limits);
422                         kfree(reg_idle_calc_limits);
423                         kfree(power_edp_calc_limits);
424                         return -ENOMEM;
425                 }
426                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
427         }
428         memcpy(freq_voltage_lut_saved,
429                 freq_voltage_lut,
430                 sizeof(struct tegra_edp_freq_voltage_table) *
431                         freq_voltage_lut_size);
432
433         /* Calculate EDP table */
434         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
435                 for (temp_idx = 0;
436                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
437                         edp_calculated_limits[temp_idx].temperature =
438                                 temperatures[temp_idx];
439                         limit = edp_calculate_maxf(params,
440                                                    temperatures[temp_idx],
441                                                    -1,
442                                                    0,
443                                                    iddq_mA,
444                                                    n_cores_idx);
445                         if (limit == -EINVAL)
446                                 return -EINVAL;
447                         /* apply safety cap if it is specified */
448                         if (n_cores_idx < 4) {
449                                 cap = params->safety_cap[n_cores_idx];
450                                 if (cap && cap < limit)
451                                         limit = cap;
452                         }
453                         edp_calculated_limits[temp_idx].
454                                 freq_limits[n_cores_idx] = limit;
455
456                         /* regulator mode threshold */
457                         if (!idle_cur)
458                                 continue;
459                         reg_idle_calc_limits[temp_idx].temperature =
460                                 temperatures[temp_idx];
461                         limit = edp_calculate_maxf(params,
462                                                    temperatures[temp_idx],
463                                                    -1,
464                                                    idle_cur,
465                                                    iddq_mA,
466                                                    n_cores_idx);
467
468                         /* remove idle table if any threshold is invalid */
469                         if (limit == -EINVAL) {
470                                 pr_warn("%s: Invalid idle limit for %dmA\n",
471                                         __func__, idle_cur);
472                                 idle_cur = 0;
473                                 continue;
474                         }
475
476                         /* No mode change below G CPU minimum rate */
477                         if (limit < clk_get_min_rate(clk_cpu_g) / 1000)
478                                 limit = 0;
479                         reg_idle_calc_limits[temp_idx].
480                                 freq_limits[n_cores_idx] = limit;
481                 }
482
483                 for (pwr_idx = 0;
484                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
485                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
486                                 power_cap_levels[pwr_idx] / 100;
487                         limit = edp_calculate_maxf(params,
488                                                    50,
489                                                    power_cap_levels[pwr_idx],
490                                                    0,
491                                                    iddq_mA,
492                                                    n_cores_idx);
493                         if (limit == -EINVAL)
494                                 return -EINVAL;
495                         power_edp_calc_limits[pwr_idx].
496                                 freq_limits[n_cores_idx] = limit;
497                 }
498         }
499
500         /*
501          * If this is an EDP table update, need to overwrite old table.
502          * The old table's address must remain valid.
503          */
504         if (edp_limits != edp_default_limits) {
505                 memcpy(edp_limits, edp_calculated_limits,
506                        sizeof(struct tegra_edp_limits)
507                        * ARRAY_SIZE(temperatures));
508                 kfree(edp_calculated_limits);
509         } else {
510                 edp_limits = edp_calculated_limits;
511                 edp_limits_size = ARRAY_SIZE(temperatures);
512         }
513
514         if (idle_cur && reg_idle_edp_limits) {
515                 memcpy(reg_idle_edp_limits, reg_idle_calc_limits,
516                        sizeof(struct tegra_edp_limits)
517                        * ARRAY_SIZE(temperatures));
518                 kfree(reg_idle_calc_limits);
519         } else if (idle_cur) {
520                 reg_idle_edp_limits = reg_idle_calc_limits;
521         } else {
522                 kfree(reg_idle_edp_limits);
523                 kfree(reg_idle_calc_limits);
524                 reg_idle_edp_limits = NULL;
525         }
526
527         if (power_edp_limits != power_edp_default_limits) {
528                 memcpy(power_edp_limits, power_edp_calc_limits,
529                        sizeof(struct tegra_system_edp_entry)
530                        * ARRAY_SIZE(power_cap_levels));
531                 kfree(power_edp_calc_limits);
532         } else {
533                 power_edp_limits = power_edp_calc_limits;
534                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
535         }
536
537         kfree(freq_voltage_lut);
538         return 0;
539 }
540
541 void tegra_recalculate_cpu_edp_limits(void)
542 {
543         u32 tegra_chip_id;
544
545         tegra_chip_id = tegra_get_chip_id();
546         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
547             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
548             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
549                 return;
550
551         if (init_cpu_edp_limits_calculated() == 0)
552                 return;
553
554         /* Revert to default EDP table on error */
555         edp_limits = edp_default_limits;
556         edp_limits_size = ARRAY_SIZE(edp_default_limits);
557
558         power_edp_limits = power_edp_default_limits;
559         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
560
561         kfree(reg_idle_edp_limits);
562         reg_idle_edp_limits = NULL;
563         pr_err("%s: Failed to recalculate EDP limits\n", __func__);
564 }
565
566 /*
567  * Specify regulator current in mA, e.g. 5000mA
568  * Use 0 for default
569  */
570 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
571 {
572         if (!regulator_mA)
573                 goto end;
574         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
575
576         switch (tegra_get_chip_id()) {
577         case TEGRA_CHIPID_TEGRA11:
578         case TEGRA_CHIPID_TEGRA14:
579         case TEGRA_CHIPID_TEGRA12:
580                 if (init_cpu_edp_limits_calculated() == 0)
581                         return;
582                 break;
583         case TEGRA_CHIPID_TEGRA2:
584         case TEGRA_CHIPID_TEGRA3:
585         default:
586                 BUG();
587                 break;
588         }
589
590  end:
591         edp_limits = edp_default_limits;
592         edp_limits_size = ARRAY_SIZE(edp_default_limits);
593
594         power_edp_limits = power_edp_default_limits;
595         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
596 }
597
598 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
599 {
600         *limits = edp_limits;
601         *size = edp_limits_size;
602 }
603
604 void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
605                                            unsigned int mode)
606 {
607         if (mode == REGULATOR_MODE_IDLE) {
608                 reg_idle_cur = regulator_mA;
609                 return;
610         }
611         pr_err("%s: Not supported regulator mode 0x%x\n", __func__, mode);
612 }
613
614 void tegra_get_cpu_reg_mode_limits(const struct tegra_edp_limits **limits,
615                                    int *size, unsigned int mode)
616 {
617         if (mode == REGULATOR_MODE_IDLE) {
618                 *limits = reg_idle_edp_limits;
619                 *size = edp_limits_size;
620         } else {
621                 *limits = NULL;
622                 *size = 0;
623         }
624 }
625
626 void tegra_get_system_edp_limits(const unsigned int **limits)
627 {
628         *limits = system_edp_limits;
629 }
630
631 void tegra_platform_edp_init(struct thermal_trip_info *trips,
632                                 int *num_trips, int margin)
633 {
634         const struct tegra_edp_limits *cpu_edp_limits;
635         struct thermal_trip_info *trip_state;
636         int i, cpu_edp_limits_size;
637
638         if (!trips || !num_trips)
639                 return;
640
641         /* edp capping */
642         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
643
644         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
645                 BUG();
646
647         for (i = 0; i < cpu_edp_limits_size-1; i++) {
648                 trip_state = &trips[*num_trips];
649
650                 trip_state->cdev_type = "cpu_edp";
651                 trip_state->trip_temp =
652                         (cpu_edp_limits[i].temperature * 1000) - margin;
653                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
654                 trip_state->upper = trip_state->lower = i + 1;
655
656                 (*num_trips)++;
657
658                 if (*num_trips >= THERMAL_MAX_TRIPS)
659                         BUG();
660         }
661 }
662
663 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
664 {
665         *size = power_edp_limits_size;
666         return power_edp_limits;
667 }
668
669
670 #ifdef CONFIG_TEGRA_GPU_EDP
671 void tegra_get_gpu_edp_limits(const struct tegra_edp_gpu_limits **limits,
672                                                         int *size)
673 {
674         *limits = gpu_edp_limits;
675         *size = gpu_edp_limits_size;
676 }
677
678 void tegra_platform_gpu_edp_init(struct thermal_trip_info *trips,
679                                 int *num_trips, int margin)
680 {
681         const struct tegra_edp_gpu_limits *gpu_edp_limits;
682         struct thermal_trip_info *trip_state;
683         int i, gpu_edp_limits_size;
684
685         if (!trips || !num_trips)
686                 return;
687
688         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
689
690         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
691                 BUG();
692
693         for (i = 0; i < gpu_edp_limits_size-1; i++) {
694                 trip_state = &trips[*num_trips];
695
696                 trip_state->cdev_type = "gpu_edp";
697                 trip_state->trip_temp =
698                         (gpu_edp_limits[i].temperature * 1000) - margin;
699                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
700                 trip_state->upper = trip_state->lower = i + 1;
701
702                 (*num_trips)++;
703
704                 if (*num_trips >= THERMAL_MAX_TRIPS)
705                         BUG();
706         }
707 }
708
709 static unsigned int edp_gpu_calculate_maxf(
710                                 struct tegra_edp_gpu_leakage_params *params,
711                                 int temp_C, int iddq_mA)
712 {
713         unsigned int voltage_mV, freq_KHz = 0;
714         unsigned int cur_effective = gpu_regulator_cur -
715                                      gpu_edp_reg_override_mA;
716         int f, i, j, k;
717         s64 leakage_mA, dyn_mA, leakage_calc_step;
718
719         for (f = freq_voltage_gpu_lut_size - 1; f >= 0; f--) {
720                 freq_KHz = freq_voltage_gpu_lut[f].freq / 1000;
721                 voltage_mV = freq_voltage_gpu_lut[f].voltage_mV;
722
723                 /* Calculate leakage current */
724                 leakage_mA = 0;
725                 for (i = 0; i <= 3; i++) {
726                         for (j = 0; j <= 3; j++) {
727                                 for (k = 0; k <= 3; k++) {
728                                         leakage_calc_step =
729                                                 params->leakage_consts_ijk
730                                                 [i][j][k] * edp_pow(iddq_mA, i);
731
732                                         /* Convert (mA)^i to (A)^i */
733                                         leakage_calc_step =
734                                                 div64_s64(leakage_calc_step,
735                                                           edp_pow(1000, i));
736                                         leakage_calc_step *=
737                                                 edp_pow(voltage_mV, j);
738
739                                         /* Convert (mV)^j to (V)^j */
740                                         leakage_calc_step =
741                                                 div64_s64(leakage_calc_step,
742                                                           edp_pow(1000, j));
743                                         leakage_calc_step *=
744                                                 edp_pow(temp_C, k);
745
746                                         /* Convert (C)^k to (scaled_C)^k */
747                                         leakage_calc_step =
748                                                 div64_s64(leakage_calc_step,
749                                                 edp_pow(params->temp_scaled,
750                                                         k));
751
752                                         /* leakage_consts_ijk was scaled */
753                                         leakage_calc_step =
754                                                 div64_s64(leakage_calc_step,
755                                                           params->ijk_scaled);
756
757                                         leakage_mA += leakage_calc_step;
758                                 }
759                         }
760                 }
761                 /* set floor for leakage current */
762                 if (leakage_mA <= params->leakage_min)
763                         leakage_mA = params->leakage_min;
764
765                 /* Calculate dynamic current */
766
767                 dyn_mA = voltage_mV * freq_KHz / 1000;
768                 /* Convert mV to V */
769                 dyn_mA = div64_s64(dyn_mA, 1000);
770                 dyn_mA *= params->dyn_consts_n;
771                 /* dyn_const_n was scaled */
772                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
773
774                 if ((leakage_mA + dyn_mA) <= cur_effective)
775                         goto end;
776
777                 freq_KHz = 0;
778         }
779
780  end:
781         return freq_KHz;
782 }
783
784 static int __init start_gpu_edp(void)
785 {
786         const char *cap_name = "edp.gbus";
787
788         gpu_cap_clk = tegra_get_clock_by_name(cap_name);
789         if (!gpu_cap_clk) {
790                 pr_err("gpu_edp_set_cdev_state: cannot get clock:%s\n",
791                                 cap_name);
792                 return -EINVAL;
793         }
794         gpu_edp_thermal_idx = 0;
795
796         return 0;
797 }
798
799
800 static int edp_gpu_relate_freq_voltage(struct clk *clk_gpu,
801                         unsigned int freq_volt_lut_size,
802                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
803 {
804         unsigned int i, j, freq;
805         int voltage_mV;
806
807         for (i = 0, j = 0, freq = 0;
808                  i < freq_volt_lut_size;
809                  i++, freq += GPU_FREQ_STEP) {
810
811                 /* Predict voltages */
812                 voltage_mV = tegra_dvfs_predict_peak_millivolts(clk_gpu, freq);
813                 if (voltage_mV < 0) {
814                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
815                                __func__, freq, voltage_mV);
816                         return -EINVAL;
817                 }
818
819                 /* Cache frequency / voltage / voltage constant relationship */
820                 freq_volt_lut[i].freq = freq;
821                 freq_volt_lut[i].voltage_mV = voltage_mV;
822         }
823         return 0;
824 }
825
826 static int init_gpu_edp_limits_calculated(void)
827 {
828         unsigned int gpu_minf, gpu_maxf;
829         unsigned int limit;
830         struct tegra_edp_gpu_limits *gpu_edp_calculated_limits;
831         struct tegra_edp_gpu_limits *temp;
832         struct tegra_edp_gpu_leakage_params *params;
833         int i, ret;
834         unsigned int gpu_iddq_mA;
835         u32 tegra_chip_id;
836         struct clk *gpu_clk = clk_get_parent(gpu_cap_clk);
837         tegra_chip_id = tegra_get_chip_id();
838
839         if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
840                 gpu_iddq_mA = tegra_get_gpu_iddq_value();
841                 params = tegra12x_get_gpu_leakage_params();
842         } else
843                 return -EINVAL;
844
845         gpu_edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_gpu_limits)
846                                 * ARRAY_SIZE(gpu_temperatures), GFP_KERNEL);
847         BUG_ON(!gpu_edp_calculated_limits);
848
849         gpu_minf = 0;
850         gpu_maxf = clk_get_max_rate(gpu_clk);
851
852         freq_voltage_gpu_lut_size = (gpu_maxf - gpu_minf) / GPU_FREQ_STEP + 1;
853         freq_voltage_gpu_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
854                                    * freq_voltage_gpu_lut_size, GFP_KERNEL);
855         if (!freq_voltage_gpu_lut) {
856                 pr_err("%s: failed alloc mem for gpu freq/voltage LUT\n",
857                          __func__);
858                 kfree(gpu_edp_calculated_limits);
859                 return -ENOMEM;
860         }
861
862         ret = edp_gpu_relate_freq_voltage(gpu_clk,
863                         freq_voltage_gpu_lut_size, freq_voltage_gpu_lut);
864
865         if (ret) {
866                 kfree(gpu_edp_calculated_limits);
867                 kfree(freq_voltage_gpu_lut);
868                 return ret;
869         }
870
871         for (i = 0; i < ARRAY_SIZE(gpu_temperatures); i++) {
872                 gpu_edp_calculated_limits[i].temperature =
873                         gpu_temperatures[i];
874                 limit = edp_gpu_calculate_maxf(params,
875                                                gpu_temperatures[i],
876                                                gpu_iddq_mA);
877                 if (limit == -EINVAL) {
878                         kfree(gpu_edp_calculated_limits);
879                         kfree(freq_voltage_gpu_lut);
880                         return -EINVAL;
881                 }
882
883                 gpu_edp_calculated_limits[i].freq_limits = limit;
884         }
885
886         /*
887          * If this is an EDP table update, need to overwrite old table.
888          * The old table's address must remain valid.
889          */
890         if (gpu_edp_limits != gpu_edp_default_limits &&
891                         gpu_edp_limits != gpu_edp_calculated_limits) {
892                 temp = gpu_edp_limits;
893                 gpu_edp_limits = gpu_edp_calculated_limits;
894                 gpu_edp_limits_size = ARRAY_SIZE(gpu_temperatures);
895                 kfree(temp);
896         } else {
897                 gpu_edp_limits = gpu_edp_calculated_limits;
898                 gpu_edp_limits_size = ARRAY_SIZE(gpu_temperatures);
899         }
900
901         kfree(freq_voltage_gpu_lut);
902
903         return 0;
904 }
905
906 void tegra_platform_edp_gpu_init(struct thermal_trip_info *trips,
907                                 int *num_trips, int margin)
908 {
909         const struct tegra_edp_gpu_limits *gpu_edp_limits;
910         struct thermal_trip_info *trip_state;
911         int i, gpu_edp_limits_size;
912
913         if (!trips || !num_trips)
914                 return;
915
916         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
917
918         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
919                 BUG();
920
921         for (i = 0; i < gpu_edp_limits_size-1; i++) {
922                 trip_state = &trips[*num_trips];
923
924                 trip_state->cdev_type = "gpu_edp";
925                 trip_state->trip_temp =
926                         (gpu_edp_limits[i].temperature * 1000) - margin;
927                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
928                 trip_state->upper = trip_state->lower = i + 1;
929
930                 (*num_trips)++;
931
932                 if (*num_trips >= THERMAL_MAX_TRIPS)
933                         BUG();
934         }
935 }
936
937 void __init tegra_init_gpu_edp_limits(unsigned int regulator_mA)
938 {
939         u32 tegra_chip_id;
940         tegra_chip_id = tegra_get_chip_id();
941
942         if (!regulator_mA)
943                 goto end;
944         gpu_regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
945
946         if (start_gpu_edp()) {
947                 WARN(1, "GPU EDP failed to set initial limits");
948                 return;
949         }
950
951         switch (tegra_chip_id) {
952         case TEGRA_CHIPID_TEGRA12:
953                 if (init_gpu_edp_limits_calculated() == 0)
954                         return;
955                 break;
956
957         default:
958                 BUG();
959                 break;
960         }
961
962  end:
963         gpu_edp_limits = gpu_edp_default_limits;
964         gpu_edp_limits_size = ARRAY_SIZE(gpu_edp_default_limits);
965 }
966
967 static int gpu_edp_get_cdev_max_state(struct thermal_cooling_device *cdev,
968                                        unsigned long *max_state)
969 {
970         *max_state = gpu_edp_limits_size - 1;
971         return 0;
972 }
973
974 static int gpu_edp_get_cdev_cur_state(struct thermal_cooling_device *cdev,
975                                        unsigned long *cur_state)
976 {
977         *cur_state = gpu_edp_thermal_idx;
978         return 0;
979 }
980
981 static int gpu_edp_set_cdev_state(struct thermal_cooling_device *cdev,
982                                    unsigned long cur_state)
983 {
984         unsigned long clk_rate;
985         BUG_ON(cur_state >= gpu_edp_limits_size);
986         clk_rate = gpu_edp_limits[cur_state].freq_limits;
987         mutex_lock(&gpu_edp_lock);
988         gpu_edp_thermal_idx = cur_state;
989         clk_set_rate(gpu_cap_clk, clk_rate * 1000);
990         mutex_unlock(&gpu_edp_lock);
991         return 0;
992 }
993
994 static struct thermal_cooling_device_ops gpu_edp_cooling_ops = {
995         .get_max_state = gpu_edp_get_cdev_max_state,
996         .get_cur_state = gpu_edp_get_cdev_cur_state,
997         .set_cur_state = gpu_edp_set_cdev_state,
998 };
999
1000 static int __init tegra_gpu_edp_late_init(void)
1001 {
1002         if (IS_ERR_OR_NULL(thermal_cooling_device_register(
1003                 "gpu_edp", NULL, &gpu_edp_cooling_ops)))
1004                 pr_err("%s: failed to register edp cooling device\n", __func__);
1005
1006         return 0;
1007 }
1008 late_initcall(tegra_gpu_edp_late_init);
1009
1010 #endif
1011
1012 #ifdef CONFIG_DEBUG_FS
1013
1014 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
1015 {
1016 #ifdef CONFIG_CPU_FREQ
1017         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
1018 #endif
1019         return 0;
1020 }
1021
1022 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
1023 {
1024         int i;
1025
1026         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1027                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1028         for (i = 0; i < edp_limits_size; i++) {
1029                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1030                            i == th_idx ? '>' : ' ',
1031                            edp_limits[i].temperature,
1032                            edp_limits[i].freq_limits[0],
1033                            edp_limits[i].freq_limits[1],
1034                            edp_limits[i].freq_limits[2],
1035                            edp_limits[i].freq_limits[3]);
1036         }
1037 }
1038
1039 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
1040 {
1041         int i;
1042
1043         seq_printf(s, "%6s %10s %10s\n",
1044                    " Temp.", "1-core", "2-cores");
1045         for (i = 0; i < edp_limits_size; i++) {
1046                 seq_printf(s, "%c%3dC: %10u %10u\n",
1047                            i == th_idx ? '>' : ' ',
1048                            edp_limits[i].temperature,
1049                            edp_limits[i].freq_limits[0],
1050                            edp_limits[i].freq_limits[1]);
1051         }
1052 }
1053
1054 static inline void edp_show_4core_reg_mode_table(struct seq_file *s, int th_idx)
1055 {
1056         int i;
1057
1058         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1059                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1060         for (i = 0; i < edp_limits_size; i++) {
1061                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1062                            i == th_idx ? '>' : ' ',
1063                            reg_idle_edp_limits[i].temperature,
1064                            reg_idle_edp_limits[i].freq_limits[0],
1065                            reg_idle_edp_limits[i].freq_limits[1],
1066                            reg_idle_edp_limits[i].freq_limits[2],
1067                            reg_idle_edp_limits[i].freq_limits[3]);
1068         }
1069 }
1070
1071 static inline void edp_show_2core_reg_mode_table(struct seq_file *s, int th_idx)
1072 {
1073         int i;
1074
1075         seq_printf(s, "%6s %10s %10s\n",
1076                    " Temp.", "1-core", "2-cores");
1077         for (i = 0; i < edp_limits_size; i++) {
1078                 seq_printf(s, "%c%3dC: %10u %10u\n",
1079                            i == th_idx ? '>' : ' ',
1080                            reg_idle_edp_limits[i].temperature,
1081                            reg_idle_edp_limits[i].freq_limits[0],
1082                            reg_idle_edp_limits[i].freq_limits[1]);
1083         }
1084 }
1085
1086 static inline void edp_show_2core_system_table(struct seq_file *s)
1087 {
1088         seq_printf(s, "%10u %10u\n",
1089                    system_edp_limits[0],
1090                    system_edp_limits[1]);
1091 }
1092
1093 static inline void edp_show_4core_system_table(struct seq_file *s)
1094 {
1095         seq_printf(s, "%10u %10u %10u %10u\n",
1096                    system_edp_limits[0],
1097                    system_edp_limits[1],
1098                    system_edp_limits[2],
1099                    system_edp_limits[3]);
1100 }
1101
1102 static int edp_debugfs_show(struct seq_file *s, void *data)
1103 {
1104         unsigned int max_nr_cpus = num_possible_cpus();
1105         int th_idx;
1106
1107         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
1108                 seq_printf(s, "Unsupported number of CPUs\n");
1109                 return 0;
1110         }
1111
1112 #ifdef CONFIG_CPU_FREQ
1113         tegra_get_edp_limit(&th_idx);
1114 #else
1115         th_idx = 0;
1116 #endif
1117
1118         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
1119                    edp_limits == edp_default_limits ? "**default** " : "",
1120                    regulator_cur - edp_reg_override_mA,
1121                    regulator_cur, edp_reg_override_mA);
1122
1123         if (max_nr_cpus == 2)
1124                 edp_show_2core_edp_table(s, th_idx);
1125         else if (max_nr_cpus == 4)
1126                 edp_show_4core_edp_table(s, th_idx);
1127
1128         if (reg_idle_edp_limits) {
1129                 seq_printf(s, "\n-- Regulator mode thresholds @ %dmA --\n",
1130                            reg_idle_cur);
1131                 if (max_nr_cpus == 2)
1132                         edp_show_2core_reg_mode_table(s, th_idx);
1133                 else if (max_nr_cpus == 4)
1134                         edp_show_4core_reg_mode_table(s, th_idx);
1135         }
1136
1137         if (system_edp_limits) {
1138                 seq_printf(s, "\n-- System EDP table --\n");
1139                 if (max_nr_cpus == 2)
1140                         edp_show_2core_system_table(s);
1141                 else if (max_nr_cpus == 4)
1142                         edp_show_4core_system_table(s);
1143         }
1144
1145         return 0;
1146 }
1147
1148 #ifdef CONFIG_TEGRA_GPU_EDP
1149 static int gpu_edp_limit_debugfs_show(struct seq_file *s, void *data)
1150 {
1151         seq_printf(s, "%u\n", gpu_edp_limits[gpu_edp_thermal_idx].freq_limits);
1152         return 0;
1153 }
1154
1155 static inline void gpu_edp_show_table(struct seq_file *s)
1156 {
1157         int i;
1158
1159         seq_printf(s, "%6s %10s\n",
1160                    " Temp.", "Freq_limit");
1161         for (i = 0; i < gpu_edp_limits_size; i++) {
1162                 seq_printf(s, "%3dC: %10u\n",
1163                            gpu_edp_limits[i].temperature,
1164                            gpu_edp_limits[i].freq_limits);
1165         }
1166 }
1167
1168 static int gpu_edp_debugfs_show(struct seq_file *s, void *data)
1169 {
1170         seq_printf(s, "-- VDD_GPU %sEDP table (%umA = %umA - %umA) --\n",
1171                    gpu_edp_limits == gpu_edp_default_limits ?
1172                    "**default** " : "",
1173                    gpu_regulator_cur - gpu_edp_reg_override_mA,
1174                    gpu_regulator_cur, gpu_edp_reg_override_mA);
1175
1176         gpu_edp_show_table(s);
1177
1178         return 0;
1179 }
1180
1181 static int gpu_edp_reg_override_show(struct seq_file *s, void *data)
1182 {
1183         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
1184                    gpu_edp_reg_override_mA,
1185                    gpu_regulator_cur - gpu_edp_reg_override_mA);
1186         return 0;
1187 }
1188
1189 static int gpu_edp_reg_override_write(struct file *file,
1190         const char __user *userbuf, size_t count, loff_t *ppos)
1191 {
1192         char buf[32], *end;
1193         unsigned int gpu_edp_reg_override_mA_temp;
1194         unsigned int gpu_edp_reg_override_mA_prev = gpu_edp_reg_override_mA;
1195         u32 tegra_chip_id;
1196
1197         tegra_chip_id = tegra_get_chip_id();
1198         if (tegra_chip_id != TEGRA_CHIPID_TEGRA12)
1199                 goto override_err;
1200
1201         if (sizeof(buf) <= count)
1202                 goto override_err;
1203
1204         if (copy_from_user(buf, userbuf, count))
1205                 goto override_err;
1206
1207         /* terminate buffer and trim - white spaces may be appended
1208          *  at the end when invoked from shell command line */
1209         buf[count] ='\0';
1210         strim(buf);
1211
1212         gpu_edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
1213         if (*end != '\0')
1214                 goto override_err;
1215
1216         if (gpu_edp_reg_override_mA_temp >= gpu_regulator_cur)
1217                 goto override_err;
1218
1219         if (gpu_edp_reg_override_mA == gpu_edp_reg_override_mA_temp)
1220                 return count;
1221
1222         gpu_edp_reg_override_mA = gpu_edp_reg_override_mA_temp;
1223         if (init_gpu_edp_limits_calculated()) {
1224                 /* Revert to previous override value if new value fails */
1225                 gpu_edp_reg_override_mA = gpu_edp_reg_override_mA_prev;
1226                 goto override_err;
1227         }
1228
1229         gpu_edp_set_cdev_state(NULL, gpu_edp_thermal_idx);
1230         pr_info("Reinitialized VDD_GPU EDP table with regulator current limit"
1231                 " %u mA\n", gpu_regulator_cur - gpu_edp_reg_override_mA);
1232
1233         return count;
1234
1235  override_err:
1236         pr_err("FAILED: Override VDD_GPU EDP table with \"%s\"",
1237                buf);
1238         return -EINVAL;
1239 }
1240 #endif
1241
1242 static int edp_reg_override_show(struct seq_file *s, void *data)
1243 {
1244         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
1245                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
1246         return 0;
1247 }
1248
1249 static int edp_reg_override_write(struct file *file,
1250         const char __user *userbuf, size_t count, loff_t *ppos)
1251 {
1252         char buf[32], *end;
1253         unsigned int edp_reg_override_mA_temp;
1254         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
1255         u32 tegra_chip_id;
1256
1257         tegra_chip_id = tegra_get_chip_id();
1258         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
1259                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
1260                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
1261                 goto override_err;
1262
1263         if (sizeof(buf) <= count)
1264                 goto override_err;
1265
1266         if (copy_from_user(buf, userbuf, count))
1267                 goto override_err;
1268
1269         /* terminate buffer and trim - white spaces may be appended
1270          *  at the end when invoked from shell command line */
1271         buf[count]='\0';
1272         strim(buf);
1273
1274         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
1275         if (*end != '\0')
1276                 goto override_err;
1277
1278         if (edp_reg_override_mA_temp >= regulator_cur)
1279                 goto override_err;
1280
1281         if (edp_reg_override_mA == edp_reg_override_mA_temp)
1282                 return count;
1283
1284         edp_reg_override_mA = edp_reg_override_mA_temp;
1285         if (init_cpu_edp_limits_calculated()) {
1286                 /* Revert to previous override value if new value fails */
1287                 edp_reg_override_mA = edp_reg_override_mA_prev;
1288                 goto override_err;
1289         }
1290
1291 #ifdef CONFIG_CPU_FREQ
1292         if (tegra_cpu_set_speed_cap(NULL)) {
1293                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
1294                 goto override_out;
1295         }
1296
1297         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
1298                         " %u mA\n", regulator_cur - edp_reg_override_mA);
1299 #else
1300         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
1301 #endif
1302
1303         return count;
1304
1305 override_err:
1306         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
1307                buf);
1308 #ifdef CONFIG_CPU_FREQ
1309 override_out:
1310 #endif
1311         return -EINVAL;
1312 }
1313
1314 static int edp_debugfs_open(struct inode *inode, struct file *file)
1315 {
1316         return single_open(file, edp_debugfs_show, inode->i_private);
1317 }
1318
1319 #ifdef CONFIG_TEGRA_GPU_EDP
1320 static int gpu_edp_debugfs_open(struct inode *inode, struct file *file)
1321 {
1322         return single_open(file, gpu_edp_debugfs_show, inode->i_private);
1323 }
1324
1325 static int gpu_edp_limit_debugfs_open(struct inode *inode, struct file *file)
1326 {
1327         return single_open(file, gpu_edp_limit_debugfs_show, inode->i_private);
1328 }
1329
1330 static int gpu_edp_reg_override_open(struct inode *inode, struct file *file)
1331 {
1332         return single_open(file, gpu_edp_reg_override_show, inode->i_private);
1333 }
1334 #endif
1335
1336 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
1337 {
1338         return single_open(file, edp_limit_debugfs_show, inode->i_private);
1339 }
1340
1341 static int edp_reg_override_open(struct inode *inode, struct file *file)
1342 {
1343         return single_open(file, edp_reg_override_show, inode->i_private);
1344 }
1345
1346 static const struct file_operations edp_debugfs_fops = {
1347         .open           = edp_debugfs_open,
1348         .read           = seq_read,
1349         .llseek         = seq_lseek,
1350         .release        = single_release,
1351 };
1352
1353 #ifdef CONFIG_TEGRA_GPU_EDP
1354 static const struct file_operations gpu_edp_debugfs_fops = {
1355         .open           = gpu_edp_debugfs_open,
1356         .read           = seq_read,
1357         .llseek         = seq_lseek,
1358         .release        = single_release,
1359 };
1360
1361 static const struct file_operations gpu_edp_limit_debugfs_fops = {
1362         .open           = gpu_edp_limit_debugfs_open,
1363         .read           = seq_read,
1364         .llseek         = seq_lseek,
1365         .release        = single_release,
1366 };
1367
1368 static const struct file_operations gpu_edp_reg_override_debugfs_fops = {
1369         .open           = gpu_edp_reg_override_open,
1370         .read           = seq_read,
1371         .write          = gpu_edp_reg_override_write,
1372         .llseek         = seq_lseek,
1373         .release        = single_release,
1374 };
1375 #endif
1376
1377 static const struct file_operations edp_limit_debugfs_fops = {
1378         .open           = edp_limit_debugfs_open,
1379         .read           = seq_read,
1380         .llseek         = seq_lseek,
1381         .release        = single_release,
1382 };
1383
1384 static const struct file_operations edp_reg_override_debugfs_fops = {
1385         .open           = edp_reg_override_open,
1386         .read           = seq_read,
1387         .write          = edp_reg_override_write,
1388         .llseek         = seq_lseek,
1389         .release        = single_release,
1390 };
1391
1392 static int reg_idle_cur_get(void *data, u64 *val)
1393 {
1394         *val = reg_idle_cur;
1395         return 0;
1396 }
1397 static int reg_idle_cur_set(void *data, u64 val)
1398 {
1399         int ret;
1400
1401         ret = tegra_cpu_reg_mode_force_normal(true);
1402         if (ret) {
1403                 pr_err("%s: Failed to force regulator normal mode\n", __func__);
1404                 return ret;
1405         }
1406
1407         reg_idle_cur = (int)val;
1408         tegra_update_cpu_edp_limits();
1409         return 0;
1410 }
1411 DEFINE_SIMPLE_ATTRIBUTE(reg_idle_cur_debugfs_fops,
1412                         reg_idle_cur_get, reg_idle_cur_set, "%llu\n");
1413
1414 #ifdef CONFIG_TEGRA_GPU_EDP
1415 static int __init tegra_gpu_edp_debugfs_init(struct dentry *edp_dir)
1416 {
1417         struct dentry *d_edp;
1418         struct dentry *d_edp_limit;
1419         struct dentry *d_edp_reg_override;
1420         struct dentry *vdd_gpu_dir;
1421
1422         if (!tegra_platform_is_silicon())
1423                 return -ENOSYS;
1424
1425         vdd_gpu_dir = debugfs_create_dir("vdd_gpu", edp_dir);
1426         if (!vdd_gpu_dir)
1427                 goto err_0;
1428
1429         d_edp = debugfs_create_file("gpu_edp",  S_IRUGO, vdd_gpu_dir, NULL,
1430                                     &gpu_edp_debugfs_fops);
1431         if (!d_edp)
1432                 goto err_1;
1433
1434         d_edp_limit = debugfs_create_file("gpu_edp_limit", S_IRUGO, vdd_gpu_dir,
1435                                           NULL, &gpu_edp_limit_debugfs_fops);
1436         if (!d_edp_limit)
1437                 goto err_2;
1438
1439         d_edp_reg_override = debugfs_create_file("gpu_edp_reg_override",
1440                                 S_IRUGO | S_IWUSR, vdd_gpu_dir, NULL,
1441                                 &gpu_edp_reg_override_debugfs_fops);
1442         if (!d_edp_reg_override)
1443                 goto err_3;
1444
1445         return 0;
1446
1447 err_3:
1448         debugfs_remove(d_edp_limit);
1449 err_2:
1450         debugfs_remove(d_edp);
1451 err_1:
1452         debugfs_remove(vdd_gpu_dir);
1453 err_0:
1454         return -ENOMEM;
1455 }
1456 #endif
1457
1458 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
1459 static __init struct dentry *tegra_edp_debugfs_dir(void)
1460 {
1461         if (edp_debugfs_dir)
1462                 return edp_debugfs_dir;
1463         else
1464                 return debugfs_create_dir("edp", NULL);
1465 }
1466 #else
1467 static __init struct dentry *tegra_edp_debugfs_dir(void)
1468 {
1469         return debugfs_create_dir("edp", NULL);
1470 }
1471 #endif
1472
1473 static int __init tegra_edp_debugfs_init(void)
1474 {
1475         struct dentry *d_reg_idle_cur;
1476         struct dentry *d_edp;
1477         struct dentry *d_edp_limit;
1478         struct dentry *d_edp_reg_override;
1479         struct dentry *edp_dir;
1480         struct dentry *vdd_cpu_dir;
1481
1482         if (!tegra_platform_is_silicon())
1483                 return -ENOSYS;
1484
1485         edp_dir = tegra_edp_debugfs_dir();
1486         if (!edp_dir)
1487                 goto err_0;
1488
1489         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
1490         if (!vdd_cpu_dir)
1491                 goto err_0;
1492
1493         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
1494                                     &edp_debugfs_fops);
1495         if (!d_edp)
1496                 goto err_1;
1497
1498         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
1499                                           NULL, &edp_limit_debugfs_fops);
1500         if (!d_edp_limit)
1501                 goto err_2;
1502
1503         d_edp_reg_override = debugfs_create_file("edp_reg_override",
1504                                         S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1505                                         &edp_reg_override_debugfs_fops);
1506         if (!d_edp_reg_override)
1507                 goto err_3;
1508
1509         d_reg_idle_cur = debugfs_create_file("reg_idle_mA",
1510                                         S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1511                                         &reg_idle_cur_debugfs_fops);
1512         if (!d_reg_idle_cur)
1513                 goto err_4;
1514
1515         if (tegra_core_edp_debugfs_init(edp_dir))
1516                 return -ENOMEM;
1517
1518 #ifdef CONFIG_TEGRA_GPU_EDP
1519         if (tegra_gpu_edp_debugfs_init(edp_dir))
1520                 return -ENOMEM;
1521 #endif
1522
1523         return 0;
1524
1525 err_4:
1526         debugfs_remove(d_edp_reg_override);
1527 err_3:
1528         debugfs_remove(d_edp_limit);
1529 err_2:
1530         debugfs_remove(d_edp);
1531 err_1:
1532         debugfs_remove(vdd_cpu_dir);
1533 err_0:
1534         return -ENOMEM;
1535 }
1536
1537 late_initcall(tegra_edp_debugfs_init);
1538 #endif /* CONFIG_DEBUG_FS */