arm: tegra: loose cpu edp power table calculation.
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/tegra-fuse.h>
30
31 #include <mach/edp.h>
32
33 #include "dvfs.h"
34 #include "clock.h"
35 #include "cpu-tegra.h"
36 #include "common.h"
37
38 #define FREQ_STEP 12750000
39 #define OVERRIDE_DEFAULT 6000
40
41 #define GPU_FREQ_STEP 12000000
42
43 static struct tegra_edp_limits *edp_limits;
44 static int edp_limits_size;
45 static unsigned int regulator_cur;
46 /* Value to subtract from regulator current limit */
47 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
48
49 static struct tegra_edp_limits *reg_idle_edp_limits;
50 static int reg_idle_cur;
51
52 static const unsigned int *system_edp_limits;
53
54 static struct tegra_system_edp_entry *power_edp_limits;
55 static int power_edp_limits_size;
56
57 /*
58  * "Safe entry" to be used when no match for speedo_id /
59  * regulator_cur is found; must be the last one
60  */
61 static struct tegra_edp_limits edp_default_limits[] = {
62         {85, {1000000, 1000000, 1000000, 1000000} },
63 };
64
65 static struct tegra_system_edp_entry power_edp_default_limits[] = {
66         {0, 20, {1000000, 1000000, 1000000, 1000000} },
67 };
68
69 /* Constants for EDP calculations */
70 static const int temperatures[] = { /* degree celcius (C) */
71         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
72 };
73
74 static const int power_cap_levels[] = { /* milliwatts (mW) */
75           500,  1000,  1500,  2000,  2500,  3000,  3500,
76          4000,  4500,  5000,  5500,  6000,  6500,  7000,
77          7500,  8000,  8500,  9000,  9500, 10000, 10500,
78         11000, 11500, 12000, 12500, 13000, 13500, 14000,
79         14500, 15000, 15500, 16000, 16500, 17000
80 };
81
82 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
83 static unsigned int freq_voltage_lut_size_saved;
84 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
85 static unsigned int freq_voltage_lut_size;
86
87 #ifdef CONFIG_TEGRA_GPU_EDP
88 static struct tegra_edp_gpu_limits *edp_gpu_limits;
89 static int edp_gpu_limits_size;
90 static int edp_gpu_thermal_idx;
91 static struct clk *gpu_cap_clk;
92 static DEFINE_MUTEX(gpu_edp_lock);
93
94 static struct tegra_edp_freq_voltage_table *freq_voltage_gpu_lut;
95 static unsigned int freq_voltage_gpu_lut_size;
96
97 static unsigned int gpu_regulator_cur;
98
99 static struct tegra_edp_gpu_limits edp_gpu_default_limits[] = {
100         {85, 350000},
101 };
102
103 static const int gpu_temperatures[] = { /* degree celcius (C) */
104         20, 50, 70, 75, 80, 85, 90, 95, 100, 105,
105 };
106 #endif
107
108 static inline s64 edp_pow(s64 val, int pwr)
109 {
110         s64 retval = 1;
111
112         while (val && pwr) {
113                 if (pwr & 1)
114                         retval *= val;
115                 pwr >>= 1;
116                 if (pwr)
117                         val *= val;
118         }
119
120         return retval;
121 }
122
123
124 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
125 static inline unsigned int edp_apply_fixed_limits(
126                                 unsigned int in_freq_KHz,
127                                 struct tegra_edp_cpu_leakage_params *params,
128                                 unsigned int cur_effective,
129                                 int temp_C, int n_cores_idx)
130 {
131         unsigned int out_freq_KHz = in_freq_KHz;
132         unsigned int max_cur, max_temp, max_freq;
133         int i;
134
135         /* Apply any additional fixed limits */
136         for (i = 0; i < 8; i++) {
137                 max_cur = params->max_current_cap[i].max_cur;
138                 if (max_cur != 0 && cur_effective <= max_cur) {
139                         max_temp = params->max_current_cap[i].max_temp;
140                         if (max_temp != 0 && temp_C > max_temp) {
141                                 max_freq = params->max_current_cap[i].
142                                         max_freq[n_cores_idx];
143                                 if (max_freq && max_freq < out_freq_KHz)
144                                         out_freq_KHz = max_freq;
145                         }
146                 }
147         }
148
149         return out_freq_KHz;
150 }
151 #else
152 #define edp_apply_fixed_limits(freq, unused...) (freq)
153 #endif
154
155 /*
156  * Find the maximum frequency that results in dynamic and leakage current that
157  * is less than the regulator current limit.
158  * temp_C - valid or -EINVAL
159  * power_mW - valid or -1 (infinite) or -EINVAL
160  */
161 static unsigned int edp_calculate_maxf(
162                                 struct tegra_edp_cpu_leakage_params *params,
163                                 int temp_C, int power_mW, unsigned int cur_mA,
164                                 int iddq_mA,
165                                 int n_cores_idx)
166 {
167         unsigned int voltage_mV, freq_KHz = 0;
168         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
169         int f, i, j, k;
170         s64 leakage_mA, dyn_mA, leakage_calc_step;
171         s64 leakage_mW, dyn_mW;
172
173         /* If current limit is not specified, use max by default */
174         cur_mA = cur_mA ? : cur_effective;
175
176         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
177                 freq_KHz = freq_voltage_lut[f].freq / 1000;
178                 voltage_mV = freq_voltage_lut[f].voltage_mV;
179
180                 /* Constrain Volt-Temp */
181                 if (params->volt_temp_cap.temperature &&
182                     temp_C > params->volt_temp_cap.temperature &&
183                     params->volt_temp_cap.voltage_limit_mV &&
184                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
185                         continue;
186
187                 /* Calculate leakage current */
188                 leakage_mA = 0;
189                 for (i = 0; i <= 3; i++) {
190                         for (j = 0; j <= 3; j++) {
191                                 for (k = 0; k <= 3; k++) {
192                                         leakage_calc_step =
193                                                 params->leakage_consts_ijk
194                                                 [i][j][k] * edp_pow(iddq_mA, i);
195                                         /* Convert (mA)^i to (A)^i */
196                                         leakage_calc_step =
197                                                 div64_s64(leakage_calc_step,
198                                                           edp_pow(1000, i));
199                                         leakage_calc_step *=
200                                                 edp_pow(voltage_mV, j);
201                                         /* Convert (mV)^j to (V)^j */
202                                         leakage_calc_step =
203                                                 div64_s64(leakage_calc_step,
204                                                           edp_pow(1000, j));
205                                         leakage_calc_step *=
206                                                 edp_pow(temp_C, k);
207                                         /* Convert (C)^k to (scaled_C)^k */
208                                         leakage_calc_step =
209                                                 div64_s64(leakage_calc_step,
210                                                 edp_pow(params->temp_scaled,
211                                                         k));
212                                         /* leakage_consts_ijk was scaled */
213                                         leakage_calc_step =
214                                                 div64_s64(leakage_calc_step,
215                                                           params->ijk_scaled);
216                                         leakage_mA += leakage_calc_step;
217                                 }
218                         }
219                 }
220
221                 /* set floor for leakage current */
222                 if (leakage_mA <= params->leakage_min)
223                         leakage_mA = params->leakage_min;
224
225                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
226
227                 /* leakage_const_n was scaled */
228                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
229
230                 /* Calculate dynamic current */
231                 dyn_mA = voltage_mV * freq_KHz / 1000;
232                 /* Convert mV to V */
233                 dyn_mA = div64_s64(dyn_mA, 1000);
234                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
235                 /* dyn_const_n was scaled */
236                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
237
238                 if (power_mW != -1) {
239                         leakage_mW = leakage_mA * voltage_mV;
240                         dyn_mW = dyn_mA * voltage_mV;
241                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
242                                 goto end;
243                 } else if ((leakage_mA + dyn_mA) <= cur_mA) {
244                         goto end;
245                 }
246                 freq_KHz = 0;
247         }
248
249  end:
250         return edp_apply_fixed_limits(freq_KHz, params,
251                                         cur_effective, temp_C, n_cores_idx);
252 }
253
254 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
255                         unsigned int cpu_speedo_idx,
256                         unsigned int freq_volt_lut_size,
257                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
258 {
259         unsigned int i, j, freq;
260         int voltage_mV;
261
262         for (i = 0, j = 0, freq = 0;
263                  i < freq_volt_lut_size;
264                  i++, freq += FREQ_STEP) {
265
266                 /* Predict voltages */
267                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
268                         clk_cpu_g, freq);
269                 if (voltage_mV < 0) {
270                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
271                                __func__, freq, voltage_mV);
272                         return -EINVAL;
273                 }
274
275                 /* Cache frequency / voltage / voltage constant relationship */
276                 freq_volt_lut[i].freq = freq;
277                 freq_volt_lut[i].voltage_mV = voltage_mV;
278         }
279         return 0;
280 }
281
282 /*
283  * Finds the maximum frequency whose corresponding voltage is <= volt
284  * If no such frequency is found, the least possible frequency is returned
285  */
286 unsigned int tegra_edp_find_maxf(int volt)
287 {
288         unsigned int i;
289
290         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
291                 if (freq_voltage_lut_saved[i].voltage_mV > volt) {
292                         if (!i)
293                                 return freq_voltage_lut_saved[i].freq;
294                         break;
295                 }
296         }
297         return freq_voltage_lut_saved[i - 1].freq;
298 }
299
300
301 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
302 {
303         int i, array_size;
304         struct tegra_edp_cpu_leakage_params *params;
305
306         switch (tegra_get_chip_id()) {
307         case TEGRA_CHIPID_TEGRA11:
308                 params = tegra11x_get_leakage_params(0, &array_size);
309                 break;
310         case TEGRA_CHIPID_TEGRA14:
311                 params = tegra14x_get_leakage_params(0, &array_size);
312                 break;
313         case TEGRA_CHIPID_TEGRA12:
314                 params = tegra12x_get_leakage_params(0, &array_size);
315                 break;
316         case TEGRA_CHIPID_TEGRA3:
317         case TEGRA_CHIPID_TEGRA2:
318         default:
319                 array_size = 0;
320                 break;
321         }
322
323         for (i = 0; i < array_size; i++)
324                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
325                         *cpu_speedo_idx = i;
326                         return 0;
327                 }
328
329         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
330                __func__, cpu_speedo_id);
331         return -EINVAL;
332 }
333
334 static int init_cpu_edp_limits_calculated(void)
335 {
336         unsigned int max_nr_cpus = num_possible_cpus();
337         unsigned int temp_idx, n_cores_idx, pwr_idx;
338         unsigned int cpu_g_minf, cpu_g_maxf;
339         unsigned int iddq_mA;
340         unsigned int cpu_speedo_idx;
341         unsigned int cap, limit;
342         struct tegra_edp_limits *edp_calculated_limits;
343         struct tegra_edp_limits *reg_idle_calc_limits;
344         struct tegra_system_edp_entry *power_edp_calc_limits;
345         struct tegra_edp_cpu_leakage_params *params;
346         int ret;
347         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
348         int cpu_speedo_id = tegra_cpu_speedo_id();
349         int idle_cur = reg_idle_cur;
350
351         /* Determine all inputs to EDP formula */
352         iddq_mA = tegra_get_cpu_iddq_value();
353         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
354         if (ret)
355                 return ret;
356
357         switch (tegra_get_chip_id()) {
358         case TEGRA_CHIPID_TEGRA11:
359                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
360                 break;
361         case TEGRA_CHIPID_TEGRA14:
362                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
363                 break;
364         case TEGRA_CHIPID_TEGRA12:
365                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
366                 break;
367         case TEGRA_CHIPID_TEGRA3:
368         case TEGRA_CHIPID_TEGRA2:
369         default:
370                 return -EINVAL;
371         }
372
373         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
374                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
375         BUG_ON(!edp_calculated_limits);
376
377         reg_idle_calc_limits = kmalloc(sizeof(struct tegra_edp_limits)
378                                        * ARRAY_SIZE(temperatures), GFP_KERNEL);
379         BUG_ON(!reg_idle_calc_limits);
380
381         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
382                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
383         BUG_ON(!power_edp_calc_limits);
384
385         cpu_g_minf = 0;
386         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
387         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
388         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
389                                    * freq_voltage_lut_size, GFP_KERNEL);
390         if (!freq_voltage_lut) {
391                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
392                 kfree(power_edp_calc_limits);
393                 kfree(reg_idle_calc_limits);
394                 kfree(edp_calculated_limits);
395                 return -ENOMEM;
396         }
397
398         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
399                                 freq_voltage_lut_size, freq_voltage_lut);
400         if (ret) {
401                 kfree(power_edp_calc_limits);
402                 kfree(reg_idle_calc_limits);
403                 kfree(edp_calculated_limits);
404                 kfree(freq_voltage_lut);
405                 return ret;
406         }
407
408         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
409                 /* release previous table if present */
410                 kfree(freq_voltage_lut_saved);
411                 /* create table to save */
412                 freq_voltage_lut_saved =
413                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
414                         freq_voltage_lut_size, GFP_KERNEL);
415                 if (!freq_voltage_lut_saved) {
416                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
417                                 __func__);
418                         kfree(freq_voltage_lut);
419                         return -ENOMEM;
420                 }
421                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
422         }
423         memcpy(freq_voltage_lut_saved,
424                 freq_voltage_lut,
425                 sizeof(struct tegra_edp_freq_voltage_table) *
426                         freq_voltage_lut_size);
427
428         /* Calculate EDP table */
429         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
430                 for (temp_idx = 0;
431                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
432                         edp_calculated_limits[temp_idx].temperature =
433                                 temperatures[temp_idx];
434                         limit = edp_calculate_maxf(params,
435                                                    temperatures[temp_idx],
436                                                    -1,
437                                                    0,
438                                                    iddq_mA,
439                                                    n_cores_idx);
440                         if (limit == -EINVAL)
441                                 return -EINVAL;
442                         /* apply safety cap if it is specified */
443                         if (n_cores_idx < 4) {
444                                 cap = params->safety_cap[n_cores_idx];
445                                 if (cap && cap < limit)
446                                         limit = cap;
447                         }
448                         edp_calculated_limits[temp_idx].
449                                 freq_limits[n_cores_idx] = limit;
450
451                         /* regulator mode threshold */
452                         if (!idle_cur)
453                                 continue;
454                         reg_idle_calc_limits[temp_idx].temperature =
455                                 temperatures[temp_idx];
456                         limit = edp_calculate_maxf(params,
457                                                    temperatures[temp_idx],
458                                                    -1,
459                                                    idle_cur,
460                                                    iddq_mA,
461                                                    n_cores_idx);
462
463                         /* remove idle table if any threshold is invalid */
464                         if (limit == -EINVAL) {
465                                 pr_warn("%s: Invalid idle limit for %dmA\n",
466                                         __func__, idle_cur);
467                                 idle_cur = 0;
468                                 continue;
469                         }
470
471                         /* No mode change below G CPU minimum rate */
472                         if (limit < clk_get_min_rate(clk_cpu_g) / 1000)
473                                 limit = 0;
474                         reg_idle_calc_limits[temp_idx].
475                                 freq_limits[n_cores_idx] = limit;
476                 }
477
478                 for (pwr_idx = 0;
479                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
480                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
481                                 power_cap_levels[pwr_idx] / 100;
482                         limit = edp_calculate_maxf(params,
483                                                    50,
484                                                    power_cap_levels[pwr_idx],
485                                                    0,
486                                                    iddq_mA,
487                                                    n_cores_idx);
488                         if (limit == -EINVAL)
489                                 return -EINVAL;
490                         power_edp_calc_limits[pwr_idx].
491                                 freq_limits[n_cores_idx] = limit;
492                 }
493         }
494
495         /*
496          * If this is an EDP table update, need to overwrite old table.
497          * The old table's address must remain valid.
498          */
499         if (edp_limits != edp_default_limits) {
500                 memcpy(edp_limits, edp_calculated_limits,
501                        sizeof(struct tegra_edp_limits)
502                        * ARRAY_SIZE(temperatures));
503                 kfree(edp_calculated_limits);
504         } else {
505                 edp_limits = edp_calculated_limits;
506                 edp_limits_size = ARRAY_SIZE(temperatures);
507         }
508
509         if (idle_cur && reg_idle_edp_limits) {
510                 memcpy(reg_idle_edp_limits, reg_idle_calc_limits,
511                        sizeof(struct tegra_edp_limits)
512                        * ARRAY_SIZE(temperatures));
513                 kfree(reg_idle_calc_limits);
514         } else if (idle_cur) {
515                 reg_idle_edp_limits = reg_idle_calc_limits;
516         } else {
517                 kfree(reg_idle_edp_limits);
518                 kfree(reg_idle_calc_limits);
519                 reg_idle_edp_limits = NULL;
520         }
521
522         if (power_edp_limits != power_edp_default_limits) {
523                 memcpy(power_edp_limits, power_edp_calc_limits,
524                        sizeof(struct tegra_system_edp_entry)
525                        * ARRAY_SIZE(power_cap_levels));
526                 kfree(power_edp_calc_limits);
527         } else {
528                 power_edp_limits = power_edp_calc_limits;
529                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
530         }
531
532         kfree(freq_voltage_lut);
533         return 0;
534 }
535
536 void tegra_recalculate_cpu_edp_limits(void)
537 {
538         u32 tegra_chip_id;
539
540         tegra_chip_id = tegra_get_chip_id();
541         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
542             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
543             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
544                 return;
545
546         if (init_cpu_edp_limits_calculated() == 0)
547                 return;
548
549         /* Revert to default EDP table on error */
550         edp_limits = edp_default_limits;
551         edp_limits_size = ARRAY_SIZE(edp_default_limits);
552
553         power_edp_limits = power_edp_default_limits;
554         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
555
556         kfree(reg_idle_edp_limits);
557         reg_idle_edp_limits = NULL;
558         pr_err("%s: Failed to recalculate EDP limits\n", __func__);
559 }
560
561 /*
562  * Specify regulator current in mA, e.g. 5000mA
563  * Use 0 for default
564  */
565 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
566 {
567         if (!regulator_mA)
568                 goto end;
569         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
570
571         switch (tegra_get_chip_id()) {
572         case TEGRA_CHIPID_TEGRA11:
573         case TEGRA_CHIPID_TEGRA14:
574         case TEGRA_CHIPID_TEGRA12:
575                 if (init_cpu_edp_limits_calculated() == 0)
576                         return;
577                 break;
578         case TEGRA_CHIPID_TEGRA2:
579         case TEGRA_CHIPID_TEGRA3:
580         default:
581                 BUG();
582                 break;
583         }
584
585  end:
586         edp_limits = edp_default_limits;
587         edp_limits_size = ARRAY_SIZE(edp_default_limits);
588
589         power_edp_limits = power_edp_default_limits;
590         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
591 }
592
593 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
594 {
595         *limits = edp_limits;
596         *size = edp_limits_size;
597 }
598
599 void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
600                                            unsigned int mode)
601 {
602         if (mode == REGULATOR_MODE_IDLE) {
603                 reg_idle_cur = regulator_mA;
604                 return;
605         }
606         pr_err("%s: Not supported regulator mode 0x%x\n", __func__, mode);
607 }
608
609 void tegra_get_cpu_reg_mode_limits(const struct tegra_edp_limits **limits,
610                                    int *size, unsigned int mode)
611 {
612         if (mode == REGULATOR_MODE_IDLE) {
613                 *limits = reg_idle_edp_limits;
614                 *size = edp_limits_size;
615         } else {
616                 *limits = NULL;
617                 *size = 0;
618         }
619 }
620
621 void tegra_get_system_edp_limits(const unsigned int **limits)
622 {
623         *limits = system_edp_limits;
624 }
625
626 void tegra_platform_edp_init(struct thermal_trip_info *trips,
627                                 int *num_trips, int margin)
628 {
629         const struct tegra_edp_limits *cpu_edp_limits;
630         struct thermal_trip_info *trip_state;
631         int i, cpu_edp_limits_size;
632
633         if (!trips || !num_trips)
634                 return;
635
636         /* edp capping */
637         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
638
639         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
640                 BUG();
641
642         for (i = 0; i < cpu_edp_limits_size-1; i++) {
643                 trip_state = &trips[*num_trips];
644
645                 trip_state->cdev_type = "cpu_edp";
646                 trip_state->trip_temp =
647                         (cpu_edp_limits[i].temperature * 1000) - margin;
648                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
649                 trip_state->upper = trip_state->lower = i + 1;
650
651                 (*num_trips)++;
652
653                 if (*num_trips >= THERMAL_MAX_TRIPS)
654                         BUG();
655         }
656 }
657
658 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
659 {
660         *size = power_edp_limits_size;
661         return power_edp_limits;
662 }
663
664
665 #ifdef CONFIG_TEGRA_GPU_EDP
666 void tegra_get_gpu_edp_limits(const struct tegra_edp_gpu_limits **limits,
667                                                         int *size)
668 {
669         *limits = edp_gpu_limits;
670         *size = edp_gpu_limits_size;
671 }
672
673 void tegra_platform_gpu_edp_init(struct thermal_trip_info *trips,
674                                 int *num_trips, int margin)
675 {
676         const struct tegra_edp_gpu_limits *gpu_edp_limits;
677         struct thermal_trip_info *trip_state;
678         int i, gpu_edp_limits_size;
679
680         if (!trips || !num_trips)
681                 return;
682
683         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
684
685         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
686                 BUG();
687
688         for (i = 0; i < gpu_edp_limits_size-1; i++) {
689                 trip_state = &trips[*num_trips];
690
691                 trip_state->cdev_type = "gpu_edp";
692                 trip_state->trip_temp =
693                         (gpu_edp_limits[i].temperature * 1000) - margin;
694                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
695                 trip_state->upper = trip_state->lower = i + 1;
696
697                 (*num_trips)++;
698
699                 if (*num_trips >= THERMAL_MAX_TRIPS)
700                         BUG();
701         }
702 }
703
704 static unsigned int edp_gpu_calculate_maxf(
705                                 struct tegra_edp_gpu_leakage_params *params,
706                                 int temp_C, int iddq_mA)
707 {
708         unsigned int voltage_mV, freq_KHz = 0;
709         unsigned int cur_effective = gpu_regulator_cur;
710         int f, i, j, k;
711         s64 leakage_mA, dyn_mA, leakage_calc_step;
712
713         for (f = freq_voltage_gpu_lut_size - 1; f >= 0; f--) {
714                 freq_KHz = freq_voltage_gpu_lut[f].freq / 1000;
715                 voltage_mV = freq_voltage_gpu_lut[f].voltage_mV;
716
717                 /* Calculate leakage current */
718                 leakage_mA = 0;
719                 for (i = 0; i <= 3; i++) {
720                         for (j = 0; j <= 3; j++) {
721                                 for (k = 0; k <= 3; k++) {
722                                         leakage_calc_step =
723                                                 params->leakage_consts_ijk
724                                                 [i][j][k] * edp_pow(iddq_mA, i);
725
726                                         /* Convert (mA)^i to (A)^i */
727                                         leakage_calc_step =
728                                                 div64_s64(leakage_calc_step,
729                                                           edp_pow(1000, i));
730                                         leakage_calc_step *=
731                                                 edp_pow(voltage_mV, j);
732
733                                         /* Convert (mV)^j to (V)^j */
734                                         leakage_calc_step =
735                                                 div64_s64(leakage_calc_step,
736                                                           edp_pow(1000, j));
737                                         leakage_calc_step *=
738                                                 edp_pow(temp_C, k);
739
740                                         /* Convert (C)^k to (scaled_C)^k */
741                                         leakage_calc_step =
742                                                 div64_s64(leakage_calc_step,
743                                                 edp_pow(params->temp_scaled,
744                                                         k));
745
746                                         /* leakage_consts_ijk was scaled */
747                                         leakage_calc_step =
748                                                 div64_s64(leakage_calc_step,
749                                                           params->ijk_scaled);
750
751                                         leakage_mA += leakage_calc_step;
752                                 }
753                         }
754                 }
755                 /* set floor for leakage current */
756                 if (leakage_mA <= params->leakage_min)
757                         leakage_mA = params->leakage_min;
758
759                 /* Calculate dynamic current */
760
761                 dyn_mA = voltage_mV * freq_KHz / 1000;
762                 /* Convert mV to V */
763                 dyn_mA = div64_s64(dyn_mA, 1000);
764                 dyn_mA *= params->dyn_consts_n;
765                 /* dyn_const_n was scaled */
766                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
767
768                 if ((leakage_mA + dyn_mA) <= cur_effective)
769                         goto end;
770
771                 freq_KHz = 0;
772         }
773
774  end:
775         return freq_KHz;
776 }
777
778 static int __init start_gpu_edp(void)
779 {
780         const char *cap_name = "edp.gbus";
781
782         gpu_cap_clk = tegra_get_clock_by_name(cap_name);
783         if (!gpu_cap_clk) {
784                 pr_err("gpu_edp_set_cdev_state: cannot get clock:%s\n",
785                                 cap_name);
786                 return -EINVAL;
787         }
788         edp_gpu_thermal_idx = 0;
789
790         return 0;
791 }
792
793
794 static int edp_gpu_relate_freq_voltage(struct clk *clk_gpu,
795                         unsigned int freq_volt_lut_size,
796                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
797 {
798         unsigned int i, j, freq;
799         int voltage_mV;
800
801         for (i = 0, j = 0, freq = 0;
802                  i < freq_volt_lut_size;
803                  i++, freq += GPU_FREQ_STEP) {
804
805                 /* Predict voltages */
806                 voltage_mV = tegra_dvfs_predict_peak_millivolts(clk_gpu, freq);
807                 if (voltage_mV < 0) {
808                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
809                                __func__, freq, voltage_mV);
810                         return -EINVAL;
811                 }
812
813                 /* Cache frequency / voltage / voltage constant relationship */
814                 freq_volt_lut[i].freq = freq;
815                 freq_volt_lut[i].voltage_mV = voltage_mV;
816         }
817         return 0;
818 }
819
820 static int init_gpu_edp_limits_calculated(void)
821 {
822         unsigned int temp_idx;
823         unsigned int gpu_minf, gpu_maxf;
824         unsigned int limit;
825         struct tegra_edp_gpu_limits *edp_gpu_calculated_limits;
826         struct tegra_edp_gpu_limits *temp;
827         struct tegra_edp_gpu_leakage_params *params;
828         int ret;
829         unsigned int gpu_iddq_mA;
830         u32 tegra_chip_id;
831         struct clk *gpu_clk = clk_get_parent(gpu_cap_clk);
832         tegra_chip_id = tegra_get_chip_id();
833
834         if (tegra_chip_id == TEGRA_CHIPID_TEGRA12) {
835                 gpu_iddq_mA = tegra_get_gpu_iddq_value();
836                 params = tegra12x_get_gpu_leakage_params();
837         } else
838                 return -EINVAL;
839
840         edp_gpu_calculated_limits = kmalloc(sizeof(struct tegra_edp_gpu_limits)
841                                 * ARRAY_SIZE(gpu_temperatures), GFP_KERNEL);
842         BUG_ON(!edp_gpu_calculated_limits);
843
844         gpu_minf = 0;
845         gpu_maxf = clk_get_max_rate(gpu_clk);
846
847         freq_voltage_gpu_lut_size = (gpu_maxf - gpu_minf) / GPU_FREQ_STEP + 1;
848         freq_voltage_gpu_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
849                                    * freq_voltage_gpu_lut_size, GFP_KERNEL);
850         if (!freq_voltage_gpu_lut) {
851                 pr_err("%s: failed alloc mem for gpu freq/voltage LUT\n",
852                          __func__);
853                 kfree(edp_gpu_calculated_limits);
854                 return -ENOMEM;
855         }
856
857         ret = edp_gpu_relate_freq_voltage(gpu_clk,
858                         freq_voltage_gpu_lut_size, freq_voltage_gpu_lut);
859
860         if (ret) {
861                 kfree(edp_gpu_calculated_limits);
862                 kfree(freq_voltage_gpu_lut);
863                 return ret;
864         }
865
866         for (temp_idx = 0;
867                      temp_idx < ARRAY_SIZE(gpu_temperatures); temp_idx++) {
868                         edp_gpu_calculated_limits[temp_idx].temperature =
869                                 gpu_temperatures[temp_idx];
870                         limit = edp_gpu_calculate_maxf(params,
871                                                    gpu_temperatures[temp_idx],
872                                                    gpu_iddq_mA);
873                         if (limit == -EINVAL)
874                                 return -EINVAL;
875                         edp_gpu_calculated_limits[temp_idx].freq_limits = limit;
876         }
877
878         /*
879          * If this is an EDP table update, need to overwrite old table.
880          * The old table's address must remain valid.
881          */
882         if (edp_gpu_limits != edp_gpu_default_limits &&
883                         edp_gpu_limits != edp_gpu_calculated_limits) {
884                 temp = edp_gpu_limits;
885                 edp_gpu_limits = edp_gpu_calculated_limits;
886                 edp_gpu_limits_size = ARRAY_SIZE(gpu_temperatures);
887                 kfree(temp);
888         } else {
889                 edp_gpu_limits = edp_gpu_calculated_limits;
890                 edp_gpu_limits_size = ARRAY_SIZE(gpu_temperatures);
891         }
892
893         kfree(freq_voltage_gpu_lut);
894
895         return 0;
896 }
897
898 void tegra_platform_edp_gpu_init(struct thermal_trip_info *trips,
899                                 int *num_trips, int margin)
900 {
901         const struct tegra_edp_gpu_limits *gpu_edp_limits;
902         struct thermal_trip_info *trip_state;
903         int i, gpu_edp_limits_size;
904
905         if (!trips || !num_trips)
906                 return;
907
908         tegra_get_gpu_edp_limits(&gpu_edp_limits, &gpu_edp_limits_size);
909
910         if (gpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
911                 BUG();
912
913         for (i = 0; i < gpu_edp_limits_size-1; i++) {
914                 trip_state = &trips[*num_trips];
915
916                 trip_state->cdev_type = "gpu_edp";
917                 trip_state->trip_temp =
918                         (gpu_edp_limits[i].temperature * 1000) - margin;
919                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
920                 trip_state->upper = trip_state->lower = i + 1;
921
922                 (*num_trips)++;
923
924                 if (*num_trips >= THERMAL_MAX_TRIPS)
925                         BUG();
926         }
927 }
928
929 void __init tegra_init_gpu_edp_limits(unsigned int regulator_mA)
930 {
931         u32 tegra_chip_id;
932         tegra_chip_id = tegra_get_chip_id();
933
934         if (!regulator_mA)
935                 goto end;
936         gpu_regulator_cur = regulator_mA;
937
938         if (start_gpu_edp()) {
939                 WARN(1, "GPU EDP failed to set initialial limits");
940                 return;
941         }
942
943         switch (tegra_chip_id) {
944         case TEGRA_CHIPID_TEGRA12:
945                 if (init_gpu_edp_limits_calculated() == 0)
946                         return;
947                 break;
948
949         default:
950                 BUG();
951                 break;
952         }
953
954  end:
955         edp_gpu_limits = edp_gpu_default_limits;
956         edp_gpu_limits_size = ARRAY_SIZE(edp_gpu_default_limits);
957 }
958
959 static int gpu_edp_get_cdev_max_state(struct thermal_cooling_device *cdev,
960                                        unsigned long *max_state)
961 {
962         *max_state = edp_gpu_limits_size - 1;
963         return 0;
964 }
965
966 static int gpu_edp_get_cdev_cur_state(struct thermal_cooling_device *cdev,
967                                        unsigned long *cur_state)
968 {
969         *cur_state = edp_gpu_thermal_idx;
970         return 0;
971 }
972
973 static int gpu_edp_set_cdev_state(struct thermal_cooling_device *cdev,
974                                    unsigned long cur_state)
975 {
976         unsigned long clk_rate;
977         BUG_ON(cur_state >= edp_gpu_limits_size);
978         clk_rate = edp_gpu_limits[cur_state].freq_limits;
979         mutex_lock(&gpu_edp_lock);
980         edp_gpu_thermal_idx = cur_state;
981         clk_set_rate(gpu_cap_clk, clk_rate * 1000);
982         mutex_unlock(&gpu_edp_lock);
983         return 0;
984 }
985
986 static struct thermal_cooling_device_ops gpu_edp_cooling_ops = {
987         .get_max_state = gpu_edp_get_cdev_max_state,
988         .get_cur_state = gpu_edp_get_cdev_cur_state,
989         .set_cur_state = gpu_edp_set_cdev_state,
990 };
991
992 static int __init tegra_gpu_edp_late_init(void)
993 {
994         if (IS_ERR_OR_NULL(thermal_cooling_device_register(
995                 "gpu_edp", NULL, &gpu_edp_cooling_ops)))
996                 pr_err("%s: failed to register edp cooling device\n", __func__);
997
998         return 0;
999 }
1000 late_initcall(tegra_gpu_edp_late_init);
1001
1002 #endif
1003
1004 #ifdef CONFIG_DEBUG_FS
1005
1006 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
1007 {
1008 #ifdef CONFIG_CPU_FREQ
1009         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
1010 #endif
1011         return 0;
1012 }
1013
1014 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
1015 {
1016         int i;
1017
1018         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1019                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1020         for (i = 0; i < edp_limits_size; i++) {
1021                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1022                            i == th_idx ? '>' : ' ',
1023                            edp_limits[i].temperature,
1024                            edp_limits[i].freq_limits[0],
1025                            edp_limits[i].freq_limits[1],
1026                            edp_limits[i].freq_limits[2],
1027                            edp_limits[i].freq_limits[3]);
1028         }
1029 }
1030
1031 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
1032 {
1033         int i;
1034
1035         seq_printf(s, "%6s %10s %10s\n",
1036                    " Temp.", "1-core", "2-cores");
1037         for (i = 0; i < edp_limits_size; i++) {
1038                 seq_printf(s, "%c%3dC: %10u %10u\n",
1039                            i == th_idx ? '>' : ' ',
1040                            edp_limits[i].temperature,
1041                            edp_limits[i].freq_limits[0],
1042                            edp_limits[i].freq_limits[1]);
1043         }
1044 }
1045
1046 static inline void edp_show_4core_reg_mode_table(struct seq_file *s, int th_idx)
1047 {
1048         int i;
1049
1050         seq_printf(s, "%6s %10s %10s %10s %10s\n",
1051                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
1052         for (i = 0; i < edp_limits_size; i++) {
1053                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
1054                            i == th_idx ? '>' : ' ',
1055                            reg_idle_edp_limits[i].temperature,
1056                            reg_idle_edp_limits[i].freq_limits[0],
1057                            reg_idle_edp_limits[i].freq_limits[1],
1058                            reg_idle_edp_limits[i].freq_limits[2],
1059                            reg_idle_edp_limits[i].freq_limits[3]);
1060         }
1061 }
1062
1063 static inline void edp_show_2core_reg_mode_table(struct seq_file *s, int th_idx)
1064 {
1065         int i;
1066
1067         seq_printf(s, "%6s %10s %10s\n",
1068                    " Temp.", "1-core", "2-cores");
1069         for (i = 0; i < edp_limits_size; i++) {
1070                 seq_printf(s, "%c%3dC: %10u %10u\n",
1071                            i == th_idx ? '>' : ' ',
1072                            reg_idle_edp_limits[i].temperature,
1073                            reg_idle_edp_limits[i].freq_limits[0],
1074                            reg_idle_edp_limits[i].freq_limits[1]);
1075         }
1076 }
1077
1078 static inline void edp_show_2core_system_table(struct seq_file *s)
1079 {
1080         seq_printf(s, "%10u %10u\n",
1081                    system_edp_limits[0],
1082                    system_edp_limits[1]);
1083 }
1084
1085 static inline void edp_show_4core_system_table(struct seq_file *s)
1086 {
1087         seq_printf(s, "%10u %10u %10u %10u\n",
1088                    system_edp_limits[0],
1089                    system_edp_limits[1],
1090                    system_edp_limits[2],
1091                    system_edp_limits[3]);
1092 }
1093
1094 static int edp_debugfs_show(struct seq_file *s, void *data)
1095 {
1096         unsigned int max_nr_cpus = num_possible_cpus();
1097         int th_idx;
1098
1099         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
1100                 seq_printf(s, "Unsupported number of CPUs\n");
1101                 return 0;
1102         }
1103
1104 #ifdef CONFIG_CPU_FREQ
1105         tegra_get_edp_limit(&th_idx);
1106 #else
1107         th_idx = 0;
1108 #endif
1109
1110         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
1111                    edp_limits == edp_default_limits ? "**default** " : "",
1112                    regulator_cur - edp_reg_override_mA,
1113                    regulator_cur, edp_reg_override_mA);
1114
1115         if (max_nr_cpus == 2)
1116                 edp_show_2core_edp_table(s, th_idx);
1117         else if (max_nr_cpus == 4)
1118                 edp_show_4core_edp_table(s, th_idx);
1119
1120         if (reg_idle_edp_limits) {
1121                 seq_printf(s, "\n-- Regulator mode thresholds @ %dmA --\n",
1122                            reg_idle_cur);
1123                 if (max_nr_cpus == 2)
1124                         edp_show_2core_reg_mode_table(s, th_idx);
1125                 else if (max_nr_cpus == 4)
1126                         edp_show_4core_reg_mode_table(s, th_idx);
1127         }
1128
1129         if (system_edp_limits) {
1130                 seq_printf(s, "\n-- System EDP table --\n");
1131                 if (max_nr_cpus == 2)
1132                         edp_show_2core_system_table(s);
1133                 else if (max_nr_cpus == 4)
1134                         edp_show_4core_system_table(s);
1135         }
1136
1137         return 0;
1138 }
1139
1140 #ifdef CONFIG_TEGRA_GPU_EDP
1141 static inline void gpu_edp_show_table(struct seq_file *s)
1142 {
1143         int i;
1144
1145         seq_printf(s, "%6s %10s\n",
1146                    " Temp.", "Freq_limit");
1147         for (i = 0; i < edp_gpu_limits_size; i++) {
1148                 seq_printf(s, "%3dC: %10u \n",
1149                            edp_gpu_limits[i].temperature,
1150                            edp_gpu_limits[i].freq_limits);
1151         }
1152 }
1153
1154
1155 static int gpu_edp_debugfs_show(struct seq_file *s, void *data)
1156 {
1157         seq_printf(s, "-- VDD_GPU EDP table --\n");
1158
1159         gpu_edp_show_table(s);
1160
1161         return 0;
1162 }
1163 #endif
1164
1165 static int edp_reg_override_show(struct seq_file *s, void *data)
1166 {
1167         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
1168                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
1169         return 0;
1170 }
1171
1172 static int edp_reg_override_write(struct file *file,
1173         const char __user *userbuf, size_t count, loff_t *ppos)
1174 {
1175         char buf[32], *end;
1176         unsigned int edp_reg_override_mA_temp;
1177         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
1178         u32 tegra_chip_id;
1179
1180         tegra_chip_id = tegra_get_chip_id();
1181         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
1182                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
1183                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
1184                 goto override_err;
1185
1186         if (sizeof(buf) <= count)
1187                 goto override_err;
1188
1189         if (copy_from_user(buf, userbuf, count))
1190                 goto override_err;
1191
1192         /* terminate buffer and trim - white spaces may be appended
1193          *  at the end when invoked from shell command line */
1194         buf[count]='\0';
1195         strim(buf);
1196
1197         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
1198         if (*end != '\0')
1199                 goto override_err;
1200
1201         if (edp_reg_override_mA_temp >= regulator_cur)
1202                 goto override_err;
1203
1204         if (edp_reg_override_mA == edp_reg_override_mA_temp)
1205                 return count;
1206
1207         edp_reg_override_mA = edp_reg_override_mA_temp;
1208         if (init_cpu_edp_limits_calculated()) {
1209                 /* Revert to previous override value if new value fails */
1210                 edp_reg_override_mA = edp_reg_override_mA_prev;
1211                 goto override_err;
1212         }
1213
1214 #ifdef CONFIG_CPU_FREQ
1215         if (tegra_cpu_set_speed_cap(NULL)) {
1216                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
1217                 goto override_out;
1218         }
1219
1220         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
1221                         " %u mA\n", regulator_cur - edp_reg_override_mA);
1222 #else
1223         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
1224 #endif
1225
1226         return count;
1227
1228 override_err:
1229         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
1230                buf);
1231 #ifdef CONFIG_CPU_FREQ
1232 override_out:
1233 #endif
1234         return -EINVAL;
1235 }
1236
1237 static int edp_debugfs_open(struct inode *inode, struct file *file)
1238 {
1239         return single_open(file, edp_debugfs_show, inode->i_private);
1240 }
1241
1242 #ifdef CONFIG_TEGRA_GPU_EDP
1243 static int gpu_edp_debugfs_open(struct inode *inode, struct file *file)
1244 {
1245         return single_open(file, gpu_edp_debugfs_show, inode->i_private);
1246 }
1247 #endif
1248
1249 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
1250 {
1251         return single_open(file, edp_limit_debugfs_show, inode->i_private);
1252 }
1253
1254 static int edp_reg_override_open(struct inode *inode, struct file *file)
1255 {
1256         return single_open(file, edp_reg_override_show, inode->i_private);
1257 }
1258
1259 static const struct file_operations edp_debugfs_fops = {
1260         .open           = edp_debugfs_open,
1261         .read           = seq_read,
1262         .llseek         = seq_lseek,
1263         .release        = single_release,
1264 };
1265
1266 #ifdef CONFIG_TEGRA_GPU_EDP
1267 static const struct file_operations gpu_edp_debugfs_fops = {
1268         .open           = gpu_edp_debugfs_open,
1269         .read           = seq_read,
1270         .llseek         = seq_lseek,
1271         .release        = single_release,
1272 };
1273 #endif
1274
1275 static const struct file_operations edp_limit_debugfs_fops = {
1276         .open           = edp_limit_debugfs_open,
1277         .read           = seq_read,
1278         .llseek         = seq_lseek,
1279         .release        = single_release,
1280 };
1281
1282 static const struct file_operations edp_reg_override_debugfs_fops = {
1283         .open           = edp_reg_override_open,
1284         .read           = seq_read,
1285         .write          = edp_reg_override_write,
1286         .llseek         = seq_lseek,
1287         .release        = single_release,
1288 };
1289
1290 static int reg_idle_cur_get(void *data, u64 *val)
1291 {
1292         *val = reg_idle_cur;
1293         return 0;
1294 }
1295 static int reg_idle_cur_set(void *data, u64 val)
1296 {
1297         int ret;
1298
1299         ret = tegra_cpu_reg_mode_force_normal(true);
1300         if (ret) {
1301                 pr_err("%s: Failed to force regulator normal mode\n", __func__);
1302                 return ret;
1303         }
1304
1305         reg_idle_cur = (int)val;
1306         tegra_update_cpu_edp_limits();
1307         return 0;
1308 }
1309 DEFINE_SIMPLE_ATTRIBUTE(reg_idle_cur_debugfs_fops,
1310                         reg_idle_cur_get, reg_idle_cur_set, "%llu\n");
1311
1312 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
1313 static __init struct dentry *tegra_edp_debugfs_dir(void)
1314 {
1315         if (edp_debugfs_dir)
1316                 return edp_debugfs_dir;
1317         else
1318                 return debugfs_create_dir("edp", NULL);
1319 }
1320 #else
1321 static __init struct dentry *tegra_edp_debugfs_dir(void)
1322 {
1323         return debugfs_create_dir("edp", NULL);
1324 }
1325 #endif
1326
1327 static int __init tegra_edp_debugfs_init(void)
1328 {
1329         struct dentry *d_reg_idle_cur;
1330         struct dentry *d_edp;
1331         struct dentry *d_edp_limit;
1332         struct dentry *d_edp_reg_override;
1333         struct dentry *edp_dir;
1334         struct dentry *vdd_cpu_dir;
1335 #ifdef CONFIG_TEGRA_GPU_EDP
1336         struct dentry *gpu_edp;
1337         struct dentry *vdd_gpu_dir;
1338 #endif
1339
1340         if (!tegra_platform_is_silicon())
1341                 return -ENOSYS;
1342
1343         edp_dir = tegra_edp_debugfs_dir();
1344
1345         if (!edp_dir)
1346                 goto edp_dir_err;
1347
1348         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
1349
1350         if (!vdd_cpu_dir)
1351                 goto vdd_cpu_dir_err;
1352
1353 #ifdef CONFIG_TEGRA_GPU_EDP
1354         vdd_gpu_dir = debugfs_create_dir("vdd_gpu", edp_dir);
1355
1356         if (!vdd_gpu_dir)
1357                 goto vdd_gpu_dir_err;
1358 #endif
1359
1360         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
1361                                 &edp_debugfs_fops);
1362
1363         if (!d_edp)
1364                 goto edp_err;
1365 #ifdef CONFIG_TEGRA_GPU_EDP
1366         gpu_edp = debugfs_create_file("gpu_edp",  S_IRUGO, vdd_gpu_dir, NULL,
1367                          &gpu_edp_debugfs_fops);
1368         if (!gpu_edp)
1369                 goto gpu_edp_err;
1370 #endif
1371
1372         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
1373                                 NULL, &edp_limit_debugfs_fops);
1374
1375         if (!d_edp_limit)
1376                 goto edp_limit_err;
1377
1378         d_edp_reg_override = debugfs_create_file("edp_reg_override",
1379                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1380                                 &edp_reg_override_debugfs_fops);
1381
1382         if (!d_edp_reg_override)
1383                 goto edp_reg_override_err;
1384
1385         d_reg_idle_cur = debugfs_create_file("reg_idle_mA",
1386                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
1387                                 &reg_idle_cur_debugfs_fops);
1388         if (!d_reg_idle_cur)
1389                 goto reg_idle_cur_err;
1390
1391         if (tegra_core_edp_debugfs_init(edp_dir))
1392                 return -ENOMEM;
1393
1394         return 0;
1395
1396 reg_idle_cur_err:
1397         debugfs_remove(d_edp_reg_override);
1398 edp_reg_override_err:
1399         debugfs_remove(d_edp_limit);
1400 edp_limit_err:
1401 #ifdef CONFIG_TEGRA_GPU_EDP
1402         debugfs_remove(gpu_edp);
1403 gpu_edp_err:
1404 #endif
1405         debugfs_remove(d_edp);
1406 edp_err:
1407 #ifdef CONFIG_TEGRA_GPU_EDP
1408         debugfs_remove(vdd_gpu_dir);
1409 vdd_gpu_dir_err:
1410 #endif
1411         debugfs_remove(vdd_cpu_dir);
1412 vdd_cpu_dir_err:
1413         debugfs_remove(edp_dir);
1414 edp_dir_err:
1415         return -ENOMEM;
1416 }
1417
1418 late_initcall(tegra_edp_debugfs_init);
1419 #endif /* CONFIG_DEBUG_FS */