ARM: tegra: power: Add dynamic CPU regulator mode control
[linux-3.10.git] / arch / arm / mach-tegra / edp.c
1 /*
2  * arch/arm/mach-tegra/edp.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION. All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/uaccess.h>
25 #include <linux/edp.h>
26 #include <linux/sysedp.h>
27 #include <linux/tegra-soc.h>
28
29 #include <mach/edp.h>
30
31 #include "fuse.h"
32 #include "dvfs.h"
33 #include "clock.h"
34 #include "cpu-tegra.h"
35
36 #define FREQ_STEP 12750000
37 #define OVERRIDE_DEFAULT 6000
38
39 static struct tegra_edp_limits *edp_limits;
40 static int edp_limits_size;
41 static unsigned int regulator_cur;
42 /* Value to subtract from regulator current limit */
43 static unsigned int edp_reg_override_mA = OVERRIDE_DEFAULT;
44
45 static struct tegra_edp_limits *reg_mode_limits;
46
47 static const unsigned int *system_edp_limits;
48
49 static struct tegra_system_edp_entry *power_edp_limits;
50 static int power_edp_limits_size;
51
52 /*
53  * "Safe entry" to be used when no match for speedo_id /
54  * regulator_cur is found; must be the last one
55  */
56 static struct tegra_edp_limits edp_default_limits[] = {
57         {85, {1000000, 1000000, 1000000, 1000000} },
58 };
59
60 static struct tegra_system_edp_entry power_edp_default_limits[] = {
61         {0, 20, {1000000, 1000000, 1000000, 1000000} },
62 };
63
64 /* Constants for EDP calculations */
65 static const int temperatures[] = { /* degree celcius (C) */
66         23, 40, 50, 60, 70, 74, 78, 82, 86, 90, 94, 98, 102,
67 };
68
69 static const int power_cap_levels[] = { /* milliwatts (mW) */
70           500,  1000,  1500,  2000,  2500,  3000,  3500,
71          4000,  4500,  5000,  5500,  6000,  6500,  7000,
72          7500,  8000,  8500,  9000,  9500, 10000, 10500,
73         11000, 11500, 12000, 12500, 13000, 13500, 14000,
74         14500, 15000, 15500, 16000, 16500, 17000
75 };
76
77 static struct tegra_edp_freq_voltage_table *freq_voltage_lut_saved;
78 static unsigned int freq_voltage_lut_size_saved;
79 static struct tegra_edp_freq_voltage_table *freq_voltage_lut;
80 static unsigned int freq_voltage_lut_size;
81
82 static inline s64 edp_pow(s64 val, int pwr)
83 {
84         s64 retval = 1;
85
86         while (val && pwr) {
87                 if (pwr & 1)
88                         retval *= val;
89                 pwr >>= 1;
90                 if (pwr)
91                         val *= val;
92         }
93
94         return retval;
95 }
96
97
98 #ifdef CONFIG_TEGRA_CPU_EDP_FIXED_LIMITS
99 static inline unsigned int edp_apply_fixed_limits(
100                                 unsigned int in_freq_KHz,
101                                 struct tegra_edp_cpu_leakage_params *params,
102                                 unsigned int cur_effective,
103                                 int temp_C, int n_cores_idx)
104 {
105         unsigned int out_freq_KHz = in_freq_KHz;
106         unsigned int max_cur, max_temp, max_freq;
107         int i;
108
109         /* Apply any additional fixed limits */
110         for (i = 0; i < 8; i++) {
111                 max_cur = params->max_current_cap[i].max_cur;
112                 if (max_cur != 0 && cur_effective <= max_cur) {
113                         max_temp = params->max_current_cap[i].max_temp;
114                         if (max_temp != 0 && temp_C > max_temp) {
115                                 max_freq = params->max_current_cap[i].
116                                         max_freq[n_cores_idx];
117                                 if (max_freq && max_freq < out_freq_KHz)
118                                         out_freq_KHz = max_freq;
119                         }
120                 }
121         }
122
123         return out_freq_KHz;
124 }
125 #else
126 #define edp_apply_fixed_limits(freq, unused...) (freq)
127 #endif
128
129 /*
130  * Find the maximum frequency that results in dynamic and leakage current that
131  * is less than the regulator current limit.
132  * temp_C - valid or -EINVAL
133  * power_mW - valid or -1 (infinite) or -EINVAL
134  */
135 static unsigned int edp_calculate_maxf(
136                                 struct tegra_edp_cpu_leakage_params *params,
137                                 int temp_C, int power_mW,
138                                 int iddq_mA,
139                                 int n_cores_idx)
140 {
141         unsigned int voltage_mV, freq_KHz = 0;
142         unsigned int cur_effective = regulator_cur - edp_reg_override_mA;
143         int f, i, j, k;
144         s64 leakage_mA, dyn_mA, leakage_calc_step;
145         s64 leakage_mW, dyn_mW;
146
147         for (f = freq_voltage_lut_size - 1; f >= 0; f--) {
148                 freq_KHz = freq_voltage_lut[f].freq / 1000;
149                 voltage_mV = freq_voltage_lut[f].voltage_mV;
150
151                 /* Constrain Volt-Temp */
152                 if (params->volt_temp_cap.temperature &&
153                     temp_C > params->volt_temp_cap.temperature &&
154                     params->volt_temp_cap.voltage_limit_mV &&
155                     voltage_mV > params->volt_temp_cap.voltage_limit_mV)
156                         continue;
157
158                 /* Calculate leakage current */
159                 leakage_mA = 0;
160                 for (i = 0; i <= 3; i++) {
161                         for (j = 0; j <= 3; j++) {
162                                 for (k = 0; k <= 3; k++) {
163                                         leakage_calc_step =
164                                                 params->leakage_consts_ijk
165                                                 [i][j][k] * edp_pow(iddq_mA, i);
166                                         /* Convert (mA)^i to (A)^i */
167                                         leakage_calc_step =
168                                                 div64_s64(leakage_calc_step,
169                                                           edp_pow(1000, i));
170                                         leakage_calc_step *=
171                                                 edp_pow(voltage_mV, j);
172                                         /* Convert (mV)^j to (V)^j */
173                                         leakage_calc_step =
174                                                 div64_s64(leakage_calc_step,
175                                                           edp_pow(1000, j));
176                                         leakage_calc_step *=
177                                                 edp_pow(temp_C, k);
178                                         /* Convert (C)^k to (scaled_C)^k */
179                                         leakage_calc_step =
180                                                 div64_s64(leakage_calc_step,
181                                                 edp_pow(params->temp_scaled,
182                                                         k));
183                                         /* leakage_consts_ijk was scaled */
184                                         leakage_calc_step =
185                                                 div64_s64(leakage_calc_step,
186                                                           params->ijk_scaled);
187                                         leakage_mA += leakage_calc_step;
188                                 }
189                         }
190                 }
191
192                 /* set floor for leakage current */
193                 if (leakage_mA <= params->leakage_min)
194                         leakage_mA = params->leakage_min;
195
196                 leakage_mA *= params->leakage_consts_n[n_cores_idx];
197
198                 /* leakage_const_n was scaled */
199                 leakage_mA = div64_s64(leakage_mA, params->consts_scaled);
200
201                 /* Calculate dynamic current */
202                 dyn_mA = voltage_mV * freq_KHz / 1000;
203                 /* Convert mV to V */
204                 dyn_mA = div64_s64(dyn_mA, 1000);
205                 dyn_mA *= params->dyn_consts_n[n_cores_idx];
206                 /* dyn_const_n was scaled */
207                 dyn_mA = div64_s64(dyn_mA, params->dyn_scaled);
208
209                 if (power_mW != -1) {
210                         leakage_mW = leakage_mA * voltage_mV;
211                         dyn_mW = dyn_mA * voltage_mV;
212                         if (div64_s64(leakage_mW + dyn_mW, 1000) <= power_mW)
213                                 goto end;
214                 } else if ((leakage_mA + dyn_mA) <= cur_effective) {
215                         goto end;
216                 }
217                 freq_KHz = 0;
218         }
219
220  end:
221         return edp_apply_fixed_limits(freq_KHz, params,
222                                         cur_effective, temp_C, n_cores_idx);
223 }
224
225 static int edp_relate_freq_voltage(struct clk *clk_cpu_g,
226                         unsigned int cpu_speedo_idx,
227                         unsigned int freq_volt_lut_size,
228                         struct tegra_edp_freq_voltage_table *freq_volt_lut)
229 {
230         unsigned int i, j, freq;
231         int voltage_mV;
232
233         for (i = 0, j = 0, freq = 0;
234                  i < freq_volt_lut_size;
235                  i++, freq += FREQ_STEP) {
236
237                 /* Predict voltages */
238                 voltage_mV = tegra_dvfs_predict_peak_millivolts(
239                         clk_cpu_g, freq);
240                 if (voltage_mV < 0) {
241                         pr_err("%s: couldn't predict voltage: freq %u; err %d",
242                                __func__, freq, voltage_mV);
243                         return -EINVAL;
244                 }
245
246                 /* Cache frequency / voltage / voltage constant relationship */
247                 freq_volt_lut[i].freq = freq;
248                 freq_volt_lut[i].voltage_mV = voltage_mV;
249         }
250         return 0;
251 }
252
253 unsigned int tegra_edp_find_maxf(int volt)
254 {
255         unsigned int i;
256
257         for (i = 0; i < freq_voltage_lut_size_saved; i++) {
258                 if (freq_voltage_lut_saved[i].voltage_mV > volt)
259                         break;
260         }
261         return freq_voltage_lut[i - 1].freq;
262 }
263
264
265 static int edp_find_speedo_idx(int cpu_speedo_id, unsigned int *cpu_speedo_idx)
266 {
267         int i, array_size;
268         struct tegra_edp_cpu_leakage_params *params;
269
270         switch (tegra_get_chip_id()) {
271         case TEGRA_CHIPID_TEGRA11:
272                 params = tegra11x_get_leakage_params(0, &array_size);
273                 break;
274         case TEGRA_CHIPID_TEGRA14:
275                 params = tegra14x_get_leakage_params(0, &array_size);
276                 break;
277         case TEGRA_CHIPID_TEGRA12:
278                 params = tegra12x_get_leakage_params(0, &array_size);
279                 break;
280         case TEGRA_CHIPID_TEGRA3:
281         case TEGRA_CHIPID_TEGRA2:
282         default:
283                 array_size = 0;
284                 break;
285         }
286
287         for (i = 0; i < array_size; i++)
288                 if (cpu_speedo_id == params[i].cpu_speedo_id) {
289                         *cpu_speedo_idx = i;
290                         return 0;
291                 }
292
293         pr_err("%s: couldn't find cpu speedo id %d in freq/voltage LUT\n",
294                __func__, cpu_speedo_id);
295         return -EINVAL;
296 }
297
298 static int init_cpu_edp_limits_calculated(void)
299 {
300         unsigned int max_nr_cpus = num_possible_cpus();
301         unsigned int temp_idx, n_cores_idx, pwr_idx;
302         unsigned int cpu_g_minf, cpu_g_maxf;
303         unsigned int iddq_mA;
304         unsigned int cpu_speedo_idx;
305         unsigned int cap, limit;
306         struct tegra_edp_limits *edp_calculated_limits;
307         struct tegra_system_edp_entry *power_edp_calc_limits;
308         struct tegra_edp_cpu_leakage_params *params;
309         int ret;
310         struct clk *clk_cpu_g = tegra_get_clock_by_name("cpu_g");
311         int cpu_speedo_id = tegra_cpu_speedo_id();
312
313         /* Determine all inputs to EDP formula */
314         iddq_mA = tegra_get_cpu_iddq_value();
315         iddq_mA = 1281; /* hard code for testing */
316         ret = edp_find_speedo_idx(cpu_speedo_id, &cpu_speedo_idx);
317         if (ret)
318                 return ret;
319
320         switch (tegra_get_chip_id()) {
321         case TEGRA_CHIPID_TEGRA11:
322                 params = tegra11x_get_leakage_params(cpu_speedo_idx, NULL);
323                 break;
324         case TEGRA_CHIPID_TEGRA14:
325                 params = tegra14x_get_leakage_params(cpu_speedo_idx, NULL);
326                 break;
327         case TEGRA_CHIPID_TEGRA12:
328                 params = tegra12x_get_leakage_params(cpu_speedo_idx, NULL);
329                 break;
330         case TEGRA_CHIPID_TEGRA3:
331         case TEGRA_CHIPID_TEGRA2:
332         default:
333                 return -EINVAL;
334         }
335
336         edp_calculated_limits = kmalloc(sizeof(struct tegra_edp_limits)
337                                         * ARRAY_SIZE(temperatures), GFP_KERNEL);
338         BUG_ON(!edp_calculated_limits);
339
340         power_edp_calc_limits = kmalloc(sizeof(struct tegra_system_edp_entry)
341                                 * ARRAY_SIZE(power_cap_levels), GFP_KERNEL);
342         BUG_ON(!power_edp_calc_limits);
343
344         cpu_g_minf = 0;
345         cpu_g_maxf = clk_get_max_rate(clk_cpu_g);
346         freq_voltage_lut_size = (cpu_g_maxf - cpu_g_minf) / FREQ_STEP + 1;
347         freq_voltage_lut = kmalloc(sizeof(struct tegra_edp_freq_voltage_table)
348                                    * freq_voltage_lut_size, GFP_KERNEL);
349         if (!freq_voltage_lut) {
350                 pr_err("%s: failed alloc mem for freq/voltage LUT\n", __func__);
351                 kfree(power_edp_calc_limits);
352                 kfree(edp_calculated_limits);
353                 return -ENOMEM;
354         }
355
356         ret = edp_relate_freq_voltage(clk_cpu_g, cpu_speedo_idx,
357                                 freq_voltage_lut_size, freq_voltage_lut);
358         if (ret) {
359                 kfree(power_edp_calc_limits);
360                 kfree(edp_calculated_limits);
361                 kfree(freq_voltage_lut);
362                 return ret;
363         }
364
365         if (freq_voltage_lut_size != freq_voltage_lut_size_saved) {
366                 /* release previous table if present */
367                 kfree(freq_voltage_lut_saved);
368                 /* create table to save */
369                 freq_voltage_lut_saved =
370                         kmalloc(sizeof(struct tegra_edp_freq_voltage_table) *
371                         freq_voltage_lut_size, GFP_KERNEL);
372                 if (!freq_voltage_lut_saved) {
373                         pr_err("%s: failed alloc mem for freq/voltage LUT\n",
374                                 __func__);
375                         kfree(freq_voltage_lut);
376                         return -ENOMEM;
377                 }
378                 freq_voltage_lut_size_saved = freq_voltage_lut_size;
379         }
380         memcpy(freq_voltage_lut_saved,
381                 freq_voltage_lut,
382                 sizeof(struct tegra_edp_freq_voltage_table) *
383                         freq_voltage_lut_size);
384
385         /* Calculate EDP table */
386         for (n_cores_idx = 0; n_cores_idx < max_nr_cpus; n_cores_idx++) {
387                 for (temp_idx = 0;
388                      temp_idx < ARRAY_SIZE(temperatures); temp_idx++) {
389                         edp_calculated_limits[temp_idx].temperature =
390                                 temperatures[temp_idx];
391                         limit = edp_calculate_maxf(params,
392                                                    temperatures[temp_idx],
393                                                    -1,
394                                                    iddq_mA,
395                                                    n_cores_idx);
396                         if (limit == -EINVAL)
397                                 return -EINVAL;
398                         /* apply safety cap if it is specified */
399                         if (n_cores_idx < 4) {
400                                 cap = params->safety_cap[n_cores_idx];
401                                 if (cap && cap < limit)
402                                         limit = cap;
403                         }
404                         edp_calculated_limits[temp_idx].
405                                 freq_limits[n_cores_idx] = limit;
406                 }
407
408                 for (pwr_idx = 0;
409                      pwr_idx < ARRAY_SIZE(power_cap_levels); pwr_idx++) {
410                         power_edp_calc_limits[pwr_idx].power_limit_100mW =
411                                 power_cap_levels[pwr_idx] / 100;
412                         limit = edp_calculate_maxf(params,
413                                                    90,
414                                                    power_cap_levels[pwr_idx],
415                                                    iddq_mA,
416                                                    n_cores_idx);
417                         if (limit == -EINVAL)
418                                 return -EINVAL;
419                         power_edp_calc_limits[pwr_idx].
420                                 freq_limits[n_cores_idx] = limit;
421                 }
422         }
423
424         /*
425          * If this is an EDP table update, need to overwrite old table.
426          * The old table's address must remain valid.
427          */
428         if (edp_limits != edp_default_limits) {
429                 memcpy(edp_limits, edp_calculated_limits,
430                        sizeof(struct tegra_edp_limits)
431                        * ARRAY_SIZE(temperatures));
432                 kfree(edp_calculated_limits);
433         }
434         else {
435                 edp_limits = edp_calculated_limits;
436                 edp_limits_size = ARRAY_SIZE(temperatures);
437         }
438
439         if (power_edp_limits != power_edp_default_limits) {
440                 memcpy(power_edp_limits, power_edp_calc_limits,
441                        sizeof(struct tegra_system_edp_entry)
442                        * ARRAY_SIZE(power_cap_levels));
443                 kfree(power_edp_calc_limits);
444         } else {
445                 power_edp_limits = power_edp_calc_limits;
446                 power_edp_limits_size = ARRAY_SIZE(power_cap_levels);
447         }
448
449         kfree(freq_voltage_lut);
450         return 0;
451 }
452
453 void tegra_recalculate_cpu_edp_limits(void)
454 {
455         u32 tegra_chip_id;
456
457         tegra_chip_id = tegra_get_chip_id();
458         if (tegra_chip_id != TEGRA_CHIPID_TEGRA11 &&
459             tegra_chip_id != TEGRA_CHIPID_TEGRA14 &&
460             tegra_chip_id != TEGRA_CHIPID_TEGRA12)
461                 return;
462
463         if (init_cpu_edp_limits_calculated() == 0)
464                 return;
465
466         /* Revert to default EDP table on error */
467         edp_limits = edp_default_limits;
468         edp_limits_size = ARRAY_SIZE(edp_default_limits);
469
470         power_edp_limits = power_edp_default_limits;
471         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
472 }
473
474 /*
475  * Specify regulator current in mA, e.g. 5000mA
476  * Use 0 for default
477  */
478 void __init tegra_init_cpu_edp_limits(unsigned int regulator_mA)
479 {
480         if (!regulator_mA)
481                 goto end;
482         regulator_cur = regulator_mA + OVERRIDE_DEFAULT;
483
484         switch (tegra_get_chip_id()) {
485         case TEGRA_CHIPID_TEGRA11:
486         case TEGRA_CHIPID_TEGRA14:
487         case TEGRA_CHIPID_TEGRA12:
488                 if (init_cpu_edp_limits_calculated() == 0)
489                         return;
490                 break;
491         case TEGRA_CHIPID_TEGRA2:
492         case TEGRA_CHIPID_TEGRA3:
493         default:
494                 BUG();
495                 break;
496         }
497
498  end:
499         edp_limits = edp_default_limits;
500         edp_limits_size = ARRAY_SIZE(edp_default_limits);
501
502         power_edp_limits = power_edp_default_limits;
503         power_edp_limits_size = ARRAY_SIZE(power_edp_default_limits);
504 }
505
506 void tegra_get_cpu_edp_limits(const struct tegra_edp_limits **limits, int *size)
507 {
508         *limits = edp_limits;
509         *size = edp_limits_size;
510 }
511
512 void __init tegra_init_cpu_reg_mode_limits(unsigned int regulator_mA,
513                                            unsigned int mode)
514 {
515 }
516
517 void tegra_get_cpu_reg_mode_limits(const struct tegra_edp_limits **limits,
518                                    int *size, unsigned int mode)
519 {
520         *limits = reg_mode_limits;
521         *size = edp_limits_size;
522 }
523
524 void tegra_get_system_edp_limits(const unsigned int **limits)
525 {
526         *limits = system_edp_limits;
527 }
528
529 void tegra_platform_edp_init(struct thermal_trip_info *trips,
530                                 int *num_trips, int margin)
531 {
532         const struct tegra_edp_limits *cpu_edp_limits;
533         struct thermal_trip_info *trip_state;
534         int i, cpu_edp_limits_size;
535
536         if (!trips || !num_trips)
537                 return;
538
539         /* edp capping */
540         tegra_get_cpu_edp_limits(&cpu_edp_limits, &cpu_edp_limits_size);
541
542         if (cpu_edp_limits_size > MAX_THROT_TABLE_SIZE)
543                 BUG();
544
545         for (i = 0; i < cpu_edp_limits_size-1; i++) {
546                 trip_state = &trips[*num_trips];
547
548                 trip_state->cdev_type = "cpu_edp";
549                 trip_state->trip_temp =
550                         (cpu_edp_limits[i].temperature * 1000) - margin;
551                 trip_state->trip_type = THERMAL_TRIP_ACTIVE;
552                 trip_state->upper = trip_state->lower = i + 1;
553
554                 (*num_trips)++;
555
556                 if (*num_trips >= THERMAL_MAX_TRIPS)
557                         BUG();
558         }
559 }
560
561 struct tegra_system_edp_entry *tegra_get_system_edp_entries(int *size)
562 {
563         *size = power_edp_limits_size;
564         return power_edp_limits;
565 }
566
567 #ifdef CONFIG_DEBUG_FS
568
569 static int edp_limit_debugfs_show(struct seq_file *s, void *data)
570 {
571 #ifdef CONFIG_CPU_FREQ
572         seq_printf(s, "%u\n", tegra_get_edp_limit(NULL));
573 #endif
574         return 0;
575 }
576
577 static inline void edp_show_4core_edp_table(struct seq_file *s, int th_idx)
578 {
579         int i;
580
581         seq_printf(s, "%6s %10s %10s %10s %10s\n",
582                    " Temp.", "1-core", "2-cores", "3-cores", "4-cores");
583         for (i = 0; i < edp_limits_size; i++) {
584                 seq_printf(s, "%c%3dC: %10u %10u %10u %10u\n",
585                            i == th_idx ? '>' : ' ',
586                            edp_limits[i].temperature,
587                            edp_limits[i].freq_limits[0],
588                            edp_limits[i].freq_limits[1],
589                            edp_limits[i].freq_limits[2],
590                            edp_limits[i].freq_limits[3]);
591         }
592 }
593
594 static inline void edp_show_2core_edp_table(struct seq_file *s, int th_idx)
595 {
596         int i;
597
598         seq_printf(s, "%6s %10s %10s\n",
599                    " Temp.", "1-core", "2-cores");
600         for (i = 0; i < edp_limits_size; i++) {
601                 seq_printf(s, "%c%3dC: %10u %10u\n",
602                            i == th_idx ? '>' : ' ',
603                            edp_limits[i].temperature,
604                            edp_limits[i].freq_limits[0],
605                            edp_limits[i].freq_limits[1]);
606         }
607 }
608
609 static inline void edp_show_2core_system_table(struct seq_file *s)
610 {
611         seq_printf(s, "%10u %10u\n",
612                    system_edp_limits[0],
613                    system_edp_limits[1]);
614 }
615
616 static inline void edp_show_4core_system_table(struct seq_file *s)
617 {
618         seq_printf(s, "%10u %10u %10u %10u\n",
619                    system_edp_limits[0],
620                    system_edp_limits[1],
621                    system_edp_limits[2],
622                    system_edp_limits[3]);
623 }
624
625 static int edp_debugfs_show(struct seq_file *s, void *data)
626 {
627         unsigned int max_nr_cpus = num_possible_cpus();
628         int th_idx;
629
630         if (max_nr_cpus != 2 && max_nr_cpus != 4) {
631                 seq_printf(s, "Unsupported number of CPUs\n");
632                 return 0;
633         }
634
635 #ifdef CONFIG_CPU_FREQ
636         tegra_get_edp_limit(&th_idx);
637 #else
638         th_idx = 0;
639 #endif
640
641         seq_printf(s, "-- VDD_CPU %sEDP table (%umA = %umA - %umA) --\n",
642                    edp_limits == edp_default_limits ? "**default** " : "",
643                    regulator_cur - edp_reg_override_mA,
644                    regulator_cur, edp_reg_override_mA);
645
646         if (max_nr_cpus == 2)
647                 edp_show_2core_edp_table(s, th_idx);
648         else if (max_nr_cpus == 4)
649                 edp_show_4core_edp_table(s, th_idx);
650
651         if (system_edp_limits) {
652                 seq_printf(s, "\n-- System EDP table --\n");
653                 if (max_nr_cpus == 2)
654                         edp_show_2core_system_table(s);
655                 else if (max_nr_cpus == 4)
656                         edp_show_4core_system_table(s);
657         }
658
659         return 0;
660 }
661
662 static int edp_reg_override_show(struct seq_file *s, void *data)
663 {
664         seq_printf(s, "Limit override: %u mA. Effective limit: %u mA\n",
665                    edp_reg_override_mA, regulator_cur - edp_reg_override_mA);
666         return 0;
667 }
668
669 static int edp_reg_override_write(struct file *file,
670         const char __user *userbuf, size_t count, loff_t *ppos)
671 {
672         char buf[32], *end;
673         unsigned int edp_reg_override_mA_temp;
674         unsigned int edp_reg_override_mA_prev = edp_reg_override_mA;
675         u32 tegra_chip_id;
676
677         tegra_chip_id = tegra_get_chip_id();
678         if (!(tegra_chip_id == TEGRA_CHIPID_TEGRA11 ||
679                 tegra_chip_id == TEGRA_CHIPID_TEGRA14 ||
680                 tegra_chip_id == TEGRA_CHIPID_TEGRA12))
681                 goto override_err;
682
683         if (sizeof(buf) <= count)
684                 goto override_err;
685
686         if (copy_from_user(buf, userbuf, count))
687                 goto override_err;
688
689         /* terminate buffer and trim - white spaces may be appended
690          *  at the end when invoked from shell command line */
691         buf[count]='\0';
692         strim(buf);
693
694         edp_reg_override_mA_temp = simple_strtoul(buf, &end, 10);
695         if (*end != '\0')
696                 goto override_err;
697
698         if (edp_reg_override_mA_temp >= regulator_cur)
699                 goto override_err;
700
701         if (edp_reg_override_mA == edp_reg_override_mA_temp)
702                 return count;
703
704         edp_reg_override_mA = edp_reg_override_mA_temp;
705         if (init_cpu_edp_limits_calculated()) {
706                 /* Revert to previous override value if new value fails */
707                 edp_reg_override_mA = edp_reg_override_mA_prev;
708                 goto override_err;
709         }
710
711 #ifdef CONFIG_CPU_FREQ
712         if (tegra_cpu_set_speed_cap(NULL)) {
713                 pr_err("FAILED: Set CPU freq cap with new VDD_CPU EDP table\n");
714                 goto override_out;
715         }
716
717         pr_info("Reinitialized VDD_CPU EDP table with regulator current limit"
718                         " %u mA\n", regulator_cur - edp_reg_override_mA);
719 #else
720         pr_err("FAILED: tegra_cpu_set_speed_cap() does not exist, failed to reinitialize VDD_CPU EDP table");
721 #endif
722
723         return count;
724
725 override_err:
726         pr_err("FAILED: Reinitialize VDD_CPU EDP table with override \"%s\"",
727                buf);
728 #ifdef CONFIG_CPU_FREQ
729 override_out:
730 #endif
731         return -EINVAL;
732 }
733
734 static int edp_debugfs_open(struct inode *inode, struct file *file)
735 {
736         return single_open(file, edp_debugfs_show, inode->i_private);
737 }
738
739 static int edp_limit_debugfs_open(struct inode *inode, struct file *file)
740 {
741         return single_open(file, edp_limit_debugfs_show, inode->i_private);
742 }
743
744 static int edp_reg_override_open(struct inode *inode, struct file *file)
745 {
746         return single_open(file, edp_reg_override_show, inode->i_private);
747 }
748
749 static const struct file_operations edp_debugfs_fops = {
750         .open           = edp_debugfs_open,
751         .read           = seq_read,
752         .llseek         = seq_lseek,
753         .release        = single_release,
754 };
755
756 static const struct file_operations edp_limit_debugfs_fops = {
757         .open           = edp_limit_debugfs_open,
758         .read           = seq_read,
759         .llseek         = seq_lseek,
760         .release        = single_release,
761 };
762
763 static const struct file_operations edp_reg_override_debugfs_fops = {
764         .open           = edp_reg_override_open,
765         .read           = seq_read,
766         .write          = edp_reg_override_write,
767         .llseek         = seq_lseek,
768         .release        = single_release,
769 };
770
771 #if defined(CONFIG_EDP_FRAMEWORK) || defined(CONFIG_SYSEDP_FRAMEWORK)
772 static __init struct dentry *tegra_edp_debugfs_dir(void)
773 {
774         if (edp_debugfs_dir)
775                 return edp_debugfs_dir;
776         else
777                 return debugfs_create_dir("edp", NULL);
778 }
779 #else
780 static __init struct dentry *tegra_edp_debugfs_dir(void)
781 {
782         return debugfs_create_dir("edp", NULL);
783 }
784 #endif
785
786 static int __init tegra_edp_debugfs_init(void)
787 {
788         struct dentry *d_edp;
789         struct dentry *d_edp_limit;
790         struct dentry *d_edp_reg_override;
791         struct dentry *edp_dir;
792         struct dentry *vdd_cpu_dir;
793
794         if (!tegra_platform_is_silicon())
795                 return -ENOSYS;
796
797         edp_dir = tegra_edp_debugfs_dir();
798
799         if (!edp_dir)
800                 goto edp_dir_err;
801
802         vdd_cpu_dir = debugfs_create_dir("vdd_cpu", edp_dir);
803
804         if (!vdd_cpu_dir)
805                 goto vdd_cpu_dir_err;
806
807         d_edp = debugfs_create_file("edp", S_IRUGO, vdd_cpu_dir, NULL,
808                                 &edp_debugfs_fops);
809
810         if (!d_edp)
811                 goto edp_err;
812
813         d_edp_limit = debugfs_create_file("edp_limit", S_IRUGO, vdd_cpu_dir,
814                                 NULL, &edp_limit_debugfs_fops);
815
816         if (!d_edp_limit)
817                 goto edp_limit_err;
818
819         d_edp_reg_override = debugfs_create_file("edp_reg_override",
820                                 S_IRUGO | S_IWUSR, vdd_cpu_dir, NULL,
821                                 &edp_reg_override_debugfs_fops);
822
823         if (!d_edp_reg_override)
824                 goto edp_reg_override_err;
825
826         if (tegra_core_edp_debugfs_init(edp_dir))
827                 goto edp_reg_override_err;
828
829         return 0;
830
831 edp_reg_override_err:
832         debugfs_remove(d_edp_limit);
833 edp_limit_err:
834         debugfs_remove(d_edp);
835 edp_err:
836         debugfs_remove(vdd_cpu_dir);
837 vdd_cpu_dir_err:
838         debugfs_remove(edp_dir);
839 edp_dir_err:
840         return -ENOMEM;
841 }
842
843 late_initcall(tegra_edp_debugfs_init);
844 #endif /* CONFIG_DEBUG_FS */