unknown changes from android-tegra-nv-3.4
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/platform_data/tegra_usb.h>
28 #include <linux/tegra_avp.h>
29 #include <linux/nvhost.h>
30 #include <linux/clk.h>
31 #include <mach/irqs.h>
32 #include <linux/usb/tegra_usb_phy.h>
33 #include <mach/tegra_smmu.h>
34
35 #include "gpio-names.h"
36 #include "iomap.h"
37 #include "devices.h"
38
39 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
40 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
41 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
42 #define TEGRA_DMA_REQ_SEL_SPI                   11
43 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
44
45 static struct resource emc_resource[] = {
46         [0] = {
47                 .start  = TEGRA_EMC_BASE,
48                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
49                 .flags  = IORESOURCE_MEM,
50         }
51 };
52
53 struct platform_device tegra_emc_device = {
54         .name           = "tegra-emc",
55         .id             = -1,
56         .resource       = emc_resource,
57         .num_resources  = ARRAY_SIZE(emc_resource),
58 };
59
60 static struct resource gpio_resource[] = {
61         [0] = {
62                 .start  = TEGRA_GPIO_BASE,
63                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
64                 .flags  = IORESOURCE_MEM,
65         },
66         [1] = {
67                 .start  = INT_GPIO1,
68                 .end    = INT_GPIO1,
69                 .flags  = IORESOURCE_IRQ,
70         },
71         [2] = {
72                 .start  = INT_GPIO2,
73                 .end    = INT_GPIO2,
74                 .flags  = IORESOURCE_IRQ,
75         },
76         [3] = {
77                 .start  = INT_GPIO3,
78                 .end    = INT_GPIO3,
79                 .flags  = IORESOURCE_IRQ,
80         },
81         [4] = {
82                 .start  = INT_GPIO4,
83                 .end    = INT_GPIO4,
84                 .flags  = IORESOURCE_IRQ,
85         },
86         [5] = {
87                 .start  = INT_GPIO5,
88                 .end    = INT_GPIO5,
89                 .flags  = IORESOURCE_IRQ,
90         },
91         [6] = {
92                 .start  = INT_GPIO6,
93                 .end    = INT_GPIO6,
94                 .flags  = IORESOURCE_IRQ,
95         },
96         [7] = {
97                 .start  = INT_GPIO7,
98                 .end    = INT_GPIO7,
99                 .flags  = IORESOURCE_IRQ,
100         },
101 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
102         [8] = {
103                 .start  = INT_GPIO8,
104                 .end    = INT_GPIO8,
105                 .flags  = IORESOURCE_IRQ,
106         },
107 #endif
108 };
109
110 struct platform_device tegra_gpio_device = {
111         .name           = "tegra-gpio",
112         .id             = -1,
113         .resource       = gpio_resource,
114         .num_resources  = ARRAY_SIZE(gpio_resource),
115 };
116
117 static struct resource pinmux_resource[] = {
118 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
119         [0] = {
120                 /* Tri-state registers */
121                 .start  = TEGRA_APB_MISC_BASE + 0x14,
122                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
123                 .flags  = IORESOURCE_MEM,
124         },
125         [1] = {
126                 /* Mux registers */
127                 .start  = TEGRA_APB_MISC_BASE + 0x80,
128                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
129                 .flags  = IORESOURCE_MEM,
130         },
131         [2] = {
132                 /* Pull-up/down registers */
133                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
134                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
135                 .flags  = IORESOURCE_MEM,
136         },
137         [3] = {
138                 /* Pad control registers */
139                 .start  = TEGRA_APB_MISC_BASE + 0x868,
140                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
141                 .flags  = IORESOURCE_MEM,
142         },
143 #else
144         [0] = {
145                 /* Drive registers */
146                 .start  = TEGRA_APB_MISC_BASE + 0x868,
147                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
148                 .flags  = IORESOURCE_MEM,
149         },
150         [1] = {
151                 /* Mux registers */
152                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
153                 .end    = TEGRA_APB_MISC_BASE + 0x33e0 + 3,
154                 .flags  = IORESOURCE_MEM,
155         },
156 #endif
157 };
158
159 struct platform_device tegra_pinmux_device = {
160 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
161         .name           = "tegra30-pinmux",
162 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
163         .name           = "tegra20-pinctrl",
164 #endif
165         .id             = -1,
166         .resource       = pinmux_resource,
167         .num_resources  = ARRAY_SIZE(pinmux_resource),
168 };
169
170 static struct resource i2c_resource1[] = {
171         [0] = {
172                 .start  = INT_I2C,
173                 .end    = INT_I2C,
174                 .flags  = IORESOURCE_IRQ,
175         },
176         [1] = {
177                 .start  = TEGRA_I2C_BASE,
178                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
179                 .flags  = IORESOURCE_MEM,
180         },
181 };
182
183 static struct resource i2c_resource2[] = {
184         [0] = {
185                 .start  = INT_I2C2,
186                 .end    = INT_I2C2,
187                 .flags  = IORESOURCE_IRQ,
188         },
189         [1] = {
190                 .start  = TEGRA_I2C2_BASE,
191                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
192                 .flags  = IORESOURCE_MEM,
193         },
194 };
195
196 static struct resource i2c_resource3[] = {
197         [0] = {
198                 .start  = INT_I2C3,
199                 .end    = INT_I2C3,
200                 .flags  = IORESOURCE_IRQ,
201         },
202         [1] = {
203                 .start  = TEGRA_I2C3_BASE,
204                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
205                 .flags  = IORESOURCE_MEM,
206         },
207 };
208
209 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
210 static struct resource i2c_resource4[] = {
211         [0] = {
212                 .start  = INT_DVC,
213                 .end    = INT_DVC,
214                 .flags  = IORESOURCE_IRQ,
215         },
216         [1] = {
217                 .start  = TEGRA_DVC_BASE,
218                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
219                 .flags  = IORESOURCE_MEM,
220         },
221 };
222
223 #else
224 static struct resource i2c_resource4[] = {
225         [0] = {
226                 .start  = INT_I2C4,
227                 .end    = INT_I2C4,
228                 .flags  = IORESOURCE_IRQ,
229         },
230         [1] = {
231                 .start  = TEGRA_I2C4_BASE,
232                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
233                 .flags  = IORESOURCE_MEM,
234         },
235 };
236
237 static struct resource i2c_resource5[] = {
238         [0] = {
239                 .start  = INT_I2C5,
240                 .end    = INT_I2C5,
241                 .flags  = IORESOURCE_IRQ,
242         },
243         [1] = {
244                 .start  = TEGRA_I2C5_BASE,
245                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
246                 .flags  = IORESOURCE_MEM,
247         },
248 };
249 #endif
250
251 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
252         .bus_clk_rate   = 400000,
253 };
254
255 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
256         .bus_clk_rate   = 400000,
257 };
258
259 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
260         .bus_clk_rate   = 400000,
261 };
262
263 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
264         .bus_clk_rate   = 400000,
265 };
266
267 struct platform_device tegra_i2c_device1 = {
268         .name           = "tegra-i2c",
269         .id             = 0,
270         .resource       = i2c_resource1,
271         .num_resources  = ARRAY_SIZE(i2c_resource1),
272         .dev = {
273                 .platform_data = &tegra_i2c1_platform_data,
274         },
275 };
276
277 struct platform_device tegra_i2c_device2 = {
278         .name           = "tegra-i2c",
279         .id             = 1,
280         .resource       = i2c_resource2,
281         .num_resources  = ARRAY_SIZE(i2c_resource2),
282         .dev = {
283                 .platform_data = &tegra_i2c2_platform_data,
284         },
285 };
286
287 struct platform_device tegra_i2c_device3 = {
288         .name           = "tegra-i2c",
289         .id             = 2,
290         .resource       = i2c_resource3,
291         .num_resources  = ARRAY_SIZE(i2c_resource3),
292         .dev = {
293                 .platform_data = &tegra_i2c3_platform_data,
294         },
295 };
296
297 struct platform_device tegra_i2c_device4 = {
298         .name           = "tegra-i2c",
299         .id             = 3,
300         .resource       = i2c_resource4,
301         .num_resources  = ARRAY_SIZE(i2c_resource4),
302         .dev = {
303                 .platform_data = &tegra_dvc_platform_data,
304         },
305 };
306
307 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
308 struct platform_device tegra_i2c_device5 = {
309         .name           = "tegra-i2c",
310         .id             = 4,
311         .resource       = i2c_resource5,
312         .num_resources  = ARRAY_SIZE(i2c_resource5),
313         .dev = {
314                 .platform_data = 0,
315         },
316 };
317 #endif
318
319 static struct resource spi_resource1[] = {
320         [0] = {
321                 .start  = INT_SPI_1,
322                 .end    = INT_SPI_1,
323                 .flags  = IORESOURCE_IRQ,
324         },
325         [1] = {
326                 .start  = TEGRA_SPI1_BASE,
327                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
328                 .flags  = IORESOURCE_MEM,
329         },
330 };
331
332 static struct resource spi_resource2[] = {
333         [0] = {
334                 .start  = INT_SPI_2,
335                 .end    = INT_SPI_2,
336                 .flags  = IORESOURCE_IRQ,
337         },
338         [1] = {
339                 .start  = TEGRA_SPI2_BASE,
340                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
341                 .flags  = IORESOURCE_MEM,
342         },
343 };
344
345 static struct resource spi_resource3[] = {
346         [0] = {
347                 .start  = INT_SPI_3,
348                 .end    = INT_SPI_3,
349                 .flags  = IORESOURCE_IRQ,
350         },
351         [1] = {
352                 .start  = TEGRA_SPI3_BASE,
353                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
354                 .flags  = IORESOURCE_MEM,
355         },
356 };
357
358 static struct resource spi_resource4[] = {
359         [0] = {
360                 .start  = INT_SPI_4,
361                 .end    = INT_SPI_4,
362                 .flags  = IORESOURCE_IRQ,
363         },
364         [1] = {
365                 .start  = TEGRA_SPI4_BASE,
366                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
367                 .flags  = IORESOURCE_MEM,
368         },
369 };
370 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
371 static struct resource spi_resource5[] = {
372         [0] = {
373                 .start  = INT_SPI_5,
374                 .end    = INT_SPI_5,
375                 .flags  = IORESOURCE_IRQ,
376         },
377         [1] = {
378                 .start  = TEGRA_SPI5_BASE,
379                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
380                 .flags  = IORESOURCE_MEM,
381         },
382 };
383
384 static struct resource spi_resource6[] = {
385         [0] = {
386                 .start  = INT_SPI_6,
387                 .end    = INT_SPI_6,
388                 .flags  = IORESOURCE_IRQ,
389         },
390         [1] = {
391                 .start  = TEGRA_SPI6_BASE,
392                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
393                 .flags  = IORESOURCE_MEM,
394         },
395 };
396 #endif
397
398 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
399 static struct resource dtv_resource[] = {
400         [0] = {
401                 .start  = INT_DTV,
402                 .end    = INT_DTV,
403                 .flags  = IORESOURCE_IRQ,
404         },
405         [1] = {
406                 .start  = TEGRA_DTV_BASE,
407                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
408                 .flags  = IORESOURCE_MEM,
409         },
410         [2] = {
411                 .start  = TEGRA_DMA_REQ_SEL_DTV,
412                 .end    = TEGRA_DMA_REQ_SEL_DTV,
413                 .flags  = IORESOURCE_DMA
414         },
415 };
416 #endif
417
418
419 struct platform_device tegra_spi_device1 = {
420         .name           = "spi_tegra",
421         .id             = 0,
422         .resource       = spi_resource1,
423         .num_resources  = ARRAY_SIZE(spi_resource1),
424         .dev            = {
425                 .coherent_dma_mask      = 0xffffffff,
426         },
427 };
428
429 struct platform_device tegra_spi_device2 = {
430         .name           = "spi_tegra",
431         .id             = 1,
432         .resource       = spi_resource2,
433         .num_resources  = ARRAY_SIZE(spi_resource2),
434         .dev            = {
435                 .coherent_dma_mask      = 0xffffffff,
436         },
437 };
438
439 struct platform_device tegra_spi_device3 = {
440         .name           = "spi_tegra",
441         .id             = 2,
442         .resource       = spi_resource3,
443         .num_resources  = ARRAY_SIZE(spi_resource3),
444         .dev            = {
445                 .coherent_dma_mask      = 0xffffffff,
446         },
447 };
448
449 struct platform_device tegra_spi_device4 = {
450         .name           = "spi_tegra",
451         .id             = 3,
452         .resource       = spi_resource4,
453         .num_resources  = ARRAY_SIZE(spi_resource4),
454         .dev            = {
455                 .coherent_dma_mask      = 0xffffffff,
456         },
457 };
458 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
459 struct platform_device tegra_spi_device5 = {
460         .name           = "spi_tegra",
461         .id             = 4,
462         .resource       = spi_resource5,
463         .num_resources  = ARRAY_SIZE(spi_resource5),
464         .dev  = {
465                 .coherent_dma_mask      = 0xffffffff,
466         },
467 };
468
469 struct platform_device tegra_spi_device6 = {
470         .name           = "spi_tegra",
471         .id             = 5,
472         .resource       = spi_resource6,
473         .num_resources  = ARRAY_SIZE(spi_resource6),
474         .dev  = {
475                 .coherent_dma_mask      = 0xffffffff,
476         },
477 };
478 #endif
479
480 struct platform_device tegra_spi_slave_device1 = {
481         .name           = "spi_slave_tegra",
482         .id             = 0,
483         .resource       = spi_resource1,
484         .num_resources  = ARRAY_SIZE(spi_resource1),
485         .dev  = {
486                 .coherent_dma_mask      = 0xffffffff,
487         },
488 };
489
490 struct platform_device tegra_spi_slave_device2 = {
491         .name           = "spi_slave_tegra",
492         .id             = 1,
493         .resource       = spi_resource2,
494         .num_resources  = ARRAY_SIZE(spi_resource2),
495         .dev  = {
496                 .coherent_dma_mask      = 0xffffffff,
497         },
498 };
499
500 struct platform_device tegra_spi_slave_device3 = {
501         .name           = "spi_slave_tegra",
502         .id             = 2,
503         .resource       = spi_resource3,
504         .num_resources  = ARRAY_SIZE(spi_resource3),
505         .dev  = {
506                 .coherent_dma_mask      = 0xffffffff,
507         },
508 };
509
510 struct platform_device tegra_spi_slave_device4 = {
511         .name           = "spi_slave_tegra",
512         .id             = 3,
513         .resource       = spi_resource4,
514         .num_resources  = ARRAY_SIZE(spi_resource4),
515         .dev  = {
516                 .coherent_dma_mask      = 0xffffffff,
517         },
518 };
519 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
520 struct platform_device tegra_spi_slave_device5 = {
521         .name           = "spi_slave_tegra",
522         .id             = 4,
523         .resource       = spi_resource5,
524         .num_resources  = ARRAY_SIZE(spi_resource5),
525         .dev  = {
526                 .coherent_dma_mask      = 0xffffffff,
527         },
528 };
529
530 struct platform_device tegra_spi_slave_device6 = {
531         .name           = "spi_slave_tegra",
532         .id             = 5,
533         .resource       = spi_resource6,
534         .num_resources  = ARRAY_SIZE(spi_resource6),
535         .dev  = {
536                 .coherent_dma_mask      = 0xffffffff,
537         },
538 };
539 #endif
540
541 static struct resource resources_nor[] = {
542         [0] = {
543                 .start = INT_SNOR,
544                 .end = INT_SNOR,
545                 .flags = IORESOURCE_IRQ,
546         },
547         [1] = {
548                 /* Map SNOR Controller */
549                 .start = TEGRA_SNOR_BASE,
550                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
551                 .flags = IORESOURCE_MEM,
552         },
553         [2] = {
554                 /* Map the size of flash */
555                 .start = TEGRA_NOR_FLASH_BASE,
556                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
557                 .flags = IORESOURCE_MEM,
558         }
559 };
560
561 struct platform_device tegra_nor_device = {
562         .name = "tegra-nor",
563         .id = -1,
564         .num_resources = ARRAY_SIZE(resources_nor),
565         .resource = resources_nor,
566         .dev = {
567                 .coherent_dma_mask = 0xffffffff,
568         },
569 };
570
571 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
572 struct platform_device tegra_dtv_device = {
573         .name           = "tegra_dtv",
574         .id             = -1,
575         .resource       = dtv_resource,
576         .num_resources  = ARRAY_SIZE(dtv_resource),
577         .dev = {
578                 .init_name = "dtv",
579                 .coherent_dma_mask = 0xffffffff,
580         },
581 };
582 #endif
583
584 static struct resource sdhci_resource1[] = {
585         [0] = {
586                 .start  = INT_SDMMC1,
587                 .end    = INT_SDMMC1,
588                 .flags  = IORESOURCE_IRQ,
589         },
590         [1] = {
591                 .start  = TEGRA_SDMMC1_BASE,
592                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
593                 .flags  = IORESOURCE_MEM,
594         },
595 };
596
597 static struct resource sdhci_resource2[] = {
598         [0] = {
599                 .start  = INT_SDMMC2,
600                 .end    = INT_SDMMC2,
601                 .flags  = IORESOURCE_IRQ,
602         },
603         [1] = {
604                 .start  = TEGRA_SDMMC2_BASE,
605                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
606                 .flags  = IORESOURCE_MEM,
607         },
608 };
609
610 static struct resource sdhci_resource3[] = {
611         [0] = {
612                 .start  = INT_SDMMC3,
613                 .end    = INT_SDMMC3,
614                 .flags  = IORESOURCE_IRQ,
615         },
616         [1] = {
617                 .start  = TEGRA_SDMMC3_BASE,
618                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
619                 .flags  = IORESOURCE_MEM,
620         },
621 };
622
623 static struct resource sdhci_resource4[] = {
624         [0] = {
625                 .start  = INT_SDMMC4,
626                 .end    = INT_SDMMC4,
627                 .flags  = IORESOURCE_IRQ,
628         },
629         [1] = {
630                 .start  = TEGRA_SDMMC4_BASE,
631                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
632                 .flags  = IORESOURCE_MEM,
633         },
634 };
635
636 struct platform_device tegra_pci_device = {
637         .name           = "tegra-pcie",
638         .id             = 0,
639         .resource       = 0,
640         .num_resources  = 0,
641         .dev = {
642                 .platform_data = 0,
643         },
644 };
645
646 /* board files should fill in platform_data register the devices themselvs.
647  * See board-harmony.c for an example
648  */
649 struct platform_device tegra_sdhci_device1 = {
650         .name           = "sdhci-tegra",
651         .id             = 0,
652         .resource       = sdhci_resource1,
653         .num_resources  = ARRAY_SIZE(sdhci_resource1),
654 };
655
656 struct platform_device tegra_sdhci_device2 = {
657         .name           = "sdhci-tegra",
658         .id             = 1,
659         .resource       = sdhci_resource2,
660         .num_resources  = ARRAY_SIZE(sdhci_resource2),
661 };
662
663 struct platform_device tegra_sdhci_device3 = {
664         .name           = "sdhci-tegra",
665         .id             = 2,
666         .resource       = sdhci_resource3,
667         .num_resources  = ARRAY_SIZE(sdhci_resource3),
668 };
669
670 struct platform_device tegra_sdhci_device4 = {
671         .name           = "sdhci-tegra",
672         .id             = 3,
673         .resource       = sdhci_resource4,
674         .num_resources  = ARRAY_SIZE(sdhci_resource4),
675 };
676
677 static struct resource tegra_usb1_resources[] = {
678         [0] = {
679                 .start  = TEGRA_USB_BASE,
680                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
681                 .flags  = IORESOURCE_MEM,
682         },
683         [1] = {
684                 .start  = INT_USB,
685                 .end    = INT_USB,
686                 .flags  = IORESOURCE_IRQ,
687         },
688 };
689
690 static struct resource tegra_usb2_resources[] = {
691         [0] = {
692                 .start  = TEGRA_USB2_BASE,
693                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
694                 .flags  = IORESOURCE_MEM,
695         },
696         [1] = {
697                 .start  = INT_USB2,
698                 .end    = INT_USB2,
699                 .flags  = IORESOURCE_IRQ,
700         },
701 };
702
703 static struct resource tegra_usb3_resources[] = {
704         [0] = {
705                 .start  = TEGRA_USB3_BASE,
706                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
707                 .flags  = IORESOURCE_MEM,
708         },
709         [1] = {
710                 .start  = INT_USB3,
711                 .end    = INT_USB3,
712                 .flags  = IORESOURCE_IRQ,
713         },
714 };
715
716 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
717
718 struct platform_device tegra_ehci1_device = {
719         .name   = "tegra-ehci",
720         .id     = 0,
721         .dev    = {
722                 .dma_mask       = &tegra_ehci_dmamask,
723                 .coherent_dma_mask = DMA_BIT_MASK(32),
724         },
725         .resource = tegra_usb1_resources,
726         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
727 };
728
729 struct platform_device tegra_ehci2_device = {
730         .name   = "tegra-ehci",
731         .id     = 1,
732         .dev    = {
733                 .dma_mask       = &tegra_ehci_dmamask,
734                 .coherent_dma_mask = DMA_BIT_MASK(32),
735         },
736         .resource = tegra_usb2_resources,
737         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
738 };
739
740 struct platform_device tegra_ehci3_device = {
741         .name   = "tegra-ehci",
742         .id     = 2,
743         .dev    = {
744                 .dma_mask       = &tegra_ehci_dmamask,
745                 .coherent_dma_mask = DMA_BIT_MASK(32),
746         },
747         .resource = tegra_usb3_resources,
748         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
749 };
750
751 static struct resource tegra_pmu_resources[] = {
752         [0] = {
753                 .start  = INT_CPU0_PMU_INTR,
754                 .end    = INT_CPU0_PMU_INTR,
755                 .flags  = IORESOURCE_IRQ,
756         },
757         [1] = {
758                 .start  = INT_CPU1_PMU_INTR,
759                 .end    = INT_CPU1_PMU_INTR,
760                 .flags  = IORESOURCE_IRQ,
761         },
762 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
763         [2] = {
764                 .start  = INT_CPU2_PMU_INTR,
765                 .end    = INT_CPU2_PMU_INTR,
766                 .flags  = IORESOURCE_IRQ,
767         },
768         [3] = {
769                 .start  = INT_CPU3_PMU_INTR,
770                 .end    = INT_CPU3_PMU_INTR,
771                 .flags  = IORESOURCE_IRQ,
772         },
773 #endif
774 };
775
776 struct platform_device tegra_pmu_device = {
777         .name           = "arm-pmu",
778         .id             = -1,
779         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
780         .resource       = tegra_pmu_resources,
781 };
782
783 static struct resource tegra_uarta_resources[] = {
784         [0] = {
785                 .start  = TEGRA_UARTA_BASE,
786                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
787                 .flags  = IORESOURCE_MEM,
788         },
789         [1] = {
790                 .start  = INT_UARTA,
791                 .end    = INT_UARTA,
792                 .flags  = IORESOURCE_IRQ,
793         },
794 };
795
796 static struct resource tegra_uartb_resources[] = {
797         [0] = {
798                 .start  = TEGRA_UARTB_BASE,
799                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
800                 .flags  = IORESOURCE_MEM,
801         },
802         [1] = {
803                 .start  = INT_UARTB,
804                 .end    = INT_UARTB,
805                 .flags  = IORESOURCE_IRQ,
806         },
807 };
808
809 static struct resource tegra_uartc_resources[] = {
810         [0] = {
811                 .start  = TEGRA_UARTC_BASE,
812                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
813                 .flags  = IORESOURCE_MEM,
814         },
815         [1] = {
816                 .start  = INT_UARTC,
817                 .end    = INT_UARTC,
818                 .flags  = IORESOURCE_IRQ,
819         },
820 };
821
822 static struct resource tegra_uartd_resources[] = {
823         [0] = {
824                 .start  = TEGRA_UARTD_BASE,
825                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
826                 .flags  = IORESOURCE_MEM,
827         },
828         [1] = {
829                 .start  = INT_UARTD,
830                 .end    = INT_UARTD,
831                 .flags  = IORESOURCE_IRQ,
832         },
833 };
834
835 static struct resource tegra_uarte_resources[] = {
836         [0] = {
837                 .start  = TEGRA_UARTE_BASE,
838                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
839                 .flags  = IORESOURCE_MEM,
840         },
841         [1] = {
842                 .start  = INT_UARTE,
843                 .end    = INT_UARTE,
844                 .flags  = IORESOURCE_IRQ,
845         },
846 };
847
848 struct platform_device tegra_uarta_device = {
849         .name   = "tegra_uart",
850         .id     = 0,
851         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
852         .resource       = tegra_uarta_resources,
853         .dev    = {
854                 .coherent_dma_mask      = DMA_BIT_MASK(32),
855         },
856 };
857
858 struct platform_device tegra_uartb_device = {
859         .name   = "tegra_uart",
860         .id     = 1,
861         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
862         .resource       = tegra_uartb_resources,
863         .dev    = {
864                 .coherent_dma_mask      = DMA_BIT_MASK(32),
865         },
866 };
867
868 struct platform_device tegra_uartc_device = {
869         .name   = "tegra_uart",
870         .id     = 2,
871         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
872         .resource       = tegra_uartc_resources,
873         .dev    = {
874                 .coherent_dma_mask      = DMA_BIT_MASK(32),
875         },
876 };
877
878 struct platform_device tegra_uartd_device = {
879         .name   = "tegra_uart",
880         .id     = 3,
881         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
882         .resource       = tegra_uartd_resources,
883         .dev    = {
884                 .coherent_dma_mask      = DMA_BIT_MASK(32),
885         },
886 };
887
888 struct platform_device tegra_uarte_device = {
889         .name   = "tegra_uart",
890         .id     = 4,
891         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
892         .resource       = tegra_uarte_resources,
893         .dev    = {
894                 .coherent_dma_mask      = DMA_BIT_MASK(32),
895         },
896 };
897
898 static struct plat_serial8250_port debug_uarta_platform_data[] = {
899         {
900                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
901                 .mapbase        = TEGRA_UARTA_BASE,
902                 .irq            = INT_UARTA,
903                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
904                 .type           = PORT_TEGRA,
905                 .iotype         = UPIO_MEM,
906                 .regshift       = 2,
907         },
908         {
909                 .flags          = 0,
910         },
911 };
912
913 static struct plat_serial8250_port debug_uartb_platform_data[] = {
914         {
915                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
916                 .mapbase        = TEGRA_UARTB_BASE,
917                 .irq            = INT_UARTB,
918                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
919                 .type           = PORT_TEGRA,
920                 .iotype         = UPIO_MEM,
921                 .regshift       = 2,
922         },
923         {
924                 .flags          = 0,
925         },
926 };
927
928 static struct plat_serial8250_port debug_uartc_platform_data[] = {
929         {
930                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
931                 .mapbase        = TEGRA_UARTC_BASE,
932                 .irq            = INT_UARTC,
933                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
934                 .type           = PORT_TEGRA,
935                 .iotype         = UPIO_MEM,
936                 .regshift       = 2,
937         },
938         {
939                 .flags          = 0,
940         },
941 };
942
943 static struct plat_serial8250_port debug_uartd_platform_data[] = {
944         {
945                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
946                 .mapbase        = TEGRA_UARTD_BASE,
947                 .irq            = INT_UARTD,
948                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
949                 .type           = PORT_TEGRA,
950                 .iotype         = UPIO_MEM,
951                 .regshift       = 2,
952         },
953         {
954                 .flags          = 0,
955         },
956 };
957
958 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
959 static struct plat_serial8250_port debug_uarte_platform_data[] = {
960         {
961                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
962                 .mapbase        = TEGRA_UARTE_BASE,
963                 .irq            = INT_UARTE,
964                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
965                 .type           = PORT_TEGRA,
966                 .iotype         = UPIO_MEM,
967                 .regshift       = 2,
968         },
969         {
970                 .flags          = 0,
971         },
972 };
973 #endif
974
975 struct platform_device debug_uarta_device = {
976         .name = "serial8250",
977         .id = PLAT8250_DEV_PLATFORM,
978         .dev = {
979                 .platform_data = debug_uarta_platform_data,
980         },
981 };
982
983 struct platform_device debug_uartb_device = {
984         .name = "serial8250",
985         .id = PLAT8250_DEV_PLATFORM,
986         .dev = {
987                 .platform_data = debug_uartb_platform_data,
988         },
989 };
990
991 struct platform_device debug_uartc_device = {
992         .name = "serial8250",
993         .id = PLAT8250_DEV_PLATFORM,
994         .dev = {
995                 .platform_data = debug_uartc_platform_data,
996         },
997 };
998
999 struct platform_device debug_uartd_device = {
1000         .name = "serial8250",
1001         .id = PLAT8250_DEV_PLATFORM,
1002         .dev = {
1003                 .platform_data = debug_uartd_platform_data,
1004         },
1005 };
1006
1007 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1008 struct platform_device debug_uarte_device = {
1009         .name = "serial8250",
1010         .id = PLAT8250_DEV_PLATFORM,
1011         .dev = {
1012                 .platform_data = debug_uarte_platform_data,
1013         },
1014 };
1015 #endif
1016
1017 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1018 static struct resource i2s_resource1[] = {
1019         [0] = {
1020                 .start  = INT_I2S1,
1021                 .end    = INT_I2S1,
1022                 .flags  = IORESOURCE_IRQ
1023         },
1024         [1] = {
1025                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1026                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1027                 .flags  = IORESOURCE_DMA
1028         },
1029         [2] = {
1030                 .start  = TEGRA_I2S1_BASE,
1031                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1032                 .flags  = IORESOURCE_MEM
1033         }
1034 };
1035
1036 struct platform_device tegra_i2s_device1 = {
1037         .name           = "tegra20-i2s",
1038         .id             = 0,
1039         .resource       = i2s_resource1,
1040         .num_resources  = ARRAY_SIZE(i2s_resource1),
1041 };
1042
1043 static struct resource i2s_resource2[] = {
1044         [0] = {
1045                 .start  = INT_I2S2,
1046                 .end    = INT_I2S2,
1047                 .flags  = IORESOURCE_IRQ
1048         },
1049         [1] = {
1050                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1051                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1052                 .flags  = IORESOURCE_DMA
1053         },
1054         [2] = {
1055                 .start  = TEGRA_I2S2_BASE,
1056                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1057                 .flags  = IORESOURCE_MEM
1058         }
1059 };
1060
1061 struct platform_device tegra_i2s_device2 = {
1062         .name           = "tegra20-i2s",
1063         .id             = 1,
1064         .resource       = i2s_resource2,
1065         .num_resources  = ARRAY_SIZE(i2s_resource2),
1066 };
1067 #else
1068 static struct resource i2s_resource0[] = {
1069         [0] = {
1070                 .start  = TEGRA_I2S0_BASE,
1071                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1072                 .flags  = IORESOURCE_MEM
1073         }
1074 };
1075
1076 struct platform_device tegra_i2s_device0 = {
1077         .name           = "tegra30-i2s",
1078         .id             = 0,
1079         .resource       = i2s_resource0,
1080         .num_resources  = ARRAY_SIZE(i2s_resource0),
1081 };
1082
1083 static struct resource i2s_resource1[] = {
1084         [0] = {
1085                 .start  = TEGRA_I2S1_BASE,
1086                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1087                 .flags  = IORESOURCE_MEM
1088         }
1089 };
1090
1091 struct platform_device tegra_i2s_device1 = {
1092         .name           = "tegra30-i2s",
1093         .id             = 1,
1094         .resource       = i2s_resource1,
1095         .num_resources  = ARRAY_SIZE(i2s_resource1),
1096 };
1097
1098 static struct resource i2s_resource2[] = {
1099         [0] = {
1100                 .start  = TEGRA_I2S2_BASE,
1101                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1102                 .flags  = IORESOURCE_MEM
1103         }
1104 };
1105
1106 struct platform_device tegra_i2s_device2 = {
1107         .name           = "tegra30-i2s",
1108         .id             = 2,
1109         .resource       = i2s_resource2,
1110         .num_resources  = ARRAY_SIZE(i2s_resource2),
1111 };
1112
1113 static struct resource i2s_resource3[] = {
1114         [0] = {
1115                 .start  = TEGRA_I2S3_BASE,
1116                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1117                 .flags  = IORESOURCE_MEM
1118         }
1119 };
1120
1121 struct platform_device tegra_i2s_device3 = {
1122         .name           = "tegra30-i2s",
1123         .id             = 3,
1124         .resource       = i2s_resource3,
1125         .num_resources  = ARRAY_SIZE(i2s_resource3),
1126 };
1127
1128 static struct resource i2s_resource4[] = {
1129         [0] = {
1130                 .start  = TEGRA_I2S4_BASE,
1131                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1132                 .flags  = IORESOURCE_MEM
1133         }
1134 };
1135
1136 struct platform_device tegra_i2s_device4 = {
1137         .name           = "tegra30-i2s",
1138         .id             = 4,
1139         .resource       = i2s_resource4,
1140         .num_resources  = ARRAY_SIZE(i2s_resource4),
1141 };
1142 #endif
1143
1144 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1145 static struct resource spdif_resource[] = {
1146         [0] = {
1147                 .start  = INT_SPDIF,
1148                 .end    = INT_SPDIF,
1149                 .flags  = IORESOURCE_IRQ
1150         },
1151         [1] = {
1152                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1153                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1154                 .flags  = IORESOURCE_DMA
1155         },
1156         [2] = {
1157                 .start  = TEGRA_SPDIF_BASE,
1158                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1159                 .flags  = IORESOURCE_MEM
1160         }
1161 };
1162
1163 struct platform_device tegra_spdif_device = {
1164         .name           = "tegra20-spdif",
1165         .id             = -1,
1166         .resource       = spdif_resource,
1167         .num_resources  = ARRAY_SIZE(spdif_resource),
1168 };
1169 #else
1170 static struct resource spdif_resource[] = {
1171         [0] = {
1172                 .start  = TEGRA_SPDIF_BASE,
1173                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1174                 .flags  = IORESOURCE_MEM
1175         }
1176 };
1177
1178 struct platform_device tegra_spdif_device = {
1179         .name           = "tegra30-spdif",
1180         .id             = -1,
1181         .resource       = spdif_resource,
1182         .num_resources  = ARRAY_SIZE(spdif_resource),
1183 };
1184 #endif
1185
1186 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1187 static struct resource ahub_resource[] = {
1188         [0] = {
1189                 .start  = TEGRA_APBIF0_BASE,
1190                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1191                 .flags  = IORESOURCE_MEM
1192         },
1193         [1] = {
1194                 .start  = TEGRA_AHUB_BASE,
1195                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1196                 .flags  = IORESOURCE_MEM
1197         }
1198 };
1199
1200 struct platform_device tegra_ahub_device = {
1201         .name   = "tegra30-ahub",
1202         .id     = -1,
1203         .resource       = ahub_resource,
1204         .num_resources  = ARRAY_SIZE(ahub_resource),
1205 };
1206
1207 static struct resource dam_resource0[] = {
1208         [0] = {
1209                 .start = TEGRA_DAM0_BASE,
1210                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1211                 .flags = IORESOURCE_MEM
1212         }
1213 };
1214
1215 struct platform_device tegra_dam_device0 = {
1216         .name = "tegra30-dam",
1217         .id = 0,
1218         .resource      = dam_resource0,
1219         .num_resources = ARRAY_SIZE(dam_resource0),
1220 };
1221
1222 static struct resource dam_resource1[] = {
1223         [0] = {
1224                 .start = TEGRA_DAM1_BASE,
1225                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1226                 .flags = IORESOURCE_MEM
1227         }
1228 };
1229
1230 struct platform_device tegra_dam_device1 = {
1231         .name = "tegra30-dam",
1232         .id = 1,
1233         .resource      = dam_resource1,
1234         .num_resources = ARRAY_SIZE(dam_resource1),
1235 };
1236
1237 static struct resource dam_resource2[] = {
1238         [0] = {
1239                 .start = TEGRA_DAM2_BASE,
1240                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1241                 .flags = IORESOURCE_MEM
1242         }
1243 };
1244
1245 struct platform_device tegra_dam_device2 = {
1246         .name = "tegra30-dam",
1247         .id = 2,
1248         .resource      = dam_resource2,
1249         .num_resources = ARRAY_SIZE(dam_resource2),
1250 };
1251
1252 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1253 static struct resource hda_platform_resources[] = {
1254         [0] = {
1255                 .start  = TEGRA_HDA_BASE,
1256                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1257                 .flags  = IORESOURCE_MEM
1258         },
1259         [1] = {
1260                 .start  = INT_HDA,
1261                 .end    = INT_HDA,
1262                 .flags  = IORESOURCE_IRQ
1263         },
1264 };
1265
1266 struct platform_device tegra_hda_device = {
1267         .name           = "tegra30-hda",
1268         .id             = -1,
1269         .dev = {
1270                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1271                 .dma_mask               = &tegra_hda_dma_mask,
1272         },
1273         .resource       = hda_platform_resources,
1274         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1275 };
1276 #endif
1277
1278 struct platform_device spdif_dit_device = {
1279         .name = "spdif-dit",
1280         .id = 0,
1281 };
1282
1283 struct platform_device bluetooth_dit_device = {
1284         .name = "spdif-dit",
1285         .id = 1,
1286 };
1287
1288 struct platform_device baseband_dit_device = {
1289         .name = "spdif-dit",
1290         .id = 2,
1291 };
1292
1293 struct platform_device tegra_tdm_pcm_device = {
1294         .name = "tegra-tdm-pcm-audio",
1295         .id = -1,
1296 };
1297
1298 static struct resource w1_resources[] = {
1299         [0] = {
1300                 .start = INT_OWR,
1301                 .end   = INT_OWR,
1302                 .flags = IORESOURCE_IRQ
1303         },
1304         [1] = {
1305                 .start = TEGRA_OWR_BASE,
1306                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1307                 .flags = IORESOURCE_MEM
1308         }
1309 };
1310
1311 struct platform_device tegra_w1_device = {
1312         .name          = "tegra_w1",
1313         .id            = -1,
1314         .resource      = w1_resources,
1315         .num_resources = ARRAY_SIZE(w1_resources),
1316 };
1317
1318 static struct resource tegra_udc_resources[] = {
1319         [0] = {
1320                 .start  = TEGRA_USB_BASE,
1321                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1322                 .flags  = IORESOURCE_MEM,
1323         },
1324         [1] = {
1325                 .start  = INT_USB,
1326                 .end    = INT_USB,
1327                 .flags  = IORESOURCE_IRQ,
1328         },
1329 };
1330
1331 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1332
1333 struct platform_device tegra_udc_device = {
1334         .name   = "tegra-udc",
1335         .id     = 0,
1336         .dev    = {
1337                 .dma_mask       = &tegra_udc_dmamask,
1338                 .coherent_dma_mask = DMA_BIT_MASK(32),
1339         },
1340         .resource = tegra_udc_resources,
1341         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1342 };
1343
1344 static struct resource tegra_otg_resources[] = {
1345         [0] = {
1346                 .start  = TEGRA_USB_BASE,
1347                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1348                 .flags  = IORESOURCE_MEM,
1349         },
1350         [1] = {
1351                 .start  = INT_USB,
1352                 .end    = INT_USB,
1353                 .flags  = IORESOURCE_IRQ,
1354         },
1355 };
1356
1357 struct platform_device tegra_otg_device = {
1358         .name           = "tegra-otg",
1359         .id             = -1,
1360         .resource       = tegra_otg_resources,
1361         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1362 };
1363
1364 #ifdef CONFIG_SATA_AHCI_TEGRA
1365 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1366
1367 static struct resource tegra_sata_resources[] = {
1368         [0] = {
1369                 .start = TEGRA_SATA_BAR5_BASE,
1370                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1371                 .flags = IORESOURCE_MEM,
1372         },
1373         [1] = {
1374                 .start = TEGRA_SATA_CONFIG_BASE,
1375                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1376                 .flags = IORESOURCE_MEM,
1377         },
1378         [2] = {
1379                 .start = INT_SATA_CTL,
1380                 .end = INT_SATA_CTL,
1381                 .flags = IORESOURCE_IRQ,
1382         },
1383 };
1384
1385 struct platform_device tegra_sata_device = {
1386         .name   = "tegra-sata",
1387         .id     = 0,
1388         .dev    = {
1389                 .platform_data = 0,
1390                 .coherent_dma_mask = DMA_BIT_MASK(32),
1391                 .dma_mask = &tegra_sata_dma_mask,
1392         },
1393         .resource = tegra_sata_resources,
1394         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1395 };
1396 #endif
1397
1398 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1399 static struct resource das_resource[] = {
1400         [0] = {
1401                 .start  = TEGRA_APB_MISC_DAS_BASE,
1402                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1403                 .flags  = IORESOURCE_MEM
1404         }
1405 };
1406
1407 struct platform_device tegra_das_device = {
1408         .name           = "tegra20-das",
1409         .id             = -1,
1410         .resource       = das_resource,
1411         .num_resources  = ARRAY_SIZE(das_resource),
1412 };
1413 #endif
1414
1415 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1416 static struct resource tegra_gart_resources[] = {
1417         [0] = {
1418                 .name   = "mc",
1419                 .flags  = IORESOURCE_MEM,
1420                 .start  = TEGRA_MC_BASE,
1421                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1422         },
1423         [1] = {
1424                 .name   = "gart",
1425                 .flags  = IORESOURCE_MEM,
1426                 .start  = TEGRA_GART_BASE,
1427                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1428         }
1429 };
1430
1431 struct platform_device tegra_gart_device = {
1432         .name           = "tegra_gart",
1433         .id             = -1,
1434         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1435         .resource       = tegra_gart_resources
1436 };
1437 #endif
1438
1439 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
1440 static struct resource tegra_smmu_resources[] = {
1441         [0] = {
1442                 .name   = "mc",
1443                 .flags  = IORESOURCE_MEM,
1444                 .start  = TEGRA_MC_BASE,
1445                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1446         },
1447         [1] = {
1448                 .name   = "ahbarb",
1449                 .flags  = IORESOURCE_MEM,
1450                 .start  = TEGRA_AHB_ARB_BASE,
1451                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1452         }
1453 };
1454
1455 struct platform_device tegra_smmu_device = {
1456         .name           = "tegra_smmu",
1457         .id             = -1,
1458         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1459         .resource       = tegra_smmu_resources
1460 };
1461
1462
1463 static struct tegra_smmu_window tegra_smmu[] = {
1464         [0] = {
1465                 .start  = TEGRA_SMMU_BASE,
1466                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1467         },
1468 };
1469
1470 struct tegra_smmu_window *tegra_smmu_window(int wnum)
1471 {
1472         return &tegra_smmu[wnum];
1473 }
1474
1475 int tegra_smmu_window_count(void)
1476 {
1477         return ARRAY_SIZE(tegra_smmu);
1478 }
1479 #endif
1480
1481 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1482 #define CLK_RESET_RST_SOURCE    0x0
1483 static struct resource tegra_wdt_resources[] = {
1484         [0] = {
1485                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1486                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1487                 .flags  = IORESOURCE_MEM,
1488         },
1489         [1] = {
1490                 .start  = TEGRA_TMR1_BASE,
1491                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1492                 .flags  = IORESOURCE_MEM,
1493         },
1494         [2] = {
1495                 .start  = INT_TMR1,
1496                 .end    = INT_TMR1,
1497                 .flags  = IORESOURCE_IRQ,
1498         },
1499 };
1500 #else
1501 static struct resource tegra_wdt_resources[] = {
1502         [0] = {
1503                 .start  = TEGRA_WDT0_BASE,
1504                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1505                 .flags  = IORESOURCE_MEM,
1506         },
1507         [1] = {
1508                 .start  = TEGRA_TMR10_BASE,
1509                 .end    = TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
1510                 .flags  = IORESOURCE_MEM,
1511         },
1512         [2] = {
1513                 .start  = INT_WDT_CPU,
1514                 .end    = INT_WDT_CPU,
1515                 .flags  = IORESOURCE_IRQ,
1516         },
1517 };
1518 #endif
1519
1520 struct platform_device tegra_wdt_device = {
1521         .name           = "tegra_wdt",
1522         .id             = -1,
1523         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1524         .resource       = tegra_wdt_resources,
1525 };
1526
1527 static struct resource tegra_pwfm_resource = {
1528         .start  = TEGRA_PWFM_BASE,
1529         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
1530         .flags  = IORESOURCE_MEM,
1531 };
1532
1533 struct platform_device tegra_pwfm_device = {
1534         .name           = "tegra-pwm",
1535         .id             = 0,
1536         .num_resources  = 1,
1537         .resource       = &tegra_pwfm_resource,
1538 };
1539
1540 static struct tegra_avp_platform_data tegra_avp_pdata = {
1541 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1542         .emc_clk_rate = ULONG_MAX,
1543 #else
1544         .emc_clk_rate = 200000000,
1545 #endif
1546 };
1547
1548 struct resource tegra_nvavp_resources[] = {
1549         [0] = {
1550                 .start  = INT_SHR_SEM_INBOX_IBF,
1551                 .end    = INT_SHR_SEM_INBOX_IBF,
1552                 .flags  = IORESOURCE_IRQ,
1553                 .name   = "mbox_from_nvavp_pending",
1554         },
1555 };
1556
1557 struct nvhost_device nvavp_device = {
1558         .name           = "nvavp",
1559         .id             = -1,
1560         .resource       = tegra_nvavp_resources,
1561         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
1562 };
1563
1564 static struct resource tegra_avp_resources[] = {
1565         [0] = {
1566                 .start  = INT_SHR_SEM_INBOX_IBF,
1567                 .end    = INT_SHR_SEM_INBOX_IBF,
1568                 .flags  = IORESOURCE_IRQ,
1569                 .name   = "mbox_from_avp_pending",
1570         },
1571 };
1572
1573 struct platform_device tegra_avp_device = {
1574         .name           = "tegra-avp",
1575         .id             = -1,
1576         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1577         .resource       = tegra_avp_resources,
1578         .dev  = {
1579                 .coherent_dma_mask      = 0xffffffffULL,
1580                 .platform_data          = &tegra_avp_pdata,
1581         },
1582 };
1583
1584 static struct resource tegra_aes_resources[] = {
1585         {
1586                 .start  = TEGRA_VDE_BASE,
1587                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1588                 .flags  = IORESOURCE_MEM,
1589         },
1590         {
1591                 .start  = TEGRA_BSEA_BASE,
1592                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1593                 .flags  = IORESOURCE_MEM,
1594         },
1595         {
1596                 .start  = INT_VDE_BSE_V,
1597                 .end    = INT_VDE_BSE_V,
1598                 .flags  = IORESOURCE_IRQ,
1599         },
1600         {
1601                 .start  = INT_VDE_BSE_A,
1602                 .end    = INT_VDE_BSE_A,
1603                 .flags  = IORESOURCE_IRQ,
1604         },
1605 };
1606
1607 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1608
1609 struct platform_device tegra_aes_device = {
1610         .name           = "tegra-aes",
1611         .id             = -1,
1612         .resource       = tegra_aes_resources,
1613         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1614         .dev    = {
1615                 .dma_mask = &tegra_aes_dma_mask,
1616                 .coherent_dma_mask = DMA_BIT_MASK(32),
1617         },
1618 };
1619
1620 static struct resource tegra_kbc_resources[] = {
1621         [0] = {
1622                 .start = TEGRA_KBC_BASE,
1623                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1624                 .flags = IORESOURCE_MEM,
1625         },
1626         [1] = {
1627                 .start = INT_KBC,
1628                 .end   = INT_KBC,
1629                 .flags = IORESOURCE_IRQ,
1630         },
1631 };
1632
1633 struct platform_device tegra_kbc_device = {
1634         .name = "tegra-kbc",
1635         .id = -1,
1636         .resource = tegra_kbc_resources,
1637         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1638         .dev = {
1639                 .platform_data = 0,
1640         },
1641 };
1642
1643 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1644 static struct resource tegra_tsensor_resources[]= {
1645         {
1646                 .start  = TEGRA_TSENSOR_BASE,
1647                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1648                 .flags  = IORESOURCE_MEM,
1649         },
1650         {
1651                 .start  = INT_TSENSOR,
1652                 .end    = INT_TSENSOR,
1653                 .flags  = IORESOURCE_IRQ,
1654         },
1655         {
1656                 .start  = TEGRA_PMC_BASE + 0x1B0,
1657                 /* 2 pmc registers mapped */
1658                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
1659                 .flags  = IORESOURCE_MEM,
1660         },
1661 };
1662
1663 struct platform_device tegra_tsensor_device = {
1664         .name   = "tegra-tsensor",
1665         .id     = -1,
1666         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
1667         .resource       = tegra_tsensor_resources,
1668         .dev = {
1669                 .platform_data = 0,
1670         },
1671 };
1672 #endif
1673
1674 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1675 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
1676
1677 struct resource tegra_se_resources[] = {
1678         [0] = {
1679                 .start = TEGRA_SE_BASE,
1680                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
1681                 .flags = IORESOURCE_MEM,
1682         },
1683         [1] = {
1684                 .start  = TEGRA_PMC_BASE,
1685                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
1686                 .flags  = IORESOURCE_MEM,
1687         },
1688         [2] = {
1689                 .start = INT_SE,
1690                 .end = INT_SE,
1691                 .flags = IORESOURCE_IRQ,
1692         },
1693 };
1694
1695 struct platform_device tegra_se_device = {
1696         .name = "tegra-se",
1697         .id = -1,
1698         .dev = {
1699                 .coherent_dma_mask = DMA_BIT_MASK(32),
1700                 .dma_mask = &tegra_se_dma_mask,
1701         },
1702         .resource = tegra_se_resources,
1703         .num_resources = ARRAY_SIZE(tegra_se_resources),
1704 };
1705 #endif
1706
1707 static struct resource tegra_disp1_resources[] = {
1708         {
1709                 .name   = "irq",
1710                 .start  = INT_DISPLAY_GENERAL,
1711                 .end    = INT_DISPLAY_GENERAL,
1712                 .flags  = IORESOURCE_IRQ,
1713         },
1714         {
1715                 .name   = "regs",
1716                 .start  = TEGRA_DISPLAY_BASE,
1717                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
1718                 .flags  = IORESOURCE_MEM,
1719         },
1720         {
1721                 .name   = "fbmem",
1722                 .start  = 0,
1723                 .end    = 0,
1724                 .flags  = IORESOURCE_MEM,
1725         },
1726         {
1727                 .name   = "dsi_regs",
1728                 .start  = TEGRA_DSI_BASE,
1729                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
1730                 .flags  = IORESOURCE_MEM,
1731         },
1732 };
1733
1734 struct nvhost_device tegra_disp1_device = {
1735         .name           = "tegradc",
1736         .id             = 0,
1737         .resource       = tegra_disp1_resources,
1738         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
1739 };
1740
1741 struct platform_device tegra_nvmap_device = {
1742         .name   = "tegra-nvmap",
1743         .id     = -1,
1744 };
1745
1746 void __init tegra_init_debug_uart_rate(void)
1747 {
1748         unsigned int uartclk;
1749         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
1750
1751         BUG_ON(IS_ERR(debug_uart_parent));
1752         uartclk = clk_get_rate(debug_uart_parent);
1753
1754         debug_uarta_platform_data[0].uartclk = uartclk;
1755         debug_uartb_platform_data[0].uartclk = uartclk;
1756         debug_uartc_platform_data[0].uartclk = uartclk;
1757         debug_uartd_platform_data[0].uartclk = uartclk;
1758 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1759         debug_uarte_platform_data[0].uartclk = uartclk;
1760 #endif
1761 }