ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/mipi-bif-tegra.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/tegra_avp.h>
30 #include <linux/nvhost.h>
31 #include <linux/clk.h>
32 #include <linux/tegra-soc.h>
33 #include <mach/irqs.h>
34 #include <linux/usb/tegra_usb_phy.h>
35 #include <mach/tegra_smmu.h>
36 #include <mach/tegra-swgid.h>
37 #include <linux/dma-contiguous.h>
38
39 #ifdef CONFIG_TEGRA_WAKEUP_MONITOR
40 #include <mach/tegra_wakeup_monitor.h>
41 #endif
42
43 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
44 #include <asm/dma-iommu.h>
45 #endif
46
47 #include "gpio-names.h"
48 #include "iomap.h"
49 #include "devices.h"
50 #include "board.h"
51 #include "tegra_ptm.h"
52
53 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
54 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
55 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
56 #define TEGRA_DMA_REQ_SEL_SPI                   11
57 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
58
59 static struct resource emc_resource[] = {
60         [0] = {
61                 .start  = TEGRA_EMC_BASE,
62                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
63                 .flags  = IORESOURCE_MEM,
64         }
65 };
66
67 struct platform_device tegra_emc_device = {
68         .name           = "tegra-emc",
69         .id             = -1,
70         .resource       = emc_resource,
71         .num_resources  = ARRAY_SIZE(emc_resource),
72 };
73
74 static struct resource gpio_resource[] = {
75         [0] = {
76                 .start  = TEGRA_GPIO_BASE,
77                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
78                 .flags  = IORESOURCE_MEM,
79         },
80         [1] = {
81                 .start  = INT_GPIO1,
82                 .end    = INT_GPIO1,
83                 .flags  = IORESOURCE_IRQ,
84         },
85         [2] = {
86                 .start  = INT_GPIO2,
87                 .end    = INT_GPIO2,
88                 .flags  = IORESOURCE_IRQ,
89         },
90         [3] = {
91                 .start  = INT_GPIO3,
92                 .end    = INT_GPIO3,
93                 .flags  = IORESOURCE_IRQ,
94         },
95         [4] = {
96                 .start  = INT_GPIO4,
97                 .end    = INT_GPIO4,
98                 .flags  = IORESOURCE_IRQ,
99         },
100         [5] = {
101                 .start  = INT_GPIO5,
102                 .end    = INT_GPIO5,
103                 .flags  = IORESOURCE_IRQ,
104         },
105         [6] = {
106                 .start  = INT_GPIO6,
107                 .end    = INT_GPIO6,
108                 .flags  = IORESOURCE_IRQ,
109         },
110         [7] = {
111                 .start  = INT_GPIO7,
112                 .end    = INT_GPIO7,
113                 .flags  = IORESOURCE_IRQ,
114         },
115 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
116         [8] = {
117                 .start  = INT_GPIO8,
118                 .end    = INT_GPIO8,
119                 .flags  = IORESOURCE_IRQ,
120         },
121 #endif
122 };
123
124 struct platform_device tegra_gpio_device = {
125         .name           = "tegra-gpio",
126         .id             = -1,
127         .resource       = gpio_resource,
128         .num_resources  = ARRAY_SIZE(gpio_resource),
129 };
130
131 static struct resource tegra124_pinctrl_resource[] = {
132         [0] = {
133                 /* Drive registers */
134                 .start  = TEGRA_APB_MISC_BASE + 0x868,
135                 .end    = TEGRA_APB_MISC_BASE + 0x9c8 + 3,
136                 .flags  = IORESOURCE_MEM,
137         },
138         [1] = {
139                 /* Mux registers */
140                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
141                 .end    = TEGRA_APB_MISC_BASE + 0x3430 + 3,
142                 .flags  = IORESOURCE_MEM,
143         },
144 };
145
146 struct platform_device tegra124_pinctrl_device = {
147         .name           = "tegra124-pinctrl",
148         .id             = -1,
149         .resource       = tegra124_pinctrl_resource,
150         .num_resources  = ARRAY_SIZE(tegra124_pinctrl_resource),
151 };
152
153 static struct resource tegra114_pinctrl_resource[] = {
154         [0] = {
155                 /* Drive registers */
156                 .start  = TEGRA_APB_MISC_BASE + 0x868,
157                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
158                 .flags  = IORESOURCE_MEM,
159         },
160         [1] = {
161                 /* Mux registers */
162                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
163                 .end    = TEGRA_APB_MISC_BASE + 0x3408 + 3,
164                 .flags  = IORESOURCE_MEM,
165         },
166 };
167
168 struct platform_device tegra114_pinctrl_device = {
169         .name           = "tegra114-pinctrl",
170         .id             = -1,
171         .resource       = tegra114_pinctrl_resource,
172         .num_resources  = ARRAY_SIZE(tegra114_pinctrl_resource),
173 };
174
175 static struct resource apbdma_resource[] = {
176         [0] = {
177                 .start  = TEGRA_APB_DMA_BASE,
178                 .end    = TEGRA_APB_DMA_BASE + TEGRA_APB_DMA_SIZE-1,
179                 .flags  = IORESOURCE_MEM,
180         },
181         [1] = {
182                 .start  = INT_APB_DMA_CH0,
183                 .end    = INT_APB_DMA_CH0,
184                 .flags  = IORESOURCE_IRQ,
185         },
186         [2] = {
187                 .start  = INT_APB_DMA_CH1,
188                 .end    = INT_APB_DMA_CH1,
189                 .flags  = IORESOURCE_IRQ,
190         },
191         [3] = {
192                 .start  = INT_APB_DMA_CH2,
193                 .end    = INT_APB_DMA_CH2,
194                 .flags  = IORESOURCE_IRQ,
195         },
196         [4] = {
197                 .start  = INT_APB_DMA_CH3,
198                 .end    = INT_APB_DMA_CH3,
199                 .flags  = IORESOURCE_IRQ,
200         },
201         [5] = {
202                 .start  = INT_APB_DMA_CH4,
203                 .end    = INT_APB_DMA_CH4,
204                 .flags  = IORESOURCE_IRQ,
205         },
206         [6] = {
207                 .start  = INT_APB_DMA_CH5,
208                 .end    = INT_APB_DMA_CH5,
209                 .flags  = IORESOURCE_IRQ,
210         },
211         [7] = {
212                 .start  = INT_APB_DMA_CH6,
213                 .end    = INT_APB_DMA_CH6,
214                 .flags  = IORESOURCE_IRQ,
215         },
216         [8] = {
217                 .start  = INT_APB_DMA_CH7,
218                 .end    = INT_APB_DMA_CH7,
219                 .flags  = IORESOURCE_IRQ,
220         },
221         [9] = {
222                 .start  = INT_APB_DMA_CH8,
223                 .end    = INT_APB_DMA_CH8,
224                 .flags  = IORESOURCE_IRQ,
225         },
226         [10] = {
227                 .start  = INT_APB_DMA_CH9,
228                 .end    = INT_APB_DMA_CH9,
229                 .flags  = IORESOURCE_IRQ,
230         },
231         [11] = {
232                 .start  = INT_APB_DMA_CH10,
233                 .end    = INT_APB_DMA_CH10,
234                 .flags  = IORESOURCE_IRQ,
235         },
236         [12] = {
237                 .start  = INT_APB_DMA_CH11,
238                 .end    = INT_APB_DMA_CH11,
239                 .flags  = IORESOURCE_IRQ,
240         },
241         [13] = {
242                 .start  = INT_APB_DMA_CH12,
243                 .end    = INT_APB_DMA_CH12,
244                 .flags  = IORESOURCE_IRQ,
245         },
246         [14] = {
247                 .start  = INT_APB_DMA_CH13,
248                 .end    = INT_APB_DMA_CH13,
249                 .flags  = IORESOURCE_IRQ,
250         },
251         [15] = {
252                 .start  = INT_APB_DMA_CH14,
253                 .end    = INT_APB_DMA_CH14,
254                 .flags  = IORESOURCE_IRQ,
255         },
256         [16] = {
257                 .start  = INT_APB_DMA_CH15,
258                 .end    = INT_APB_DMA_CH15,
259                 .flags  = IORESOURCE_IRQ,
260         },
261         [17] = {
262                 .start  = INT_APB_DMA_CH16,
263                 .end    = INT_APB_DMA_CH16,
264                 .flags  = IORESOURCE_IRQ,
265         },
266         [18] = {
267                 .start  = INT_APB_DMA_CH17,
268                 .end    = INT_APB_DMA_CH17,
269                 .flags  = IORESOURCE_IRQ,
270         },
271         [19] = {
272                 .start  = INT_APB_DMA_CH18,
273                 .end    = INT_APB_DMA_CH18,
274                 .flags  = IORESOURCE_IRQ,
275         },
276         [20] = {
277                 .start  = INT_APB_DMA_CH19,
278                 .end    = INT_APB_DMA_CH19,
279                 .flags  = IORESOURCE_IRQ,
280         },
281         [21] = {
282                 .start  = INT_APB_DMA_CH20,
283                 .end    = INT_APB_DMA_CH20,
284                 .flags  = IORESOURCE_IRQ,
285         },
286         [22] = {
287                 .start  = INT_APB_DMA_CH21,
288                 .end    = INT_APB_DMA_CH21,
289                 .flags  = IORESOURCE_IRQ,
290         },
291         [23] = {
292                 .start  = INT_APB_DMA_CH22,
293                 .end    = INT_APB_DMA_CH22,
294                 .flags  = IORESOURCE_IRQ,
295         },
296         [24] = {
297                 .start  = INT_APB_DMA_CH23,
298                 .end    = INT_APB_DMA_CH23,
299                 .flags  = IORESOURCE_IRQ,
300         },
301         [25] = {
302                 .start  = INT_APB_DMA_CH24,
303                 .end    = INT_APB_DMA_CH24,
304                 .flags  = IORESOURCE_IRQ,
305         },
306         [26] = {
307                 .start  = INT_APB_DMA_CH25,
308                 .end    = INT_APB_DMA_CH25,
309                 .flags  = IORESOURCE_IRQ,
310         },
311         [27] = {
312                 .start  = INT_APB_DMA_CH26,
313                 .end    = INT_APB_DMA_CH26,
314                 .flags  = IORESOURCE_IRQ,
315         },
316         [28] = {
317                 .start  = INT_APB_DMA_CH27,
318                 .end    = INT_APB_DMA_CH27,
319                 .flags  = IORESOURCE_IRQ,
320         },
321         [29] = {
322                 .start  = INT_APB_DMA_CH28,
323                 .end    = INT_APB_DMA_CH28,
324                 .flags  = IORESOURCE_IRQ,
325         },
326         [30] = {
327                 .start  = INT_APB_DMA_CH29,
328                 .end    = INT_APB_DMA_CH29,
329                 .flags  = IORESOURCE_IRQ,
330         },
331         [31] = {
332                 .start  = INT_APB_DMA_CH30,
333                 .end    = INT_APB_DMA_CH30,
334                 .flags  = IORESOURCE_IRQ,
335         },
336         [32] = {
337                 .start  = INT_APB_DMA_CH31,
338                 .end    = INT_APB_DMA_CH31,
339                 .flags  = IORESOURCE_IRQ,
340         },
341
342 };
343
344 struct platform_device tegra_apbdma = {
345         .name           = "tegra124-apbdma",
346         .id             = -1,
347         .resource       = apbdma_resource,
348         .num_resources  = ARRAY_SIZE(apbdma_resource),
349 };
350
351 static struct resource i2c_resource1[] = {
352         [0] = {
353                 .start  = INT_I2C,
354                 .end    = INT_I2C,
355                 .flags  = IORESOURCE_IRQ,
356         },
357         [1] = {
358                 .start  = TEGRA_I2C_BASE,
359                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
360                 .flags  = IORESOURCE_MEM,
361         },
362 };
363
364 static struct resource i2c_resource2[] = {
365         [0] = {
366                 .start  = INT_I2C2,
367                 .end    = INT_I2C2,
368                 .flags  = IORESOURCE_IRQ,
369         },
370         [1] = {
371                 .start  = TEGRA_I2C2_BASE,
372                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
373                 .flags  = IORESOURCE_MEM,
374         },
375 };
376
377 static struct resource i2c_resource3[] = {
378         [0] = {
379                 .start  = INT_I2C3,
380                 .end    = INT_I2C3,
381                 .flags  = IORESOURCE_IRQ,
382         },
383         [1] = {
384                 .start  = TEGRA_I2C3_BASE,
385                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
386                 .flags  = IORESOURCE_MEM,
387         },
388 };
389
390 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
391 static struct resource i2c_resource4[] = {
392         [0] = {
393                 .start  = INT_DVC,
394                 .end    = INT_DVC,
395                 .flags  = IORESOURCE_IRQ,
396         },
397         [1] = {
398                 .start  = TEGRA_DVC_BASE,
399                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
400                 .flags  = IORESOURCE_MEM,
401         },
402 };
403
404 #else
405 static struct resource i2c_resource4[] = {
406         [0] = {
407                 .start  = INT_I2C4,
408                 .end    = INT_I2C4,
409                 .flags  = IORESOURCE_IRQ,
410         },
411         [1] = {
412                 .start  = TEGRA_I2C4_BASE,
413                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
414                 .flags  = IORESOURCE_MEM,
415         },
416 };
417
418 static struct resource i2c_resource5[] = {
419         [0] = {
420                 .start  = INT_I2C5,
421                 .end    = INT_I2C5,
422                 .flags  = IORESOURCE_IRQ,
423         },
424         [1] = {
425                 .start  = TEGRA_I2C5_BASE,
426                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
427                 .flags  = IORESOURCE_MEM,
428         },
429 };
430 #endif
431
432 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
433 static struct resource i2c_resource6[] = {
434         [0] = {
435                 .start  = INT_I2C6,
436                 .end    = INT_I2C6,
437                 .flags  = IORESOURCE_IRQ,
438         },
439         [1] = {
440                 .start  = TEGRA_I2C6_BASE,
441                 .end    = TEGRA_I2C6_BASE + TEGRA_I2C6_SIZE-1,
442                 .flags  = IORESOURCE_MEM,
443         },
444 };
445 #endif
446
447 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
448         .bus_clk_rate   = 400000,
449 };
450
451 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
452         .bus_clk_rate   = 400000,
453 };
454
455 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
456         .bus_clk_rate   = 400000,
457 };
458
459 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
460         .bus_clk_rate   = 400000,
461 };
462
463 struct platform_device tegra_i2c_device1 = {
464         .name           = "tegra-i2c",
465         .id             = 0,
466         .resource       = i2c_resource1,
467         .num_resources  = ARRAY_SIZE(i2c_resource1),
468         .dev = {
469                 .platform_data = &tegra_i2c1_platform_data,
470         },
471 };
472
473 struct platform_device tegra_i2c_device2 = {
474         .name           = "tegra-i2c",
475         .id             = 1,
476         .resource       = i2c_resource2,
477         .num_resources  = ARRAY_SIZE(i2c_resource2),
478         .dev = {
479                 .platform_data = &tegra_i2c2_platform_data,
480         },
481 };
482
483 struct platform_device tegra_i2c_device3 = {
484         .name           = "tegra-i2c",
485         .id             = 2,
486         .resource       = i2c_resource3,
487         .num_resources  = ARRAY_SIZE(i2c_resource3),
488         .dev = {
489                 .platform_data = &tegra_i2c3_platform_data,
490         },
491 };
492
493 struct platform_device tegra_i2c_device4 = {
494         .name           = "tegra-i2c",
495         .id             = 3,
496         .resource       = i2c_resource4,
497         .num_resources  = ARRAY_SIZE(i2c_resource4),
498         .dev = {
499                 .platform_data = &tegra_dvc_platform_data,
500         },
501 };
502
503 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
504 struct platform_device tegra_i2c_device5 = {
505         .name           = "tegra-i2c",
506         .id             = 4,
507         .resource       = i2c_resource5,
508         .num_resources  = ARRAY_SIZE(i2c_resource5),
509         .dev = {
510                 .platform_data = 0,
511         },
512 };
513 #endif
514
515 struct platform_device tegra11_i2c_device1 = {
516         .name           = "tegra11-i2c",
517         .id             = 0,
518         .resource       = i2c_resource1,
519         .num_resources  = ARRAY_SIZE(i2c_resource1),
520         .dev = {
521                 .platform_data = 0,
522         },
523 };
524
525 struct platform_device tegra11_i2c_device2 = {
526         .name           = "tegra11-i2c",
527         .id             = 1,
528         .resource       = i2c_resource2,
529         .num_resources  = ARRAY_SIZE(i2c_resource2),
530         .dev = {
531                 .platform_data = 0,
532         },
533 };
534
535 struct platform_device tegra11_i2c_device3 = {
536         .name           = "tegra11-i2c",
537         .id             = 2,
538         .resource       = i2c_resource3,
539         .num_resources  = ARRAY_SIZE(i2c_resource3),
540         .dev = {
541                 .platform_data = 0,
542         },
543 };
544
545 struct platform_device tegra11_i2c_device4 = {
546         .name           = "tegra11-i2c",
547         .id             = 3,
548         .resource       = i2c_resource4,
549         .num_resources  = ARRAY_SIZE(i2c_resource4),
550         .dev = {
551                 .platform_data = 0,
552         },
553 };
554
555 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
556 struct platform_device tegra11_i2c_device5 = {
557         .name           = "tegra11-i2c",
558         .id             = 4,
559         .resource       = i2c_resource5,
560         .num_resources  = ARRAY_SIZE(i2c_resource5),
561         .dev = {
562                 .platform_data = 0,
563         },
564 };
565 #endif
566
567 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
568
569 struct platform_device tegra14_i2c_device1 = {
570         .name           = "tegra14-i2c",
571         .id             = 0,
572         .resource       = i2c_resource1,
573         .num_resources  = ARRAY_SIZE(i2c_resource1),
574         .dev = {
575                 .platform_data = 0,
576         },
577 };
578
579 struct platform_device tegra14_i2c_device2 = {
580         .name           = "tegra14-i2c",
581         .id             = 1,
582         .resource       = i2c_resource2,
583         .num_resources  = ARRAY_SIZE(i2c_resource2),
584         .dev = {
585                 .platform_data = 0,
586         },
587 };
588
589 struct platform_device tegra14_i2c_device3 = {
590         .name           = "tegra14-i2c",
591         .id             = 2,
592         .resource       = i2c_resource3,
593         .num_resources  = ARRAY_SIZE(i2c_resource3),
594         .dev = {
595                 .platform_data = 0,
596         },
597 };
598
599 struct platform_device tegra14_i2c_device4 = {
600         .name           = "tegra14-i2c",
601         .id             = 3,
602         .resource       = i2c_resource4,
603         .num_resources  = ARRAY_SIZE(i2c_resource4),
604         .dev = {
605                 .platform_data = 0,
606         },
607 };
608
609 struct platform_device tegra14_i2c_device5 = {
610         .name           = "tegra14-i2c",
611         .id             = 4,
612         .resource       = i2c_resource5,
613         .num_resources  = ARRAY_SIZE(i2c_resource5),
614         .dev = {
615                 .platform_data = 0,
616         },
617 };
618
619 struct platform_device tegra14_i2c_device6 = {
620         .name           = "tegra14-i2c",
621         .id             = 5,
622         .resource       = i2c_resource6,
623         .num_resources  = ARRAY_SIZE(i2c_resource6),
624         .dev = {
625                 .platform_data = 0,
626         },
627 };
628
629 #endif
630
631 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
632 struct platform_device tegra12_i2c_device1 = {
633         .name           = "tegra12-i2c",
634         .id             = 0,
635         .resource       = i2c_resource1,
636         .num_resources  = ARRAY_SIZE(i2c_resource1),
637         .dev = {
638                 .platform_data = 0,
639         },
640 };
641
642 struct platform_device tegra12_i2c_device2 = {
643         .name           = "tegra12-i2c",
644         .id             = 1,
645         .resource       = i2c_resource2,
646         .num_resources  = ARRAY_SIZE(i2c_resource2),
647         .dev = {
648                 .platform_data = 0,
649         },
650 };
651
652 struct platform_device tegra12_i2c_device3 = {
653         .name           = "tegra12-i2c",
654         .id             = 2,
655         .resource       = i2c_resource3,
656         .num_resources  = ARRAY_SIZE(i2c_resource3),
657         .dev = {
658                 .platform_data = 0,
659         },
660 };
661
662 struct platform_device tegra12_i2c_device4 = {
663         .name           = "tegra12-i2c",
664         .id             = 3,
665         .resource       = i2c_resource4,
666         .num_resources  = ARRAY_SIZE(i2c_resource4),
667         .dev = {
668                 .platform_data = 0,
669         },
670 };
671
672 struct platform_device tegra12_i2c_device5 = {
673         .name           = "tegra12-i2c",
674         .id             = 4,
675         .resource       = i2c_resource5,
676         .num_resources  = ARRAY_SIZE(i2c_resource5),
677         .dev = {
678                 .platform_data = 0,
679         },
680 };
681
682 struct platform_device tegra12_i2c_device6 = {
683         .name           = "tegra12-i2c",
684         .id             = 5,
685         .resource       = i2c_resource6,
686         .num_resources  = ARRAY_SIZE(i2c_resource6),
687         .dev = {
688                 .platform_data = 0,
689         },
690 };
691 #endif
692
693 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
694
695 static struct tegra_mipi_bif_platform_data mipi_bif_pdata = {
696         .adapter_nr     = -1,
697         .tauBIF         = 2,
698         .bus_clk_rate   = 13,
699 };
700
701 static struct resource mipi_bif_resource[] = {
702         [0] = {
703                 .start  = INT_MIPI_BIF,
704                 .end    = INT_MIPI_BIF,
705                 .flags  = IORESOURCE_IRQ,
706         },
707         [1] = {
708                 .start  = TEGRA_MIPI_BIF_BASE,
709                 .end    = TEGRA_MIPI_BIF_BASE + TEGRA_MIPI_BIF_SIZE - 1,
710                 .flags  = IORESOURCE_MEM,
711         },
712 };
713
714 struct platform_device tegra_mipi_bif_device = {
715         .name           = "tegra-mipi-bif",
716         .id             = -1,
717         .resource       = mipi_bif_resource,
718         .num_resources  = ARRAY_SIZE(mipi_bif_resource),
719         .dev = {
720                 .platform_data = &mipi_bif_pdata,
721         },
722 };
723
724 #endif
725
726 static struct resource spi_resource1[] = {
727         [0] = {
728                 .start  = INT_SPI_1,
729                 .end    = INT_SPI_1,
730                 .flags  = IORESOURCE_IRQ,
731         },
732         [1] = {
733                 .start  = TEGRA_SPI1_BASE,
734                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
735                 .flags  = IORESOURCE_MEM,
736         },
737 };
738
739 static struct resource spi_resource2[] = {
740         [0] = {
741                 .start  = INT_SPI_2,
742                 .end    = INT_SPI_2,
743                 .flags  = IORESOURCE_IRQ,
744         },
745         [1] = {
746                 .start  = TEGRA_SPI2_BASE,
747                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
748                 .flags  = IORESOURCE_MEM,
749         },
750 };
751
752 static struct resource spi_resource3[] = {
753         [0] = {
754                 .start  = INT_SPI_3,
755                 .end    = INT_SPI_3,
756                 .flags  = IORESOURCE_IRQ,
757         },
758         [1] = {
759                 .start  = TEGRA_SPI3_BASE,
760                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
761                 .flags  = IORESOURCE_MEM,
762         },
763 };
764
765 static struct resource spi_resource4[] = {
766         [0] = {
767                 .start  = INT_SPI_4,
768                 .end    = INT_SPI_4,
769                 .flags  = IORESOURCE_IRQ,
770         },
771         [1] = {
772                 .start  = TEGRA_SPI4_BASE,
773                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
774                 .flags  = IORESOURCE_MEM,
775         },
776 };
777 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
778 static struct resource spi_resource5[] = {
779         [0] = {
780                 .start  = INT_SPI_5,
781                 .end    = INT_SPI_5,
782                 .flags  = IORESOURCE_IRQ,
783         },
784         [1] = {
785                 .start  = TEGRA_SPI5_BASE,
786                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
787                 .flags  = IORESOURCE_MEM,
788         },
789 };
790
791 static struct resource spi_resource6[] = {
792         [0] = {
793                 .start  = INT_SPI_6,
794                 .end    = INT_SPI_6,
795                 .flags  = IORESOURCE_IRQ,
796         },
797         [1] = {
798                 .start  = TEGRA_SPI6_BASE,
799                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
800                 .flags  = IORESOURCE_MEM,
801         },
802 };
803 #endif
804
805 struct platform_device tegra_spi_device1 = {
806         .name           = "spi_tegra",
807         .id             = 0,
808         .resource       = spi_resource1,
809         .num_resources  = ARRAY_SIZE(spi_resource1),
810         .dev            = {
811                 .coherent_dma_mask      = 0xffffffff,
812         },
813 };
814
815 struct platform_device tegra_spi_device2 = {
816         .name           = "spi_tegra",
817         .id             = 1,
818         .resource       = spi_resource2,
819         .num_resources  = ARRAY_SIZE(spi_resource2),
820         .dev            = {
821                 .coherent_dma_mask      = 0xffffffff,
822         },
823 };
824
825 struct platform_device tegra_spi_device3 = {
826         .name           = "spi_tegra",
827         .id             = 2,
828         .resource       = spi_resource3,
829         .num_resources  = ARRAY_SIZE(spi_resource3),
830         .dev            = {
831                 .coherent_dma_mask      = 0xffffffff,
832         },
833 };
834
835 struct platform_device tegra_spi_device4 = {
836         .name           = "spi_tegra",
837         .id             = 3,
838         .resource       = spi_resource4,
839         .num_resources  = ARRAY_SIZE(spi_resource4),
840         .dev            = {
841                 .coherent_dma_mask      = 0xffffffff,
842         },
843 };
844 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
845 struct platform_device tegra_spi_device5 = {
846         .name           = "spi_tegra",
847         .id             = 4,
848         .resource       = spi_resource5,
849         .num_resources  = ARRAY_SIZE(spi_resource5),
850         .dev  = {
851                 .coherent_dma_mask      = 0xffffffff,
852         },
853 };
854
855 struct platform_device tegra_spi_device6 = {
856         .name           = "spi_tegra",
857         .id             = 5,
858         .resource       = spi_resource6,
859         .num_resources  = ARRAY_SIZE(spi_resource6),
860         .dev  = {
861                 .coherent_dma_mask      = 0xffffffff,
862         },
863 };
864 #endif
865
866 struct platform_device tegra11_spi_device1 = {
867         .name           = "spi-tegra114",
868         .id             = 0,
869         .resource       = spi_resource1,
870         .num_resources  = ARRAY_SIZE(spi_resource1),
871         .dev            = {
872                 .coherent_dma_mask      = DMA_BIT_MASK(64),
873         },
874 };
875
876 struct platform_device tegra11_spi_device2 = {
877         .name           = "spi-tegra114",
878         .id             = 1,
879         .resource       = spi_resource2,
880         .num_resources  = ARRAY_SIZE(spi_resource2),
881         .dev            = {
882                 .coherent_dma_mask      = DMA_BIT_MASK(64),
883         },
884 };
885
886 struct platform_device tegra11_spi_device3 = {
887         .name           = "spi-tegra114",
888         .id             = 2,
889         .resource       = spi_resource3,
890         .num_resources  = ARRAY_SIZE(spi_resource3),
891         .dev            = {
892                 .coherent_dma_mask      = DMA_BIT_MASK(64),
893         },
894 };
895
896 struct platform_device tegra11_spi_device4 = {
897         .name           = "spi-tegra114",
898         .id             = 3,
899         .resource       = spi_resource4,
900         .num_resources  = ARRAY_SIZE(spi_resource4),
901         .dev            = {
902                 .coherent_dma_mask      = DMA_BIT_MASK(64),
903         },
904 };
905
906 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
907 struct platform_device tegra11_spi_device5 = {
908         .name           = "spi-tegra114",
909         .id             = 4,
910         .resource       = spi_resource5,
911         .num_resources  = ARRAY_SIZE(spi_resource5),
912         .dev  = {
913                 .coherent_dma_mask      = DMA_BIT_MASK(64),
914         },
915 };
916
917 struct platform_device tegra11_spi_device6 = {
918         .name           = "spi-tegra114",
919         .id             = 5,
920         .resource       = spi_resource6,
921         .num_resources  = ARRAY_SIZE(spi_resource6),
922         .dev  = {
923                 .coherent_dma_mask      = DMA_BIT_MASK(64),
924         },
925 };
926 #endif
927
928 struct platform_device tegra_spi_slave_device1 = {
929         .name           = "spi_slave_tegra",
930         .id             = 0,
931         .resource       = spi_resource1,
932         .num_resources  = ARRAY_SIZE(spi_resource1),
933         .dev  = {
934                 .coherent_dma_mask      = 0xffffffff,
935         },
936 };
937
938 struct platform_device tegra_spi_slave_device2 = {
939         .name           = "spi_slave_tegra",
940         .id             = 1,
941         .resource       = spi_resource2,
942         .num_resources  = ARRAY_SIZE(spi_resource2),
943         .dev  = {
944                 .coherent_dma_mask      = 0xffffffff,
945         },
946 };
947
948 struct platform_device tegra_spi_slave_device3 = {
949         .name           = "spi_slave_tegra",
950         .id             = 2,
951         .resource       = spi_resource3,
952         .num_resources  = ARRAY_SIZE(spi_resource3),
953         .dev  = {
954                 .coherent_dma_mask      = 0xffffffff,
955         },
956 };
957
958 struct platform_device tegra_spi_slave_device4 = {
959         .name           = "spi_slave_tegra",
960         .id             = 3,
961         .resource       = spi_resource4,
962         .num_resources  = ARRAY_SIZE(spi_resource4),
963         .dev  = {
964                 .coherent_dma_mask      = 0xffffffff,
965         },
966 };
967 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
968 struct platform_device tegra_spi_slave_device5 = {
969         .name           = "spi_slave_tegra",
970         .id             = 4,
971         .resource       = spi_resource5,
972         .num_resources  = ARRAY_SIZE(spi_resource5),
973         .dev  = {
974                 .coherent_dma_mask      = 0xffffffff,
975         },
976 };
977
978 struct platform_device tegra_spi_slave_device6 = {
979         .name           = "spi_slave_tegra",
980         .id             = 5,
981         .resource       = spi_resource6,
982         .num_resources  = ARRAY_SIZE(spi_resource6),
983         .dev  = {
984                 .coherent_dma_mask      = 0xffffffff,
985         },
986 };
987 #endif
988
989 struct platform_device tegra11_spi_slave_device1 = {
990         .name           = "tegra11-spi-slave",
991         .id             = 0,
992         .resource       = spi_resource1,
993         .num_resources  = ARRAY_SIZE(spi_resource1),
994         .dev  = {
995                 .coherent_dma_mask      = 0xffffffff,
996         },
997 };
998
999 struct platform_device tegra11_spi_slave_device2 = {
1000         .name           = "tegra11-spi-slave",
1001         .id             = 1,
1002         .resource       = spi_resource2,
1003         .num_resources  = ARRAY_SIZE(spi_resource2),
1004         .dev  = {
1005                 .coherent_dma_mask      = 0xffffffff,
1006         },
1007 };
1008
1009 struct platform_device tegra11_spi_slave_device3 = {
1010         .name           = "tegra11-spi-slave",
1011         .id             = 2,
1012         .resource       = spi_resource3,
1013         .num_resources  = ARRAY_SIZE(spi_resource3),
1014         .dev  = {
1015                 .coherent_dma_mask      = 0xffffffff,
1016         },
1017 };
1018
1019 struct platform_device tegra11_spi_slave_device4 = {
1020         .name           = "tegra11-spi-slave",
1021         .id             = 3,
1022         .resource       = spi_resource4,
1023         .num_resources  = ARRAY_SIZE(spi_resource4),
1024         .dev  = {
1025                 .coherent_dma_mask      = 0xffffffff,
1026         },
1027 };
1028 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1029 struct platform_device tegra11_spi_slave_device5 = {
1030         .name           = "tegra11-spi-slave",
1031         .id             = 4,
1032         .resource       = spi_resource5,
1033         .num_resources  = ARRAY_SIZE(spi_resource5),
1034         .dev  = {
1035                 .coherent_dma_mask      = 0xffffffff,
1036         },
1037 };
1038
1039 struct platform_device tegra11_spi_slave_device6 = {
1040         .name           = "tegra11-spi-slave",
1041         .id             = 5,
1042         .resource       = spi_resource6,
1043         .num_resources  = ARRAY_SIZE(spi_resource6),
1044         .dev  = {
1045                 .coherent_dma_mask      = 0xffffffff,
1046         },
1047 };
1048 #endif
1049
1050 static struct resource resources_nor[] = {
1051         [0] = {
1052                 .start = INT_SNOR,
1053                 .end = INT_SNOR,
1054                 .flags = IORESOURCE_IRQ,
1055         },
1056         [1] = {
1057                 /* Map SNOR Controller */
1058                 .start = TEGRA_SNOR_BASE,
1059                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
1060                 .flags = IORESOURCE_MEM,
1061         },
1062         [2] = {
1063                 /* Map the size of flash */
1064                 .start = TEGRA_NOR_FLASH_BASE,
1065                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
1066                 .flags = IORESOURCE_MEM,
1067         }
1068 };
1069
1070 struct platform_device tegra_nor_device = {
1071         .name = "tegra-nor",
1072         .id = -1,
1073         .num_resources = ARRAY_SIZE(resources_nor),
1074         .resource = resources_nor,
1075         .dev = {
1076                 .coherent_dma_mask = 0xffffffff,
1077         },
1078 };
1079
1080 static struct resource dtv_resource[] = {
1081         [0] = {
1082                 .start  = TEGRA_DTV_BASE,
1083                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
1084                 .flags  = IORESOURCE_MEM,
1085         },
1086         [1] = {
1087                 .start  = TEGRA_DMA_REQ_SEL_DTV,
1088                 .end    = TEGRA_DMA_REQ_SEL_DTV,
1089                 .flags  = IORESOURCE_DMA
1090         },
1091 };
1092
1093 struct platform_device tegra_dtv_device = {
1094         .name           = "tegra_dtv",
1095         .id             = -1,
1096         .resource       = dtv_resource,
1097         .num_resources  = ARRAY_SIZE(dtv_resource),
1098         .dev = {
1099                 .init_name = "dtv",
1100                 .coherent_dma_mask = 0xffffffff,
1101         },
1102 };
1103
1104 static struct resource sdhci_resource1[] = {
1105         [0] = {
1106                 .start  = INT_SDMMC1,
1107                 .end    = INT_SDMMC1,
1108                 .flags  = IORESOURCE_IRQ,
1109         },
1110         [1] = {
1111                 .start  = TEGRA_SDMMC1_BASE,
1112                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
1113                 .flags  = IORESOURCE_MEM,
1114         },
1115 };
1116
1117 static struct resource sdhci_resource2[] = {
1118         [0] = {
1119                 .start  = INT_SDMMC2,
1120                 .end    = INT_SDMMC2,
1121                 .flags  = IORESOURCE_IRQ,
1122         },
1123         [1] = {
1124                 .start  = TEGRA_SDMMC2_BASE,
1125                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
1126                 .flags  = IORESOURCE_MEM,
1127         },
1128 };
1129
1130 static struct resource sdhci_resource3[] = {
1131         [0] = {
1132                 .start  = INT_SDMMC3,
1133                 .end    = INT_SDMMC3,
1134                 .flags  = IORESOURCE_IRQ,
1135         },
1136         [1] = {
1137                 .start  = TEGRA_SDMMC3_BASE,
1138                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
1139                 .flags  = IORESOURCE_MEM,
1140         },
1141 };
1142
1143 static struct resource sdhci_resource4[] = {
1144         [0] = {
1145                 .start  = INT_SDMMC4,
1146                 .end    = INT_SDMMC4,
1147                 .flags  = IORESOURCE_IRQ,
1148         },
1149         [1] = {
1150                 .start  = TEGRA_SDMMC4_BASE,
1151                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
1152                 .flags  = IORESOURCE_MEM,
1153         },
1154 };
1155
1156 struct platform_device tegra_pci_device = {
1157         .name           = "tegra-pcie",
1158         .id             = 0,
1159         .resource       = 0,
1160         .num_resources  = 0,
1161         .dev = {
1162                 .platform_data = 0,
1163         },
1164 };
1165
1166 /* board files should fill in platform_data register the devices themselvs.
1167  * See board-harmony.c for an example
1168  */
1169 struct platform_device tegra_sdhci_device1 = {
1170         .name           = "sdhci-tegra",
1171         .id             = 0,
1172         .resource       = sdhci_resource1,
1173         .num_resources  = ARRAY_SIZE(sdhci_resource1),
1174 };
1175
1176 struct platform_device tegra_sdhci_device2 = {
1177         .name           = "sdhci-tegra",
1178         .id             = 1,
1179         .resource       = sdhci_resource2,
1180         .num_resources  = ARRAY_SIZE(sdhci_resource2),
1181 };
1182
1183 struct platform_device tegra_sdhci_device3 = {
1184         .name           = "sdhci-tegra",
1185         .id             = 2,
1186         .resource       = sdhci_resource3,
1187         .num_resources  = ARRAY_SIZE(sdhci_resource3),
1188 };
1189
1190 struct platform_device tegra_sdhci_device4 = {
1191         .name           = "sdhci-tegra",
1192         .id             = 3,
1193         .resource       = sdhci_resource4,
1194         .num_resources  = ARRAY_SIZE(sdhci_resource4),
1195 };
1196
1197 static struct resource tegra_usb1_resources[] = {
1198         [0] = {
1199                 .start  = TEGRA_USB_BASE,
1200                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1201                 .flags  = IORESOURCE_MEM,
1202         },
1203         [1] = {
1204                 .start  = INT_USB,
1205                 .end    = INT_USB,
1206                 .flags  = IORESOURCE_IRQ,
1207         },
1208 };
1209
1210 static struct resource tegra_usb2_resources[] = {
1211         [0] = {
1212                 .start  = TEGRA_USB2_BASE,
1213                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
1214                 .flags  = IORESOURCE_MEM,
1215         },
1216         [1] = {
1217                 .start  = INT_USB2,
1218                 .end    = INT_USB2,
1219                 .flags  = IORESOURCE_IRQ,
1220         },
1221 };
1222
1223 static struct resource tegra_usb3_resources[] = {
1224         [0] = {
1225                 .start  = TEGRA_USB3_BASE,
1226                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
1227                 .flags  = IORESOURCE_MEM,
1228         },
1229         [1] = {
1230                 .start  = INT_USB3,
1231                 .end    = INT_USB3,
1232                 .flags  = IORESOURCE_IRQ,
1233         },
1234 };
1235
1236 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1237 static struct resource tegra_xusb_resources[] = {
1238         [0] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_HOST_BASE, TEGRA_XUSB_HOST_SIZE,
1239                         "host"),
1240         [1] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_FPCI_BASE, TEGRA_XUSB_FPCI_SIZE,
1241                         "fpci"),
1242         [2] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_IPFS_BASE, TEGRA_XUSB_IPFS_SIZE,
1243                         "ipfs"),
1244         [3] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_PADCTL_BASE,
1245                         TEGRA_XUSB_PADCTL_SIZE, "padctl"),
1246         [4] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_INT, "host"),
1247         [5] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_SMI, "host-smi"),
1248         [6] = DEFINE_RES_IRQ_NAMED(INT_XUSB_PADCTL, "padctl"),
1249         [7] = DEFINE_RES_IRQ_NAMED(INT_USB3, "usb3"),
1250         [8] = DEFINE_RES_IRQ_NAMED(INT_USB2, "usb2"),
1251 };
1252
1253 static u64 tegra_xusb_dmamask = DMA_BIT_MASK(64);
1254
1255 struct platform_device tegra_xhci_device = {
1256         .name = "tegra-xhci",
1257         .id = -1,
1258         .dev = {
1259                 .dma_mask = &tegra_xusb_dmamask,
1260                 .coherent_dma_mask = DMA_BIT_MASK(64),
1261         },
1262         .resource = tegra_xusb_resources,
1263         .num_resources = ARRAY_SIZE(tegra_xusb_resources),
1264 };
1265 #endif
1266
1267 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(64);
1268
1269 struct platform_device tegra_ehci1_device = {
1270         .name   = "tegra-ehci",
1271         .id     = 0,
1272         .dev    = {
1273                 .dma_mask       = &tegra_ehci_dmamask,
1274                 .coherent_dma_mask = DMA_BIT_MASK(64),
1275         },
1276         .resource = tegra_usb1_resources,
1277         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
1278 };
1279
1280 struct platform_device tegra_ehci2_device = {
1281         .name   = "tegra-ehci",
1282         .id     = 1,
1283         .dev    = {
1284                 .dma_mask       = &tegra_ehci_dmamask,
1285                 .coherent_dma_mask = DMA_BIT_MASK(64),
1286         },
1287         .resource = tegra_usb2_resources,
1288         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
1289 };
1290
1291 struct platform_device tegra_ehci3_device = {
1292         .name   = "tegra-ehci",
1293         .id     = 2,
1294         .dev    = {
1295                 .dma_mask       = &tegra_ehci_dmamask,
1296                 .coherent_dma_mask = DMA_BIT_MASK(64),
1297         },
1298         .resource = tegra_usb3_resources,
1299         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
1300 };
1301
1302 static struct resource tegra_pmu_resources[] = {
1303         [0] = {
1304                 .start  = INT_CPU0_PMU_INTR,
1305                 .end    = INT_CPU0_PMU_INTR,
1306                 .flags  = IORESOURCE_IRQ,
1307         },
1308         [1] = {
1309                 .start  = INT_CPU1_PMU_INTR,
1310                 .end    = INT_CPU1_PMU_INTR,
1311                 .flags  = IORESOURCE_IRQ,
1312         },
1313 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1314         [2] = {
1315                 .start  = INT_CPU2_PMU_INTR,
1316                 .end    = INT_CPU2_PMU_INTR,
1317                 .flags  = IORESOURCE_IRQ,
1318         },
1319         [3] = {
1320                 .start  = INT_CPU3_PMU_INTR,
1321                 .end    = INT_CPU3_PMU_INTR,
1322                 .flags  = IORESOURCE_IRQ,
1323         },
1324 #endif
1325 };
1326
1327 struct platform_device tegra_pmu_device = {
1328         .name           = "arm-pmu",
1329         .id             = -1,
1330         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
1331         .resource       = tegra_pmu_resources,
1332 };
1333
1334 static struct resource tegra_uarta_resources[] = {
1335         [0] = {
1336                 .start  = TEGRA_UARTA_BASE,
1337                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
1338                 .flags  = IORESOURCE_MEM,
1339         },
1340         [1] = {
1341                 .start  = INT_UARTA,
1342                 .end    = INT_UARTA,
1343                 .flags  = IORESOURCE_IRQ,
1344         },
1345 };
1346
1347 static struct resource tegra_uartb_resources[] = {
1348         [0] = {
1349                 .start  = TEGRA_UARTB_BASE,
1350                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
1351                 .flags  = IORESOURCE_MEM,
1352         },
1353         [1] = {
1354                 .start  = INT_UARTB,
1355                 .end    = INT_UARTB,
1356                 .flags  = IORESOURCE_IRQ,
1357         },
1358 };
1359
1360 static struct resource tegra_uartc_resources[] = {
1361         [0] = {
1362                 .start  = TEGRA_UARTC_BASE,
1363                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
1364                 .flags  = IORESOURCE_MEM,
1365         },
1366         [1] = {
1367                 .start  = INT_UARTC,
1368                 .end    = INT_UARTC,
1369                 .flags  = IORESOURCE_IRQ,
1370         },
1371 };
1372
1373 static struct resource tegra_uartd_resources[] = {
1374         [0] = {
1375                 .start  = TEGRA_UARTD_BASE,
1376                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
1377                 .flags  = IORESOURCE_MEM,
1378         },
1379         [1] = {
1380                 .start  = INT_UARTD,
1381                 .end    = INT_UARTD,
1382                 .flags  = IORESOURCE_IRQ,
1383         },
1384 };
1385
1386 static struct resource tegra_uarte_resources[] = {
1387         [0] = {
1388                 .start  = TEGRA_UARTE_BASE,
1389                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
1390                 .flags  = IORESOURCE_MEM,
1391         },
1392         [1] = {
1393                 .start  = INT_UARTE,
1394                 .end    = INT_UARTE,
1395                 .flags  = IORESOURCE_IRQ,
1396         },
1397 };
1398
1399 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
1400 #define UART_DMA_BIT_MASK DMA_BIT_MASK(64)
1401 #else
1402 #define UART_DMA_BIT_MASK DMA_BIT_MASK(32)
1403 #endif
1404
1405 struct platform_device tegra_uarta_device = {
1406         .name   = "serial-tegra",
1407         .id     = 0,
1408         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
1409         .resource       = tegra_uarta_resources,
1410         .dev    = {
1411                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1412         },
1413 };
1414
1415 struct platform_device tegra_uartb_device = {
1416         .name   = "serial-tegra",
1417         .id     = 1,
1418         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
1419         .resource       = tegra_uartb_resources,
1420         .dev    = {
1421                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1422         },
1423 };
1424
1425 struct platform_device tegra_uartc_device = {
1426         .name   = "serial-tegra",
1427         .id     = 2,
1428         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
1429         .resource       = tegra_uartc_resources,
1430         .dev    = {
1431                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1432         },
1433 };
1434
1435 struct platform_device tegra_uartd_device = {
1436         .name   = "serial-tegra",
1437         .id     = 3,
1438         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
1439         .resource       = tegra_uartd_resources,
1440         .dev    = {
1441                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1442         },
1443 };
1444
1445 struct platform_device tegra_uarte_device = {
1446         .name   = "serial-tegra",
1447         .id     = 4,
1448         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
1449         .resource       = tegra_uarte_resources,
1450         .dev    = {
1451                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1452         },
1453 };
1454
1455 static struct plat_serial8250_port debug_uarta_platform_data[] = {
1456         {
1457                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
1458                 .mapbase        = TEGRA_UARTA_BASE,
1459                 .irq            = INT_UARTA,
1460                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1461                 .type           = PORT_TEGRA,
1462                 .iotype         = UPIO_MEM,
1463                 .regshift       = 2,
1464         },
1465         {
1466                 .flags          = 0,
1467         },
1468 };
1469
1470 static struct plat_serial8250_port debug_uartb_platform_data[] = {
1471         {
1472                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
1473                 .mapbase        = TEGRA_UARTB_BASE,
1474                 .irq            = INT_UARTB,
1475                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1476                 .type           = PORT_TEGRA,
1477                 .iotype         = UPIO_MEM,
1478                 .regshift       = 2,
1479         },
1480         {
1481                 .flags          = 0,
1482         },
1483 };
1484
1485 static struct plat_serial8250_port debug_uartc_platform_data[] = {
1486         {
1487                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
1488                 .mapbase        = TEGRA_UARTC_BASE,
1489                 .irq            = INT_UARTC,
1490                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1491                 .type           = PORT_TEGRA,
1492                 .iotype         = UPIO_MEM,
1493                 .regshift       = 2,
1494         },
1495         {
1496                 .flags          = 0,
1497         },
1498 };
1499
1500 static struct plat_serial8250_port debug_uartd_platform_data[] = {
1501         {
1502                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
1503                 .mapbase        = TEGRA_UARTD_BASE,
1504                 .irq            = INT_UARTD,
1505                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1506                 .type           = PORT_TEGRA,
1507                 .iotype         = UPIO_MEM,
1508                 .regshift       = 2,
1509         },
1510         {
1511                 .flags          = 0,
1512         },
1513 };
1514
1515 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1516 static struct plat_serial8250_port debug_uarte_platform_data[] = {
1517         {
1518                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
1519                 .mapbase        = TEGRA_UARTE_BASE,
1520                 .irq            = INT_UARTE,
1521                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1522                 .type           = PORT_TEGRA,
1523                 .iotype         = UPIO_MEM,
1524                 .regshift       = 2,
1525         },
1526         {
1527                 .flags          = 0,
1528         },
1529 };
1530 #endif
1531
1532 struct platform_device debug_uarta_device = {
1533         .name = "serial8250",
1534         .id = PLAT8250_DEV_PLATFORM,
1535         .dev = {
1536                 .platform_data = debug_uarta_platform_data,
1537         },
1538 };
1539
1540 struct platform_device debug_uartb_device = {
1541         .name = "serial8250",
1542         .id = PLAT8250_DEV_PLATFORM,
1543         .dev = {
1544                 .platform_data = debug_uartb_platform_data,
1545         },
1546 };
1547
1548 struct platform_device debug_uartc_device = {
1549         .name = "serial8250",
1550         .id = PLAT8250_DEV_PLATFORM,
1551         .dev = {
1552                 .platform_data = debug_uartc_platform_data,
1553         },
1554 };
1555
1556 struct platform_device debug_uartd_device = {
1557         .name = "serial8250",
1558         .id = PLAT8250_DEV_PLATFORM,
1559         .dev = {
1560                 .platform_data = debug_uartd_platform_data,
1561         },
1562 };
1563
1564 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1565 struct platform_device debug_uarte_device = {
1566         .name = "serial8250",
1567         .id = PLAT8250_DEV_PLATFORM,
1568         .dev = {
1569                 .platform_data = debug_uarte_platform_data,
1570         },
1571 };
1572 #endif
1573
1574 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1575 static struct resource i2s_resource1[] = {
1576         [0] = {
1577                 .start  = INT_I2S1,
1578                 .end    = INT_I2S1,
1579                 .flags  = IORESOURCE_IRQ
1580         },
1581         [1] = {
1582                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1583                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1584                 .flags  = IORESOURCE_DMA
1585         },
1586         [2] = {
1587                 .start  = TEGRA_I2S1_BASE,
1588                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1589                 .flags  = IORESOURCE_MEM
1590         }
1591 };
1592
1593 struct platform_device tegra_i2s_device1 = {
1594         .name           = "tegra20-i2s",
1595         .id             = 0,
1596         .resource       = i2s_resource1,
1597         .num_resources  = ARRAY_SIZE(i2s_resource1),
1598 };
1599
1600 static struct resource i2s_resource2[] = {
1601         [0] = {
1602                 .start  = INT_I2S2,
1603                 .end    = INT_I2S2,
1604                 .flags  = IORESOURCE_IRQ
1605         },
1606         [1] = {
1607                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1608                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1609                 .flags  = IORESOURCE_DMA
1610         },
1611         [2] = {
1612                 .start  = TEGRA_I2S2_BASE,
1613                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1614                 .flags  = IORESOURCE_MEM
1615         }
1616 };
1617
1618 struct platform_device tegra_i2s_device2 = {
1619         .name           = "tegra20-i2s",
1620         .id             = 1,
1621         .resource       = i2s_resource2,
1622         .num_resources  = ARRAY_SIZE(i2s_resource2),
1623 };
1624 #else
1625 static struct resource i2s_resource0[] = {
1626         [0] = {
1627                 .start  = TEGRA_I2S0_BASE,
1628                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1629                 .flags  = IORESOURCE_MEM
1630         }
1631 };
1632
1633 struct platform_device tegra_i2s_device0 = {
1634         .name           = "tegra30-i2s",
1635         .id             = 0,
1636         .resource       = i2s_resource0,
1637         .num_resources  = ARRAY_SIZE(i2s_resource0),
1638 };
1639
1640 static struct resource i2s_resource1[] = {
1641         [0] = {
1642                 .start  = TEGRA_I2S1_BASE,
1643                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1644                 .flags  = IORESOURCE_MEM
1645         }
1646 };
1647
1648 struct platform_device tegra_i2s_device1 = {
1649         .name           = "tegra30-i2s",
1650         .id             = 1,
1651         .resource       = i2s_resource1,
1652         .num_resources  = ARRAY_SIZE(i2s_resource1),
1653 };
1654
1655 static struct resource i2s_resource2[] = {
1656         [0] = {
1657                 .start  = TEGRA_I2S2_BASE,
1658                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1659                 .flags  = IORESOURCE_MEM
1660         }
1661 };
1662
1663 struct platform_device tegra_i2s_device2 = {
1664         .name           = "tegra30-i2s",
1665         .id             = 2,
1666         .resource       = i2s_resource2,
1667         .num_resources  = ARRAY_SIZE(i2s_resource2),
1668 };
1669
1670 static struct resource i2s_resource3[] = {
1671         [0] = {
1672                 .start  = TEGRA_I2S3_BASE,
1673                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1674                 .flags  = IORESOURCE_MEM
1675         }
1676 };
1677
1678 struct platform_device tegra_i2s_device3 = {
1679         .name           = "tegra30-i2s",
1680         .id             = 3,
1681         .resource       = i2s_resource3,
1682         .num_resources  = ARRAY_SIZE(i2s_resource3),
1683 };
1684
1685 static struct resource i2s_resource4[] = {
1686         [0] = {
1687                 .start  = TEGRA_I2S4_BASE,
1688                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1689                 .flags  = IORESOURCE_MEM
1690         }
1691 };
1692
1693 struct platform_device tegra_i2s_device4 = {
1694         .name           = "tegra30-i2s",
1695         .id             = 4,
1696         .resource       = i2s_resource4,
1697         .num_resources  = ARRAY_SIZE(i2s_resource4),
1698 };
1699 #endif
1700
1701 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1702 static struct resource spdif_resource[] = {
1703         [0] = {
1704                 .start  = INT_SPDIF,
1705                 .end    = INT_SPDIF,
1706                 .flags  = IORESOURCE_IRQ
1707         },
1708         [1] = {
1709                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1710                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1711                 .flags  = IORESOURCE_DMA
1712         },
1713         [2] = {
1714                 .start  = TEGRA_SPDIF_BASE,
1715                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1716                 .flags  = IORESOURCE_MEM
1717         }
1718 };
1719
1720 struct platform_device tegra_spdif_device = {
1721         .name           = "tegra20-spdif",
1722         .id             = -1,
1723         .resource       = spdif_resource,
1724         .num_resources  = ARRAY_SIZE(spdif_resource),
1725 };
1726 #else
1727 static struct resource spdif_resource[] = {
1728         [0] = {
1729                 .start  = TEGRA_SPDIF_BASE,
1730                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1731                 .flags  = IORESOURCE_MEM
1732         }
1733 };
1734
1735 struct platform_device tegra_spdif_device = {
1736         .name           = "tegra30-spdif",
1737         .id             = -1,
1738         .resource       = spdif_resource,
1739         .num_resources  = ARRAY_SIZE(spdif_resource),
1740 };
1741 #endif
1742
1743 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1744 static struct resource ahub_resource[] = {
1745         [0] = {
1746                 .start  = TEGRA_APBIF0_BASE,
1747                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1748                 .flags  = IORESOURCE_MEM
1749         },
1750         [1] = {
1751                 .start  = TEGRA_AHUB_BASE,
1752                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1753                 .flags  = IORESOURCE_MEM
1754         }
1755 };
1756
1757 struct platform_device tegra_ahub_device = {
1758         .name   = "tegra30-ahub",
1759         .id     = -1,
1760         .resource       = ahub_resource,
1761         .num_resources  = ARRAY_SIZE(ahub_resource),
1762 };
1763
1764 static struct resource dam_resource0[] = {
1765         [0] = {
1766                 .start = TEGRA_DAM0_BASE,
1767                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1768                 .flags = IORESOURCE_MEM
1769         }
1770 };
1771
1772 struct platform_device tegra_dam_device0 = {
1773         .name = "tegra30-dam",
1774         .id = 0,
1775         .resource      = dam_resource0,
1776         .num_resources = ARRAY_SIZE(dam_resource0),
1777 };
1778
1779 static struct resource dam_resource1[] = {
1780         [0] = {
1781                 .start = TEGRA_DAM1_BASE,
1782                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1783                 .flags = IORESOURCE_MEM
1784         }
1785 };
1786
1787 struct platform_device tegra_dam_device1 = {
1788         .name = "tegra30-dam",
1789         .id = 1,
1790         .resource      = dam_resource1,
1791         .num_resources = ARRAY_SIZE(dam_resource1),
1792 };
1793
1794 static struct resource dam_resource2[] = {
1795         [0] = {
1796                 .start = TEGRA_DAM2_BASE,
1797                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1798                 .flags = IORESOURCE_MEM
1799         }
1800 };
1801
1802 struct platform_device tegra_dam_device2 = {
1803         .name = "tegra30-dam",
1804         .id = 2,
1805         .resource      = dam_resource2,
1806         .num_resources = ARRAY_SIZE(dam_resource2),
1807 };
1808
1809 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1810 static struct resource hda_platform_resources[] = {
1811         [0] = {
1812                 .start  = TEGRA_HDA_BASE,
1813                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1814                 .flags  = IORESOURCE_MEM
1815         },
1816         [1] = {
1817                 .start  = INT_HDA,
1818                 .end    = INT_HDA,
1819                 .flags  = IORESOURCE_IRQ
1820         },
1821 };
1822
1823 struct platform_device tegra_hda_device = {
1824         .name           = "tegra30-hda",
1825         .id             = -1,
1826         .dev = {
1827                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1828                 .dma_mask               = &tegra_hda_dma_mask,
1829         },
1830         .resource       = hda_platform_resources,
1831         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1832 };
1833 #endif
1834
1835 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1836 static struct resource dmic_resource0[] = {
1837         [0] = {
1838                 .start = TEGRA_DMIC0_BASE,
1839                 .end   = TEGRA_DMIC0_BASE + TEGRA_DMIC0_SIZE - 1,
1840                 .flags = IORESOURCE_MEM
1841         }
1842 };
1843
1844 struct platform_device tegra_dmic_device0 = {
1845         .name = "tegra-dmic",
1846         .id = 0,
1847         .resource      = dmic_resource0,
1848         .num_resources = ARRAY_SIZE(dmic_resource0),
1849 };
1850
1851 static struct resource dmic_resource1[] = {
1852         [0] = {
1853                 .start = TEGRA_DMIC1_BASE,
1854                 .end   = TEGRA_DMIC1_BASE + TEGRA_DMIC1_SIZE - 1,
1855                 .flags = IORESOURCE_MEM
1856         }
1857 };
1858
1859 struct platform_device tegra_dmic_device1 = {
1860         .name = "tegra-dmic",
1861         .id = 1,
1862         .resource      = dmic_resource1,
1863         .num_resources = ARRAY_SIZE(dmic_resource1),
1864 };
1865 #endif
1866
1867 struct platform_device spdif_dit_device = {
1868         .name = "spdif-dit",
1869         .id = 0,
1870 };
1871
1872 struct platform_device bluetooth_dit_device = {
1873         .name = "spdif-dit",
1874         .id = 1,
1875 };
1876
1877 struct platform_device baseband_dit_device = {
1878         .name = "spdif-dit",
1879         .id = 2,
1880 };
1881
1882 struct platform_device tegra_pcm_device = {
1883         .name = "tegra-pcm-audio",
1884         .id = -1,
1885 };
1886
1887 struct platform_device tegra_tdm_pcm_device = {
1888         .name = "tegra-tdm-pcm-audio",
1889         .id = -1,
1890 };
1891
1892 static struct resource w1_resources[] = {
1893         [0] = {
1894                 .start = INT_OWR,
1895                 .end   = INT_OWR,
1896                 .flags = IORESOURCE_IRQ
1897         },
1898         [1] = {
1899                 .start = TEGRA_OWR_BASE,
1900                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1901                 .flags = IORESOURCE_MEM
1902         }
1903 };
1904
1905 struct platform_device tegra_w1_device = {
1906         .name          = "tegra_w1",
1907         .id            = -1,
1908         .resource      = w1_resources,
1909         .num_resources = ARRAY_SIZE(w1_resources),
1910 };
1911
1912 static struct resource tegra_udc_resources[] = {
1913         [0] = {
1914                 .start  = TEGRA_USB_BASE,
1915                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1916                 .flags  = IORESOURCE_MEM,
1917         },
1918         [1] = {
1919                 .start  = INT_USB,
1920                 .end    = INT_USB,
1921                 .flags  = IORESOURCE_IRQ,
1922         },
1923 };
1924
1925 static u64 tegra_udc_dmamask = DMA_BIT_MASK(64);
1926
1927 struct platform_device tegra_udc_device = {
1928         .name   = "tegra-udc",
1929         .id     = 0,
1930         .dev    = {
1931                 .dma_mask       = &tegra_udc_dmamask,
1932                 .coherent_dma_mask = DMA_BIT_MASK(64),
1933         },
1934         .resource = tegra_udc_resources,
1935         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1936 };
1937
1938 static struct resource tegra_otg_resources[] = {
1939         [0] = {
1940                 .start  = TEGRA_USB_BASE,
1941                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1942                 .flags  = IORESOURCE_MEM,
1943         },
1944         [1] = {
1945                 .start  = INT_USB,
1946                 .end    = INT_USB,
1947                 .flags  = IORESOURCE_IRQ,
1948         },
1949 };
1950
1951 struct platform_device tegra_otg_device = {
1952         .name           = "tegra-otg",
1953         .id             = -1,
1954         .resource       = tegra_otg_resources,
1955         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1956 };
1957
1958 #ifdef CONFIG_SATA_AHCI_TEGRA
1959 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(64);
1960
1961 static struct resource tegra_sata_resources[] = {
1962         [0] = {
1963                 .start = TEGRA_SATA_BAR5_BASE,
1964                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1965                 .flags = IORESOURCE_MEM,
1966         },
1967         [1] = {
1968                 .start = TEGRA_SATA_CONFIG_BASE,
1969                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1970                 .flags = IORESOURCE_MEM,
1971         },
1972         [2] = {
1973                 .start = INT_SATA_CTL,
1974                 .end = INT_SATA_CTL,
1975                 .flags = IORESOURCE_IRQ,
1976         },
1977 };
1978
1979 struct platform_device tegra_sata_device = {
1980         .name   = "tegra-sata",
1981         .id     = 0,
1982         .dev    = {
1983                 .coherent_dma_mask = DMA_BIT_MASK(64),
1984                 .dma_mask = &tegra_sata_dma_mask,
1985         },
1986         .resource = tegra_sata_resources,
1987         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1988 };
1989 #endif
1990
1991 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1992 static struct resource das_resource[] = {
1993         [0] = {
1994                 .start  = TEGRA_APB_MISC_DAS_BASE,
1995                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1996                 .flags  = IORESOURCE_MEM
1997         }
1998 };
1999
2000 struct platform_device tegra_das_device = {
2001         .name           = "tegra20-das",
2002         .id             = -1,
2003         .resource       = das_resource,
2004         .num_resources  = ARRAY_SIZE(das_resource),
2005 };
2006 #endif
2007
2008 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
2009 static struct resource tegra_gart_resources[] = {
2010         [0] = {
2011                 .name   = "mc",
2012                 .flags  = IORESOURCE_MEM,
2013                 .start  = TEGRA_MC_BASE,
2014                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
2015         },
2016         [1] = {
2017                 .name   = "gart",
2018                 .flags  = IORESOURCE_MEM,
2019                 .start  = TEGRA_GART_BASE,
2020                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
2021         }
2022 };
2023
2024 struct platform_device tegra_gart_device = {
2025         .name           = "tegra_gart",
2026         .id             = -1,
2027         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
2028         .resource       = tegra_gart_resources
2029 };
2030 #endif
2031
2032 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
2033 static struct resource tegra_smmu_resources[] = {
2034         {
2035                 .name   = "mc",
2036                 .flags  = IORESOURCE_MEM,
2037                 .start  = TEGRA_MC_BASE,
2038                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
2039         },
2040         {
2041                 .name   = "ahbarb",
2042                 .flags  = IORESOURCE_MEM,
2043                 .start  = TEGRA_AHB_ARB_BASE,
2044                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
2045         },
2046 };
2047
2048 struct platform_device tegra_smmu_device = {
2049         .name           = "tegra_smmu",
2050         .id             = -1,
2051         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
2052         .resource       = tegra_smmu_resources
2053 };
2054
2055 static struct resource tegra_smmu[] = {
2056         [0] = {
2057                 .start  = TEGRA_SMMU_BASE,
2058                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
2059         },
2060 };
2061
2062 struct resource *tegra_smmu_window(int wnum)
2063 {
2064         return &tegra_smmu[wnum];
2065 }
2066
2067 int tegra_smmu_window_count(void)
2068 {
2069         return ARRAY_SIZE(tegra_smmu);
2070 }
2071
2072 static struct iommu_linear_map tegra_fb_linear_map[16]; /* Terminated with 0 */
2073
2074 #define LINEAR_MAP_ADD(n) \
2075 do { \
2076         if (n##_start && n##_size) { \
2077                 map[i].start = n##_start; \
2078                 map[i++].size = n##_size; \
2079         } \
2080 } while (0)
2081
2082 void tegra_fb_linear_set(struct iommu_linear_map *map)
2083 {
2084         int i = 0;
2085
2086         map = tegra_fb_linear_map;
2087
2088         LINEAR_MAP_ADD(tegra_fb);
2089         LINEAR_MAP_ADD(tegra_fb2);
2090         LINEAR_MAP_ADD(tegra_bootloader_fb);
2091         LINEAR_MAP_ADD(tegra_bootloader_fb2);
2092 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2093         LINEAR_MAP_ADD(tegra_vpr);
2094         LINEAR_MAP_ADD(tegra_carveout);
2095 #endif
2096 }
2097
2098 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2099 void carveout_linear_set(struct device *cma_dev)
2100 {
2101         struct dma_contiguous_stats stats;
2102         struct iommu_linear_map *map = &tegra_fb_linear_map[0];
2103
2104         if (dma_get_contiguous_stats(cma_dev, &stats))
2105                 return;
2106
2107         /* get the free slot at end and add carveout entry */
2108         while (map && map->size)
2109                 map++;
2110         map->start = stats.base;
2111         map->size = stats.size;
2112 }
2113 #endif
2114
2115 struct swgid_fixup {
2116         const char * const name;
2117         u64 swgids;
2118         struct iommu_linear_map *linear_map;
2119 };
2120
2121 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2122 #define DUMMY_DEV_NAME "dummy_dev"
2123 #define DUMMY_DEV_MAX_NAME_SIZE 100
2124 static char dummy_name[DUMMY_DEV_MAX_NAME_SIZE] = DUMMY_DEV_NAME;
2125 #endif
2126
2127 /*
2128  * FIXME: They should have a DT entry with swgroup IDs.
2129  */
2130 struct swgid_fixup tegra_swgid_fixup[] = {
2131         { .name = "540c0000.epp",       .swgids = SWGID(EPP), },
2132         { .name = "epp",        .swgids = SWGID(EPP), },
2133         { .name = "54200000.dc",        .swgids = SWGID(DC),
2134           .linear_map = tegra_fb_linear_map, },
2135         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
2136         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
2137         { .name = "gr2d",       .swgids = SWGID(G2), },
2138         { .name = "gr3d",       .swgids = SWGID(NV) | SWGID(NV2), },
2139         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |      \
2140           SWGID(EPP) | SWGID(HDA), },
2141         { .name = "isp",        .swgids = SWGID(ISP), },
2142         { .name = "max77660",   .swgids = SWGID(PPCS), },
2143         { .name = "max8831",    .swgids = SWGID(PPCS), },
2144         { .name = "msenc",      .swgids = SWGID(MSENC), },
2145         { .name = "mpe",        .swgids = SWGID(MPE), },
2146         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
2147         { .name = "nvavp",      .swgids = SWGID(AVPC), },
2148         { .name = "sdhci-tegra",        .swgids = SWGID(PPCS), },
2149         { .name = "serial8250", .swgids = SWGID(PPCS), },
2150         { .name = "serial-tegra",      .swgids = SWGID(PPCS), },
2151         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS), },
2152         { .name = "spdif-dit",  .swgids = SWGID(PPCS), },
2153         { .name = "tegra11-se", .swgids = SWGID(PPCS), },
2154         { .name = "tegra11-spi",        .swgids = SWGID(PPCS), },
2155         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS), },
2156         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS), },
2157         { .name = "tegra30-dam",        .swgids = SWGID(PPCS), },
2158         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
2159         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS), },
2160         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS), },
2161         { .name = "tegradc.0", .swgids = SWGID(DC),
2162           .linear_map = tegra_fb_linear_map},
2163         { .name = "tegradc.1", .swgids = SWGID(DCB), },
2164         { .name = "tegra_bb",   .swgids = SWGID(PPCS), },
2165         { .name = "tegra_dma",  .swgids = SWGID(PPCS), },
2166         { .name = "tegra-ehci", .swgids = SWGID(PPCS), },
2167         { .name = "tegra-fuse", .swgids = SWGID(PPCS), },
2168         { .name = "tegra-i2c",  .swgids = SWGID(PPCS), },
2169         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
2170         { .name = "tegra-otg",  .swgids = SWGID(PPCS), },
2171         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS), },
2172         { .name = "tegra-rtc",  .swgids = SWGID(PPCS), },
2173         { .name = "tegra-sata", .swgids = SWGID(SATA), },
2174         { .name = "tegra-se",   .swgids = SWGID(PPCS), },
2175         { .name = "tegra-snd",  .swgids = SWGID(PPCS), },
2176         { .name = "tegra-tzram",        .swgids = SWGID(VDE), },
2177         { .name = "tegra_uart", .swgids = SWGID(PPCS), },
2178         { .name = "tegra-udc",  .swgids = SWGID(PPCS), },
2179         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS), },
2180         { .name = "tsec",       .swgids = SWGID(TSEC), },
2181         { .name = "vi", .swgids = SWGID(VI), },
2182         { .name = "therm_est",  .swgids = SWGID(PPCS), },
2183         { .name = "tegra-xhci", .swgids = SWGID(XUSB_HOST), },
2184 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2185         { .name = dummy_name,   .swgids = SWGID(PPCS) },
2186 #endif
2187         {},
2188 };
2189
2190 struct swgid_fixup tegra_swgid_fixup_t124[] = {
2191         { .name = "54200000.dc",        .swgids = SWGID(DC), },
2192         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
2193         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
2194         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |
2195           SWGID(EPP) | SWGID(HDA), },
2196         { .name = "isp",        .swgids = SWGID(ISP2) | SWGID(ISP2B), },
2197         { .name = "max77660",   .swgids = SWGID(PPCS), },
2198         { .name = "max8831",    .swgids = SWGID(PPCS), },
2199         { .name = "msenc",      .swgids = SWGID(MSENC), },
2200         { .name = "mpe",        .swgids = SWGID(MPE), },
2201         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
2202         { .name = "nvavp",      .swgids = SWGID(AVPC) | SWGID(A9AVP), },
2203         { .name = "serial8250", .swgids = SWGID(PPCS), },
2204         { .name = "serial-tegra",       .swgids = SWGID(PPCS), },
2205         { .name = "dtv",        .swgids = SWGID(PPCS), },
2206         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS), },
2207         { .name = "spdif-dit",  .swgids = SWGID(PPCS), },
2208         { .name = "tegra12-se", .swgids = SWGID(PPCS), },
2209         { .name = "spi-tegra114",       .swgids = SWGID(PPCS), },
2210         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS), },
2211         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS), },
2212         { .name = "tegra30-dam",        .swgids = SWGID(PPCS), },
2213         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
2214         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS), },
2215         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS), },
2216         { .name = "tegradc.0", .swgids = SWGID(DC) | SWGID(DC12),
2217           .linear_map = tegra_fb_linear_map, },
2218         { .name = "tegradc.1", .swgids = SWGID(DCB),
2219           .linear_map = tegra_fb_linear_map, },
2220         { .name = "tegra_bb",   .swgids = SWGID(PPCS), },
2221         { .name = "tegra_dma",  .swgids = SWGID(PPCS), },
2222         { .name = "tegra-ehci", .swgids = SWGID(PPCS), },
2223         { .name = "tegra-fuse", .swgids = SWGID(PPCS), },
2224         { .name = "tegra-i2c",  .swgids = SWGID(PPCS), },
2225         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
2226         { .name = "tegra-otg",  .swgids = SWGID(PPCS), },
2227         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS), },
2228         { .name = "tegra-rtc",  .swgids = SWGID(PPCS), },
2229         { .name = "tegra-sata", .swgids = SWGID(SATA2), },
2230         { .name = "tegra-se",   .swgids = SWGID(PPCS), },
2231         { .name = "tegra-snd",  .swgids = SWGID(PPCS), },
2232         { .name = "tegra-tzram",        .swgids = SWGID(PPCS), },
2233         { .name = "tegra_uart", .swgids = SWGID(PPCS), },
2234         { .name = "tegra-udc",  .swgids = SWGID(PPCS), },
2235         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS), },
2236         { .name = "tsec",       .swgids = SWGID(TSEC), },
2237         /* vic must be before vi to prevent incorrect matching */
2238         { .name = "vic",        .swgids = SWGID(VIC), },
2239         { .name = "vi", .swgids = SWGID(VI), },
2240         { .name = "therm_est",  .swgids = SWGID(PPCS), },
2241         { .name = "gk20a",      .swgids = SWGID(GPU) | SWGID(GPUB), },
2242         { .name = "tegra124-apbdma",    .swgids = SWGID(PPCS), },
2243         { .name = "tegra-nor",  .swgids = SWGID(PPCS), },
2244 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2245         { .name = dummy_name,   .swgids = SWGID(PPCS) },
2246 #endif
2247         { .name = "tegra-xhci", .swgids = SWGID(XUSB_HOST), },
2248         {},
2249 };
2250
2251 u64 tegra_smmu_fixup_swgids(struct device *dev, struct iommu_linear_map **map)
2252 {
2253         const char *s;
2254         struct swgid_fixup *table = tegra_swgid_fixup;
2255
2256         if (!dev)
2257                 return 0;
2258
2259         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA12)
2260                 table = tegra_swgid_fixup_t124;
2261
2262         while ((s = table->name) != NULL) {
2263                 if (!strncmp(s, dev_name(dev), strlen(s))) {
2264                         if (map)
2265                                 *map = table->linear_map;
2266
2267                         return table->swgids;
2268                 }
2269                 table++;
2270         }
2271
2272         return 0;
2273 }
2274
2275 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2276
2277 struct tegra_iommu_mapping {
2278         dma_addr_t base;
2279         size_t size;
2280         struct dma_iommu_mapping *map;
2281 };
2282
2283 static struct tegra_iommu_mapping smmu_default_map[] = {
2284         [SYSTEM_DEFAULT] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
2285         [SYSTEM_PROTECTED] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
2286         [SYSTEM_DC] = {0x10000, (u32)~0},
2287         [SYSTEM_DCB] = {0x10000, (u32)~0},
2288         /* Non-zero base to account for gk20a driver's assumptions */
2289         [SYSTEM_GK20A] = {0x100000, (u32)~0},
2290 };
2291
2292 static void tegra_smmu_map_init(struct platform_device *pdev)
2293 {
2294         int i;
2295
2296         for (i = 0; i < ARRAY_SIZE(smmu_default_map); i++) {
2297                 struct tegra_iommu_mapping *m = &smmu_default_map[i];
2298                 struct dma_iommu_mapping *map;
2299                 int order = 0;
2300
2301                 if (IS_ENABLED(CONFIG_TEGRA_ERRATA_1053704))
2302                         order = get_order(SZ_16K);
2303
2304                 map = arm_iommu_create_mapping(&platform_bus_type,
2305                                                m->base, m->size, 0);
2306
2307                 if (IS_ERR(map))
2308                         dev_err(&pdev->dev,
2309                                 "Failed create IOVA map for ASID[%d]\n", i);
2310
2311                 m->map = map;
2312         }
2313 }
2314
2315 void tegra_smmu_map_misc_device(struct device *dev)
2316 {
2317         struct dma_iommu_mapping *map = smmu_default_map[SYSTEM_PROTECTED].map;
2318         if (!strncmp(dummy_name, DUMMY_DEV_NAME, strlen(dummy_name))) {
2319                 strncpy(dummy_name, dev_name(dev),
2320                         DUMMY_DEV_MAX_NAME_SIZE);
2321                 arm_iommu_attach_device(dev, map);
2322                 dev_info(dev, "Mapped the misc device\n");
2323                 return;
2324         }
2325         dev_err(dev, "Can't Map device\n");
2326 }
2327 EXPORT_SYMBOL(tegra_smmu_map_misc_device);
2328
2329 void tegra_smmu_unmap_misc_device(struct device *dev)
2330 {
2331         if (!strncmp(dummy_name, dev_name(dev), strlen(dummy_name))) {
2332                 arm_iommu_detach_device(dev);
2333                 strncpy(dummy_name, DUMMY_DEV_NAME,
2334                         DUMMY_DEV_MAX_NAME_SIZE);
2335                 dev_info(dev, "Un-mapped the misc device\n");
2336                 return;
2337         }
2338         dev_err(dev, "Can't Unmap device\n");
2339 }
2340 EXPORT_SYMBOL(tegra_smmu_unmap_misc_device);
2341
2342 static int _tegra_smmu_get_asid(u64 swgids)
2343 {
2344         if (swgids & SWGID(PPCS))
2345                 return SYSTEM_PROTECTED;
2346
2347         if (swgids & SWGID(GPUB))
2348                 return SYSTEM_GK20A;
2349
2350 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
2351         if (swgids & SWGID(DC) ||
2352             swgids & SWGID(DCB))
2353                 return SYSTEM_DC;
2354 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
2355         if (swgids & SWGID(DC) ||
2356             swgids & SWGID(DC12))
2357                 return SYSTEM_DC;
2358         if (swgids & SWGID(DCB))
2359                 return SYSTEM_DCB;
2360 #endif
2361
2362         return SYSTEM_DEFAULT;
2363 }
2364
2365 int tegra_smmu_get_asid(struct device *dev)
2366 {
2367         u64 swgids = tegra_smmu_fixup_swgids(dev, NULL);
2368         return _tegra_smmu_get_asid(swgids);
2369 }
2370
2371 struct dma_iommu_mapping *tegra_smmu_get_map(struct device *dev, u64 swgids)
2372 {
2373         if (!swgids)
2374                 swgids = tegra_smmu_fixup_swgids(dev, NULL);
2375
2376         if (!swgids)
2377                 return NULL;
2378
2379         return smmu_default_map[_tegra_smmu_get_asid(swgids)].map;
2380 }
2381 #else
2382 static inline void tegra_smmu_map_init(struct platform_device *pdev)
2383 {
2384 }
2385 #endif
2386
2387 static int __init tegra_smmu_init(void)
2388 {
2389         platform_device_register(&tegra_smmu_device);
2390         tegra_smmu_map_init(&tegra_smmu_device);
2391         return 0;
2392 }
2393 postcore_initcall(tegra_smmu_init);
2394 #endif
2395
2396 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2397 #define CLK_RESET_RST_SOURCE    0x0
2398 static struct resource tegra_wdt_resources[] = {
2399         [0] = {
2400                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
2401                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
2402                 .flags  = IORESOURCE_MEM,
2403         },
2404         [1] = {
2405                 .start  = TEGRA_TMR1_BASE,
2406                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
2407                 .flags  = IORESOURCE_MEM,
2408         },
2409         [2] = {
2410                 .start  = TEGRA_PMC_BASE,
2411                 .end    = TEGRA_PMC_BASE + TEGRA_PMC_SIZE - 1,
2412                 .flags  = IORESOURCE_MEM,
2413         },
2414         [3] = {
2415                 .start  = INT_TMR1,
2416                 .end    = INT_TMR1,
2417                 .flags  = IORESOURCE_IRQ,
2418         },
2419 };
2420
2421 struct platform_device tegra_wdt_device = {
2422         .name           = "tegra_wdt",
2423         .id             = -1,
2424         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
2425         .resource       = tegra_wdt_resources,
2426 };
2427 #else
2428 static struct resource tegra_wdt0_resources[] = {
2429         [0] = {
2430                 .start  = TEGRA_WDT0_BASE,
2431                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
2432                 .flags  = IORESOURCE_MEM,
2433         },
2434         [1] = {
2435                 .start  = TEGRA_TMR7_BASE,
2436                 .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
2437                 .flags  = IORESOURCE_MEM,
2438         },
2439         [2] = {
2440                 .start  = TEGRA_PMC_BASE,
2441                 .end    = TEGRA_PMC_BASE + TEGRA_PMC_SIZE - 1,
2442                 .flags  = IORESOURCE_MEM,
2443         },
2444         [3] = {
2445                 .start  = INT_WDT_CPU,
2446                 .end    = INT_WDT_CPU,
2447                 .flags  = IORESOURCE_IRQ,
2448         },
2449 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
2450         [4] = {
2451                 .start  = TEGRA_QUATERNARY_ICTLR_BASE,
2452                 .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
2453                                 TEGRA_QUATERNARY_ICTLR_SIZE -1,
2454                 .flags  = IORESOURCE_MEM,
2455         },
2456 #endif
2457 #if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \
2458         defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER)
2459         [5] = {
2460                 .start  = TEGRA_WDT4_BASE,
2461                 .end    = TEGRA_WDT4_BASE + TEGRA_WDT4_SIZE - 1,
2462                 .flags  = IORESOURCE_MEM,
2463         },
2464         [6] = {
2465                 .start  = INT_WDT_AVP,
2466                 .end    = INT_WDT_AVP,
2467                 .flags  = IORESOURCE_IRQ,
2468         },
2469 #endif
2470 };
2471
2472 struct platform_device tegra_wdt0_device = {
2473         .name           = "tegra_wdt",
2474         .id             = 0,
2475         .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
2476         .resource       = tegra_wdt0_resources,
2477 };
2478
2479 #endif
2480
2481 static struct resource tegra_pwfm_resource = {
2482         .start  = TEGRA_PWFM_BASE,
2483         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
2484         .flags  = IORESOURCE_MEM,
2485 };
2486
2487 struct platform_device tegra_pwfm_device = {
2488         .name           = "tegra-pwm",
2489         .id             = -1,
2490         .num_resources  = 1,
2491         .resource       = &tegra_pwfm_resource,
2492 };
2493
2494 static struct tegra_avp_platform_data tegra_avp_pdata = {
2495 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2496         .emc_clk_rate = ULONG_MAX,
2497 #else
2498         .emc_clk_rate = 200000000,
2499 #endif
2500 };
2501
2502 struct resource tegra_nvavp_resources[] = {
2503         [0] = {
2504                 .start  = INT_SHR_SEM_INBOX_IBF,
2505                 .end    = INT_SHR_SEM_INBOX_IBF,
2506                 .flags  = IORESOURCE_IRQ,
2507                 .name   = "mbox_from_nvavp_pending",
2508         },
2509 };
2510
2511 struct platform_device nvavp_device = {
2512         .name           = "nvavp",
2513         .id             = -1,
2514         .resource       = tegra_nvavp_resources,
2515         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
2516         .dev  = {
2517                 .coherent_dma_mask      = 0xffffffffULL,
2518                 .platform_data          = &tegra_avp_pdata,
2519         },
2520 };
2521
2522 static struct resource tegra_avp_resources[] = {
2523         [0] = {
2524                 .start  = INT_SHR_SEM_INBOX_IBF,
2525                 .end    = INT_SHR_SEM_INBOX_IBF,
2526                 .flags  = IORESOURCE_IRQ,
2527                 .name   = "mbox_from_avp_pending",
2528         },
2529 };
2530
2531 struct platform_device tegra_avp_device = {
2532         .name           = "tegra-avp",
2533         .id             = -1,
2534         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
2535         .resource       = tegra_avp_resources,
2536         .dev  = {
2537                 .coherent_dma_mask      = 0xffffffffULL,
2538                 .platform_data          = &tegra_avp_pdata,
2539         },
2540 };
2541
2542 static struct resource tegra_aes_resources[] = {
2543         {
2544                 .start  = TEGRA_VDE_BASE,
2545                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
2546                 .flags  = IORESOURCE_MEM,
2547         },
2548         {
2549                 .start  = TEGRA_BSEA_BASE,
2550                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
2551                 .flags  = IORESOURCE_MEM,
2552         },
2553         {
2554                 .start  = INT_VDE_BSE_V,
2555                 .end    = INT_VDE_BSE_V,
2556                 .flags  = IORESOURCE_IRQ,
2557         },
2558         {
2559                 .start  = INT_VDE_BSE_A,
2560                 .end    = INT_VDE_BSE_A,
2561                 .flags  = IORESOURCE_IRQ,
2562         },
2563 };
2564
2565 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
2566
2567 struct platform_device tegra_aes_device = {
2568         .name           = "tegra-aes",
2569         .id             = -1,
2570         .resource       = tegra_aes_resources,
2571         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
2572         .dev    = {
2573                 .dma_mask = &tegra_aes_dma_mask,
2574                 .coherent_dma_mask = DMA_BIT_MASK(32),
2575         },
2576 };
2577
2578 static struct resource tegra_kbc_resources[] = {
2579         [0] = {
2580                 .start = TEGRA_KBC_BASE,
2581                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
2582                 .flags = IORESOURCE_MEM,
2583         },
2584         [1] = {
2585                 .start = INT_KBC,
2586                 .end   = INT_KBC,
2587                 .flags = IORESOURCE_IRQ,
2588         },
2589 };
2590
2591 struct platform_device tegra_kbc_device = {
2592         .name = "tegra-kbc",
2593         .id = -1,
2594         .resource = tegra_kbc_resources,
2595         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
2596         .dev = {
2597                 .platform_data = 0,
2598         },
2599 };
2600
2601 #if defined(CONFIG_TEGRA_SKIN_THROTTLE)
2602 struct platform_device tegra_skin_therm_est_device = {
2603         .name   = "therm_est",
2604         .id     = -1,
2605         .num_resources  = 0,
2606         .dev = {
2607                 .platform_data = 0,
2608         },
2609 };
2610 #endif
2611
2612 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
2613 static struct resource tegra_tsensor_resources[]= {
2614         {
2615                 .start  = TEGRA_TSENSOR_BASE,
2616                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
2617                 .flags  = IORESOURCE_MEM,
2618         },
2619         {
2620                 .start  = INT_TSENSOR,
2621                 .end    = INT_TSENSOR,
2622                 .flags  = IORESOURCE_IRQ,
2623         },
2624         {
2625                 .start  = TEGRA_PMC_BASE + 0x1B0,
2626                 /* 2 pmc registers mapped */
2627                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
2628                 .flags  = IORESOURCE_MEM,
2629         },
2630 };
2631
2632 struct platform_device tegra_tsensor_device = {
2633         .name   = "tegra-tsensor",
2634         .id     = -1,
2635         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
2636         .resource       = tegra_tsensor_resources,
2637         .dev = {
2638                 .platform_data = 0,
2639         },
2640 };
2641 #endif
2642
2643 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2644 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
2645 static u64 tegra12_se_dma_mask = DMA_BIT_MASK(64);
2646
2647 struct resource tegra_se_resources[] = {
2648         [0] = {
2649                 .start = TEGRA_SE_BASE,
2650                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
2651                 .flags = IORESOURCE_MEM,
2652         },
2653         [1] = {
2654                 .start  = TEGRA_PMC_BASE,
2655                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
2656                 .flags  = IORESOURCE_MEM,
2657         },
2658         [2] = {
2659                 .start = INT_SE,
2660                 .end = INT_SE,
2661                 .flags = IORESOURCE_IRQ,
2662         },
2663 };
2664
2665 struct platform_device tegra_se_device = {
2666         .name = "tegra-se",
2667         .id = -1,
2668         .dev = {
2669                 .coherent_dma_mask = DMA_BIT_MASK(32),
2670                 .dma_mask = &tegra_se_dma_mask,
2671         },
2672         .resource = tegra_se_resources,
2673         .num_resources = ARRAY_SIZE(tegra_se_resources),
2674 };
2675
2676 struct platform_device tegra11_se_device = {
2677         .name = "tegra11-se",
2678         .id = -1,
2679         .dev = {
2680                 .coherent_dma_mask = DMA_BIT_MASK(32),
2681                 .dma_mask = &tegra_se_dma_mask,
2682         },
2683         .resource = tegra_se_resources,
2684         .num_resources = ARRAY_SIZE(tegra_se_resources),
2685 };
2686
2687 struct platform_device tegra12_se_device = {
2688         .name = "tegra12-se",
2689         .id = -1,
2690         .dev = {
2691                 .coherent_dma_mask = DMA_BIT_MASK(64),
2692                 .dma_mask = &tegra12_se_dma_mask,
2693         },
2694         .resource = tegra_se_resources,
2695         .num_resources = ARRAY_SIZE(tegra_se_resources),
2696 };
2697 #endif
2698
2699 static struct resource tegra_disp1_resources[] = {
2700         {
2701                 .name   = "irq",
2702                 .start  = INT_DISPLAY_GENERAL,
2703                 .end    = INT_DISPLAY_GENERAL,
2704                 .flags  = IORESOURCE_IRQ,
2705         },
2706         {
2707                 .name   = "regs",
2708                 .start  = TEGRA_DISPLAY_BASE,
2709                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
2710                 .flags  = IORESOURCE_MEM,
2711         },
2712         {
2713                 .name   = "fbmem",
2714                 .start  = 0,
2715                 .end    = 0,
2716                 .flags  = IORESOURCE_MEM,
2717         },
2718         {
2719                 .name   = "dsi_regs",
2720                 .start  = TEGRA_DSI_BASE,
2721                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
2722                 .flags  = IORESOURCE_MEM,
2723         },
2724 };
2725
2726 struct platform_device tegra_disp1_device = {
2727         .name           = "tegradc",
2728         .id             = 0,
2729         .resource       = tegra_disp1_resources,
2730         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
2731 };
2732
2733 static struct resource tegra_disp2_resources[] = {
2734         {
2735                 .name   = "irq",
2736                 .start  = INT_DISPLAY_B_GENERAL,
2737                 .end    = INT_DISPLAY_B_GENERAL,
2738                 .flags  = IORESOURCE_IRQ,
2739         },
2740         {
2741                 .name   = "regs",
2742                 .start  = TEGRA_DISPLAY2_BASE,
2743                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
2744                 .flags  = IORESOURCE_MEM,
2745         },
2746         {
2747                 .name   = "fbmem",
2748                 .flags  = IORESOURCE_MEM,
2749                 .start  = 0,
2750                 .end    = 0,
2751         },
2752         {
2753                 .name   = "hdmi_regs",
2754                 .start  = TEGRA_HDMI_BASE,
2755                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
2756                 .flags  = IORESOURCE_MEM,
2757         },
2758 };
2759
2760 struct platform_device tegra_disp2_device = {
2761         .name           = "tegradc",
2762         .id             = 1,
2763         .resource       = tegra_disp2_resources,
2764         .num_resources  = ARRAY_SIZE(tegra_disp2_resources),
2765         .dev = {
2766                 .platform_data = 0,
2767         },
2768 };
2769
2770 struct platform_device tegra_nvmap_device = {
2771         .name   = "tegra-nvmap",
2772         .id     = -1,
2773 };
2774
2775 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2776 static struct resource tegra_cec_resources[] = {
2777         [0] = {
2778                 .start = TEGRA_CEC_BASE,
2779                 .end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
2780                 .flags = IORESOURCE_MEM,
2781         },
2782         [1] = {
2783                 .start = INT_CEC,
2784                 .end = INT_CEC,
2785                 .flags = IORESOURCE_IRQ,
2786         },
2787 };
2788
2789 struct platform_device tegra_cec_device = {
2790         .name = "tegra_cec",
2791         .id   = -1,
2792         .resource = tegra_cec_resources,
2793         .num_resources = ARRAY_SIZE(tegra_cec_resources),
2794 };
2795 #endif
2796
2797 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
2798 static struct resource cl_dvfs_resource[] = {
2799         [0] = {
2800                 .start  = TEGRA_CL_DVFS_BASE,
2801                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2802                 .flags  = IORESOURCE_MEM,
2803         }
2804 };
2805
2806 struct platform_device tegra_cl_dvfs_device = {
2807         .name           = "tegra_cl_dvfs",
2808         .id             = -1,
2809         .resource       = cl_dvfs_resource,
2810         .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
2811 };
2812 #endif
2813
2814 struct platform_device tegra_fuse_device = {
2815         .name   = "tegra-fuse",
2816         .id     = -1,
2817 };
2818
2819 #if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
2820 static struct tegra_wakeup_monitor_platform_data
2821                         tegratab_tegra_wakeup_monitor_pdata = {
2822         .wifi_wakeup_source     = 6,
2823         .rtc_wakeup_source      = 18,
2824 };
2825
2826 struct platform_device tegratab_tegra_wakeup_monitor_device = {
2827         .name = "tegra_wakeup_monitor",
2828         .id   = -1,
2829         .dev  = {
2830                 .platform_data = &tegratab_tegra_wakeup_monitor_pdata,
2831         },
2832 };
2833 #endif
2834
2835 static struct resource ptm_resources[] = {
2836         {
2837                 .name  = "ptm",
2838                 .start = PTM0_BASE,
2839                 .end   = PTM0_BASE + SZ_4K - 1,
2840                 .flags = IORESOURCE_MEM,
2841         },
2842         {
2843                 .name  = "ptm",
2844                 .start = PTM1_BASE,
2845                 .end   = PTM1_BASE + SZ_4K - 1,
2846                 .flags = IORESOURCE_MEM,
2847         },
2848         {
2849                 .name  = "ptm",
2850                 .start = PTM2_BASE,
2851                 .end   = PTM2_BASE + SZ_4K - 1,
2852                 .flags = IORESOURCE_MEM,
2853         },
2854         {
2855                 .name  = "ptm",
2856                 .start = PTM3_BASE,
2857                 .end   = PTM3_BASE + SZ_4K - 1,
2858                 .flags = IORESOURCE_MEM,
2859         },
2860         {
2861                 .name  = "etb",
2862                 .start = ETB_BASE,
2863                 .end   = ETB_BASE + SZ_4K - 1,
2864                 .flags = IORESOURCE_MEM,
2865         },
2866         {
2867                 .name  = "funnel",
2868                 .start = FUNNEL_BASE,
2869                 .end   = FUNNEL_BASE + SZ_4K - 1,
2870                 .flags = IORESOURCE_MEM,
2871         },
2872         {
2873                 .name  = "tpiu",
2874                 .start = TPIU_BASE,
2875                 .end   = TPIU_BASE + SZ_4K - 1,
2876                 .flags = IORESOURCE_MEM,
2877         },
2878 };
2879
2880 struct platform_device tegra_ptm_device = {
2881         .name          = "ptm",
2882         .id            = -1,
2883         .num_resources = ARRAY_SIZE(ptm_resources),
2884         .resource      = ptm_resources,
2885 };
2886
2887 void __init tegra_init_debug_uart_rate(void)
2888 {
2889         unsigned int uartclk;
2890         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
2891
2892         BUG_ON(IS_ERR(debug_uart_parent));
2893         uartclk = clk_get_rate(debug_uart_parent);
2894
2895         debug_uarta_platform_data[0].uartclk = uartclk;
2896         debug_uartb_platform_data[0].uartclk = uartclk;
2897         debug_uartc_platform_data[0].uartclk = uartclk;
2898         debug_uartd_platform_data[0].uartclk = uartclk;
2899 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2900         debug_uarte_platform_data[0].uartclk = uartclk;
2901 #endif
2902 }