ARM: Build fix after Tegra14 K3.4 merge
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/platform_data/tegra_usb.h>
28 #include <linux/tegra_avp.h>
29 #include <linux/nvhost.h>
30 #include <linux/clk.h>
31 #include <mach/irqs.h>
32 #include <linux/usb/tegra_usb_phy.h>
33 #include <mach/tegra_smmu.h>
34
35 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
36 #include <asm/dma-iommu.h>
37 #endif
38
39 #include "gpio-names.h"
40 #include "iomap.h"
41 #include "devices.h"
42
43 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
44 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
45 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
46 #define TEGRA_DMA_REQ_SEL_SPI                   11
47 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
48
49 static struct resource emc_resource[] = {
50         [0] = {
51                 .start  = TEGRA_EMC_BASE,
52                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
53                 .flags  = IORESOURCE_MEM,
54         }
55 };
56
57 struct platform_device tegra_emc_device = {
58         .name           = "tegra-emc",
59         .id             = -1,
60         .resource       = emc_resource,
61         .num_resources  = ARRAY_SIZE(emc_resource),
62 };
63
64 static struct resource gpio_resource[] = {
65         [0] = {
66                 .start  = TEGRA_GPIO_BASE,
67                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
68                 .flags  = IORESOURCE_MEM,
69         },
70         [1] = {
71                 .start  = INT_GPIO1,
72                 .end    = INT_GPIO1,
73                 .flags  = IORESOURCE_IRQ,
74         },
75         [2] = {
76                 .start  = INT_GPIO2,
77                 .end    = INT_GPIO2,
78                 .flags  = IORESOURCE_IRQ,
79         },
80         [3] = {
81                 .start  = INT_GPIO3,
82                 .end    = INT_GPIO3,
83                 .flags  = IORESOURCE_IRQ,
84         },
85         [4] = {
86                 .start  = INT_GPIO4,
87                 .end    = INT_GPIO4,
88                 .flags  = IORESOURCE_IRQ,
89         },
90         [5] = {
91                 .start  = INT_GPIO5,
92                 .end    = INT_GPIO5,
93                 .flags  = IORESOURCE_IRQ,
94         },
95         [6] = {
96                 .start  = INT_GPIO6,
97                 .end    = INT_GPIO6,
98                 .flags  = IORESOURCE_IRQ,
99         },
100         [7] = {
101                 .start  = INT_GPIO7,
102                 .end    = INT_GPIO7,
103                 .flags  = IORESOURCE_IRQ,
104         },
105 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
106         [8] = {
107                 .start  = INT_GPIO8,
108                 .end    = INT_GPIO8,
109                 .flags  = IORESOURCE_IRQ,
110         },
111 #endif
112 };
113
114 struct platform_device tegra_gpio_device = {
115         .name           = "tegra-gpio",
116         .id             = -1,
117         .resource       = gpio_resource,
118         .num_resources  = ARRAY_SIZE(gpio_resource),
119 };
120
121 static struct resource pinmux_resource[] = {
122 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
123         [0] = {
124                 /* Tri-state registers */
125                 .start  = TEGRA_APB_MISC_BASE + 0x14,
126                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
127                 .flags  = IORESOURCE_MEM,
128         },
129         [1] = {
130                 /* Mux registers */
131                 .start  = TEGRA_APB_MISC_BASE + 0x80,
132                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
133                 .flags  = IORESOURCE_MEM,
134         },
135         [2] = {
136                 /* Pull-up/down registers */
137                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
138                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
139                 .flags  = IORESOURCE_MEM,
140         },
141         [3] = {
142                 /* Pad control registers */
143                 .start  = TEGRA_APB_MISC_BASE + 0x868,
144                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
145                 .flags  = IORESOURCE_MEM,
146         },
147 #else
148         [0] = {
149                 /* Drive registers */
150                 .start  = TEGRA_APB_MISC_BASE + 0x868,
151                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
152                 .flags  = IORESOURCE_MEM,
153         },
154         [1] = {
155                 /* Mux registers */
156                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
157                 .end    = TEGRA_APB_MISC_BASE + 0x33e0 + 3,
158                 .flags  = IORESOURCE_MEM,
159         },
160 #endif
161 };
162
163 struct platform_device tegra_pinmux_device = {
164 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
165         .name           = "tegra30-pinmux-ctl",
166 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
167         .name           = "tegra20-pinmux-ctl",
168 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
169         .name           = "tegra11x-pinmux-ctl",
170 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
171         .name           = "tegra14x-pinmux",
172 #endif
173         .id             = -1,
174         .resource       = pinmux_resource,
175         .num_resources  = ARRAY_SIZE(pinmux_resource),
176 };
177
178 static struct resource i2c_resource1[] = {
179         [0] = {
180                 .start  = INT_I2C,
181                 .end    = INT_I2C,
182                 .flags  = IORESOURCE_IRQ,
183         },
184         [1] = {
185                 .start  = TEGRA_I2C_BASE,
186                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
187                 .flags  = IORESOURCE_MEM,
188         },
189 };
190
191 static struct resource i2c_resource2[] = {
192         [0] = {
193                 .start  = INT_I2C2,
194                 .end    = INT_I2C2,
195                 .flags  = IORESOURCE_IRQ,
196         },
197         [1] = {
198                 .start  = TEGRA_I2C2_BASE,
199                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
200                 .flags  = IORESOURCE_MEM,
201         },
202 };
203
204 static struct resource i2c_resource3[] = {
205         [0] = {
206                 .start  = INT_I2C3,
207                 .end    = INT_I2C3,
208                 .flags  = IORESOURCE_IRQ,
209         },
210         [1] = {
211                 .start  = TEGRA_I2C3_BASE,
212                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
213                 .flags  = IORESOURCE_MEM,
214         },
215 };
216
217 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
218 static struct resource i2c_resource4[] = {
219         [0] = {
220                 .start  = INT_DVC,
221                 .end    = INT_DVC,
222                 .flags  = IORESOURCE_IRQ,
223         },
224         [1] = {
225                 .start  = TEGRA_DVC_BASE,
226                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
227                 .flags  = IORESOURCE_MEM,
228         },
229 };
230
231 #else
232 static struct resource i2c_resource4[] = {
233         [0] = {
234                 .start  = INT_I2C4,
235                 .end    = INT_I2C4,
236                 .flags  = IORESOURCE_IRQ,
237         },
238         [1] = {
239                 .start  = TEGRA_I2C4_BASE,
240                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
241                 .flags  = IORESOURCE_MEM,
242         },
243 };
244
245 static struct resource i2c_resource5[] = {
246         [0] = {
247                 .start  = INT_I2C5,
248                 .end    = INT_I2C5,
249                 .flags  = IORESOURCE_IRQ,
250         },
251         [1] = {
252                 .start  = TEGRA_I2C5_BASE,
253                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
254                 .flags  = IORESOURCE_MEM,
255         },
256 };
257 #endif
258
259 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
260         .bus_clk_rate   = 400000,
261 };
262
263 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
264         .bus_clk_rate   = 400000,
265 };
266
267 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
268         .bus_clk_rate   = 400000,
269 };
270
271 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
272         .bus_clk_rate   = 400000,
273 };
274
275 struct platform_device tegra_i2c_device1 = {
276         .name           = "tegra-i2c",
277         .id             = 0,
278         .resource       = i2c_resource1,
279         .num_resources  = ARRAY_SIZE(i2c_resource1),
280         .dev = {
281                 .platform_data = &tegra_i2c1_platform_data,
282         },
283 };
284
285 struct platform_device tegra_i2c_device2 = {
286         .name           = "tegra-i2c",
287         .id             = 1,
288         .resource       = i2c_resource2,
289         .num_resources  = ARRAY_SIZE(i2c_resource2),
290         .dev = {
291                 .platform_data = &tegra_i2c2_platform_data,
292         },
293 };
294
295 struct platform_device tegra_i2c_device3 = {
296         .name           = "tegra-i2c",
297         .id             = 2,
298         .resource       = i2c_resource3,
299         .num_resources  = ARRAY_SIZE(i2c_resource3),
300         .dev = {
301                 .platform_data = &tegra_i2c3_platform_data,
302         },
303 };
304
305 struct platform_device tegra_i2c_device4 = {
306         .name           = "tegra-i2c",
307         .id             = 3,
308         .resource       = i2c_resource4,
309         .num_resources  = ARRAY_SIZE(i2c_resource4),
310         .dev = {
311                 .platform_data = &tegra_dvc_platform_data,
312         },
313 };
314
315 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
316 struct platform_device tegra_i2c_device5 = {
317         .name           = "tegra-i2c",
318         .id             = 4,
319         .resource       = i2c_resource5,
320         .num_resources  = ARRAY_SIZE(i2c_resource5),
321         .dev = {
322                 .platform_data = 0,
323         },
324 };
325 #endif
326
327 struct platform_device tegra11_i2c_device1 = {
328         .name           = "tegra11-i2c",
329         .id             = 0,
330         .resource       = i2c_resource1,
331         .num_resources  = ARRAY_SIZE(i2c_resource1),
332         .dev = {
333                 .platform_data = 0,
334         },
335 };
336
337 struct platform_device tegra11_i2c_device2 = {
338         .name           = "tegra11-i2c",
339         .id             = 1,
340         .resource       = i2c_resource2,
341         .num_resources  = ARRAY_SIZE(i2c_resource2),
342         .dev = {
343                 .platform_data = 0,
344         },
345 };
346
347 struct platform_device tegra11_i2c_device3 = {
348         .name           = "tegra11-i2c",
349         .id             = 2,
350         .resource       = i2c_resource3,
351         .num_resources  = ARRAY_SIZE(i2c_resource3),
352         .dev = {
353                 .platform_data = 0,
354         },
355 };
356
357 struct platform_device tegra11_i2c_device4 = {
358         .name           = "tegra11-i2c",
359         .id             = 3,
360         .resource       = i2c_resource4,
361         .num_resources  = ARRAY_SIZE(i2c_resource4),
362         .dev = {
363                 .platform_data = 0,
364         },
365 };
366
367 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
368 struct platform_device tegra11_i2c_device5 = {
369         .name           = "tegra11-i2c",
370         .id             = 4,
371         .resource       = i2c_resource5,
372         .num_resources  = ARRAY_SIZE(i2c_resource5),
373         .dev = {
374                 .platform_data = 0,
375         },
376 };
377 #endif
378
379 static struct resource spi_resource1[] = {
380         [0] = {
381                 .start  = INT_SPI_1,
382                 .end    = INT_SPI_1,
383                 .flags  = IORESOURCE_IRQ,
384         },
385         [1] = {
386                 .start  = TEGRA_SPI1_BASE,
387                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
388                 .flags  = IORESOURCE_MEM,
389         },
390 };
391
392 static struct resource spi_resource2[] = {
393         [0] = {
394                 .start  = INT_SPI_2,
395                 .end    = INT_SPI_2,
396                 .flags  = IORESOURCE_IRQ,
397         },
398         [1] = {
399                 .start  = TEGRA_SPI2_BASE,
400                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
401                 .flags  = IORESOURCE_MEM,
402         },
403 };
404
405 static struct resource spi_resource3[] = {
406         [0] = {
407                 .start  = INT_SPI_3,
408                 .end    = INT_SPI_3,
409                 .flags  = IORESOURCE_IRQ,
410         },
411         [1] = {
412                 .start  = TEGRA_SPI3_BASE,
413                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
414                 .flags  = IORESOURCE_MEM,
415         },
416 };
417
418 static struct resource spi_resource4[] = {
419         [0] = {
420                 .start  = INT_SPI_4,
421                 .end    = INT_SPI_4,
422                 .flags  = IORESOURCE_IRQ,
423         },
424         [1] = {
425                 .start  = TEGRA_SPI4_BASE,
426                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
427                 .flags  = IORESOURCE_MEM,
428         },
429 };
430 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
431 static struct resource spi_resource5[] = {
432         [0] = {
433                 .start  = INT_SPI_5,
434                 .end    = INT_SPI_5,
435                 .flags  = IORESOURCE_IRQ,
436         },
437         [1] = {
438                 .start  = TEGRA_SPI5_BASE,
439                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
440                 .flags  = IORESOURCE_MEM,
441         },
442 };
443
444 static struct resource spi_resource6[] = {
445         [0] = {
446                 .start  = INT_SPI_6,
447                 .end    = INT_SPI_6,
448                 .flags  = IORESOURCE_IRQ,
449         },
450         [1] = {
451                 .start  = TEGRA_SPI6_BASE,
452                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
453                 .flags  = IORESOURCE_MEM,
454         },
455 };
456 #endif
457
458 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
459 static struct resource dtv_resource[] = {
460         [0] = {
461                 .start  = INT_DTV,
462                 .end    = INT_DTV,
463                 .flags  = IORESOURCE_IRQ,
464         },
465         [1] = {
466                 .start  = TEGRA_DTV_BASE,
467                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
468                 .flags  = IORESOURCE_MEM,
469         },
470         [2] = {
471                 .start  = TEGRA_DMA_REQ_SEL_DTV,
472                 .end    = TEGRA_DMA_REQ_SEL_DTV,
473                 .flags  = IORESOURCE_DMA
474         },
475 };
476 #endif
477
478
479 struct platform_device tegra_spi_device1 = {
480         .name           = "spi_tegra",
481         .id             = 0,
482         .resource       = spi_resource1,
483         .num_resources  = ARRAY_SIZE(spi_resource1),
484         .dev            = {
485                 .coherent_dma_mask      = 0xffffffff,
486         },
487 };
488
489 struct platform_device tegra_spi_device2 = {
490         .name           = "spi_tegra",
491         .id             = 1,
492         .resource       = spi_resource2,
493         .num_resources  = ARRAY_SIZE(spi_resource2),
494         .dev            = {
495                 .coherent_dma_mask      = 0xffffffff,
496         },
497 };
498
499 struct platform_device tegra_spi_device3 = {
500         .name           = "spi_tegra",
501         .id             = 2,
502         .resource       = spi_resource3,
503         .num_resources  = ARRAY_SIZE(spi_resource3),
504         .dev            = {
505                 .coherent_dma_mask      = 0xffffffff,
506         },
507 };
508
509 struct platform_device tegra_spi_device4 = {
510         .name           = "spi_tegra",
511         .id             = 3,
512         .resource       = spi_resource4,
513         .num_resources  = ARRAY_SIZE(spi_resource4),
514         .dev            = {
515                 .coherent_dma_mask      = 0xffffffff,
516         },
517 };
518 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
519 struct platform_device tegra_spi_device5 = {
520         .name           = "spi_tegra",
521         .id             = 4,
522         .resource       = spi_resource5,
523         .num_resources  = ARRAY_SIZE(spi_resource5),
524         .dev  = {
525                 .coherent_dma_mask      = 0xffffffff,
526         },
527 };
528
529 struct platform_device tegra_spi_device6 = {
530         .name           = "spi_tegra",
531         .id             = 5,
532         .resource       = spi_resource6,
533         .num_resources  = ARRAY_SIZE(spi_resource6),
534         .dev  = {
535                 .coherent_dma_mask      = 0xffffffff,
536         },
537 };
538 #endif
539
540 struct platform_device tegra11_spi_device1 = {
541         .name           = "tegra11-spi",
542         .id             = 0,
543         .resource       = spi_resource1,
544         .num_resources  = ARRAY_SIZE(spi_resource1),
545         .dev            = {
546                 .coherent_dma_mask      = 0xffffffff,
547         },
548 };
549
550 struct platform_device tegra11_spi_device2 = {
551         .name           = "tegra11-spi",
552         .id             = 1,
553         .resource       = spi_resource2,
554         .num_resources  = ARRAY_SIZE(spi_resource2),
555         .dev            = {
556                 .coherent_dma_mask      = 0xffffffff,
557         },
558 };
559
560 struct platform_device tegra11_spi_device3 = {
561         .name           = "tegra11-spi",
562         .id             = 2,
563         .resource       = spi_resource3,
564         .num_resources  = ARRAY_SIZE(spi_resource3),
565         .dev            = {
566                 .coherent_dma_mask      = 0xffffffff,
567         },
568 };
569
570 struct platform_device tegra11_spi_device4 = {
571         .name           = "tegra11-spi",
572         .id             = 3,
573         .resource       = spi_resource4,
574         .num_resources  = ARRAY_SIZE(spi_resource4),
575         .dev            = {
576                 .coherent_dma_mask      = 0xffffffff,
577         },
578 };
579
580 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
581 struct platform_device tegra11_spi_device5 = {
582         .name           = "tegra11-spi",
583         .id             = 4,
584         .resource       = spi_resource5,
585         .num_resources  = ARRAY_SIZE(spi_resource5),
586         .dev  = {
587                 .coherent_dma_mask      = 0xffffffff,
588         },
589 };
590
591 struct platform_device tegra11_spi_device6 = {
592         .name           = "tegra11-spi",
593         .id             = 5,
594         .resource       = spi_resource6,
595         .num_resources  = ARRAY_SIZE(spi_resource6),
596         .dev  = {
597                 .coherent_dma_mask      = 0xffffffff,
598         },
599 };
600 #endif
601
602 struct platform_device tegra_spi_slave_device1 = {
603         .name           = "spi_slave_tegra",
604         .id             = 0,
605         .resource       = spi_resource1,
606         .num_resources  = ARRAY_SIZE(spi_resource1),
607         .dev  = {
608                 .coherent_dma_mask      = 0xffffffff,
609         },
610 };
611
612 struct platform_device tegra_spi_slave_device2 = {
613         .name           = "spi_slave_tegra",
614         .id             = 1,
615         .resource       = spi_resource2,
616         .num_resources  = ARRAY_SIZE(spi_resource2),
617         .dev  = {
618                 .coherent_dma_mask      = 0xffffffff,
619         },
620 };
621
622 struct platform_device tegra_spi_slave_device3 = {
623         .name           = "spi_slave_tegra",
624         .id             = 2,
625         .resource       = spi_resource3,
626         .num_resources  = ARRAY_SIZE(spi_resource3),
627         .dev  = {
628                 .coherent_dma_mask      = 0xffffffff,
629         },
630 };
631
632 struct platform_device tegra_spi_slave_device4 = {
633         .name           = "spi_slave_tegra",
634         .id             = 3,
635         .resource       = spi_resource4,
636         .num_resources  = ARRAY_SIZE(spi_resource4),
637         .dev  = {
638                 .coherent_dma_mask      = 0xffffffff,
639         },
640 };
641 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
642 struct platform_device tegra_spi_slave_device5 = {
643         .name           = "spi_slave_tegra",
644         .id             = 4,
645         .resource       = spi_resource5,
646         .num_resources  = ARRAY_SIZE(spi_resource5),
647         .dev  = {
648                 .coherent_dma_mask      = 0xffffffff,
649         },
650 };
651
652 struct platform_device tegra_spi_slave_device6 = {
653         .name           = "spi_slave_tegra",
654         .id             = 5,
655         .resource       = spi_resource6,
656         .num_resources  = ARRAY_SIZE(spi_resource6),
657         .dev  = {
658                 .coherent_dma_mask      = 0xffffffff,
659         },
660 };
661 #endif
662
663 struct platform_device tegra11_spi_slave_device1 = {
664         .name           = "tegra11-spi-slave",
665         .id             = 0,
666         .resource       = spi_resource1,
667         .num_resources  = ARRAY_SIZE(spi_resource1),
668         .dev  = {
669                 .coherent_dma_mask      = 0xffffffff,
670         },
671 };
672
673 struct platform_device tegra11_spi_slave_device2 = {
674         .name           = "tegra11-spi-slave",
675         .id             = 1,
676         .resource       = spi_resource2,
677         .num_resources  = ARRAY_SIZE(spi_resource2),
678         .dev  = {
679                 .coherent_dma_mask      = 0xffffffff,
680         },
681 };
682
683 struct platform_device tegra11_spi_slave_device3 = {
684         .name           = "tegra11-spi-slave",
685         .id             = 2,
686         .resource       = spi_resource3,
687         .num_resources  = ARRAY_SIZE(spi_resource3),
688         .dev  = {
689                 .coherent_dma_mask      = 0xffffffff,
690         },
691 };
692
693 struct platform_device tegra11_spi_slave_device4 = {
694         .name           = "tegra11-spi-slave",
695         .id             = 3,
696         .resource       = spi_resource4,
697         .num_resources  = ARRAY_SIZE(spi_resource4),
698         .dev  = {
699                 .coherent_dma_mask      = 0xffffffff,
700         },
701 };
702 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
703 struct platform_device tegra11_spi_slave_device5 = {
704         .name           = "tegra11-spi-slave",
705         .id             = 4,
706         .resource       = spi_resource5,
707         .num_resources  = ARRAY_SIZE(spi_resource5),
708         .dev  = {
709                 .coherent_dma_mask      = 0xffffffff,
710         },
711 };
712
713 struct platform_device tegra11_spi_slave_device6 = {
714         .name           = "tegra11-spi-slave",
715         .id             = 5,
716         .resource       = spi_resource6,
717         .num_resources  = ARRAY_SIZE(spi_resource6),
718         .dev  = {
719                 .coherent_dma_mask      = 0xffffffff,
720         },
721 };
722 #endif
723
724 static struct resource resources_nor[] = {
725         [0] = {
726                 .start = INT_SNOR,
727                 .end = INT_SNOR,
728                 .flags = IORESOURCE_IRQ,
729         },
730         [1] = {
731                 /* Map SNOR Controller */
732                 .start = TEGRA_SNOR_BASE,
733                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
734                 .flags = IORESOURCE_MEM,
735         },
736         [2] = {
737                 /* Map the size of flash */
738                 .start = TEGRA_NOR_FLASH_BASE,
739                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
740                 .flags = IORESOURCE_MEM,
741         }
742 };
743
744 struct platform_device tegra_nor_device = {
745         .name = "tegra-nor",
746         .id = -1,
747         .num_resources = ARRAY_SIZE(resources_nor),
748         .resource = resources_nor,
749         .dev = {
750                 .coherent_dma_mask = 0xffffffff,
751         },
752 };
753
754 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
755 struct platform_device tegra_dtv_device = {
756         .name           = "tegra_dtv",
757         .id             = -1,
758         .resource       = dtv_resource,
759         .num_resources  = ARRAY_SIZE(dtv_resource),
760         .dev = {
761                 .init_name = "dtv",
762                 .coherent_dma_mask = 0xffffffff,
763         },
764 };
765 #endif
766
767 static struct resource sdhci_resource1[] = {
768         [0] = {
769                 .start  = INT_SDMMC1,
770                 .end    = INT_SDMMC1,
771                 .flags  = IORESOURCE_IRQ,
772         },
773         [1] = {
774                 .start  = TEGRA_SDMMC1_BASE,
775                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
776                 .flags  = IORESOURCE_MEM,
777         },
778 };
779
780 static struct resource sdhci_resource2[] = {
781         [0] = {
782                 .start  = INT_SDMMC2,
783                 .end    = INT_SDMMC2,
784                 .flags  = IORESOURCE_IRQ,
785         },
786         [1] = {
787                 .start  = TEGRA_SDMMC2_BASE,
788                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
789                 .flags  = IORESOURCE_MEM,
790         },
791 };
792
793 static struct resource sdhci_resource3[] = {
794         [0] = {
795                 .start  = INT_SDMMC3,
796                 .end    = INT_SDMMC3,
797                 .flags  = IORESOURCE_IRQ,
798         },
799         [1] = {
800                 .start  = TEGRA_SDMMC3_BASE,
801                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
802                 .flags  = IORESOURCE_MEM,
803         },
804 };
805
806 static struct resource sdhci_resource4[] = {
807         [0] = {
808                 .start  = INT_SDMMC4,
809                 .end    = INT_SDMMC4,
810                 .flags  = IORESOURCE_IRQ,
811         },
812         [1] = {
813                 .start  = TEGRA_SDMMC4_BASE,
814                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
815                 .flags  = IORESOURCE_MEM,
816         },
817 };
818
819 struct platform_device tegra_pci_device = {
820         .name           = "tegra-pcie",
821         .id             = 0,
822         .resource       = 0,
823         .num_resources  = 0,
824         .dev = {
825                 .platform_data = 0,
826         },
827 };
828
829 /* board files should fill in platform_data register the devices themselvs.
830  * See board-harmony.c for an example
831  */
832 struct platform_device tegra_sdhci_device1 = {
833         .name           = "sdhci-tegra",
834         .id             = 0,
835         .resource       = sdhci_resource1,
836         .num_resources  = ARRAY_SIZE(sdhci_resource1),
837 };
838
839 struct platform_device tegra_sdhci_device2 = {
840         .name           = "sdhci-tegra",
841         .id             = 1,
842         .resource       = sdhci_resource2,
843         .num_resources  = ARRAY_SIZE(sdhci_resource2),
844 };
845
846 struct platform_device tegra_sdhci_device3 = {
847         .name           = "sdhci-tegra",
848         .id             = 2,
849         .resource       = sdhci_resource3,
850         .num_resources  = ARRAY_SIZE(sdhci_resource3),
851 };
852
853 struct platform_device tegra_sdhci_device4 = {
854         .name           = "sdhci-tegra",
855         .id             = 3,
856         .resource       = sdhci_resource4,
857         .num_resources  = ARRAY_SIZE(sdhci_resource4),
858 };
859
860 static struct resource tegra_usb1_resources[] = {
861         [0] = {
862                 .start  = TEGRA_USB_BASE,
863                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
864                 .flags  = IORESOURCE_MEM,
865         },
866         [1] = {
867                 .start  = INT_USB,
868                 .end    = INT_USB,
869                 .flags  = IORESOURCE_IRQ,
870         },
871 };
872
873 static struct resource tegra_usb2_resources[] = {
874         [0] = {
875                 .start  = TEGRA_USB2_BASE,
876                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
877                 .flags  = IORESOURCE_MEM,
878         },
879         [1] = {
880                 .start  = INT_USB2,
881                 .end    = INT_USB2,
882                 .flags  = IORESOURCE_IRQ,
883         },
884 };
885
886 static struct resource tegra_usb3_resources[] = {
887         [0] = {
888                 .start  = TEGRA_USB3_BASE,
889                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
890                 .flags  = IORESOURCE_MEM,
891         },
892         [1] = {
893                 .start  = INT_USB3,
894                 .end    = INT_USB3,
895                 .flags  = IORESOURCE_IRQ,
896         },
897 };
898
899 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
900 static struct resource tegra_xusb_resources[] = {
901         [0] = {
902                 .start  = TEGRA_XUSB_HOST_BASE,
903                 .end    = TEGRA_XUSB_HOST_BASE + TEGRA_XUSB_HOST_SIZE - 1,
904                 .flags  = IORESOURCE_MEM,
905         },
906         [1] = {
907                 .start  = INT_USB3_HOST_INT,
908                 .end    = INT_USB3_HOST_INT,
909                 .flags  = IORESOURCE_IRQ,
910         },
911         [2] = {
912                 .start  = INT_USB3_NOT_SMI,
913                 .end    = INT_USB3_NOT_SMI,
914                 .flags  = IORESOURCE_IRQ,
915         },
916         [3] = {
917                 .start  = INT_XUSB_PADCTL,
918                 .end    = INT_XUSB_PADCTL,
919                 .flags  = IORESOURCE_IRQ,
920         },
921 };
922
923 static u64 tegra_xusb_dmamask = DMA_BIT_MASK(64);
924
925 struct platform_device tegra_xhci_device = {
926         .name = "tegra-xhci",
927         .id = -1,
928         .dev = {
929                 .dma_mask = &tegra_xusb_dmamask,
930                 .coherent_dma_mask = DMA_BIT_MASK(64),
931         },
932         .resource = tegra_xusb_resources,
933         .num_resources = ARRAY_SIZE(tegra_xusb_resources),
934 };
935 #endif
936
937 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
938
939 struct platform_device tegra_ehci1_device = {
940         .name   = "tegra-ehci",
941         .id     = 0,
942         .dev    = {
943                 .dma_mask       = &tegra_ehci_dmamask,
944                 .coherent_dma_mask = DMA_BIT_MASK(32),
945         },
946         .resource = tegra_usb1_resources,
947         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
948 };
949
950 struct platform_device tegra_ehci2_device = {
951         .name   = "tegra-ehci",
952         .id     = 1,
953         .dev    = {
954                 .dma_mask       = &tegra_ehci_dmamask,
955                 .coherent_dma_mask = DMA_BIT_MASK(32),
956         },
957         .resource = tegra_usb2_resources,
958         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
959 };
960
961 struct platform_device tegra_ehci3_device = {
962         .name   = "tegra-ehci",
963         .id     = 2,
964         .dev    = {
965                 .dma_mask       = &tegra_ehci_dmamask,
966                 .coherent_dma_mask = DMA_BIT_MASK(32),
967         },
968         .resource = tegra_usb3_resources,
969         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
970 };
971
972 static struct resource tegra_pmu_resources[] = {
973         [0] = {
974                 .start  = INT_CPU0_PMU_INTR,
975                 .end    = INT_CPU0_PMU_INTR,
976                 .flags  = IORESOURCE_IRQ,
977         },
978         [1] = {
979                 .start  = INT_CPU1_PMU_INTR,
980                 .end    = INT_CPU1_PMU_INTR,
981                 .flags  = IORESOURCE_IRQ,
982         },
983 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
984         [2] = {
985                 .start  = INT_CPU2_PMU_INTR,
986                 .end    = INT_CPU2_PMU_INTR,
987                 .flags  = IORESOURCE_IRQ,
988         },
989         [3] = {
990                 .start  = INT_CPU3_PMU_INTR,
991                 .end    = INT_CPU3_PMU_INTR,
992                 .flags  = IORESOURCE_IRQ,
993         },
994 #endif
995 };
996
997 struct platform_device tegra_pmu_device = {
998         .name           = "arm-pmu",
999         .id             = -1,
1000         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
1001         .resource       = tegra_pmu_resources,
1002 };
1003
1004 static struct resource tegra_uarta_resources[] = {
1005         [0] = {
1006                 .start  = TEGRA_UARTA_BASE,
1007                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
1008                 .flags  = IORESOURCE_MEM,
1009         },
1010         [1] = {
1011                 .start  = INT_UARTA,
1012                 .end    = INT_UARTA,
1013                 .flags  = IORESOURCE_IRQ,
1014         },
1015 };
1016
1017 static struct resource tegra_uartb_resources[] = {
1018         [0] = {
1019                 .start  = TEGRA_UARTB_BASE,
1020                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
1021                 .flags  = IORESOURCE_MEM,
1022         },
1023         [1] = {
1024                 .start  = INT_UARTB,
1025                 .end    = INT_UARTB,
1026                 .flags  = IORESOURCE_IRQ,
1027         },
1028 };
1029
1030 static struct resource tegra_uartc_resources[] = {
1031         [0] = {
1032                 .start  = TEGRA_UARTC_BASE,
1033                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
1034                 .flags  = IORESOURCE_MEM,
1035         },
1036         [1] = {
1037                 .start  = INT_UARTC,
1038                 .end    = INT_UARTC,
1039                 .flags  = IORESOURCE_IRQ,
1040         },
1041 };
1042
1043 static struct resource tegra_uartd_resources[] = {
1044         [0] = {
1045                 .start  = TEGRA_UARTD_BASE,
1046                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
1047                 .flags  = IORESOURCE_MEM,
1048         },
1049         [1] = {
1050                 .start  = INT_UARTD,
1051                 .end    = INT_UARTD,
1052                 .flags  = IORESOURCE_IRQ,
1053         },
1054 };
1055
1056 static struct resource tegra_uarte_resources[] = {
1057         [0] = {
1058                 .start  = TEGRA_UARTE_BASE,
1059                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
1060                 .flags  = IORESOURCE_MEM,
1061         },
1062         [1] = {
1063                 .start  = INT_UARTE,
1064                 .end    = INT_UARTE,
1065                 .flags  = IORESOURCE_IRQ,
1066         },
1067 };
1068
1069 struct platform_device tegra_uarta_device = {
1070         .name   = "tegra_uart",
1071         .id     = 0,
1072         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
1073         .resource       = tegra_uarta_resources,
1074         .dev    = {
1075                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1076         },
1077 };
1078
1079 struct platform_device tegra_uartb_device = {
1080         .name   = "tegra_uart",
1081         .id     = 1,
1082         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
1083         .resource       = tegra_uartb_resources,
1084         .dev    = {
1085                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1086         },
1087 };
1088
1089 struct platform_device tegra_uartc_device = {
1090         .name   = "tegra_uart",
1091         .id     = 2,
1092         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
1093         .resource       = tegra_uartc_resources,
1094         .dev    = {
1095                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1096         },
1097 };
1098
1099 struct platform_device tegra_uartd_device = {
1100         .name   = "tegra_uart",
1101         .id     = 3,
1102         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
1103         .resource       = tegra_uartd_resources,
1104         .dev    = {
1105                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1106         },
1107 };
1108
1109 struct platform_device tegra_uarte_device = {
1110         .name   = "tegra_uart",
1111         .id     = 4,
1112         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
1113         .resource       = tegra_uarte_resources,
1114         .dev    = {
1115                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1116         },
1117 };
1118
1119 static struct plat_serial8250_port debug_uarta_platform_data[] = {
1120         {
1121                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
1122                 .mapbase        = TEGRA_UARTA_BASE,
1123                 .irq            = INT_UARTA,
1124                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1125                 .type           = PORT_TEGRA,
1126                 .iotype         = UPIO_MEM,
1127                 .regshift       = 2,
1128         },
1129         {
1130                 .flags          = 0,
1131         },
1132 };
1133
1134 static struct plat_serial8250_port debug_uartb_platform_data[] = {
1135         {
1136                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
1137                 .mapbase        = TEGRA_UARTB_BASE,
1138                 .irq            = INT_UARTB,
1139                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1140                 .type           = PORT_TEGRA,
1141                 .iotype         = UPIO_MEM,
1142                 .regshift       = 2,
1143         },
1144         {
1145                 .flags          = 0,
1146         },
1147 };
1148
1149 static struct plat_serial8250_port debug_uartc_platform_data[] = {
1150         {
1151                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
1152                 .mapbase        = TEGRA_UARTC_BASE,
1153                 .irq            = INT_UARTC,
1154                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1155                 .type           = PORT_TEGRA,
1156                 .iotype         = UPIO_MEM,
1157                 .regshift       = 2,
1158         },
1159         {
1160                 .flags          = 0,
1161         },
1162 };
1163
1164 static struct plat_serial8250_port debug_uartd_platform_data[] = {
1165         {
1166                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
1167                 .mapbase        = TEGRA_UARTD_BASE,
1168                 .irq            = INT_UARTD,
1169                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1170                 .type           = PORT_TEGRA,
1171                 .iotype         = UPIO_MEM,
1172                 .regshift       = 2,
1173         },
1174         {
1175                 .flags          = 0,
1176         },
1177 };
1178
1179 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1180 static struct plat_serial8250_port debug_uarte_platform_data[] = {
1181         {
1182                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
1183                 .mapbase        = TEGRA_UARTE_BASE,
1184                 .irq            = INT_UARTE,
1185                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1186                 .type           = PORT_TEGRA,
1187                 .iotype         = UPIO_MEM,
1188                 .regshift       = 2,
1189         },
1190         {
1191                 .flags          = 0,
1192         },
1193 };
1194 #endif
1195
1196 struct platform_device debug_uarta_device = {
1197         .name = "serial8250",
1198         .id = PLAT8250_DEV_PLATFORM,
1199         .dev = {
1200                 .platform_data = debug_uarta_platform_data,
1201         },
1202 };
1203
1204 struct platform_device debug_uartb_device = {
1205         .name = "serial8250",
1206         .id = PLAT8250_DEV_PLATFORM,
1207         .dev = {
1208                 .platform_data = debug_uartb_platform_data,
1209         },
1210 };
1211
1212 struct platform_device debug_uartc_device = {
1213         .name = "serial8250",
1214         .id = PLAT8250_DEV_PLATFORM,
1215         .dev = {
1216                 .platform_data = debug_uartc_platform_data,
1217         },
1218 };
1219
1220 struct platform_device debug_uartd_device = {
1221         .name = "serial8250",
1222         .id = PLAT8250_DEV_PLATFORM,
1223         .dev = {
1224                 .platform_data = debug_uartd_platform_data,
1225         },
1226 };
1227
1228 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1229 struct platform_device debug_uarte_device = {
1230         .name = "serial8250",
1231         .id = PLAT8250_DEV_PLATFORM,
1232         .dev = {
1233                 .platform_data = debug_uarte_platform_data,
1234         },
1235 };
1236 #endif
1237
1238 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1239 static struct resource i2s_resource1[] = {
1240         [0] = {
1241                 .start  = INT_I2S1,
1242                 .end    = INT_I2S1,
1243                 .flags  = IORESOURCE_IRQ
1244         },
1245         [1] = {
1246                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1247                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1248                 .flags  = IORESOURCE_DMA
1249         },
1250         [2] = {
1251                 .start  = TEGRA_I2S1_BASE,
1252                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1253                 .flags  = IORESOURCE_MEM
1254         }
1255 };
1256
1257 struct platform_device tegra_i2s_device1 = {
1258         .name           = "tegra20-i2s",
1259         .id             = 0,
1260         .resource       = i2s_resource1,
1261         .num_resources  = ARRAY_SIZE(i2s_resource1),
1262 };
1263
1264 static struct resource i2s_resource2[] = {
1265         [0] = {
1266                 .start  = INT_I2S2,
1267                 .end    = INT_I2S2,
1268                 .flags  = IORESOURCE_IRQ
1269         },
1270         [1] = {
1271                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1272                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1273                 .flags  = IORESOURCE_DMA
1274         },
1275         [2] = {
1276                 .start  = TEGRA_I2S2_BASE,
1277                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1278                 .flags  = IORESOURCE_MEM
1279         }
1280 };
1281
1282 struct platform_device tegra_i2s_device2 = {
1283         .name           = "tegra20-i2s",
1284         .id             = 1,
1285         .resource       = i2s_resource2,
1286         .num_resources  = ARRAY_SIZE(i2s_resource2),
1287 };
1288 #else
1289 static struct resource i2s_resource0[] = {
1290         [0] = {
1291                 .start  = TEGRA_I2S0_BASE,
1292                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1293                 .flags  = IORESOURCE_MEM
1294         }
1295 };
1296
1297 struct platform_device tegra_i2s_device0 = {
1298         .name           = "tegra30-i2s",
1299         .id             = 0,
1300         .resource       = i2s_resource0,
1301         .num_resources  = ARRAY_SIZE(i2s_resource0),
1302 };
1303
1304 static struct resource i2s_resource1[] = {
1305         [0] = {
1306                 .start  = TEGRA_I2S1_BASE,
1307                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1308                 .flags  = IORESOURCE_MEM
1309         }
1310 };
1311
1312 struct platform_device tegra_i2s_device1 = {
1313         .name           = "tegra30-i2s",
1314         .id             = 1,
1315         .resource       = i2s_resource1,
1316         .num_resources  = ARRAY_SIZE(i2s_resource1),
1317 };
1318
1319 static struct resource i2s_resource2[] = {
1320         [0] = {
1321                 .start  = TEGRA_I2S2_BASE,
1322                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1323                 .flags  = IORESOURCE_MEM
1324         }
1325 };
1326
1327 struct platform_device tegra_i2s_device2 = {
1328         .name           = "tegra30-i2s",
1329         .id             = 2,
1330         .resource       = i2s_resource2,
1331         .num_resources  = ARRAY_SIZE(i2s_resource2),
1332 };
1333
1334 static struct resource i2s_resource3[] = {
1335         [0] = {
1336                 .start  = TEGRA_I2S3_BASE,
1337                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1338                 .flags  = IORESOURCE_MEM
1339         }
1340 };
1341
1342 struct platform_device tegra_i2s_device3 = {
1343         .name           = "tegra30-i2s",
1344         .id             = 3,
1345         .resource       = i2s_resource3,
1346         .num_resources  = ARRAY_SIZE(i2s_resource3),
1347 };
1348
1349 static struct resource i2s_resource4[] = {
1350         [0] = {
1351                 .start  = TEGRA_I2S4_BASE,
1352                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1353                 .flags  = IORESOURCE_MEM
1354         }
1355 };
1356
1357 struct platform_device tegra_i2s_device4 = {
1358         .name           = "tegra30-i2s",
1359         .id             = 4,
1360         .resource       = i2s_resource4,
1361         .num_resources  = ARRAY_SIZE(i2s_resource4),
1362 };
1363 #endif
1364
1365 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1366 static struct resource spdif_resource[] = {
1367         [0] = {
1368                 .start  = INT_SPDIF,
1369                 .end    = INT_SPDIF,
1370                 .flags  = IORESOURCE_IRQ
1371         },
1372         [1] = {
1373                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1374                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1375                 .flags  = IORESOURCE_DMA
1376         },
1377         [2] = {
1378                 .start  = TEGRA_SPDIF_BASE,
1379                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1380                 .flags  = IORESOURCE_MEM
1381         }
1382 };
1383
1384 struct platform_device tegra_spdif_device = {
1385         .name           = "tegra20-spdif",
1386         .id             = -1,
1387         .resource       = spdif_resource,
1388         .num_resources  = ARRAY_SIZE(spdif_resource),
1389 };
1390 #else
1391 static struct resource spdif_resource[] = {
1392         [0] = {
1393                 .start  = TEGRA_SPDIF_BASE,
1394                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1395                 .flags  = IORESOURCE_MEM
1396         }
1397 };
1398
1399 struct platform_device tegra_spdif_device = {
1400         .name           = "tegra30-spdif",
1401         .id             = -1,
1402         .resource       = spdif_resource,
1403         .num_resources  = ARRAY_SIZE(spdif_resource),
1404 };
1405 #endif
1406
1407 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1408 static struct resource ahub_resource[] = {
1409         [0] = {
1410                 .start  = TEGRA_APBIF0_BASE,
1411                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1412                 .flags  = IORESOURCE_MEM
1413         },
1414         [1] = {
1415                 .start  = TEGRA_AHUB_BASE,
1416                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1417                 .flags  = IORESOURCE_MEM
1418         }
1419 };
1420
1421 struct platform_device tegra_ahub_device = {
1422         .name   = "tegra30-ahub",
1423         .id     = -1,
1424         .resource       = ahub_resource,
1425         .num_resources  = ARRAY_SIZE(ahub_resource),
1426 };
1427
1428 static struct resource dam_resource0[] = {
1429         [0] = {
1430                 .start = TEGRA_DAM0_BASE,
1431                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1432                 .flags = IORESOURCE_MEM
1433         }
1434 };
1435
1436 struct platform_device tegra_dam_device0 = {
1437         .name = "tegra30-dam",
1438         .id = 0,
1439         .resource      = dam_resource0,
1440         .num_resources = ARRAY_SIZE(dam_resource0),
1441 };
1442
1443 static struct resource dam_resource1[] = {
1444         [0] = {
1445                 .start = TEGRA_DAM1_BASE,
1446                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1447                 .flags = IORESOURCE_MEM
1448         }
1449 };
1450
1451 struct platform_device tegra_dam_device1 = {
1452         .name = "tegra30-dam",
1453         .id = 1,
1454         .resource      = dam_resource1,
1455         .num_resources = ARRAY_SIZE(dam_resource1),
1456 };
1457
1458 static struct resource dam_resource2[] = {
1459         [0] = {
1460                 .start = TEGRA_DAM2_BASE,
1461                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1462                 .flags = IORESOURCE_MEM
1463         }
1464 };
1465
1466 struct platform_device tegra_dam_device2 = {
1467         .name = "tegra30-dam",
1468         .id = 2,
1469         .resource      = dam_resource2,
1470         .num_resources = ARRAY_SIZE(dam_resource2),
1471 };
1472
1473 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1474 static struct resource hda_platform_resources[] = {
1475         [0] = {
1476                 .start  = TEGRA_HDA_BASE,
1477                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1478                 .flags  = IORESOURCE_MEM
1479         },
1480         [1] = {
1481                 .start  = INT_HDA,
1482                 .end    = INT_HDA,
1483                 .flags  = IORESOURCE_IRQ
1484         },
1485 };
1486
1487 struct platform_device tegra_hda_device = {
1488         .name           = "tegra30-hda",
1489         .id             = -1,
1490         .dev = {
1491                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1492                 .dma_mask               = &tegra_hda_dma_mask,
1493         },
1494         .resource       = hda_platform_resources,
1495         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1496 };
1497 #endif
1498
1499 struct platform_device spdif_dit_device = {
1500         .name = "spdif-dit",
1501         .id = 0,
1502 };
1503
1504 struct platform_device bluetooth_dit_device = {
1505         .name = "spdif-dit",
1506         .id = 1,
1507 };
1508
1509 struct platform_device baseband_dit_device = {
1510         .name = "spdif-dit",
1511         .id = 2,
1512 };
1513
1514 struct platform_device tegra_tdm_pcm_device = {
1515         .name = "tegra-tdm-pcm-audio",
1516         .id = -1,
1517 };
1518
1519 static struct resource w1_resources[] = {
1520         [0] = {
1521                 .start = INT_OWR,
1522                 .end   = INT_OWR,
1523                 .flags = IORESOURCE_IRQ
1524         },
1525         [1] = {
1526                 .start = TEGRA_OWR_BASE,
1527                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1528                 .flags = IORESOURCE_MEM
1529         }
1530 };
1531
1532 struct platform_device tegra_w1_device = {
1533         .name          = "tegra_w1",
1534         .id            = -1,
1535         .resource      = w1_resources,
1536         .num_resources = ARRAY_SIZE(w1_resources),
1537 };
1538
1539 static struct resource tegra_udc_resources[] = {
1540         [0] = {
1541                 .start  = TEGRA_USB_BASE,
1542                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1543                 .flags  = IORESOURCE_MEM,
1544         },
1545         [1] = {
1546                 .start  = INT_USB,
1547                 .end    = INT_USB,
1548                 .flags  = IORESOURCE_IRQ,
1549         },
1550 };
1551
1552 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1553
1554 struct platform_device tegra_udc_device = {
1555         .name   = "tegra-udc",
1556         .id     = 0,
1557         .dev    = {
1558                 .dma_mask       = &tegra_udc_dmamask,
1559                 .coherent_dma_mask = DMA_BIT_MASK(32),
1560         },
1561         .resource = tegra_udc_resources,
1562         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1563 };
1564
1565 static struct resource tegra_otg_resources[] = {
1566         [0] = {
1567                 .start  = TEGRA_USB_BASE,
1568                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1569                 .flags  = IORESOURCE_MEM,
1570         },
1571         [1] = {
1572                 .start  = INT_USB,
1573                 .end    = INT_USB,
1574                 .flags  = IORESOURCE_IRQ,
1575         },
1576 };
1577
1578 struct platform_device tegra_otg_device = {
1579         .name           = "tegra-otg",
1580         .id             = -1,
1581         .resource       = tegra_otg_resources,
1582         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1583 };
1584
1585 #ifdef CONFIG_SATA_AHCI_TEGRA
1586 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1587
1588 static struct resource tegra_sata_resources[] = {
1589         [0] = {
1590                 .start = TEGRA_SATA_BAR5_BASE,
1591                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1592                 .flags = IORESOURCE_MEM,
1593         },
1594         [1] = {
1595                 .start = TEGRA_SATA_CONFIG_BASE,
1596                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1597                 .flags = IORESOURCE_MEM,
1598         },
1599         [2] = {
1600                 .start = INT_SATA_CTL,
1601                 .end = INT_SATA_CTL,
1602                 .flags = IORESOURCE_IRQ,
1603         },
1604 };
1605
1606 struct platform_device tegra_sata_device = {
1607         .name   = "tegra-sata",
1608         .id     = 0,
1609         .dev    = {
1610                 .platform_data = 0,
1611                 .coherent_dma_mask = DMA_BIT_MASK(32),
1612                 .dma_mask = &tegra_sata_dma_mask,
1613         },
1614         .resource = tegra_sata_resources,
1615         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1616 };
1617 #endif
1618
1619 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1620 static struct resource das_resource[] = {
1621         [0] = {
1622                 .start  = TEGRA_APB_MISC_DAS_BASE,
1623                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1624                 .flags  = IORESOURCE_MEM
1625         }
1626 };
1627
1628 struct platform_device tegra_das_device = {
1629         .name           = "tegra20-das",
1630         .id             = -1,
1631         .resource       = das_resource,
1632         .num_resources  = ARRAY_SIZE(das_resource),
1633 };
1634 #endif
1635
1636 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1637 static struct resource tegra_gart_resources[] = {
1638         [0] = {
1639                 .name   = "mc",
1640                 .flags  = IORESOURCE_MEM,
1641                 .start  = TEGRA_MC_BASE,
1642                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1643         },
1644         [1] = {
1645                 .name   = "gart",
1646                 .flags  = IORESOURCE_MEM,
1647                 .start  = TEGRA_GART_BASE,
1648                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1649         }
1650 };
1651
1652 struct platform_device tegra_gart_device = {
1653         .name           = "tegra_gart",
1654         .id             = -1,
1655         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1656         .resource       = tegra_gart_resources
1657 };
1658 #endif
1659
1660 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
1661 static struct resource tegra_smmu_resources[] = {
1662         {
1663                 .name   = "mc",
1664                 .flags  = IORESOURCE_MEM,
1665                 .start  = TEGRA_MC_BASE,
1666                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1667         },
1668         {
1669                 .name   = "ahbarb",
1670                 .flags  = IORESOURCE_MEM,
1671                 .start  = TEGRA_AHB_ARB_BASE,
1672                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1673         },
1674 };
1675
1676 struct platform_device tegra_smmu_device = {
1677         .name           = "tegra_smmu",
1678         .id             = -1,
1679         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1680         .resource       = tegra_smmu_resources
1681 };
1682
1683 static struct resource tegra_smmu[] = {
1684         [0] = {
1685                 .start  = TEGRA_SMMU_BASE,
1686                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1687         },
1688 };
1689
1690 struct resource *tegra_smmu_window(int wnum)
1691 {
1692         return &tegra_smmu[wnum];
1693 }
1694
1695 int tegra_smmu_window_count(void)
1696 {
1697         return ARRAY_SIZE(tegra_smmu);
1698 }
1699
1700 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
1701
1702 /* default global map if DT doesn't specify */
1703 static struct dma_iommu_mapping *smmu_default_map;
1704
1705 static void tegra_smmu_map_init(struct platform_device *pdev)
1706 {
1707         struct dma_iommu_mapping *map;
1708
1709         map = arm_iommu_create_mapping(&platform_bus_type,
1710                                        TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE, 0);
1711         if (IS_ERR(map)) {
1712                 dev_err(&pdev->dev, "Failed create IOVA map %08x-%08x\n",
1713                         TEGRA_IOMMU_BASE,
1714                         TEGRA_IOMMU_BASE + TEGRA_IOMMU_SIZE - 1);
1715                 return;
1716         }
1717         smmu_default_map = map;
1718 }
1719
1720 struct dma_iommu_mapping *tegra_smmu_get_map(void)
1721 {
1722         return smmu_default_map;
1723 }
1724 #else
1725 static inline void tegra_smmu_map_init(struct platform_device *pdev)
1726 {
1727 }
1728 #endif
1729
1730 void tegra_smmu_init(void)
1731 {
1732         platform_device_register(&tegra_smmu_device);
1733         tegra_smmu_map_init(&tegra_smmu_device);
1734 }
1735 #endif
1736
1737 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1738 #define CLK_RESET_RST_SOURCE    0x0
1739 static struct resource tegra_wdt_resources[] = {
1740         [0] = {
1741                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1742                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1743                 .flags  = IORESOURCE_MEM,
1744         },
1745         [1] = {
1746                 .start  = TEGRA_TMR1_BASE,
1747                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1748                 .flags  = IORESOURCE_MEM,
1749         },
1750         [2] = {
1751                 .start  = INT_TMR1,
1752                 .end    = INT_TMR1,
1753                 .flags  = IORESOURCE_IRQ,
1754         },
1755 };
1756
1757 struct platform_device tegra_wdt_device = {
1758         .name           = "tegra_wdt",
1759         .id             = -1,
1760         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1761         .resource       = tegra_wdt_resources,
1762 };
1763 #else
1764 static struct resource tegra_wdt0_resources[] = {
1765         [0] = {
1766                 .start  = TEGRA_WDT0_BASE,
1767                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1768                 .flags  = IORESOURCE_MEM,
1769         },
1770         [1] = {
1771                 .start  = TEGRA_TMR7_BASE,
1772                 .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
1773                 .flags  = IORESOURCE_MEM,
1774         },
1775         [2] = {
1776                 .start  = INT_WDT_CPU,
1777                 .end    = INT_WDT_CPU,
1778                 .flags  = IORESOURCE_IRQ,
1779         },
1780 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
1781         [3] = {
1782                 .start  = TEGRA_QUATERNARY_ICTLR_BASE,
1783                 .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
1784                                 TEGRA_QUATERNARY_ICTLR_SIZE -1,
1785                 .flags  = IORESOURCE_MEM,
1786         },
1787 #endif
1788 };
1789
1790 static struct resource tegra_wdt1_resources[] = {
1791         [0] = {
1792                 .start  = TEGRA_WDT1_BASE,
1793                 .end    = TEGRA_WDT1_BASE + TEGRA_WDT1_SIZE - 1,
1794                 .flags  = IORESOURCE_MEM,
1795         },
1796         [1] = {
1797                 .start  = TEGRA_TMR8_BASE,
1798                 .end    = TEGRA_TMR8_BASE + TEGRA_TMR8_SIZE - 1,
1799                 .flags  = IORESOURCE_MEM,
1800         },
1801 };
1802
1803 static struct resource tegra_wdt2_resources[] = {
1804         [0] = {
1805                 .start  = TEGRA_WDT2_BASE,
1806                 .end    = TEGRA_WDT2_BASE + TEGRA_WDT2_SIZE - 1,
1807                 .flags  = IORESOURCE_MEM,
1808         },
1809         [1] = {
1810                 .start  = TEGRA_TMR9_BASE,
1811                 .end    = TEGRA_TMR9_BASE + TEGRA_TMR9_SIZE - 1,
1812                 .flags  = IORESOURCE_MEM,
1813         },
1814 };
1815
1816 struct platform_device tegra_wdt0_device = {
1817         .name           = "tegra_wdt",
1818         .id             = 0,
1819         .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
1820         .resource       = tegra_wdt0_resources,
1821 };
1822
1823 struct platform_device tegra_wdt1_device = {
1824         .name           = "tegra_wdt",
1825         .id             = 1,
1826         .num_resources  = ARRAY_SIZE(tegra_wdt1_resources),
1827         .resource       = tegra_wdt1_resources,
1828 };
1829
1830 struct platform_device tegra_wdt2_device = {
1831         .name           = "tegra_wdt",
1832         .id             = 2,
1833         .num_resources  = ARRAY_SIZE(tegra_wdt2_resources),
1834         .resource       = tegra_wdt2_resources,
1835 };
1836 #endif
1837
1838 static struct resource tegra_pwfm_resource = {
1839         .start  = TEGRA_PWFM_BASE,
1840         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
1841         .flags  = IORESOURCE_MEM,
1842 };
1843
1844 struct platform_device tegra_pwfm_device = {
1845         .name           = "tegra-pwm",
1846         .id             = 0,
1847         .num_resources  = 1,
1848         .resource       = &tegra_pwfm_resource,
1849 };
1850
1851 static struct tegra_avp_platform_data tegra_avp_pdata = {
1852 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1853         .emc_clk_rate = ULONG_MAX,
1854 #else
1855         .emc_clk_rate = 200000000,
1856 #endif
1857 };
1858
1859 struct resource tegra_nvavp_resources[] = {
1860         [0] = {
1861                 .start  = INT_SHR_SEM_INBOX_IBF,
1862                 .end    = INT_SHR_SEM_INBOX_IBF,
1863                 .flags  = IORESOURCE_IRQ,
1864                 .name   = "mbox_from_nvavp_pending",
1865         },
1866 };
1867
1868 struct platform_device nvavp_device = {
1869         .name           = "nvavp",
1870         .id             = -1,
1871         .resource       = tegra_nvavp_resources,
1872         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
1873 };
1874
1875 static struct resource tegra_avp_resources[] = {
1876         [0] = {
1877                 .start  = INT_SHR_SEM_INBOX_IBF,
1878                 .end    = INT_SHR_SEM_INBOX_IBF,
1879                 .flags  = IORESOURCE_IRQ,
1880                 .name   = "mbox_from_avp_pending",
1881         },
1882 };
1883
1884 struct platform_device tegra_avp_device = {
1885         .name           = "tegra-avp",
1886         .id             = -1,
1887         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1888         .resource       = tegra_avp_resources,
1889         .dev  = {
1890                 .coherent_dma_mask      = 0xffffffffULL,
1891                 .platform_data          = &tegra_avp_pdata,
1892         },
1893 };
1894
1895 static struct resource tegra_aes_resources[] = {
1896         {
1897                 .start  = TEGRA_VDE_BASE,
1898                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1899                 .flags  = IORESOURCE_MEM,
1900         },
1901         {
1902                 .start  = TEGRA_BSEA_BASE,
1903                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1904                 .flags  = IORESOURCE_MEM,
1905         },
1906         {
1907                 .start  = INT_VDE_BSE_V,
1908                 .end    = INT_VDE_BSE_V,
1909                 .flags  = IORESOURCE_IRQ,
1910         },
1911         {
1912                 .start  = INT_VDE_BSE_A,
1913                 .end    = INT_VDE_BSE_A,
1914                 .flags  = IORESOURCE_IRQ,
1915         },
1916 };
1917
1918 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1919
1920 struct platform_device tegra_aes_device = {
1921         .name           = "tegra-aes",
1922         .id             = -1,
1923         .resource       = tegra_aes_resources,
1924         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1925         .dev    = {
1926                 .dma_mask = &tegra_aes_dma_mask,
1927                 .coherent_dma_mask = DMA_BIT_MASK(32),
1928         },
1929 };
1930
1931 static struct resource tegra_kbc_resources[] = {
1932         [0] = {
1933                 .start = TEGRA_KBC_BASE,
1934                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1935                 .flags = IORESOURCE_MEM,
1936         },
1937         [1] = {
1938                 .start = INT_KBC,
1939                 .end   = INT_KBC,
1940                 .flags = IORESOURCE_IRQ,
1941         },
1942 };
1943
1944 struct platform_device tegra_kbc_device = {
1945         .name = "tegra-kbc",
1946         .id = -1,
1947         .resource = tegra_kbc_resources,
1948         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1949         .dev = {
1950                 .platform_data = 0,
1951         },
1952 };
1953
1954 #if defined(CONFIG_TEGRA_SKIN_THROTTLE)
1955 struct platform_device tegra_skin_therm_est_device = {
1956         .name   = "therm_est",
1957         .id     = -1,
1958         .num_resources  = 0,
1959         .dev = {
1960                 .platform_data = 0,
1961         },
1962 };
1963 #endif
1964
1965 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1966 static struct resource tegra_tsensor_resources[]= {
1967         {
1968                 .start  = TEGRA_TSENSOR_BASE,
1969                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1970                 .flags  = IORESOURCE_MEM,
1971         },
1972         {
1973                 .start  = INT_TSENSOR,
1974                 .end    = INT_TSENSOR,
1975                 .flags  = IORESOURCE_IRQ,
1976         },
1977         {
1978                 .start  = TEGRA_PMC_BASE + 0x1B0,
1979                 /* 2 pmc registers mapped */
1980                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
1981                 .flags  = IORESOURCE_MEM,
1982         },
1983 };
1984
1985 struct platform_device tegra_tsensor_device = {
1986         .name   = "tegra-tsensor",
1987         .id     = -1,
1988         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
1989         .resource       = tegra_tsensor_resources,
1990         .dev = {
1991                 .platform_data = 0,
1992         },
1993 };
1994 #endif
1995
1996 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1997 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
1998
1999 struct resource tegra_se_resources[] = {
2000         [0] = {
2001                 .start = TEGRA_SE_BASE,
2002                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
2003                 .flags = IORESOURCE_MEM,
2004         },
2005         [1] = {
2006                 .start  = TEGRA_PMC_BASE,
2007                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
2008                 .flags  = IORESOURCE_MEM,
2009         },
2010         [2] = {
2011                 .start = INT_SE,
2012                 .end = INT_SE,
2013                 .flags = IORESOURCE_IRQ,
2014         },
2015 };
2016
2017 struct platform_device tegra_se_device = {
2018         .name = "tegra-se",
2019         .id = -1,
2020         .dev = {
2021                 .coherent_dma_mask = DMA_BIT_MASK(32),
2022                 .dma_mask = &tegra_se_dma_mask,
2023         },
2024         .resource = tegra_se_resources,
2025         .num_resources = ARRAY_SIZE(tegra_se_resources),
2026 };
2027
2028 struct platform_device tegra11_se_device = {
2029         .name = "tegra11-se",
2030         .id = -1,
2031         .dev = {
2032                 .coherent_dma_mask = DMA_BIT_MASK(32),
2033                 .dma_mask = &tegra_se_dma_mask,
2034         },
2035         .resource = tegra_se_resources,
2036         .num_resources = ARRAY_SIZE(tegra_se_resources),
2037 };
2038 #endif
2039
2040 static struct resource tegra_disp1_resources[] = {
2041         {
2042                 .name   = "irq",
2043                 .start  = INT_DISPLAY_GENERAL,
2044                 .end    = INT_DISPLAY_GENERAL,
2045                 .flags  = IORESOURCE_IRQ,
2046         },
2047         {
2048                 .name   = "regs",
2049                 .start  = TEGRA_DISPLAY_BASE,
2050                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
2051                 .flags  = IORESOURCE_MEM,
2052         },
2053         {
2054                 .name   = "fbmem",
2055                 .start  = 0,
2056                 .end    = 0,
2057                 .flags  = IORESOURCE_MEM,
2058         },
2059         {
2060                 .name   = "dsi_regs",
2061                 .start  = TEGRA_DSI_BASE,
2062                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
2063                 .flags  = IORESOURCE_MEM,
2064         },
2065 };
2066
2067 struct platform_device tegra_disp1_device = {
2068         .name           = "tegradc",
2069         .id             = 0,
2070         .resource       = tegra_disp1_resources,
2071         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
2072 };
2073
2074 static struct resource tegra_disp2_resources[] = {
2075         {
2076                 .name   = "irq",
2077                 .start  = INT_DISPLAY_B_GENERAL,
2078                 .end    = INT_DISPLAY_B_GENERAL,
2079                 .flags  = IORESOURCE_IRQ,
2080         },
2081         {
2082                 .name   = "regs",
2083                 .start  = TEGRA_DISPLAY2_BASE,
2084                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
2085                 .flags  = IORESOURCE_MEM,
2086         },
2087         {
2088                 .name   = "fbmem",
2089                 .flags  = IORESOURCE_MEM,
2090                 .start  = 0,
2091                 .end    = 0,
2092         },
2093         {
2094                 .name   = "hdmi_regs",
2095                 .start  = TEGRA_HDMI_BASE,
2096                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
2097                 .flags  = IORESOURCE_MEM,
2098         },
2099 };
2100
2101 struct platform_device tegra_disp2_device = {
2102         .name           = "tegradc",
2103         .id             = 1,
2104         .resource       = tegra_disp2_resources,
2105         .num_resources  = ARRAY_SIZE(tegra_disp2_resources),
2106         .dev = {
2107                 .platform_data = 0,
2108         },
2109 };
2110
2111 struct platform_device tegra_nvmap_device = {
2112         .name   = "tegra-nvmap",
2113         .id     = -1,
2114 };
2115
2116 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2117 static struct resource tegra_cec_resources[] = {
2118         [0] = {
2119                 .start = TEGRA_CEC_BASE,
2120                 .end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
2121                 .flags = IORESOURCE_MEM,
2122         },
2123         [1] = {
2124                 .start = INT_CEC,
2125                 .end = INT_CEC,
2126                 .flags = IORESOURCE_IRQ,
2127         },
2128 };
2129
2130 struct platform_device tegra_cec_device = {
2131         .name = "tegra_cec",
2132         .id   = -1,
2133         .resource = tegra_cec_resources,
2134         .num_resources = ARRAY_SIZE(tegra_cec_resources),
2135 };
2136 #endif
2137
2138 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
2139 static struct resource cl_dvfs_resource[] = {
2140         [0] = {
2141                 .start  = TEGRA_CL_DVFS_BASE,
2142                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2143                 .flags  = IORESOURCE_MEM,
2144         }
2145 };
2146
2147 struct platform_device tegra_cl_dvfs_device = {
2148         .name           = "tegra_cl_dvfs",
2149         .id             = -1,
2150         .resource       = cl_dvfs_resource,
2151         .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
2152 };
2153 #endif
2154
2155 void __init tegra_init_debug_uart_rate(void)
2156 {
2157         unsigned int uartclk;
2158         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
2159
2160         BUG_ON(IS_ERR(debug_uart_parent));
2161         uartclk = clk_get_rate(debug_uart_parent);
2162
2163         debug_uarta_platform_data[0].uartclk = uartclk;
2164         debug_uartb_platform_data[0].uartclk = uartclk;
2165         debug_uartc_platform_data[0].uartclk = uartclk;
2166         debug_uartd_platform_data[0].uartclk = uartclk;
2167 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2168         debug_uarte_platform_data[0].uartclk = uartclk;
2169 #endif
2170 }