xhci: tegra: support HSIC ports
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/mipi-bif-tegra.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/tegra_avp.h>
30 #include <linux/nvhost.h>
31 #include <linux/clk.h>
32 #include <mach/irqs.h>
33 #include <linux/usb/tegra_usb_phy.h>
34 #include <mach/tegra_smmu.h>
35 #include <mach/tegra-swgid.h>
36 #include <mach/hardware.h>
37
38 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
39 #include <asm/dma-iommu.h>
40 #endif
41
42 #include "gpio-names.h"
43 #include "iomap.h"
44 #include "devices.h"
45
46 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
47 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
48 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
49 #define TEGRA_DMA_REQ_SEL_SPI                   11
50 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
51
52 static struct resource emc_resource[] = {
53         [0] = {
54                 .start  = TEGRA_EMC_BASE,
55                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
56                 .flags  = IORESOURCE_MEM,
57         }
58 };
59
60 struct platform_device tegra_emc_device = {
61         .name           = "tegra-emc",
62         .id             = -1,
63         .resource       = emc_resource,
64         .num_resources  = ARRAY_SIZE(emc_resource),
65 };
66
67 static struct resource gpio_resource[] = {
68         [0] = {
69                 .start  = TEGRA_GPIO_BASE,
70                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
71                 .flags  = IORESOURCE_MEM,
72         },
73         [1] = {
74                 .start  = INT_GPIO1,
75                 .end    = INT_GPIO1,
76                 .flags  = IORESOURCE_IRQ,
77         },
78         [2] = {
79                 .start  = INT_GPIO2,
80                 .end    = INT_GPIO2,
81                 .flags  = IORESOURCE_IRQ,
82         },
83         [3] = {
84                 .start  = INT_GPIO3,
85                 .end    = INT_GPIO3,
86                 .flags  = IORESOURCE_IRQ,
87         },
88         [4] = {
89                 .start  = INT_GPIO4,
90                 .end    = INT_GPIO4,
91                 .flags  = IORESOURCE_IRQ,
92         },
93         [5] = {
94                 .start  = INT_GPIO5,
95                 .end    = INT_GPIO5,
96                 .flags  = IORESOURCE_IRQ,
97         },
98         [6] = {
99                 .start  = INT_GPIO6,
100                 .end    = INT_GPIO6,
101                 .flags  = IORESOURCE_IRQ,
102         },
103         [7] = {
104                 .start  = INT_GPIO7,
105                 .end    = INT_GPIO7,
106                 .flags  = IORESOURCE_IRQ,
107         },
108 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
109         [8] = {
110                 .start  = INT_GPIO8,
111                 .end    = INT_GPIO8,
112                 .flags  = IORESOURCE_IRQ,
113         },
114 #endif
115 };
116
117 struct platform_device tegra_gpio_device = {
118         .name           = "tegra-gpio",
119         .id             = -1,
120         .resource       = gpio_resource,
121         .num_resources  = ARRAY_SIZE(gpio_resource),
122 };
123
124 static struct resource pinmux_resource[] = {
125 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
126         [0] = {
127                 /* Tri-state registers */
128                 .start  = TEGRA_APB_MISC_BASE + 0x14,
129                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
130                 .flags  = IORESOURCE_MEM,
131         },
132         [1] = {
133                 /* Mux registers */
134                 .start  = TEGRA_APB_MISC_BASE + 0x80,
135                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
136                 .flags  = IORESOURCE_MEM,
137         },
138         [2] = {
139                 /* Pull-up/down registers */
140                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
141                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
142                 .flags  = IORESOURCE_MEM,
143         },
144         [3] = {
145                 /* Pad control registers */
146                 .start  = TEGRA_APB_MISC_BASE + 0x868,
147                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
148                 .flags  = IORESOURCE_MEM,
149         },
150 #else
151         [0] = {
152                 /* Drive registers */
153                 .start  = TEGRA_APB_MISC_BASE + 0x868,
154                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
155                 .flags  = IORESOURCE_MEM,
156         },
157         [1] = {
158                 /* Mux registers */
159                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
160 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
161                 .end    = TEGRA_APB_MISC_BASE + 0x3408 + 3,
162 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
163                 .end    = TEGRA_APB_MISC_BASE + 0x3514 + 3,
164 #else
165                 .end    = TEGRA_APB_MISC_BASE + 0x33e0 + 3,
166 #endif
167                 .flags  = IORESOURCE_MEM,
168         },
169 #endif
170 };
171
172 struct platform_device tegra_pinmux_device = {
173 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
174         .name           = "tegra30-pinmux-ctl",
175 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
176         .name           = "tegra20-pinmux-ctl",
177 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
178         .name           = "tegra11x-pinmux-ctl",
179 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
180         .name           = "tegra12x-pinmux",
181 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
182         .name           = "tegra14x-pinmux",
183 #endif
184         .id             = -1,
185         .resource       = pinmux_resource,
186         .num_resources  = ARRAY_SIZE(pinmux_resource),
187 };
188
189 static struct resource apbdma_resource[] = {
190         [0] = {
191                 .start  = TEGRA_APB_DMA_BASE,
192                 .end    = TEGRA_APB_DMA_BASE + TEGRA_APB_DMA_SIZE-1,
193                 .flags  = IORESOURCE_MEM,
194         },
195         [1] = {
196                 .start  = INT_APB_DMA_CH0,
197                 .end    = INT_APB_DMA_CH0,
198                 .flags  = IORESOURCE_IRQ,
199         },
200         [2] = {
201                 .start  = INT_APB_DMA_CH1,
202                 .end    = INT_APB_DMA_CH1,
203                 .flags  = IORESOURCE_IRQ,
204         },
205         [3] = {
206                 .start  = INT_APB_DMA_CH2,
207                 .end    = INT_APB_DMA_CH2,
208                 .flags  = IORESOURCE_IRQ,
209         },
210         [4] = {
211                 .start  = INT_APB_DMA_CH3,
212                 .end    = INT_APB_DMA_CH3,
213                 .flags  = IORESOURCE_IRQ,
214         },
215         [5] = {
216                 .start  = INT_APB_DMA_CH4,
217                 .end    = INT_APB_DMA_CH4,
218                 .flags  = IORESOURCE_IRQ,
219         },
220         [6] = {
221                 .start  = INT_APB_DMA_CH5,
222                 .end    = INT_APB_DMA_CH5,
223                 .flags  = IORESOURCE_IRQ,
224         },
225         [7] = {
226                 .start  = INT_APB_DMA_CH6,
227                 .end    = INT_APB_DMA_CH6,
228                 .flags  = IORESOURCE_IRQ,
229         },
230         [8] = {
231                 .start  = INT_APB_DMA_CH7,
232                 .end    = INT_APB_DMA_CH7,
233                 .flags  = IORESOURCE_IRQ,
234         },
235         [9] = {
236                 .start  = INT_APB_DMA_CH8,
237                 .end    = INT_APB_DMA_CH8,
238                 .flags  = IORESOURCE_IRQ,
239         },
240         [10] = {
241                 .start  = INT_APB_DMA_CH9,
242                 .end    = INT_APB_DMA_CH9,
243                 .flags  = IORESOURCE_IRQ,
244         },
245         [11] = {
246                 .start  = INT_APB_DMA_CH10,
247                 .end    = INT_APB_DMA_CH10,
248                 .flags  = IORESOURCE_IRQ,
249         },
250         [12] = {
251                 .start  = INT_APB_DMA_CH11,
252                 .end    = INT_APB_DMA_CH11,
253                 .flags  = IORESOURCE_IRQ,
254         },
255         [13] = {
256                 .start  = INT_APB_DMA_CH12,
257                 .end    = INT_APB_DMA_CH12,
258                 .flags  = IORESOURCE_IRQ,
259         },
260         [14] = {
261                 .start  = INT_APB_DMA_CH13,
262                 .end    = INT_APB_DMA_CH13,
263                 .flags  = IORESOURCE_IRQ,
264         },
265         [15] = {
266                 .start  = INT_APB_DMA_CH14,
267                 .end    = INT_APB_DMA_CH14,
268                 .flags  = IORESOURCE_IRQ,
269         },
270         [16] = {
271                 .start  = INT_APB_DMA_CH15,
272                 .end    = INT_APB_DMA_CH15,
273                 .flags  = IORESOURCE_IRQ,
274         },
275         [17] = {
276                 .start  = INT_APB_DMA_CH16,
277                 .end    = INT_APB_DMA_CH16,
278                 .flags  = IORESOURCE_IRQ,
279         },
280         [18] = {
281                 .start  = INT_APB_DMA_CH17,
282                 .end    = INT_APB_DMA_CH17,
283                 .flags  = IORESOURCE_IRQ,
284         },
285         [19] = {
286                 .start  = INT_APB_DMA_CH18,
287                 .end    = INT_APB_DMA_CH18,
288                 .flags  = IORESOURCE_IRQ,
289         },
290         [20] = {
291                 .start  = INT_APB_DMA_CH19,
292                 .end    = INT_APB_DMA_CH19,
293                 .flags  = IORESOURCE_IRQ,
294         },
295         [21] = {
296                 .start  = INT_APB_DMA_CH20,
297                 .end    = INT_APB_DMA_CH20,
298                 .flags  = IORESOURCE_IRQ,
299         },
300         [22] = {
301                 .start  = INT_APB_DMA_CH21,
302                 .end    = INT_APB_DMA_CH21,
303                 .flags  = IORESOURCE_IRQ,
304         },
305         [23] = {
306                 .start  = INT_APB_DMA_CH22,
307                 .end    = INT_APB_DMA_CH22,
308                 .flags  = IORESOURCE_IRQ,
309         },
310         [24] = {
311                 .start  = INT_APB_DMA_CH23,
312                 .end    = INT_APB_DMA_CH23,
313                 .flags  = IORESOURCE_IRQ,
314         },
315         [25] = {
316                 .start  = INT_APB_DMA_CH24,
317                 .end    = INT_APB_DMA_CH24,
318                 .flags  = IORESOURCE_IRQ,
319         },
320         [26] = {
321                 .start  = INT_APB_DMA_CH25,
322                 .end    = INT_APB_DMA_CH25,
323                 .flags  = IORESOURCE_IRQ,
324         },
325         [27] = {
326                 .start  = INT_APB_DMA_CH26,
327                 .end    = INT_APB_DMA_CH26,
328                 .flags  = IORESOURCE_IRQ,
329         },
330         [28] = {
331                 .start  = INT_APB_DMA_CH27,
332                 .end    = INT_APB_DMA_CH27,
333                 .flags  = IORESOURCE_IRQ,
334         },
335         [29] = {
336                 .start  = INT_APB_DMA_CH28,
337                 .end    = INT_APB_DMA_CH28,
338                 .flags  = IORESOURCE_IRQ,
339         },
340         [30] = {
341                 .start  = INT_APB_DMA_CH29,
342                 .end    = INT_APB_DMA_CH29,
343                 .flags  = IORESOURCE_IRQ,
344         },
345         [31] = {
346                 .start  = INT_APB_DMA_CH30,
347                 .end    = INT_APB_DMA_CH30,
348                 .flags  = IORESOURCE_IRQ,
349         },
350         [32] = {
351                 .start  = INT_APB_DMA_CH31,
352                 .end    = INT_APB_DMA_CH31,
353                 .flags  = IORESOURCE_IRQ,
354         },
355
356 };
357
358 struct platform_device tegra_apbdma = {
359         .name           = "tegra124-apbdma",
360         .id             = -1,
361         .resource       = apbdma_resource,
362         .num_resources  = ARRAY_SIZE(apbdma_resource),
363 };
364
365 static struct resource i2c_resource1[] = {
366         [0] = {
367                 .start  = INT_I2C,
368                 .end    = INT_I2C,
369                 .flags  = IORESOURCE_IRQ,
370         },
371         [1] = {
372                 .start  = TEGRA_I2C_BASE,
373                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
374                 .flags  = IORESOURCE_MEM,
375         },
376 };
377
378 static struct resource i2c_resource2[] = {
379         [0] = {
380                 .start  = INT_I2C2,
381                 .end    = INT_I2C2,
382                 .flags  = IORESOURCE_IRQ,
383         },
384         [1] = {
385                 .start  = TEGRA_I2C2_BASE,
386                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
387                 .flags  = IORESOURCE_MEM,
388         },
389 };
390
391 static struct resource i2c_resource3[] = {
392         [0] = {
393                 .start  = INT_I2C3,
394                 .end    = INT_I2C3,
395                 .flags  = IORESOURCE_IRQ,
396         },
397         [1] = {
398                 .start  = TEGRA_I2C3_BASE,
399                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
400                 .flags  = IORESOURCE_MEM,
401         },
402 };
403
404 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
405 static struct resource i2c_resource4[] = {
406         [0] = {
407                 .start  = INT_DVC,
408                 .end    = INT_DVC,
409                 .flags  = IORESOURCE_IRQ,
410         },
411         [1] = {
412                 .start  = TEGRA_DVC_BASE,
413                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
414                 .flags  = IORESOURCE_MEM,
415         },
416 };
417
418 #else
419 static struct resource i2c_resource4[] = {
420         [0] = {
421                 .start  = INT_I2C4,
422                 .end    = INT_I2C4,
423                 .flags  = IORESOURCE_IRQ,
424         },
425         [1] = {
426                 .start  = TEGRA_I2C4_BASE,
427                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
428                 .flags  = IORESOURCE_MEM,
429         },
430 };
431
432 static struct resource i2c_resource5[] = {
433         [0] = {
434                 .start  = INT_I2C5,
435                 .end    = INT_I2C5,
436                 .flags  = IORESOURCE_IRQ,
437         },
438         [1] = {
439                 .start  = TEGRA_I2C5_BASE,
440                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
441                 .flags  = IORESOURCE_MEM,
442         },
443 };
444 #endif
445
446 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
447 static struct resource i2c_resource6[] = {
448         [0] = {
449                 .start  = INT_I2C6,
450                 .end    = INT_I2C6,
451                 .flags  = IORESOURCE_IRQ,
452         },
453         [1] = {
454                 .start  = TEGRA_I2C6_BASE,
455                 .end    = TEGRA_I2C6_BASE + TEGRA_I2C6_SIZE-1,
456                 .flags  = IORESOURCE_MEM,
457         },
458 };
459 #endif
460
461 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
462         .bus_clk_rate   = 400000,
463 };
464
465 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
466         .bus_clk_rate   = 400000,
467 };
468
469 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
470         .bus_clk_rate   = 400000,
471 };
472
473 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
474         .bus_clk_rate   = 400000,
475 };
476
477 struct platform_device tegra_i2c_device1 = {
478         .name           = "tegra-i2c",
479         .id             = 0,
480         .resource       = i2c_resource1,
481         .num_resources  = ARRAY_SIZE(i2c_resource1),
482         .dev = {
483                 .platform_data = &tegra_i2c1_platform_data,
484         },
485 };
486
487 struct platform_device tegra_i2c_device2 = {
488         .name           = "tegra-i2c",
489         .id             = 1,
490         .resource       = i2c_resource2,
491         .num_resources  = ARRAY_SIZE(i2c_resource2),
492         .dev = {
493                 .platform_data = &tegra_i2c2_platform_data,
494         },
495 };
496
497 struct platform_device tegra_i2c_device3 = {
498         .name           = "tegra-i2c",
499         .id             = 2,
500         .resource       = i2c_resource3,
501         .num_resources  = ARRAY_SIZE(i2c_resource3),
502         .dev = {
503                 .platform_data = &tegra_i2c3_platform_data,
504         },
505 };
506
507 struct platform_device tegra_i2c_device4 = {
508         .name           = "tegra-i2c",
509         .id             = 3,
510         .resource       = i2c_resource4,
511         .num_resources  = ARRAY_SIZE(i2c_resource4),
512         .dev = {
513                 .platform_data = &tegra_dvc_platform_data,
514         },
515 };
516
517 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
518 struct platform_device tegra_i2c_device5 = {
519         .name           = "tegra-i2c",
520         .id             = 4,
521         .resource       = i2c_resource5,
522         .num_resources  = ARRAY_SIZE(i2c_resource5),
523         .dev = {
524                 .platform_data = 0,
525         },
526 };
527 #endif
528
529 struct platform_device tegra11_i2c_device1 = {
530         .name           = "tegra11-i2c",
531         .id             = 0,
532         .resource       = i2c_resource1,
533         .num_resources  = ARRAY_SIZE(i2c_resource1),
534         .dev = {
535                 .platform_data = 0,
536         },
537 };
538
539 struct platform_device tegra11_i2c_device2 = {
540         .name           = "tegra11-i2c",
541         .id             = 1,
542         .resource       = i2c_resource2,
543         .num_resources  = ARRAY_SIZE(i2c_resource2),
544         .dev = {
545                 .platform_data = 0,
546         },
547 };
548
549 struct platform_device tegra11_i2c_device3 = {
550         .name           = "tegra11-i2c",
551         .id             = 2,
552         .resource       = i2c_resource3,
553         .num_resources  = ARRAY_SIZE(i2c_resource3),
554         .dev = {
555                 .platform_data = 0,
556         },
557 };
558
559 struct platform_device tegra11_i2c_device4 = {
560         .name           = "tegra11-i2c",
561         .id             = 3,
562         .resource       = i2c_resource4,
563         .num_resources  = ARRAY_SIZE(i2c_resource4),
564         .dev = {
565                 .platform_data = 0,
566         },
567 };
568
569 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
570 struct platform_device tegra11_i2c_device5 = {
571         .name           = "tegra11-i2c",
572         .id             = 4,
573         .resource       = i2c_resource5,
574         .num_resources  = ARRAY_SIZE(i2c_resource5),
575         .dev = {
576                 .platform_data = 0,
577         },
578 };
579 #endif
580
581 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
582
583 struct platform_device tegra14_i2c_device1 = {
584         .name           = "tegra14-i2c",
585         .id             = 0,
586         .resource       = i2c_resource1,
587         .num_resources  = ARRAY_SIZE(i2c_resource1),
588         .dev = {
589                 .platform_data = 0,
590         },
591 };
592
593 struct platform_device tegra14_i2c_device2 = {
594         .name           = "tegra14-i2c",
595         .id             = 1,
596         .resource       = i2c_resource2,
597         .num_resources  = ARRAY_SIZE(i2c_resource2),
598         .dev = {
599                 .platform_data = 0,
600         },
601 };
602
603 struct platform_device tegra14_i2c_device3 = {
604         .name           = "tegra14-i2c",
605         .id             = 2,
606         .resource       = i2c_resource3,
607         .num_resources  = ARRAY_SIZE(i2c_resource3),
608         .dev = {
609                 .platform_data = 0,
610         },
611 };
612
613 struct platform_device tegra14_i2c_device4 = {
614         .name           = "tegra14-i2c",
615         .id             = 3,
616         .resource       = i2c_resource4,
617         .num_resources  = ARRAY_SIZE(i2c_resource4),
618         .dev = {
619                 .platform_data = 0,
620         },
621 };
622
623 struct platform_device tegra14_i2c_device5 = {
624         .name           = "tegra14-i2c",
625         .id             = 4,
626         .resource       = i2c_resource5,
627         .num_resources  = ARRAY_SIZE(i2c_resource5),
628         .dev = {
629                 .platform_data = 0,
630         },
631 };
632
633 struct platform_device tegra14_i2c_device6 = {
634         .name           = "tegra14-i2c",
635         .id             = 5,
636         .resource       = i2c_resource6,
637         .num_resources  = ARRAY_SIZE(i2c_resource6),
638         .dev = {
639                 .platform_data = 0,
640         },
641 };
642
643 #endif
644
645 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
646
647 static struct tegra_mipi_bif_platform_data mipi_bif_pdata = {
648         .adapter_nr     = -1,
649         .tauBIF         = 2,
650         .bus_clk_rate   = 13,
651 };
652
653 static struct resource mipi_bif_resource[] = {
654         [0] = {
655                 .start  = INT_MIPI_BIF,
656                 .end    = INT_MIPI_BIF,
657                 .flags  = IORESOURCE_IRQ,
658         },
659         [1] = {
660                 .start  = TEGRA_MIPI_BIF_BASE,
661                 .end    = TEGRA_MIPI_BIF_BASE + TEGRA_MIPI_BIF_SIZE - 1,
662                 .flags  = IORESOURCE_MEM,
663         },
664 };
665
666 struct platform_device tegra_mipi_bif_device = {
667         .name           = "tegra-mipi-bif",
668         .id             = -1,
669         .resource       = mipi_bif_resource,
670         .num_resources  = ARRAY_SIZE(mipi_bif_resource),
671         .dev = {
672                 .platform_data = &mipi_bif_pdata,
673         },
674 };
675
676 #endif
677
678 static struct resource spi_resource1[] = {
679         [0] = {
680                 .start  = INT_SPI_1,
681                 .end    = INT_SPI_1,
682                 .flags  = IORESOURCE_IRQ,
683         },
684         [1] = {
685                 .start  = TEGRA_SPI1_BASE,
686                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
687                 .flags  = IORESOURCE_MEM,
688         },
689 };
690
691 static struct resource spi_resource2[] = {
692         [0] = {
693                 .start  = INT_SPI_2,
694                 .end    = INT_SPI_2,
695                 .flags  = IORESOURCE_IRQ,
696         },
697         [1] = {
698                 .start  = TEGRA_SPI2_BASE,
699                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
700                 .flags  = IORESOURCE_MEM,
701         },
702 };
703
704 static struct resource spi_resource3[] = {
705         [0] = {
706                 .start  = INT_SPI_3,
707                 .end    = INT_SPI_3,
708                 .flags  = IORESOURCE_IRQ,
709         },
710         [1] = {
711                 .start  = TEGRA_SPI3_BASE,
712                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
713                 .flags  = IORESOURCE_MEM,
714         },
715 };
716
717 static struct resource spi_resource4[] = {
718         [0] = {
719                 .start  = INT_SPI_4,
720                 .end    = INT_SPI_4,
721                 .flags  = IORESOURCE_IRQ,
722         },
723         [1] = {
724                 .start  = TEGRA_SPI4_BASE,
725                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
726                 .flags  = IORESOURCE_MEM,
727         },
728 };
729 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
730 static struct resource spi_resource5[] = {
731         [0] = {
732                 .start  = INT_SPI_5,
733                 .end    = INT_SPI_5,
734                 .flags  = IORESOURCE_IRQ,
735         },
736         [1] = {
737                 .start  = TEGRA_SPI5_BASE,
738                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
739                 .flags  = IORESOURCE_MEM,
740         },
741 };
742
743 static struct resource spi_resource6[] = {
744         [0] = {
745                 .start  = INT_SPI_6,
746                 .end    = INT_SPI_6,
747                 .flags  = IORESOURCE_IRQ,
748         },
749         [1] = {
750                 .start  = TEGRA_SPI6_BASE,
751                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
752                 .flags  = IORESOURCE_MEM,
753         },
754 };
755 #endif
756
757 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
758 static struct resource dtv_resource[] = {
759         [0] = {
760                 .start  = INT_DTV,
761                 .end    = INT_DTV,
762                 .flags  = IORESOURCE_IRQ,
763         },
764         [1] = {
765                 .start  = TEGRA_DTV_BASE,
766                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
767                 .flags  = IORESOURCE_MEM,
768         },
769         [2] = {
770                 .start  = TEGRA_DMA_REQ_SEL_DTV,
771                 .end    = TEGRA_DMA_REQ_SEL_DTV,
772                 .flags  = IORESOURCE_DMA
773         },
774 };
775 #endif
776
777
778 struct platform_device tegra_spi_device1 = {
779         .name           = "spi_tegra",
780         .id             = 0,
781         .resource       = spi_resource1,
782         .num_resources  = ARRAY_SIZE(spi_resource1),
783         .dev            = {
784                 .coherent_dma_mask      = 0xffffffff,
785         },
786 };
787
788 struct platform_device tegra_spi_device2 = {
789         .name           = "spi_tegra",
790         .id             = 1,
791         .resource       = spi_resource2,
792         .num_resources  = ARRAY_SIZE(spi_resource2),
793         .dev            = {
794                 .coherent_dma_mask      = 0xffffffff,
795         },
796 };
797
798 struct platform_device tegra_spi_device3 = {
799         .name           = "spi_tegra",
800         .id             = 2,
801         .resource       = spi_resource3,
802         .num_resources  = ARRAY_SIZE(spi_resource3),
803         .dev            = {
804                 .coherent_dma_mask      = 0xffffffff,
805         },
806 };
807
808 struct platform_device tegra_spi_device4 = {
809         .name           = "spi_tegra",
810         .id             = 3,
811         .resource       = spi_resource4,
812         .num_resources  = ARRAY_SIZE(spi_resource4),
813         .dev            = {
814                 .coherent_dma_mask      = 0xffffffff,
815         },
816 };
817 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
818 struct platform_device tegra_spi_device5 = {
819         .name           = "spi_tegra",
820         .id             = 4,
821         .resource       = spi_resource5,
822         .num_resources  = ARRAY_SIZE(spi_resource5),
823         .dev  = {
824                 .coherent_dma_mask      = 0xffffffff,
825         },
826 };
827
828 struct platform_device tegra_spi_device6 = {
829         .name           = "spi_tegra",
830         .id             = 5,
831         .resource       = spi_resource6,
832         .num_resources  = ARRAY_SIZE(spi_resource6),
833         .dev  = {
834                 .coherent_dma_mask      = 0xffffffff,
835         },
836 };
837 #endif
838
839 struct platform_device tegra11_spi_device1 = {
840         .name           = "spi-tegra114",
841         .id             = 0,
842         .resource       = spi_resource1,
843         .num_resources  = ARRAY_SIZE(spi_resource1),
844         .dev            = {
845                 .coherent_dma_mask      = DMA_BIT_MASK(64),
846         },
847 };
848
849 struct platform_device tegra11_spi_device2 = {
850         .name           = "spi-tegra114",
851         .id             = 1,
852         .resource       = spi_resource2,
853         .num_resources  = ARRAY_SIZE(spi_resource2),
854         .dev            = {
855                 .coherent_dma_mask      = DMA_BIT_MASK(64),
856         },
857 };
858
859 struct platform_device tegra11_spi_device3 = {
860         .name           = "spi-tegra114",
861         .id             = 2,
862         .resource       = spi_resource3,
863         .num_resources  = ARRAY_SIZE(spi_resource3),
864         .dev            = {
865                 .coherent_dma_mask      = DMA_BIT_MASK(64),
866         },
867 };
868
869 struct platform_device tegra11_spi_device4 = {
870         .name           = "spi-tegra114",
871         .id             = 3,
872         .resource       = spi_resource4,
873         .num_resources  = ARRAY_SIZE(spi_resource4),
874         .dev            = {
875                 .coherent_dma_mask      = DMA_BIT_MASK(64),
876         },
877 };
878
879 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
880 struct platform_device tegra11_spi_device5 = {
881         .name           = "spi-tegra114",
882         .id             = 4,
883         .resource       = spi_resource5,
884         .num_resources  = ARRAY_SIZE(spi_resource5),
885         .dev  = {
886                 .coherent_dma_mask      = DMA_BIT_MASK(64),
887         },
888 };
889
890 struct platform_device tegra11_spi_device6 = {
891         .name           = "spi-tegra114",
892         .id             = 5,
893         .resource       = spi_resource6,
894         .num_resources  = ARRAY_SIZE(spi_resource6),
895         .dev  = {
896                 .coherent_dma_mask      = DMA_BIT_MASK(64),
897         },
898 };
899 #endif
900
901 struct platform_device tegra_spi_slave_device1 = {
902         .name           = "spi_slave_tegra",
903         .id             = 0,
904         .resource       = spi_resource1,
905         .num_resources  = ARRAY_SIZE(spi_resource1),
906         .dev  = {
907                 .coherent_dma_mask      = 0xffffffff,
908         },
909 };
910
911 struct platform_device tegra_spi_slave_device2 = {
912         .name           = "spi_slave_tegra",
913         .id             = 1,
914         .resource       = spi_resource2,
915         .num_resources  = ARRAY_SIZE(spi_resource2),
916         .dev  = {
917                 .coherent_dma_mask      = 0xffffffff,
918         },
919 };
920
921 struct platform_device tegra_spi_slave_device3 = {
922         .name           = "spi_slave_tegra",
923         .id             = 2,
924         .resource       = spi_resource3,
925         .num_resources  = ARRAY_SIZE(spi_resource3),
926         .dev  = {
927                 .coherent_dma_mask      = 0xffffffff,
928         },
929 };
930
931 struct platform_device tegra_spi_slave_device4 = {
932         .name           = "spi_slave_tegra",
933         .id             = 3,
934         .resource       = spi_resource4,
935         .num_resources  = ARRAY_SIZE(spi_resource4),
936         .dev  = {
937                 .coherent_dma_mask      = 0xffffffff,
938         },
939 };
940 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
941 struct platform_device tegra_spi_slave_device5 = {
942         .name           = "spi_slave_tegra",
943         .id             = 4,
944         .resource       = spi_resource5,
945         .num_resources  = ARRAY_SIZE(spi_resource5),
946         .dev  = {
947                 .coherent_dma_mask      = 0xffffffff,
948         },
949 };
950
951 struct platform_device tegra_spi_slave_device6 = {
952         .name           = "spi_slave_tegra",
953         .id             = 5,
954         .resource       = spi_resource6,
955         .num_resources  = ARRAY_SIZE(spi_resource6),
956         .dev  = {
957                 .coherent_dma_mask      = 0xffffffff,
958         },
959 };
960 #endif
961
962 struct platform_device tegra11_spi_slave_device1 = {
963         .name           = "tegra11-spi-slave",
964         .id             = 0,
965         .resource       = spi_resource1,
966         .num_resources  = ARRAY_SIZE(spi_resource1),
967         .dev  = {
968                 .coherent_dma_mask      = 0xffffffff,
969         },
970 };
971
972 struct platform_device tegra11_spi_slave_device2 = {
973         .name           = "tegra11-spi-slave",
974         .id             = 1,
975         .resource       = spi_resource2,
976         .num_resources  = ARRAY_SIZE(spi_resource2),
977         .dev  = {
978                 .coherent_dma_mask      = 0xffffffff,
979         },
980 };
981
982 struct platform_device tegra11_spi_slave_device3 = {
983         .name           = "tegra11-spi-slave",
984         .id             = 2,
985         .resource       = spi_resource3,
986         .num_resources  = ARRAY_SIZE(spi_resource3),
987         .dev  = {
988                 .coherent_dma_mask      = 0xffffffff,
989         },
990 };
991
992 struct platform_device tegra11_spi_slave_device4 = {
993         .name           = "tegra11-spi-slave",
994         .id             = 3,
995         .resource       = spi_resource4,
996         .num_resources  = ARRAY_SIZE(spi_resource4),
997         .dev  = {
998                 .coherent_dma_mask      = 0xffffffff,
999         },
1000 };
1001 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1002 struct platform_device tegra11_spi_slave_device5 = {
1003         .name           = "tegra11-spi-slave",
1004         .id             = 4,
1005         .resource       = spi_resource5,
1006         .num_resources  = ARRAY_SIZE(spi_resource5),
1007         .dev  = {
1008                 .coherent_dma_mask      = 0xffffffff,
1009         },
1010 };
1011
1012 struct platform_device tegra11_spi_slave_device6 = {
1013         .name           = "tegra11-spi-slave",
1014         .id             = 5,
1015         .resource       = spi_resource6,
1016         .num_resources  = ARRAY_SIZE(spi_resource6),
1017         .dev  = {
1018                 .coherent_dma_mask      = 0xffffffff,
1019         },
1020 };
1021 #endif
1022
1023 static struct resource resources_nor[] = {
1024         [0] = {
1025                 .start = INT_SNOR,
1026                 .end = INT_SNOR,
1027                 .flags = IORESOURCE_IRQ,
1028         },
1029         [1] = {
1030                 /* Map SNOR Controller */
1031                 .start = TEGRA_SNOR_BASE,
1032                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
1033                 .flags = IORESOURCE_MEM,
1034         },
1035         [2] = {
1036                 /* Map the size of flash */
1037                 .start = TEGRA_NOR_FLASH_BASE,
1038                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
1039                 .flags = IORESOURCE_MEM,
1040         }
1041 };
1042
1043 struct platform_device tegra_nor_device = {
1044         .name = "tegra-nor",
1045         .id = -1,
1046         .num_resources = ARRAY_SIZE(resources_nor),
1047         .resource = resources_nor,
1048         .dev = {
1049                 .coherent_dma_mask = 0xffffffff,
1050         },
1051 };
1052
1053 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1054 struct platform_device tegra_dtv_device = {
1055         .name           = "tegra_dtv",
1056         .id             = -1,
1057         .resource       = dtv_resource,
1058         .num_resources  = ARRAY_SIZE(dtv_resource),
1059         .dev = {
1060                 .init_name = "dtv",
1061                 .coherent_dma_mask = 0xffffffff,
1062         },
1063 };
1064 #endif
1065
1066
1067 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1068
1069 static struct resource dtv_resource[] = {
1070         [0] = {
1071                 .start  = TEGRA_DTV_BASE,
1072                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
1073                 .flags  = IORESOURCE_MEM,
1074         },
1075         [1] = {
1076                 .start  = TEGRA_DMA_REQ_SEL_DTV,
1077                 .end    = TEGRA_DMA_REQ_SEL_DTV,
1078                 .flags  = IORESOURCE_DMA
1079         },
1080 };
1081
1082 struct platform_device tegra_dtv_device = {
1083         .name           = "tegra_dtv",
1084         .id             = -1,
1085         .resource       = dtv_resource,
1086         .num_resources  = ARRAY_SIZE(dtv_resource),
1087         .dev = {
1088                 .init_name = "dtv",
1089                 .coherent_dma_mask = 0xffffffff,
1090         },
1091 };
1092 #endif
1093
1094 static struct resource sdhci_resource1[] = {
1095         [0] = {
1096                 .start  = INT_SDMMC1,
1097                 .end    = INT_SDMMC1,
1098                 .flags  = IORESOURCE_IRQ,
1099         },
1100         [1] = {
1101                 .start  = TEGRA_SDMMC1_BASE,
1102                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
1103                 .flags  = IORESOURCE_MEM,
1104         },
1105 };
1106
1107 static struct resource sdhci_resource2[] = {
1108         [0] = {
1109                 .start  = INT_SDMMC2,
1110                 .end    = INT_SDMMC2,
1111                 .flags  = IORESOURCE_IRQ,
1112         },
1113         [1] = {
1114                 .start  = TEGRA_SDMMC2_BASE,
1115                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
1116                 .flags  = IORESOURCE_MEM,
1117         },
1118 };
1119
1120 static struct resource sdhci_resource3[] = {
1121         [0] = {
1122                 .start  = INT_SDMMC3,
1123                 .end    = INT_SDMMC3,
1124                 .flags  = IORESOURCE_IRQ,
1125         },
1126         [1] = {
1127                 .start  = TEGRA_SDMMC3_BASE,
1128                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
1129                 .flags  = IORESOURCE_MEM,
1130         },
1131 };
1132
1133 static struct resource sdhci_resource4[] = {
1134         [0] = {
1135                 .start  = INT_SDMMC4,
1136                 .end    = INT_SDMMC4,
1137                 .flags  = IORESOURCE_IRQ,
1138         },
1139         [1] = {
1140                 .start  = TEGRA_SDMMC4_BASE,
1141                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
1142                 .flags  = IORESOURCE_MEM,
1143         },
1144 };
1145
1146 struct platform_device tegra_pci_device = {
1147         .name           = "tegra-pcie",
1148         .id             = 0,
1149         .resource       = 0,
1150         .num_resources  = 0,
1151         .dev = {
1152                 .platform_data = 0,
1153         },
1154 };
1155
1156 /* board files should fill in platform_data register the devices themselvs.
1157  * See board-harmony.c for an example
1158  */
1159 struct platform_device tegra_sdhci_device1 = {
1160         .name           = "sdhci-tegra",
1161         .id             = 0,
1162         .resource       = sdhci_resource1,
1163         .num_resources  = ARRAY_SIZE(sdhci_resource1),
1164 };
1165
1166 struct platform_device tegra_sdhci_device2 = {
1167         .name           = "sdhci-tegra",
1168         .id             = 1,
1169         .resource       = sdhci_resource2,
1170         .num_resources  = ARRAY_SIZE(sdhci_resource2),
1171 };
1172
1173 struct platform_device tegra_sdhci_device3 = {
1174         .name           = "sdhci-tegra",
1175         .id             = 2,
1176         .resource       = sdhci_resource3,
1177         .num_resources  = ARRAY_SIZE(sdhci_resource3),
1178 };
1179
1180 struct platform_device tegra_sdhci_device4 = {
1181         .name           = "sdhci-tegra",
1182         .id             = 3,
1183         .resource       = sdhci_resource4,
1184         .num_resources  = ARRAY_SIZE(sdhci_resource4),
1185 };
1186
1187 static struct resource tegra_usb1_resources[] = {
1188         [0] = {
1189                 .start  = TEGRA_USB_BASE,
1190                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1191                 .flags  = IORESOURCE_MEM,
1192         },
1193         [1] = {
1194                 .start  = INT_USB,
1195                 .end    = INT_USB,
1196                 .flags  = IORESOURCE_IRQ,
1197         },
1198 };
1199
1200 static struct resource tegra_usb2_resources[] = {
1201         [0] = {
1202                 .start  = TEGRA_USB2_BASE,
1203                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
1204                 .flags  = IORESOURCE_MEM,
1205         },
1206         [1] = {
1207                 .start  = INT_USB2,
1208                 .end    = INT_USB2,
1209                 .flags  = IORESOURCE_IRQ,
1210         },
1211 };
1212
1213 static struct resource tegra_usb3_resources[] = {
1214         [0] = {
1215                 .start  = TEGRA_USB3_BASE,
1216                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
1217                 .flags  = IORESOURCE_MEM,
1218         },
1219         [1] = {
1220                 .start  = INT_USB3,
1221                 .end    = INT_USB3,
1222                 .flags  = IORESOURCE_IRQ,
1223         },
1224 };
1225
1226 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1227 static struct resource tegra_xusb_resources[] = {
1228         [0] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_HOST_BASE, TEGRA_XUSB_HOST_SIZE,
1229                         "host"),
1230         [1] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_FPCI_BASE, TEGRA_XUSB_FPCI_SIZE,
1231                         "fpci"),
1232         [2] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_IPFS_BASE, TEGRA_XUSB_IPFS_SIZE,
1233                         "ipfs"),
1234         [3] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_PADCTL_BASE,
1235                         TEGRA_XUSB_PADCTL_SIZE, "padctl"),
1236         [4] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_INT, "host"),
1237         [5] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_SMI, "host-smi"),
1238         [6] = DEFINE_RES_IRQ_NAMED(INT_XUSB_PADCTL, "padctl"),
1239         [7] = DEFINE_RES_IRQ_NAMED(INT_USB3, "usb3"),
1240         [8] = DEFINE_RES_IRQ_NAMED(INT_USB2, "usb2"),
1241 };
1242
1243 static u64 tegra_xusb_dmamask = DMA_BIT_MASK(64);
1244
1245 struct platform_device tegra_xhci_device = {
1246         .name = "tegra-xhci",
1247         .id = -1,
1248         .dev = {
1249                 .dma_mask = &tegra_xusb_dmamask,
1250                 .coherent_dma_mask = DMA_BIT_MASK(64),
1251         },
1252         .resource = tegra_xusb_resources,
1253         .num_resources = ARRAY_SIZE(tegra_xusb_resources),
1254 };
1255 #endif
1256
1257 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(64);
1258
1259 struct platform_device tegra_ehci1_device = {
1260         .name   = "tegra-ehci",
1261         .id     = 0,
1262         .dev    = {
1263                 .dma_mask       = &tegra_ehci_dmamask,
1264                 .coherent_dma_mask = DMA_BIT_MASK(64),
1265         },
1266         .resource = tegra_usb1_resources,
1267         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
1268 };
1269
1270 struct platform_device tegra_ehci2_device = {
1271         .name   = "tegra-ehci",
1272         .id     = 1,
1273         .dev    = {
1274                 .dma_mask       = &tegra_ehci_dmamask,
1275                 .coherent_dma_mask = DMA_BIT_MASK(64),
1276         },
1277         .resource = tegra_usb2_resources,
1278         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
1279 };
1280
1281 struct platform_device tegra_ehci3_device = {
1282         .name   = "tegra-ehci",
1283         .id     = 2,
1284         .dev    = {
1285                 .dma_mask       = &tegra_ehci_dmamask,
1286                 .coherent_dma_mask = DMA_BIT_MASK(64),
1287         },
1288         .resource = tegra_usb3_resources,
1289         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
1290 };
1291
1292 static struct resource tegra_pmu_resources[] = {
1293         [0] = {
1294                 .start  = INT_CPU0_PMU_INTR,
1295                 .end    = INT_CPU0_PMU_INTR,
1296                 .flags  = IORESOURCE_IRQ,
1297         },
1298         [1] = {
1299                 .start  = INT_CPU1_PMU_INTR,
1300                 .end    = INT_CPU1_PMU_INTR,
1301                 .flags  = IORESOURCE_IRQ,
1302         },
1303 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1304         [2] = {
1305                 .start  = INT_CPU2_PMU_INTR,
1306                 .end    = INT_CPU2_PMU_INTR,
1307                 .flags  = IORESOURCE_IRQ,
1308         },
1309         [3] = {
1310                 .start  = INT_CPU3_PMU_INTR,
1311                 .end    = INT_CPU3_PMU_INTR,
1312                 .flags  = IORESOURCE_IRQ,
1313         },
1314 #endif
1315 };
1316
1317 struct platform_device tegra_pmu_device = {
1318         .name           = "arm-pmu",
1319         .id             = -1,
1320         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
1321         .resource       = tegra_pmu_resources,
1322 };
1323
1324 static struct resource tegra_uarta_resources[] = {
1325         [0] = {
1326                 .start  = TEGRA_UARTA_BASE,
1327                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
1328                 .flags  = IORESOURCE_MEM,
1329         },
1330         [1] = {
1331                 .start  = INT_UARTA,
1332                 .end    = INT_UARTA,
1333                 .flags  = IORESOURCE_IRQ,
1334         },
1335 };
1336
1337 static struct resource tegra_uartb_resources[] = {
1338         [0] = {
1339                 .start  = TEGRA_UARTB_BASE,
1340                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
1341                 .flags  = IORESOURCE_MEM,
1342         },
1343         [1] = {
1344                 .start  = INT_UARTB,
1345                 .end    = INT_UARTB,
1346                 .flags  = IORESOURCE_IRQ,
1347         },
1348 };
1349
1350 static struct resource tegra_uartc_resources[] = {
1351         [0] = {
1352                 .start  = TEGRA_UARTC_BASE,
1353                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
1354                 .flags  = IORESOURCE_MEM,
1355         },
1356         [1] = {
1357                 .start  = INT_UARTC,
1358                 .end    = INT_UARTC,
1359                 .flags  = IORESOURCE_IRQ,
1360         },
1361 };
1362
1363 static struct resource tegra_uartd_resources[] = {
1364         [0] = {
1365                 .start  = TEGRA_UARTD_BASE,
1366                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
1367                 .flags  = IORESOURCE_MEM,
1368         },
1369         [1] = {
1370                 .start  = INT_UARTD,
1371                 .end    = INT_UARTD,
1372                 .flags  = IORESOURCE_IRQ,
1373         },
1374 };
1375
1376 static struct resource tegra_uarte_resources[] = {
1377         [0] = {
1378                 .start  = TEGRA_UARTE_BASE,
1379                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
1380                 .flags  = IORESOURCE_MEM,
1381         },
1382         [1] = {
1383                 .start  = INT_UARTE,
1384                 .end    = INT_UARTE,
1385                 .flags  = IORESOURCE_IRQ,
1386         },
1387 };
1388
1389 #define TEGRA_UART_NAME "serial-tegra"
1390
1391 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
1392 #define UART_DMA_BIT_MASK DMA_BIT_MASK(64)
1393 #else
1394 #define UART_DMA_BIT_MASK DMA_BIT_MASK(32)
1395 #endif
1396
1397 struct platform_device tegra_uarta_device = {
1398         .name   = TEGRA_UART_NAME,
1399         .id     = 0,
1400         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
1401         .resource       = tegra_uarta_resources,
1402         .dev    = {
1403                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1404         },
1405 };
1406
1407 struct platform_device tegra_uartb_device = {
1408         .name   = TEGRA_UART_NAME,
1409         .id     = 1,
1410         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
1411         .resource       = tegra_uartb_resources,
1412         .dev    = {
1413                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1414         },
1415 };
1416
1417 struct platform_device tegra_uartc_device = {
1418         .name   = TEGRA_UART_NAME,
1419         .id     = 2,
1420         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
1421         .resource       = tegra_uartc_resources,
1422         .dev    = {
1423                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1424         },
1425 };
1426
1427 struct platform_device tegra_uartd_device = {
1428         .name   = TEGRA_UART_NAME,
1429         .id     = 3,
1430         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
1431         .resource       = tegra_uartd_resources,
1432         .dev    = {
1433                 .coherent_dma_mask      = UART_DMA_BIT_MASK,
1434         },
1435 };
1436
1437 struct platform_device tegra_uarte_device = {
1438         .name   = "tegra_uart",
1439         .id     = 4,
1440         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
1441         .resource       = tegra_uarte_resources,
1442         .dev    = {
1443                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1444         },
1445 };
1446
1447 static struct plat_serial8250_port debug_uarta_platform_data[] = {
1448         {
1449                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
1450                 .mapbase        = TEGRA_UARTA_BASE,
1451                 .irq            = INT_UARTA,
1452                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1453                 .type           = PORT_TEGRA,
1454                 .iotype         = UPIO_MEM,
1455                 .regshift       = 2,
1456         },
1457         {
1458                 .flags          = 0,
1459         },
1460 };
1461
1462 static struct plat_serial8250_port debug_uartb_platform_data[] = {
1463         {
1464                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
1465                 .mapbase        = TEGRA_UARTB_BASE,
1466                 .irq            = INT_UARTB,
1467                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1468                 .type           = PORT_TEGRA,
1469                 .iotype         = UPIO_MEM,
1470                 .regshift       = 2,
1471         },
1472         {
1473                 .flags          = 0,
1474         },
1475 };
1476
1477 static struct plat_serial8250_port debug_uartc_platform_data[] = {
1478         {
1479                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
1480                 .mapbase        = TEGRA_UARTC_BASE,
1481                 .irq            = INT_UARTC,
1482                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1483                 .type           = PORT_TEGRA,
1484                 .iotype         = UPIO_MEM,
1485                 .regshift       = 2,
1486         },
1487         {
1488                 .flags          = 0,
1489         },
1490 };
1491
1492 static struct plat_serial8250_port debug_uartd_platform_data[] = {
1493         {
1494                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
1495                 .mapbase        = TEGRA_UARTD_BASE,
1496                 .irq            = INT_UARTD,
1497                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1498                 .type           = PORT_TEGRA,
1499                 .iotype         = UPIO_MEM,
1500                 .regshift       = 2,
1501         },
1502         {
1503                 .flags          = 0,
1504         },
1505 };
1506
1507 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1508 static struct plat_serial8250_port debug_uarte_platform_data[] = {
1509         {
1510                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
1511                 .mapbase        = TEGRA_UARTE_BASE,
1512                 .irq            = INT_UARTE,
1513                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1514                 .type           = PORT_TEGRA,
1515                 .iotype         = UPIO_MEM,
1516                 .regshift       = 2,
1517         },
1518         {
1519                 .flags          = 0,
1520         },
1521 };
1522 #endif
1523
1524 struct platform_device debug_uarta_device = {
1525         .name = "serial8250",
1526         .id = PLAT8250_DEV_PLATFORM,
1527         .dev = {
1528                 .platform_data = debug_uarta_platform_data,
1529         },
1530 };
1531
1532 struct platform_device debug_uartb_device = {
1533         .name = "serial8250",
1534         .id = PLAT8250_DEV_PLATFORM,
1535         .dev = {
1536                 .platform_data = debug_uartb_platform_data,
1537         },
1538 };
1539
1540 struct platform_device debug_uartc_device = {
1541         .name = "serial8250",
1542         .id = PLAT8250_DEV_PLATFORM,
1543         .dev = {
1544                 .platform_data = debug_uartc_platform_data,
1545         },
1546 };
1547
1548 struct platform_device debug_uartd_device = {
1549         .name = "serial8250",
1550         .id = PLAT8250_DEV_PLATFORM,
1551         .dev = {
1552                 .platform_data = debug_uartd_platform_data,
1553         },
1554 };
1555
1556 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1557 struct platform_device debug_uarte_device = {
1558         .name = "serial8250",
1559         .id = PLAT8250_DEV_PLATFORM,
1560         .dev = {
1561                 .platform_data = debug_uarte_platform_data,
1562         },
1563 };
1564 #endif
1565
1566 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1567 static struct resource i2s_resource1[] = {
1568         [0] = {
1569                 .start  = INT_I2S1,
1570                 .end    = INT_I2S1,
1571                 .flags  = IORESOURCE_IRQ
1572         },
1573         [1] = {
1574                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1575                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1576                 .flags  = IORESOURCE_DMA
1577         },
1578         [2] = {
1579                 .start  = TEGRA_I2S1_BASE,
1580                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1581                 .flags  = IORESOURCE_MEM
1582         }
1583 };
1584
1585 struct platform_device tegra_i2s_device1 = {
1586         .name           = "tegra20-i2s",
1587         .id             = 0,
1588         .resource       = i2s_resource1,
1589         .num_resources  = ARRAY_SIZE(i2s_resource1),
1590 };
1591
1592 static struct resource i2s_resource2[] = {
1593         [0] = {
1594                 .start  = INT_I2S2,
1595                 .end    = INT_I2S2,
1596                 .flags  = IORESOURCE_IRQ
1597         },
1598         [1] = {
1599                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1600                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1601                 .flags  = IORESOURCE_DMA
1602         },
1603         [2] = {
1604                 .start  = TEGRA_I2S2_BASE,
1605                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1606                 .flags  = IORESOURCE_MEM
1607         }
1608 };
1609
1610 struct platform_device tegra_i2s_device2 = {
1611         .name           = "tegra20-i2s",
1612         .id             = 1,
1613         .resource       = i2s_resource2,
1614         .num_resources  = ARRAY_SIZE(i2s_resource2),
1615 };
1616 #else
1617 static struct resource i2s_resource0[] = {
1618         [0] = {
1619                 .start  = TEGRA_I2S0_BASE,
1620                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1621                 .flags  = IORESOURCE_MEM
1622         }
1623 };
1624
1625 struct platform_device tegra_i2s_device0 = {
1626         .name           = "tegra30-i2s",
1627         .id             = 0,
1628         .resource       = i2s_resource0,
1629         .num_resources  = ARRAY_SIZE(i2s_resource0),
1630 };
1631
1632 static struct resource i2s_resource1[] = {
1633         [0] = {
1634                 .start  = TEGRA_I2S1_BASE,
1635                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1636                 .flags  = IORESOURCE_MEM
1637         }
1638 };
1639
1640 struct platform_device tegra_i2s_device1 = {
1641         .name           = "tegra30-i2s",
1642         .id             = 1,
1643         .resource       = i2s_resource1,
1644         .num_resources  = ARRAY_SIZE(i2s_resource1),
1645 };
1646
1647 static struct resource i2s_resource2[] = {
1648         [0] = {
1649                 .start  = TEGRA_I2S2_BASE,
1650                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1651                 .flags  = IORESOURCE_MEM
1652         }
1653 };
1654
1655 struct platform_device tegra_i2s_device2 = {
1656         .name           = "tegra30-i2s",
1657         .id             = 2,
1658         .resource       = i2s_resource2,
1659         .num_resources  = ARRAY_SIZE(i2s_resource2),
1660 };
1661
1662 static struct resource i2s_resource3[] = {
1663         [0] = {
1664                 .start  = TEGRA_I2S3_BASE,
1665                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1666                 .flags  = IORESOURCE_MEM
1667         }
1668 };
1669
1670 struct platform_device tegra_i2s_device3 = {
1671         .name           = "tegra30-i2s",
1672         .id             = 3,
1673         .resource       = i2s_resource3,
1674         .num_resources  = ARRAY_SIZE(i2s_resource3),
1675 };
1676
1677 static struct resource i2s_resource4[] = {
1678         [0] = {
1679                 .start  = TEGRA_I2S4_BASE,
1680                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1681                 .flags  = IORESOURCE_MEM
1682         }
1683 };
1684
1685 struct platform_device tegra_i2s_device4 = {
1686         .name           = "tegra30-i2s",
1687         .id             = 4,
1688         .resource       = i2s_resource4,
1689         .num_resources  = ARRAY_SIZE(i2s_resource4),
1690 };
1691 #endif
1692
1693 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1694 static struct resource spdif_resource[] = {
1695         [0] = {
1696                 .start  = INT_SPDIF,
1697                 .end    = INT_SPDIF,
1698                 .flags  = IORESOURCE_IRQ
1699         },
1700         [1] = {
1701                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1702                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1703                 .flags  = IORESOURCE_DMA
1704         },
1705         [2] = {
1706                 .start  = TEGRA_SPDIF_BASE,
1707                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1708                 .flags  = IORESOURCE_MEM
1709         }
1710 };
1711
1712 struct platform_device tegra_spdif_device = {
1713         .name           = "tegra20-spdif",
1714         .id             = -1,
1715         .resource       = spdif_resource,
1716         .num_resources  = ARRAY_SIZE(spdif_resource),
1717 };
1718 #else
1719 static struct resource spdif_resource[] = {
1720         [0] = {
1721                 .start  = TEGRA_SPDIF_BASE,
1722                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1723                 .flags  = IORESOURCE_MEM
1724         }
1725 };
1726
1727 struct platform_device tegra_spdif_device = {
1728         .name           = "tegra30-spdif",
1729         .id             = -1,
1730         .resource       = spdif_resource,
1731         .num_resources  = ARRAY_SIZE(spdif_resource),
1732 };
1733 #endif
1734
1735 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1736 static struct resource ahub_resource[] = {
1737         [0] = {
1738                 .start  = TEGRA_APBIF0_BASE,
1739                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1740                 .flags  = IORESOURCE_MEM
1741         },
1742         [1] = {
1743                 .start  = TEGRA_AHUB_BASE,
1744                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1745                 .flags  = IORESOURCE_MEM
1746         }
1747 };
1748
1749 struct platform_device tegra_ahub_device = {
1750         .name   = "tegra30-ahub",
1751         .id     = -1,
1752         .resource       = ahub_resource,
1753         .num_resources  = ARRAY_SIZE(ahub_resource),
1754 };
1755
1756 static struct resource dam_resource0[] = {
1757         [0] = {
1758                 .start = TEGRA_DAM0_BASE,
1759                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1760                 .flags = IORESOURCE_MEM
1761         }
1762 };
1763
1764 struct platform_device tegra_dam_device0 = {
1765         .name = "tegra30-dam",
1766         .id = 0,
1767         .resource      = dam_resource0,
1768         .num_resources = ARRAY_SIZE(dam_resource0),
1769 };
1770
1771 static struct resource dam_resource1[] = {
1772         [0] = {
1773                 .start = TEGRA_DAM1_BASE,
1774                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1775                 .flags = IORESOURCE_MEM
1776         }
1777 };
1778
1779 struct platform_device tegra_dam_device1 = {
1780         .name = "tegra30-dam",
1781         .id = 1,
1782         .resource      = dam_resource1,
1783         .num_resources = ARRAY_SIZE(dam_resource1),
1784 };
1785
1786 static struct resource dam_resource2[] = {
1787         [0] = {
1788                 .start = TEGRA_DAM2_BASE,
1789                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1790                 .flags = IORESOURCE_MEM
1791         }
1792 };
1793
1794 struct platform_device tegra_dam_device2 = {
1795         .name = "tegra30-dam",
1796         .id = 2,
1797         .resource      = dam_resource2,
1798         .num_resources = ARRAY_SIZE(dam_resource2),
1799 };
1800
1801 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1802 static struct resource hda_platform_resources[] = {
1803         [0] = {
1804                 .start  = TEGRA_HDA_BASE,
1805                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1806                 .flags  = IORESOURCE_MEM
1807         },
1808         [1] = {
1809                 .start  = INT_HDA,
1810                 .end    = INT_HDA,
1811                 .flags  = IORESOURCE_IRQ
1812         },
1813 };
1814
1815 struct platform_device tegra_hda_device = {
1816         .name           = "tegra30-hda",
1817         .id             = -1,
1818         .dev = {
1819                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1820                 .dma_mask               = &tegra_hda_dma_mask,
1821         },
1822         .resource       = hda_platform_resources,
1823         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1824 };
1825 #endif
1826
1827 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1828 static struct resource dmic_resource0[] = {
1829         [0] = {
1830                 .start = TEGRA_DMIC0_BASE,
1831                 .end   = TEGRA_DMIC0_BASE + TEGRA_DMIC0_SIZE - 1,
1832                 .flags = IORESOURCE_MEM
1833         }
1834 };
1835
1836 struct platform_device tegra_dmic_device0 = {
1837         .name = "tegra-dmic",
1838         .id = 0,
1839         .resource      = dmic_resource0,
1840         .num_resources = ARRAY_SIZE(dmic_resource0),
1841 };
1842
1843 static struct resource dmic_resource1[] = {
1844         [0] = {
1845                 .start = TEGRA_DMIC1_BASE,
1846                 .end   = TEGRA_DMIC1_BASE + TEGRA_DMIC1_SIZE - 1,
1847                 .flags = IORESOURCE_MEM
1848         }
1849 };
1850
1851 struct platform_device tegra_dmic_device1 = {
1852         .name = "tegra-dmic",
1853         .id = 1,
1854         .resource      = dmic_resource1,
1855         .num_resources = ARRAY_SIZE(dmic_resource1),
1856 };
1857 #endif
1858
1859 struct platform_device spdif_dit_device = {
1860         .name = "spdif-dit",
1861         .id = 0,
1862 };
1863
1864 struct platform_device bluetooth_dit_device = {
1865         .name = "spdif-dit",
1866         .id = 1,
1867 };
1868
1869 struct platform_device baseband_dit_device = {
1870         .name = "spdif-dit",
1871         .id = 2,
1872 };
1873
1874 struct platform_device tegra_tdm_pcm_device = {
1875         .name = "tegra-tdm-pcm-audio",
1876         .id = -1,
1877 };
1878
1879 static struct resource w1_resources[] = {
1880         [0] = {
1881                 .start = INT_OWR,
1882                 .end   = INT_OWR,
1883                 .flags = IORESOURCE_IRQ
1884         },
1885         [1] = {
1886                 .start = TEGRA_OWR_BASE,
1887                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1888                 .flags = IORESOURCE_MEM
1889         }
1890 };
1891
1892 struct platform_device tegra_w1_device = {
1893         .name          = "tegra_w1",
1894         .id            = -1,
1895         .resource      = w1_resources,
1896         .num_resources = ARRAY_SIZE(w1_resources),
1897 };
1898
1899 static struct resource tegra_udc_resources[] = {
1900         [0] = {
1901                 .start  = TEGRA_USB_BASE,
1902                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1903                 .flags  = IORESOURCE_MEM,
1904         },
1905         [1] = {
1906                 .start  = INT_USB,
1907                 .end    = INT_USB,
1908                 .flags  = IORESOURCE_IRQ,
1909         },
1910 };
1911
1912 static u64 tegra_udc_dmamask = DMA_BIT_MASK(64);
1913
1914 struct platform_device tegra_udc_device = {
1915         .name   = "tegra-udc",
1916         .id     = 0,
1917         .dev    = {
1918                 .dma_mask       = &tegra_udc_dmamask,
1919                 .coherent_dma_mask = DMA_BIT_MASK(64),
1920         },
1921         .resource = tegra_udc_resources,
1922         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1923 };
1924
1925 static struct resource tegra_otg_resources[] = {
1926         [0] = {
1927                 .start  = TEGRA_USB_BASE,
1928                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1929                 .flags  = IORESOURCE_MEM,
1930         },
1931         [1] = {
1932                 .start  = INT_USB,
1933                 .end    = INT_USB,
1934                 .flags  = IORESOURCE_IRQ,
1935         },
1936 };
1937
1938 struct platform_device tegra_otg_device = {
1939         .name           = "tegra-otg",
1940         .id             = -1,
1941         .resource       = tegra_otg_resources,
1942         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1943 };
1944
1945 #ifdef CONFIG_SATA_AHCI_TEGRA
1946 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1947
1948 static struct resource tegra_sata_resources[] = {
1949         [0] = {
1950                 .start = TEGRA_SATA_BAR5_BASE,
1951                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1952                 .flags = IORESOURCE_MEM,
1953         },
1954         [1] = {
1955                 .start = TEGRA_SATA_CONFIG_BASE,
1956                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1957                 .flags = IORESOURCE_MEM,
1958         },
1959         [2] = {
1960                 .start = INT_SATA_CTL,
1961                 .end = INT_SATA_CTL,
1962                 .flags = IORESOURCE_IRQ,
1963         },
1964 };
1965
1966 struct platform_device tegra_sata_device = {
1967         .name   = "tegra-sata",
1968         .id     = 0,
1969         .dev    = {
1970                 .platform_data = 0,
1971                 .coherent_dma_mask = DMA_BIT_MASK(32),
1972                 .dma_mask = &tegra_sata_dma_mask,
1973         },
1974         .resource = tegra_sata_resources,
1975         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1976 };
1977 #endif
1978
1979 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1980 static struct resource das_resource[] = {
1981         [0] = {
1982                 .start  = TEGRA_APB_MISC_DAS_BASE,
1983                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1984                 .flags  = IORESOURCE_MEM
1985         }
1986 };
1987
1988 struct platform_device tegra_das_device = {
1989         .name           = "tegra20-das",
1990         .id             = -1,
1991         .resource       = das_resource,
1992         .num_resources  = ARRAY_SIZE(das_resource),
1993 };
1994 #endif
1995
1996 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1997 static struct resource tegra_gart_resources[] = {
1998         [0] = {
1999                 .name   = "mc",
2000                 .flags  = IORESOURCE_MEM,
2001                 .start  = TEGRA_MC_BASE,
2002                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
2003         },
2004         [1] = {
2005                 .name   = "gart",
2006                 .flags  = IORESOURCE_MEM,
2007                 .start  = TEGRA_GART_BASE,
2008                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
2009         }
2010 };
2011
2012 struct platform_device tegra_gart_device = {
2013         .name           = "tegra_gart",
2014         .id             = -1,
2015         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
2016         .resource       = tegra_gart_resources
2017 };
2018 #endif
2019
2020 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
2021 static struct resource tegra_smmu_resources[] = {
2022         {
2023                 .name   = "mc",
2024                 .flags  = IORESOURCE_MEM,
2025                 .start  = TEGRA_MC_BASE,
2026                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
2027         },
2028         {
2029                 .name   = "ahbarb",
2030                 .flags  = IORESOURCE_MEM,
2031                 .start  = TEGRA_AHB_ARB_BASE,
2032                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
2033         },
2034 };
2035
2036 struct platform_device tegra_smmu_device = {
2037         .name           = "tegra_smmu",
2038         .id             = -1,
2039         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
2040         .resource       = tegra_smmu_resources
2041 };
2042
2043 static struct resource tegra_smmu[] = {
2044         [0] = {
2045                 .start  = TEGRA_SMMU_BASE,
2046                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
2047         },
2048 };
2049
2050 struct resource *tegra_smmu_window(int wnum)
2051 {
2052         return &tegra_smmu[wnum];
2053 }
2054
2055 int tegra_smmu_window_count(void)
2056 {
2057         return ARRAY_SIZE(tegra_smmu);
2058 }
2059
2060 struct swgid_fixup {
2061         const char * const name;
2062         u64 swgids;
2063 };
2064
2065 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2066 #define DUMMY_DEV_NAME "dummy_dev"
2067 #define DUMMY_DEV_MAX_NAME_SIZE 100
2068 static char dummy_name[DUMMY_DEV_MAX_NAME_SIZE] = DUMMY_DEV_NAME;
2069 #endif
2070
2071 /*
2072  * FIXME: They should have a DT entry with swgroup IDs.
2073  */
2074 struct swgid_fixup tegra_swgid_fixup[] = {
2075         { .name = "540c0000.epp",       .swgids = SWGID(EPP), },
2076         { .name = "epp",        .swgids = SWGID(EPP), },
2077         { .name = "54200000.dc",        .swgids = SWGID(DC), },
2078         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
2079         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
2080         { .name = "gr2d",       .swgids = SWGID(G2), },
2081         { .name = "gr3d",       .swgids = SWGID(NV) | SWGID(NV2), },
2082         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |      \
2083           SWGID(EPP) | SWGID(HDA), },
2084         { .name = "isp",        .swgids = SWGID(ISP), },
2085         { .name = "max77660",   .swgids = SWGID(PPCS), },
2086         { .name = "max8831",    .swgids = SWGID(PPCS), },
2087         { .name = "msenc",      .swgids = SWGID(MSENC), },
2088         { .name = "mpe",        .swgids = SWGID(MPE), },
2089         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
2090         { .name = "nvavp",      .swgids = SWGID(AVPC), },
2091         { .name = "sdhci-tegra",        .swgids = SWGID(PPCS), },
2092         { .name = "serial8250", .swgids = SWGID(PPCS), },
2093         { .name = "serial-tegra",      .swgids = SWGID(PPCS), },
2094         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS), },
2095         { .name = "spdif-dit",  .swgids = SWGID(PPCS), },
2096         { .name = "tegra11-se", .swgids = SWGID(PPCS), },
2097         { .name = "tegra11-spi",        .swgids = SWGID(PPCS), },
2098         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS), },
2099         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS), },
2100         { .name = "tegra30-dam",        .swgids = SWGID(PPCS), },
2101         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
2102         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS), },
2103         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS), },
2104         { .name = "tegradc", .swgids = SWGID(DC) | SWGID(DCB), },
2105         { .name = "tegra_bb",   .swgids = SWGID(PPCS), },
2106         { .name = "tegra_dma",  .swgids = SWGID(PPCS), },
2107         { .name = "tegra-ehci", .swgids = SWGID(PPCS), },
2108         { .name = "tegra-fuse", .swgids = SWGID(PPCS), },
2109         { .name = "tegra-i2c",  .swgids = SWGID(PPCS), },
2110         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
2111         { .name = "tegra-otg",  .swgids = SWGID(PPCS), },
2112         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS), },
2113         { .name = "tegra-rtc",  .swgids = SWGID(PPCS), },
2114         { .name = "tegra-sata", .swgids = SWGID(SATA), },
2115         { .name = "tegra-se",   .swgids = SWGID(PPCS), },
2116         { .name = "tegra-snd",  .swgids = SWGID(PPCS), },
2117         { .name = "tegra-tzram",        .swgids = SWGID(VDE), },
2118         { .name = "tegra_uart", .swgids = SWGID(PPCS), },
2119         { .name = "tegra-udc",  .swgids = SWGID(PPCS), },
2120         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS), },
2121         { .name = "tsec",       .swgids = SWGID(TSEC), },
2122         { .name = "vi", .swgids = SWGID(VI), },
2123         { .name = "therm_est",  .swgids = SWGID(PPCS), },
2124         { .name = "tegra-xhci", .swgids = SWGID(XUSB_HOST), },
2125 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2126         { .name = dummy_name,   .swgids = SWGID(PPCS) },
2127 #endif
2128         {},
2129 };
2130
2131 struct swgid_fixup tegra_swgid_fixup_t124[] = {
2132         { .name = "54200000.dc",        .swgids = SWGID(DC), },
2133         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
2134         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
2135         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |
2136           SWGID(EPP) | SWGID(HDA), },
2137         { .name = "isp",        .swgids = SWGID(ISP2) | SWGID(ISP2B), },
2138         { .name = "max77660",   .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2139           SWGID(PPCS2), },
2140         { .name = "max8831",    .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2141           SWGID(PPCS2), },
2142         { .name = "msenc",      .swgids = SWGID(MSENC), },
2143         { .name = "mpe",        .swgids = SWGID(MPE), },
2144         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
2145         { .name = "nvavp",      .swgids = SWGID(AVPC) | SWGID(A9AVP), },
2146         { .name = "serial8250", .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2147           SWGID(PPCS2), },
2148         { .name = "serial-tegra",       .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2149           SWGID(PPCS2), },
2150         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2151           SWGID(PPCS2), },
2152         { .name = "spdif-dit",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2153           SWGID(PPCS2), },
2154         { .name = "tegra12-se", .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2155           SWGID(PPCS2), },
2156         { .name = "spi-tegra114",       .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2157           SWGID(PPCS2), },
2158         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2159           SWGID(PPCS2), },
2160         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2161           SWGID(PPCS2), },
2162         { .name = "tegra30-dam",        .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2163           SWGID(PPCS2), },
2164         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
2165         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2166           SWGID(PPCS2), },
2167         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2168           SWGID(PPCS2), },
2169         { .name = "tegradc", .swgids = SWGID(DC) | SWGID(DCB) | SWGID(DC12), },
2170         { .name = "tegra_bb",   .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2171           SWGID(PPCS2), },
2172         { .name = "tegra_dma",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2173           SWGID(PPCS2), },
2174         { .name = "tegra-ehci", .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2175           SWGID(PPCS2), },
2176         { .name = "tegra-fuse", .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2177           SWGID(PPCS2), },
2178         { .name = "tegra-i2c",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2179           SWGID(PPCS2), },
2180         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
2181         { .name = "tegra-otg",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2182           SWGID(PPCS2), },
2183         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2184           SWGID(PPCS2), },
2185         { .name = "tegra-rtc",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2186           SWGID(PPCS2), },
2187         { .name = "tegra-sata", .swgids = SWGID(SATA), },
2188         { .name = "tegra-se",   .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2189           SWGID(PPCS2), },
2190         { .name = "tegra-snd",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2191           SWGID(PPCS2), },
2192         { .name = "tegra-tzram",        .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2193           SWGID(PPCS2), },
2194         { .name = "tegra_uart", .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2195           SWGID(PPCS2), },
2196         { .name = "tegra-udc",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2197           SWGID(PPCS2), },
2198         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS) |
2199           SWGID(PPCS1) | SWGID(PPCS2), },
2200         { .name = "tsec",       .swgids = SWGID(TSEC), },
2201         /* vic must be before vi to prevent incorrect matching */
2202         { .name = "vic",        .swgids = SWGID(VIC), },
2203         { .name = "vi", .swgids = SWGID(VI), },
2204         { .name = "therm_est",  .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2205           SWGID(PPCS2), },
2206         { .name = "gk20a",      .swgids = SWGID(GPU) | SWGID(GPUB), },
2207         { .name = "tegra124-apbdma",    .swgids = SWGID(PPCS) | SWGID(PPCS1) |
2208           SWGID(PPCS2), },
2209 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2210         { .name = dummy_name,   .swgids = SWGID(PPCS) },
2211 #endif
2212         { .name = "tegra-xhci", .swgids = SWGID(XUSB_HOST), },
2213         {},
2214 };
2215
2216 u64 tegra_smmu_fixup_swgids(struct device *dev)
2217 {
2218         const char *s;
2219         struct swgid_fixup *table = tegra_swgid_fixup;
2220
2221         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA12)
2222                 table = tegra_swgid_fixup_t124;
2223
2224         while ((s = table->name) != NULL) {
2225                 if (!strncmp(s, dev_name(dev), strlen(s)))
2226                         return table->swgids;
2227                 table++;
2228         }
2229
2230         return 0;
2231 }
2232
2233 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2234
2235 /*
2236  * ASID[0] for the system default
2237  * ASID[1] for PPCS, which has SDMMC
2238  * ASID[3][4] open for drivers, first come, first served.
2239  */
2240 enum {
2241         SYSTEM_DEFAULT,
2242         SYSTEM_PROTECTED,
2243         SYSTEM_GK20A,
2244         NUM_ASIDS,
2245 };
2246
2247 struct tegra_iommu_mapping {
2248         dma_addr_t base;
2249         size_t size;
2250         struct dma_iommu_mapping *map;
2251 };
2252
2253 static struct tegra_iommu_mapping smmu_default_map[] = {
2254         [SYSTEM_DEFAULT] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
2255         [SYSTEM_PROTECTED] = {TEGRA_IOMMU_BASE, TEGRA_IOMMU_SIZE},
2256         /* Non-zero base to account for gk20a driver's assumptions */
2257         [SYSTEM_GK20A] = {0x100000, (u32)~0},
2258 };
2259
2260 static void tegra_smmu_map_init(struct platform_device *pdev)
2261 {
2262         int i;
2263
2264         for (i = 0; i < ARRAY_SIZE(smmu_default_map); i++) {
2265                 struct tegra_iommu_mapping *m = &smmu_default_map[i];
2266                 struct dma_iommu_mapping *map;
2267                 int order = 0;
2268
2269                 if (IS_ENABLED(CONFIG_TEGRA_ERRATA_1053704))
2270                         order = get_order(SZ_16K);
2271
2272                 map = arm_iommu_create_mapping(&platform_bus_type,
2273                                                m->base, m->size, 0);
2274
2275                 if (IS_ERR(map))
2276                         dev_err(&pdev->dev,
2277                                 "Failed create IOVA map for ASID[%d]\n", i);
2278
2279                 m->map = map;
2280         }
2281 }
2282
2283 void tegra_smmu_map_misc_device(struct device *dev)
2284 {
2285         struct dma_iommu_mapping *map = smmu_default_map[SYSTEM_PROTECTED].map;
2286         if (!strncmp(dummy_name, DUMMY_DEV_NAME, strlen(dummy_name))) {
2287                 strncpy(dummy_name, dev_name(dev),
2288                         DUMMY_DEV_MAX_NAME_SIZE);
2289                 arm_iommu_attach_device(dev, map);
2290                 dev_info(dev, "Mapped the misc device\n");
2291                 return;
2292         }
2293         dev_err(dev, "Can't Map device\n");
2294 }
2295 EXPORT_SYMBOL(tegra_smmu_map_misc_device);
2296
2297 void tegra_smmu_unmap_misc_device(struct device *dev)
2298 {
2299         if (!strncmp(dummy_name, dev_name(dev), strlen(dummy_name))) {
2300                 arm_iommu_detach_device(dev);
2301                 strncpy(dummy_name, DUMMY_DEV_NAME,
2302                         DUMMY_DEV_MAX_NAME_SIZE);
2303                 dev_info(dev, "Un-mapped the misc device\n");
2304                 return;
2305         }
2306         dev_err(dev, "Can't Unmap device\n");
2307 }
2308 EXPORT_SYMBOL(tegra_smmu_unmap_misc_device);
2309
2310 static int _tegra_smmu_get_asid(u64 swgids)
2311 {
2312         if (swgids & SWGID(PPCS))
2313                 return SYSTEM_PROTECTED;
2314
2315         if (swgids & SWGID(GPUB))
2316                 return SYSTEM_GK20A;
2317
2318         return SYSTEM_DEFAULT;
2319 }
2320
2321 int tegra_smmu_get_asid(struct device *dev)
2322 {
2323         u64 swgids = tegra_smmu_fixup_swgids(dev);
2324         return _tegra_smmu_get_asid(swgids);
2325 }
2326
2327 struct dma_iommu_mapping *tegra_smmu_get_map(struct device *dev, u64 swgids)
2328 {
2329         if (!swgids)
2330                 swgids = tegra_smmu_fixup_swgids(dev);
2331
2332         if (!swgids)
2333                 return NULL;
2334
2335         return smmu_default_map[_tegra_smmu_get_asid(swgids)].map;
2336 }
2337 #else
2338 static inline void tegra_smmu_map_init(struct platform_device *pdev)
2339 {
2340 }
2341 #endif
2342
2343 static int __init tegra_smmu_init(void)
2344 {
2345         platform_device_register(&tegra_smmu_device);
2346         tegra_smmu_map_init(&tegra_smmu_device);
2347         return 0;
2348 }
2349 postcore_initcall(tegra_smmu_init);
2350 #endif
2351
2352 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2353 #define CLK_RESET_RST_SOURCE    0x0
2354 static struct resource tegra_wdt_resources[] = {
2355         [0] = {
2356                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
2357                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
2358                 .flags  = IORESOURCE_MEM,
2359         },
2360         [1] = {
2361                 .start  = TEGRA_TMR1_BASE,
2362                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
2363                 .flags  = IORESOURCE_MEM,
2364         },
2365         [2] = {
2366                 .start  = INT_TMR1,
2367                 .end    = INT_TMR1,
2368                 .flags  = IORESOURCE_IRQ,
2369         },
2370 };
2371
2372 struct platform_device tegra_wdt_device = {
2373         .name           = "tegra_wdt",
2374         .id             = -1,
2375         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
2376         .resource       = tegra_wdt_resources,
2377 };
2378 #else
2379 static struct resource tegra_wdt0_resources[] = {
2380         [0] = {
2381                 .start  = TEGRA_WDT0_BASE,
2382                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
2383                 .flags  = IORESOURCE_MEM,
2384         },
2385         [1] = {
2386                 .start  = TEGRA_TMR7_BASE,
2387                 .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
2388                 .flags  = IORESOURCE_MEM,
2389         },
2390         [2] = {
2391                 .start  = INT_WDT_CPU,
2392                 .end    = INT_WDT_CPU,
2393                 .flags  = IORESOURCE_IRQ,
2394         },
2395 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
2396         [3] = {
2397                 .start  = TEGRA_QUATERNARY_ICTLR_BASE,
2398                 .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
2399                                 TEGRA_QUATERNARY_ICTLR_SIZE -1,
2400                 .flags  = IORESOURCE_MEM,
2401         },
2402 #endif
2403 };
2404
2405 struct platform_device tegra_wdt0_device = {
2406         .name           = "tegra_wdt",
2407         .id             = 0,
2408         .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
2409         .resource       = tegra_wdt0_resources,
2410 };
2411
2412 #endif
2413
2414 static struct resource tegra_pwfm_resource = {
2415         .start  = TEGRA_PWFM_BASE,
2416         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
2417         .flags  = IORESOURCE_MEM,
2418 };
2419
2420 struct platform_device tegra_pwfm_device = {
2421         .name           = "tegra-pwm",
2422         .id             = -1,
2423         .num_resources  = 1,
2424         .resource       = &tegra_pwfm_resource,
2425 };
2426
2427 static struct tegra_avp_platform_data tegra_avp_pdata = {
2428 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2429         .emc_clk_rate = ULONG_MAX,
2430 #else
2431         .emc_clk_rate = 200000000,
2432 #endif
2433 };
2434
2435 struct resource tegra_nvavp_resources[] = {
2436         [0] = {
2437                 .start  = INT_SHR_SEM_INBOX_IBF,
2438                 .end    = INT_SHR_SEM_INBOX_IBF,
2439                 .flags  = IORESOURCE_IRQ,
2440                 .name   = "mbox_from_nvavp_pending",
2441         },
2442 };
2443
2444 struct platform_device nvavp_device = {
2445         .name           = "nvavp",
2446         .id             = -1,
2447         .resource       = tegra_nvavp_resources,
2448         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
2449         .dev  = {
2450                 .coherent_dma_mask      = 0xffffffffULL,
2451                 .platform_data          = &tegra_avp_pdata,
2452         },
2453 };
2454
2455 static struct resource tegra_avp_resources[] = {
2456         [0] = {
2457                 .start  = INT_SHR_SEM_INBOX_IBF,
2458                 .end    = INT_SHR_SEM_INBOX_IBF,
2459                 .flags  = IORESOURCE_IRQ,
2460                 .name   = "mbox_from_avp_pending",
2461         },
2462 };
2463
2464 struct platform_device tegra_avp_device = {
2465         .name           = "tegra-avp",
2466         .id             = -1,
2467         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
2468         .resource       = tegra_avp_resources,
2469         .dev  = {
2470                 .coherent_dma_mask      = 0xffffffffULL,
2471                 .platform_data          = &tegra_avp_pdata,
2472         },
2473 };
2474
2475 static struct resource tegra_aes_resources[] = {
2476         {
2477                 .start  = TEGRA_VDE_BASE,
2478                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
2479                 .flags  = IORESOURCE_MEM,
2480         },
2481         {
2482                 .start  = TEGRA_BSEA_BASE,
2483                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
2484                 .flags  = IORESOURCE_MEM,
2485         },
2486         {
2487                 .start  = INT_VDE_BSE_V,
2488                 .end    = INT_VDE_BSE_V,
2489                 .flags  = IORESOURCE_IRQ,
2490         },
2491         {
2492                 .start  = INT_VDE_BSE_A,
2493                 .end    = INT_VDE_BSE_A,
2494                 .flags  = IORESOURCE_IRQ,
2495         },
2496 };
2497
2498 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
2499
2500 struct platform_device tegra_aes_device = {
2501         .name           = "tegra-aes",
2502         .id             = -1,
2503         .resource       = tegra_aes_resources,
2504         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
2505         .dev    = {
2506                 .dma_mask = &tegra_aes_dma_mask,
2507                 .coherent_dma_mask = DMA_BIT_MASK(32),
2508         },
2509 };
2510
2511 static struct resource tegra_kbc_resources[] = {
2512         [0] = {
2513                 .start = TEGRA_KBC_BASE,
2514                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
2515                 .flags = IORESOURCE_MEM,
2516         },
2517         [1] = {
2518                 .start = INT_KBC,
2519                 .end   = INT_KBC,
2520                 .flags = IORESOURCE_IRQ,
2521         },
2522 };
2523
2524 struct platform_device tegra_kbc_device = {
2525         .name = "tegra-kbc",
2526         .id = -1,
2527         .resource = tegra_kbc_resources,
2528         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
2529         .dev = {
2530                 .platform_data = 0,
2531         },
2532 };
2533
2534 #if defined(CONFIG_TEGRA_SKIN_THROTTLE)
2535 struct platform_device tegra_skin_therm_est_device = {
2536         .name   = "therm_est",
2537         .id     = -1,
2538         .num_resources  = 0,
2539         .dev = {
2540                 .platform_data = 0,
2541         },
2542 };
2543 #endif
2544
2545 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
2546 static struct resource tegra_tsensor_resources[]= {
2547         {
2548                 .start  = TEGRA_TSENSOR_BASE,
2549                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
2550                 .flags  = IORESOURCE_MEM,
2551         },
2552         {
2553                 .start  = INT_TSENSOR,
2554                 .end    = INT_TSENSOR,
2555                 .flags  = IORESOURCE_IRQ,
2556         },
2557         {
2558                 .start  = TEGRA_PMC_BASE + 0x1B0,
2559                 /* 2 pmc registers mapped */
2560                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
2561                 .flags  = IORESOURCE_MEM,
2562         },
2563 };
2564
2565 struct platform_device tegra_tsensor_device = {
2566         .name   = "tegra-tsensor",
2567         .id     = -1,
2568         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
2569         .resource       = tegra_tsensor_resources,
2570         .dev = {
2571                 .platform_data = 0,
2572         },
2573 };
2574 #endif
2575
2576 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2577 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
2578 static u64 tegra12_se_dma_mask = DMA_BIT_MASK(64);
2579
2580 struct resource tegra_se_resources[] = {
2581         [0] = {
2582                 .start = TEGRA_SE_BASE,
2583                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
2584                 .flags = IORESOURCE_MEM,
2585         },
2586         [1] = {
2587                 .start  = TEGRA_PMC_BASE,
2588                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
2589                 .flags  = IORESOURCE_MEM,
2590         },
2591         [2] = {
2592                 .start = INT_SE,
2593                 .end = INT_SE,
2594                 .flags = IORESOURCE_IRQ,
2595         },
2596 };
2597
2598 struct platform_device tegra_se_device = {
2599         .name = "tegra-se",
2600         .id = -1,
2601         .dev = {
2602                 .coherent_dma_mask = DMA_BIT_MASK(32),
2603                 .dma_mask = &tegra_se_dma_mask,
2604         },
2605         .resource = tegra_se_resources,
2606         .num_resources = ARRAY_SIZE(tegra_se_resources),
2607 };
2608
2609 struct platform_device tegra11_se_device = {
2610         .name = "tegra11-se",
2611         .id = -1,
2612         .dev = {
2613                 .coherent_dma_mask = DMA_BIT_MASK(32),
2614                 .dma_mask = &tegra_se_dma_mask,
2615         },
2616         .resource = tegra_se_resources,
2617         .num_resources = ARRAY_SIZE(tegra_se_resources),
2618 };
2619
2620 struct platform_device tegra12_se_device = {
2621         .name = "tegra12-se",
2622         .id = -1,
2623         .dev = {
2624                 .coherent_dma_mask = DMA_BIT_MASK(64),
2625                 .dma_mask = &tegra12_se_dma_mask,
2626         },
2627         .resource = tegra_se_resources,
2628         .num_resources = ARRAY_SIZE(tegra_se_resources),
2629 };
2630 #endif
2631
2632 static struct resource tegra_disp1_resources[] = {
2633         {
2634                 .name   = "irq",
2635                 .start  = INT_DISPLAY_GENERAL,
2636                 .end    = INT_DISPLAY_GENERAL,
2637                 .flags  = IORESOURCE_IRQ,
2638         },
2639         {
2640                 .name   = "regs",
2641                 .start  = TEGRA_DISPLAY_BASE,
2642                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
2643                 .flags  = IORESOURCE_MEM,
2644         },
2645         {
2646                 .name   = "fbmem",
2647                 .start  = 0,
2648                 .end    = 0,
2649                 .flags  = IORESOURCE_MEM,
2650         },
2651         {
2652                 .name   = "dsi_regs",
2653                 .start  = TEGRA_DSI_BASE,
2654                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
2655                 .flags  = IORESOURCE_MEM,
2656         },
2657 };
2658
2659 struct platform_device tegra_disp1_device = {
2660         .name           = "tegradc",
2661         .id             = 0,
2662         .resource       = tegra_disp1_resources,
2663         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
2664 };
2665
2666 static struct resource tegra_disp2_resources[] = {
2667         {
2668                 .name   = "irq",
2669                 .start  = INT_DISPLAY_B_GENERAL,
2670                 .end    = INT_DISPLAY_B_GENERAL,
2671                 .flags  = IORESOURCE_IRQ,
2672         },
2673         {
2674                 .name   = "regs",
2675                 .start  = TEGRA_DISPLAY2_BASE,
2676                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
2677                 .flags  = IORESOURCE_MEM,
2678         },
2679         {
2680                 .name   = "fbmem",
2681                 .flags  = IORESOURCE_MEM,
2682                 .start  = 0,
2683                 .end    = 0,
2684         },
2685         {
2686                 .name   = "hdmi_regs",
2687                 .start  = TEGRA_HDMI_BASE,
2688                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
2689                 .flags  = IORESOURCE_MEM,
2690         },
2691 };
2692
2693 struct platform_device tegra_disp2_device = {
2694         .name           = "tegradc",
2695         .id             = 1,
2696         .resource       = tegra_disp2_resources,
2697         .num_resources  = ARRAY_SIZE(tegra_disp2_resources),
2698         .dev = {
2699                 .platform_data = 0,
2700         },
2701 };
2702
2703 struct platform_device tegra_nvmap_device = {
2704         .name   = "tegra-nvmap",
2705         .id     = -1,
2706 };
2707
2708 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2709 static struct resource tegra_cec_resources[] = {
2710         [0] = {
2711                 .start = TEGRA_CEC_BASE,
2712                 .end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
2713                 .flags = IORESOURCE_MEM,
2714         },
2715         [1] = {
2716                 .start = INT_CEC,
2717                 .end = INT_CEC,
2718                 .flags = IORESOURCE_IRQ,
2719         },
2720 };
2721
2722 struct platform_device tegra_cec_device = {
2723         .name = "tegra_cec",
2724         .id   = -1,
2725         .resource = tegra_cec_resources,
2726         .num_resources = ARRAY_SIZE(tegra_cec_resources),
2727 };
2728 #endif
2729
2730 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
2731 static struct resource cl_dvfs_resource[] = {
2732         [0] = {
2733                 .start  = TEGRA_CL_DVFS_BASE,
2734                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2735                 .flags  = IORESOURCE_MEM,
2736         }
2737 };
2738
2739 struct platform_device tegra_cl_dvfs_device = {
2740         .name           = "tegra_cl_dvfs",
2741         .id             = -1,
2742         .resource       = cl_dvfs_resource,
2743         .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
2744 };
2745 #endif
2746
2747 struct platform_device tegra_fuse_device = {
2748         .name   = "tegra-fuse",
2749         .id     = -1,
2750 };
2751
2752 void __init tegra_init_debug_uart_rate(void)
2753 {
2754         unsigned int uartclk;
2755         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
2756
2757         BUG_ON(IS_ERR(debug_uart_parent));
2758         uartclk = clk_get_rate(debug_uart_parent);
2759
2760         debug_uarta_platform_data[0].uartclk = uartclk;
2761         debug_uartb_platform_data[0].uartclk = uartclk;
2762         debug_uartc_platform_data[0].uartclk = uartclk;
2763         debug_uartd_platform_data[0].uartclk = uartclk;
2764 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2765         debug_uarte_platform_data[0].uartclk = uartclk;
2766 #endif
2767 }