arm: tegra: Add dummy platform driver for BT and BB
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (C) 2010-2011 NVIDIA Corporation.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/fsl_devices.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c-tegra.h>
28 #include <linux/tegra_avp.h>
29 #include <linux/nvhost.h>
30 #include <mach/irqs.h>
31 #include <linux/usb/tegra_usb_phy.h>
32
33 #include "gpio-names.h"
34 #include "iomap.h"
35 #include "devices.h"
36 #include "tegra_smmu.h"
37
38 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
39 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
40 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
41 #define TEGRA_DMA_REQ_SEL_SPI                   11
42 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
43
44 static struct resource gpio_resource[] = {
45         [0] = {
46                 .start  = TEGRA_GPIO_BASE,
47                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
48                 .flags  = IORESOURCE_MEM,
49         },
50         [1] = {
51                 .start  = INT_GPIO1,
52                 .end    = INT_GPIO1,
53                 .flags  = IORESOURCE_IRQ,
54         },
55         [2] = {
56                 .start  = INT_GPIO2,
57                 .end    = INT_GPIO2,
58                 .flags  = IORESOURCE_IRQ,
59         },
60         [3] = {
61                 .start  = INT_GPIO3,
62                 .end    = INT_GPIO3,
63                 .flags  = IORESOURCE_IRQ,
64         },
65         [4] = {
66                 .start  = INT_GPIO4,
67                 .end    = INT_GPIO4,
68                 .flags  = IORESOURCE_IRQ,
69         },
70         [5] = {
71                 .start  = INT_GPIO5,
72                 .end    = INT_GPIO5,
73                 .flags  = IORESOURCE_IRQ,
74         },
75         [6] = {
76                 .start  = INT_GPIO6,
77                 .end    = INT_GPIO6,
78                 .flags  = IORESOURCE_IRQ,
79         },
80         [7] = {
81                 .start  = INT_GPIO7,
82                 .end    = INT_GPIO7,
83                 .flags  = IORESOURCE_IRQ,
84         },
85 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
86         [8] = {
87                 .start  = INT_GPIO8,
88                 .end    = INT_GPIO8,
89                 .flags  = IORESOURCE_IRQ,
90         },
91 #endif
92 };
93
94 struct platform_device tegra_gpio_device = {
95         .name           = "tegra-gpio",
96         .id             = -1,
97         .resource       = gpio_resource,
98         .num_resources  = ARRAY_SIZE(gpio_resource),
99 };
100
101 static struct resource pinmux_resource[] = {
102         [0] = {
103                 /* Tri-state registers */
104                 .start  = TEGRA_APB_MISC_BASE + 0x14,
105                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
106                 .flags  = IORESOURCE_MEM,
107         },
108         [1] = {
109                 /* Mux registers */
110                 .start  = TEGRA_APB_MISC_BASE + 0x80,
111                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
112                 .flags  = IORESOURCE_MEM,
113         },
114         [2] = {
115                 /* Pull-up/down registers */
116                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
117                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
118                 .flags  = IORESOURCE_MEM,
119         },
120         [3] = {
121                 /* Pad control registers */
122                 .start  = TEGRA_APB_MISC_BASE + 0x868,
123                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
124                 .flags  = IORESOURCE_MEM,
125         },
126 };
127
128 struct platform_device tegra_pinmux_device = {
129         .name           = "tegra20-pinctrl",
130         .id             = -1,
131         .resource       = pinmux_resource,
132         .num_resources  = ARRAY_SIZE(pinmux_resource),
133 };
134
135 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
136 #define UART_SOURCE_RATE 408000000
137 #else
138 #define UART_SOURCE_RATE 216000000
139 #endif
140
141 static struct resource i2c_resource1[] = {
142         [0] = {
143                 .start  = INT_I2C,
144                 .end    = INT_I2C,
145                 .flags  = IORESOURCE_IRQ,
146         },
147         [1] = {
148                 .start  = TEGRA_I2C_BASE,
149                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
150                 .flags  = IORESOURCE_MEM,
151         },
152 };
153
154 static struct resource i2c_resource2[] = {
155         [0] = {
156                 .start  = INT_I2C2,
157                 .end    = INT_I2C2,
158                 .flags  = IORESOURCE_IRQ,
159         },
160         [1] = {
161                 .start  = TEGRA_I2C2_BASE,
162                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
163                 .flags  = IORESOURCE_MEM,
164         },
165 };
166
167 static struct resource i2c_resource3[] = {
168         [0] = {
169                 .start  = INT_I2C3,
170                 .end    = INT_I2C3,
171                 .flags  = IORESOURCE_IRQ,
172         },
173         [1] = {
174                 .start  = TEGRA_I2C3_BASE,
175                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
176                 .flags  = IORESOURCE_MEM,
177         },
178 };
179
180 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
181 static struct resource i2c_resource4[] = {
182         [0] = {
183                 .start  = INT_DVC,
184                 .end    = INT_DVC,
185                 .flags  = IORESOURCE_IRQ,
186         },
187         [1] = {
188                 .start  = TEGRA_DVC_BASE,
189                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
190                 .flags  = IORESOURCE_MEM,
191         },
192 };
193
194 #else
195 static struct resource i2c_resource4[] = {
196         [0] = {
197                 .start  = INT_I2C4,
198                 .end    = INT_I2C4,
199                 .flags  = IORESOURCE_IRQ,
200         },
201         [1] = {
202                 .start  = TEGRA_I2C4_BASE,
203                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
204                 .flags  = IORESOURCE_MEM,
205         },
206 };
207
208 static struct resource i2c_resource5[] = {
209         [0] = {
210                 .start  = INT_I2C5,
211                 .end    = INT_I2C5,
212                 .flags  = IORESOURCE_IRQ,
213         },
214         [1] = {
215                 .start  = TEGRA_I2C5_BASE,
216                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
217                 .flags  = IORESOURCE_MEM,
218         },
219 };
220 #endif
221
222 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
223         .bus_clk_rate   = 400000,
224 };
225
226 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
227         .bus_clk_rate   = 400000,
228 };
229
230 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
231         .bus_clk_rate   = 400000,
232 };
233
234 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
235         .bus_clk_rate   = 400000,
236 };
237
238 struct platform_device tegra_i2c_device1 = {
239         .name           = "tegra-i2c",
240         .id             = 0,
241         .resource       = i2c_resource1,
242         .num_resources  = ARRAY_SIZE(i2c_resource1),
243         .dev = {
244                 .platform_data = &tegra_i2c1_platform_data,
245         },
246 };
247
248 struct platform_device tegra_i2c_device2 = {
249         .name           = "tegra-i2c",
250         .id             = 1,
251         .resource       = i2c_resource2,
252         .num_resources  = ARRAY_SIZE(i2c_resource2),
253         .dev = {
254                 .platform_data = &tegra_i2c2_platform_data,
255         },
256 };
257
258 struct platform_device tegra_i2c_device3 = {
259         .name           = "tegra-i2c",
260         .id             = 2,
261         .resource       = i2c_resource3,
262         .num_resources  = ARRAY_SIZE(i2c_resource3),
263         .dev = {
264                 .platform_data = &tegra_i2c3_platform_data,
265         },
266 };
267
268 struct platform_device tegra_i2c_device4 = {
269         .name           = "tegra-i2c",
270         .id             = 3,
271         .resource       = i2c_resource4,
272         .num_resources  = ARRAY_SIZE(i2c_resource4),
273         .dev = {
274                 .platform_data = &tegra_dvc_platform_data,
275         },
276 };
277
278 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
279 struct platform_device tegra_i2c_device5 = {
280         .name           = "tegra-i2c",
281         .id             = 4,
282         .resource       = i2c_resource5,
283         .num_resources  = ARRAY_SIZE(i2c_resource5),
284         .dev = {
285                 .platform_data = 0,
286         },
287 };
288 #endif
289
290 static struct resource spi_resource1[] = {
291         [0] = {
292                 .start  = INT_SPI_1,
293                 .end    = INT_SPI_1,
294                 .flags  = IORESOURCE_IRQ,
295         },
296         [1] = {
297                 .start  = TEGRA_SPI1_BASE,
298                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
299                 .flags  = IORESOURCE_MEM,
300         },
301 };
302
303 static struct resource spi_resource2[] = {
304         [0] = {
305                 .start  = INT_SPI_2,
306                 .end    = INT_SPI_2,
307                 .flags  = IORESOURCE_IRQ,
308         },
309         [1] = {
310                 .start  = TEGRA_SPI2_BASE,
311                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
312                 .flags  = IORESOURCE_MEM,
313         },
314 };
315
316 static struct resource spi_resource3[] = {
317         [0] = {
318                 .start  = INT_SPI_3,
319                 .end    = INT_SPI_3,
320                 .flags  = IORESOURCE_IRQ,
321         },
322         [1] = {
323                 .start  = TEGRA_SPI3_BASE,
324                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
325                 .flags  = IORESOURCE_MEM,
326         },
327 };
328
329 static struct resource spi_resource4[] = {
330         [0] = {
331                 .start  = INT_SPI_4,
332                 .end    = INT_SPI_4,
333                 .flags  = IORESOURCE_IRQ,
334         },
335         [1] = {
336                 .start  = TEGRA_SPI4_BASE,
337                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
338                 .flags  = IORESOURCE_MEM,
339         },
340 };
341 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
342 static struct resource spi_resource5[] = {
343         [0] = {
344                 .start  = INT_SPI_5,
345                 .end    = INT_SPI_5,
346                 .flags  = IORESOURCE_IRQ,
347         },
348         [1] = {
349                 .start  = TEGRA_SPI5_BASE,
350                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
351                 .flags  = IORESOURCE_MEM,
352         },
353 };
354
355 static struct resource spi_resource6[] = {
356         [0] = {
357                 .start  = INT_SPI_6,
358                 .end    = INT_SPI_6,
359                 .flags  = IORESOURCE_IRQ,
360         },
361         [1] = {
362                 .start  = TEGRA_SPI6_BASE,
363                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
364                 .flags  = IORESOURCE_MEM,
365         },
366 };
367 #endif
368
369 struct platform_device tegra_spi_device1 = {
370         .name           = "spi_tegra",
371         .id             = 0,
372         .resource       = spi_resource1,
373         .num_resources  = ARRAY_SIZE(spi_resource1),
374         .dev            = {
375                 .coherent_dma_mask      = 0xffffffff,
376         },
377 };
378
379 struct platform_device tegra_spi_device2 = {
380         .name           = "spi_tegra",
381         .id             = 1,
382         .resource       = spi_resource2,
383         .num_resources  = ARRAY_SIZE(spi_resource2),
384         .dev            = {
385                 .coherent_dma_mask      = 0xffffffff,
386         },
387 };
388
389 struct platform_device tegra_spi_device3 = {
390         .name           = "spi_tegra",
391         .id             = 2,
392         .resource       = spi_resource3,
393         .num_resources  = ARRAY_SIZE(spi_resource3),
394         .dev            = {
395                 .coherent_dma_mask      = 0xffffffff,
396         },
397 };
398
399 struct platform_device tegra_spi_device4 = {
400         .name           = "spi_tegra",
401         .id             = 3,
402         .resource       = spi_resource4,
403         .num_resources  = ARRAY_SIZE(spi_resource4),
404         .dev            = {
405                 .coherent_dma_mask      = 0xffffffff,
406         },
407 };
408 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
409 struct platform_device tegra_spi_device5 = {
410         .name           = "spi_tegra",
411         .id             = 4,
412         .resource       = spi_resource5,
413         .num_resources  = ARRAY_SIZE(spi_resource5),
414         .dev  = {
415                 .coherent_dma_mask      = 0xffffffff,
416         },
417 };
418
419 struct platform_device tegra_spi_device6 = {
420         .name           = "spi_tegra",
421         .id             = 5,
422         .resource       = spi_resource6,
423         .num_resources  = ARRAY_SIZE(spi_resource6),
424         .dev  = {
425                 .coherent_dma_mask      = 0xffffffff,
426         },
427 };
428 #endif
429
430 struct platform_device tegra_spi_slave_device1 = {
431         .name           = "spi_slave_tegra",
432         .id             = 0,
433         .resource       = spi_resource1,
434         .num_resources  = ARRAY_SIZE(spi_resource1),
435         .dev  = {
436                 .coherent_dma_mask      = 0xffffffff,
437         },
438 };
439
440 struct platform_device tegra_spi_slave_device2 = {
441         .name           = "spi_slave_tegra",
442         .id             = 1,
443         .resource       = spi_resource2,
444         .num_resources  = ARRAY_SIZE(spi_resource2),
445         .dev  = {
446                 .coherent_dma_mask      = 0xffffffff,
447         },
448 };
449
450 struct platform_device tegra_spi_slave_device3 = {
451         .name           = "spi_slave_tegra",
452         .id             = 2,
453         .resource       = spi_resource3,
454         .num_resources  = ARRAY_SIZE(spi_resource3),
455         .dev  = {
456                 .coherent_dma_mask      = 0xffffffff,
457         },
458 };
459
460 struct platform_device tegra_spi_slave_device4 = {
461         .name           = "spi_slave_tegra",
462         .id             = 3,
463         .resource       = spi_resource4,
464         .num_resources  = ARRAY_SIZE(spi_resource4),
465         .dev  = {
466                 .coherent_dma_mask      = 0xffffffff,
467         },
468 };
469 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
470 struct platform_device tegra_spi_slave_device5 = {
471         .name           = "spi_slave_tegra",
472         .id             = 4,
473         .resource       = spi_resource5,
474         .num_resources  = ARRAY_SIZE(spi_resource5),
475         .dev  = {
476                 .coherent_dma_mask      = 0xffffffff,
477         },
478 };
479
480 struct platform_device tegra_spi_slave_device6 = {
481         .name           = "spi_slave_tegra",
482         .id             = 5,
483         .resource       = spi_resource6,
484         .num_resources  = ARRAY_SIZE(spi_resource6),
485         .dev  = {
486                 .coherent_dma_mask      = 0xffffffff,
487         },
488 };
489 #endif
490
491
492
493 static struct resource sdhci_resource1[] = {
494         [0] = {
495                 .start  = INT_SDMMC1,
496                 .end    = INT_SDMMC1,
497                 .flags  = IORESOURCE_IRQ,
498         },
499         [1] = {
500                 .start  = TEGRA_SDMMC1_BASE,
501                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
502                 .flags  = IORESOURCE_MEM,
503         },
504 };
505
506 static struct resource sdhci_resource2[] = {
507         [0] = {
508                 .start  = INT_SDMMC2,
509                 .end    = INT_SDMMC2,
510                 .flags  = IORESOURCE_IRQ,
511         },
512         [1] = {
513                 .start  = TEGRA_SDMMC2_BASE,
514                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
515                 .flags  = IORESOURCE_MEM,
516         },
517 };
518
519 static struct resource sdhci_resource3[] = {
520         [0] = {
521                 .start  = INT_SDMMC3,
522                 .end    = INT_SDMMC3,
523                 .flags  = IORESOURCE_IRQ,
524         },
525         [1] = {
526                 .start  = TEGRA_SDMMC3_BASE,
527                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
528                 .flags  = IORESOURCE_MEM,
529         },
530 };
531
532 static struct resource sdhci_resource4[] = {
533         [0] = {
534                 .start  = INT_SDMMC4,
535                 .end    = INT_SDMMC4,
536                 .flags  = IORESOURCE_IRQ,
537         },
538         [1] = {
539                 .start  = TEGRA_SDMMC4_BASE,
540                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
541                 .flags  = IORESOURCE_MEM,
542         },
543 };
544
545 /* board files should fill in platform_data register the devices themselvs.
546  * See board-harmony.c for an example
547  */
548 struct platform_device tegra_sdhci_device1 = {
549         .name           = "sdhci-tegra",
550         .id             = 0,
551         .resource       = sdhci_resource1,
552         .num_resources  = ARRAY_SIZE(sdhci_resource1),
553 };
554
555 struct platform_device tegra_sdhci_device2 = {
556         .name           = "sdhci-tegra",
557         .id             = 1,
558         .resource       = sdhci_resource2,
559         .num_resources  = ARRAY_SIZE(sdhci_resource2),
560 };
561
562 struct platform_device tegra_sdhci_device3 = {
563         .name           = "sdhci-tegra",
564         .id             = 2,
565         .resource       = sdhci_resource3,
566         .num_resources  = ARRAY_SIZE(sdhci_resource3),
567 };
568
569 struct platform_device tegra_sdhci_device4 = {
570         .name           = "sdhci-tegra",
571         .id             = 3,
572         .resource       = sdhci_resource4,
573         .num_resources  = ARRAY_SIZE(sdhci_resource4),
574 };
575
576 static struct resource tegra_usb1_resources[] = {
577         [0] = {
578                 .start  = TEGRA_USB_BASE,
579                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
580                 .flags  = IORESOURCE_MEM,
581         },
582         [1] = {
583                 .start  = INT_USB,
584                 .end    = INT_USB,
585                 .flags  = IORESOURCE_IRQ,
586         },
587 };
588
589 static struct resource tegra_usb2_resources[] = {
590         [0] = {
591                 .start  = TEGRA_USB2_BASE,
592                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
593                 .flags  = IORESOURCE_MEM,
594         },
595         [1] = {
596                 .start  = INT_USB2,
597                 .end    = INT_USB2,
598                 .flags  = IORESOURCE_IRQ,
599         },
600 };
601
602 static struct resource tegra_usb3_resources[] = {
603         [0] = {
604                 .start  = TEGRA_USB3_BASE,
605                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
606                 .flags  = IORESOURCE_MEM,
607         },
608         [1] = {
609                 .start  = INT_USB3,
610                 .end    = INT_USB3,
611                 .flags  = IORESOURCE_IRQ,
612         },
613 };
614
615 struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
616         .reset_gpio = -1,
617         .clk = "cdev2",
618 };
619
620 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
621         .operating_mode = TEGRA_USB_OTG,
622         .power_down_on_bus_suspend = 1,
623         .vbus_gpio = -1,
624 };
625
626 struct tegra_ehci_platform_data tegra_ehci2_pdata = {
627         .phy_config = &tegra_ehci2_ulpi_phy_config,
628         .operating_mode = TEGRA_USB_HOST,
629         .power_down_on_bus_suspend = 1,
630         .vbus_gpio = -1,
631 };
632
633 struct tegra_ehci_platform_data tegra_ehci3_pdata = {
634         .operating_mode = TEGRA_USB_HOST,
635         .power_down_on_bus_suspend = 1,
636         .vbus_gpio = -1,
637 };
638
639 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
640
641 struct platform_device tegra_ehci1_device = {
642         .name   = "tegra-ehci",
643         .id     = 0,
644         .dev    = {
645                 .dma_mask       = &tegra_ehci_dmamask,
646                 .coherent_dma_mask = DMA_BIT_MASK(32),
647                 .platform_data = &tegra_ehci1_pdata,
648         },
649         .resource = tegra_usb1_resources,
650         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
651 };
652
653 struct platform_device tegra_ehci2_device = {
654         .name   = "tegra-ehci",
655         .id     = 1,
656         .dev    = {
657                 .dma_mask       = &tegra_ehci_dmamask,
658                 .coherent_dma_mask = DMA_BIT_MASK(32),
659                 .platform_data = &tegra_ehci2_pdata,
660         },
661         .resource = tegra_usb2_resources,
662         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
663 };
664
665 struct platform_device tegra_ehci3_device = {
666         .name   = "tegra-ehci",
667         .id     = 2,
668         .dev    = {
669                 .dma_mask       = &tegra_ehci_dmamask,
670                 .coherent_dma_mask = DMA_BIT_MASK(32),
671                 .platform_data = &tegra_ehci3_pdata,
672         },
673         .resource = tegra_usb3_resources,
674         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
675 };
676
677 static struct resource tegra_pmu_resources[] = {
678         [0] = {
679                 .start  = INT_CPU0_PMU_INTR,
680                 .end    = INT_CPU0_PMU_INTR,
681                 .flags  = IORESOURCE_IRQ,
682         },
683         [1] = {
684                 .start  = INT_CPU1_PMU_INTR,
685                 .end    = INT_CPU1_PMU_INTR,
686                 .flags  = IORESOURCE_IRQ,
687         },
688 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
689         [2] = {
690                 .start  = INT_CPU2_PMU_INTR,
691                 .end    = INT_CPU2_PMU_INTR,
692                 .flags  = IORESOURCE_IRQ,
693         },
694         [3] = {
695                 .start  = INT_CPU3_PMU_INTR,
696                 .end    = INT_CPU3_PMU_INTR,
697                 .flags  = IORESOURCE_IRQ,
698         },
699 #endif
700 };
701
702 struct platform_device tegra_pmu_device = {
703         .name           = "arm-pmu",
704         .id             = -1,
705         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
706         .resource       = tegra_pmu_resources,
707 };
708
709 static struct resource tegra_uarta_resources[] = {
710         [0] = {
711                 .start  = TEGRA_UARTA_BASE,
712                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
713                 .flags  = IORESOURCE_MEM,
714         },
715         [1] = {
716                 .start  = INT_UARTA,
717                 .end    = INT_UARTA,
718                 .flags  = IORESOURCE_IRQ,
719         },
720 };
721
722 static struct resource tegra_uartb_resources[] = {
723         [0] = {
724                 .start  = TEGRA_UARTB_BASE,
725                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
726                 .flags  = IORESOURCE_MEM,
727         },
728         [1] = {
729                 .start  = INT_UARTB,
730                 .end    = INT_UARTB,
731                 .flags  = IORESOURCE_IRQ,
732         },
733 };
734
735 static struct resource tegra_uartc_resources[] = {
736         [0] = {
737                 .start  = TEGRA_UARTC_BASE,
738                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
739                 .flags  = IORESOURCE_MEM,
740         },
741         [1] = {
742                 .start  = INT_UARTC,
743                 .end    = INT_UARTC,
744                 .flags  = IORESOURCE_IRQ,
745         },
746 };
747
748 static struct resource tegra_uartd_resources[] = {
749         [0] = {
750                 .start  = TEGRA_UARTD_BASE,
751                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
752                 .flags  = IORESOURCE_MEM,
753         },
754         [1] = {
755                 .start  = INT_UARTD,
756                 .end    = INT_UARTD,
757                 .flags  = IORESOURCE_IRQ,
758         },
759 };
760
761 static struct resource tegra_uarte_resources[] = {
762         [0] = {
763                 .start  = TEGRA_UARTE_BASE,
764                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
765                 .flags  = IORESOURCE_MEM,
766         },
767         [1] = {
768                 .start  = INT_UARTE,
769                 .end    = INT_UARTE,
770                 .flags  = IORESOURCE_IRQ,
771         },
772 };
773
774 struct platform_device tegra_uarta_device = {
775         .name   = "tegra_uart",
776         .id     = 0,
777         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
778         .resource       = tegra_uarta_resources,
779         .dev    = {
780                 .coherent_dma_mask      = DMA_BIT_MASK(32),
781         },
782 };
783
784 struct platform_device tegra_uartb_device = {
785         .name   = "tegra_uart",
786         .id     = 1,
787         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
788         .resource       = tegra_uartb_resources,
789         .dev    = {
790                 .coherent_dma_mask      = DMA_BIT_MASK(32),
791         },
792 };
793
794 struct platform_device tegra_uartc_device = {
795         .name   = "tegra_uart",
796         .id     = 2,
797         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
798         .resource       = tegra_uartc_resources,
799         .dev    = {
800                 .coherent_dma_mask      = DMA_BIT_MASK(32),
801         },
802 };
803
804 struct platform_device tegra_uartd_device = {
805         .name   = "tegra_uart",
806         .id     = 3,
807         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
808         .resource       = tegra_uartd_resources,
809         .dev    = {
810                 .coherent_dma_mask      = DMA_BIT_MASK(32),
811         },
812 };
813
814 struct platform_device tegra_uarte_device = {
815         .name   = "tegra_uart",
816         .id     = 4,
817         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
818         .resource       = tegra_uarte_resources,
819         .dev    = {
820                 .coherent_dma_mask      = DMA_BIT_MASK(32),
821         },
822 };
823
824 static struct plat_serial8250_port debug_uarta_platform_data[] = {
825         {
826                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
827                 .mapbase        = TEGRA_UARTA_BASE,
828                 .irq            = INT_UARTA,
829                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
830                 .type           = PORT_TEGRA,
831                 .iotype         = UPIO_MEM,
832                 .regshift       = 2,
833                 .uartclk        = UART_SOURCE_RATE,
834         },
835         {
836                 .flags          = 0,
837         },
838 };
839
840 static struct plat_serial8250_port debug_uartb_platform_data[] = {
841         {
842                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
843                 .mapbase        = TEGRA_UARTB_BASE,
844                 .irq            = INT_UARTB,
845                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
846                 .type           = PORT_TEGRA,
847                 .iotype         = UPIO_MEM,
848                 .regshift       = 2,
849                 .uartclk        = UART_SOURCE_RATE,
850         },
851         {
852                 .flags          = 0,
853         },
854 };
855
856 static struct plat_serial8250_port debug_uartc_platform_data[] = {
857         {
858                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
859                 .mapbase        = TEGRA_UARTC_BASE,
860                 .irq            = INT_UARTC,
861                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
862                 .type           = PORT_TEGRA,
863                 .iotype         = UPIO_MEM,
864                 .regshift       = 2,
865                 .uartclk        = UART_SOURCE_RATE,
866         },
867         {
868                 .flags          = 0,
869         },
870 };
871
872 static struct plat_serial8250_port debug_uartd_platform_data[] = {
873         {
874                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
875                 .mapbase        = TEGRA_UARTD_BASE,
876                 .irq            = INT_UARTD,
877                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
878                 .type           = PORT_TEGRA,
879                 .iotype         = UPIO_MEM,
880                 .regshift       = 2,
881                 .uartclk        = UART_SOURCE_RATE,
882         },
883         {
884                 .flags          = 0,
885         },
886 };
887
888 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
889 static struct plat_serial8250_port debug_uarte_platform_data[] = {
890         {
891                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
892                 .mapbase        = TEGRA_UARTE_BASE,
893                 .irq            = INT_UARTE,
894                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
895                 .type           = PORT_TEGRA,
896                 .iotype         = UPIO_MEM,
897                 .regshift       = 2,
898                 .uartclk        = UART_SOURCE_RATE,
899         },
900         {
901                 .flags          = 0,
902         },
903 };
904 #endif
905
906 struct platform_device debug_uarta_device = {
907         .name = "serial8250",
908         .id = PLAT8250_DEV_PLATFORM,
909         .dev = {
910                 .platform_data = debug_uarta_platform_data,
911         },
912 };
913
914 struct platform_device debug_uartb_device = {
915         .name = "serial8250",
916         .id = PLAT8250_DEV_PLATFORM,
917         .dev = {
918                 .platform_data = debug_uartb_platform_data,
919         },
920 };
921
922 struct platform_device debug_uartc_device = {
923         .name = "serial8250",
924         .id = PLAT8250_DEV_PLATFORM,
925         .dev = {
926                 .platform_data = debug_uartc_platform_data,
927         },
928 };
929
930 struct platform_device debug_uartd_device = {
931         .name = "serial8250",
932         .id = PLAT8250_DEV_PLATFORM,
933         .dev = {
934                 .platform_data = debug_uartd_platform_data,
935         },
936 };
937
938 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
939 struct platform_device debug_uarte_device = {
940         .name = "serial8250",
941         .id = PLAT8250_DEV_PLATFORM,
942         .dev = {
943                 .platform_data = debug_uarte_platform_data,
944         },
945 };
946 #endif
947
948 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
949 static struct resource i2s_resource1[] = {
950         [0] = {
951                 .start  = INT_I2S1,
952                 .end    = INT_I2S1,
953                 .flags  = IORESOURCE_IRQ
954         },
955         [1] = {
956                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
957                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
958                 .flags  = IORESOURCE_DMA
959         },
960         [2] = {
961                 .start  = TEGRA_I2S1_BASE,
962                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
963                 .flags  = IORESOURCE_MEM
964         }
965 };
966
967 struct platform_device tegra_i2s_device1 = {
968         .name           = "tegra20-i2s",
969         .id             = 0,
970         .resource       = i2s_resource1,
971         .num_resources  = ARRAY_SIZE(i2s_resource1),
972 };
973
974 static struct resource i2s_resource2[] = {
975         [0] = {
976                 .start  = INT_I2S2,
977                 .end    = INT_I2S2,
978                 .flags  = IORESOURCE_IRQ
979         },
980         [1] = {
981                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
982                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
983                 .flags  = IORESOURCE_DMA
984         },
985         [2] = {
986                 .start  = TEGRA_I2S2_BASE,
987                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
988                 .flags  = IORESOURCE_MEM
989         }
990 };
991
992 struct platform_device tegra_i2s_device2 = {
993         .name           = "tegra20-i2s",
994         .id             = 1,
995         .resource       = i2s_resource2,
996         .num_resources  = ARRAY_SIZE(i2s_resource2),
997 };
998 #else
999 static struct resource i2s_resource0[] = {
1000         [0] = {
1001                 .start  = TEGRA_I2S0_BASE,
1002                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1003                 .flags  = IORESOURCE_MEM
1004         }
1005 };
1006
1007 struct platform_device tegra_i2s_device0 = {
1008         .name           = "tegra30-i2s",
1009         .id             = 0,
1010         .resource       = i2s_resource0,
1011         .num_resources  = ARRAY_SIZE(i2s_resource0),
1012 };
1013
1014 static struct resource i2s_resource1[] = {
1015         [0] = {
1016                 .start  = TEGRA_I2S1_BASE,
1017                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1018                 .flags  = IORESOURCE_MEM
1019         }
1020 };
1021
1022 struct platform_device tegra_i2s_device1 = {
1023         .name           = "tegra30-i2s",
1024         .id             = 1,
1025         .resource       = i2s_resource1,
1026         .num_resources  = ARRAY_SIZE(i2s_resource1),
1027 };
1028
1029 static struct resource i2s_resource2[] = {
1030         [0] = {
1031                 .start  = TEGRA_I2S2_BASE,
1032                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1033                 .flags  = IORESOURCE_MEM
1034         }
1035 };
1036
1037 struct platform_device tegra_i2s_device2 = {
1038         .name           = "tegra30-i2s",
1039         .id             = 2,
1040         .resource       = i2s_resource2,
1041         .num_resources  = ARRAY_SIZE(i2s_resource2),
1042 };
1043
1044 static struct resource i2s_resource3[] = {
1045         [0] = {
1046                 .start  = TEGRA_I2S3_BASE,
1047                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1048                 .flags  = IORESOURCE_MEM
1049         }
1050 };
1051
1052 struct platform_device tegra_i2s_device3 = {
1053         .name           = "tegra30-i2s",
1054         .id             = 3,
1055         .resource       = i2s_resource3,
1056         .num_resources  = ARRAY_SIZE(i2s_resource3),
1057 };
1058
1059 static struct resource i2s_resource4[] = {
1060         [0] = {
1061                 .start  = TEGRA_I2S4_BASE,
1062                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1063                 .flags  = IORESOURCE_MEM
1064         }
1065 };
1066
1067 struct platform_device tegra_i2s_device4 = {
1068         .name           = "tegra30-i2s",
1069         .id             = 4,
1070         .resource       = i2s_resource4,
1071         .num_resources  = ARRAY_SIZE(i2s_resource4),
1072 };
1073 #endif
1074
1075 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1076 static struct resource spdif_resource[] = {
1077         [0] = {
1078                 .start  = INT_SPDIF,
1079                 .end    = INT_SPDIF,
1080                 .flags  = IORESOURCE_IRQ
1081         },
1082         [1] = {
1083                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1084                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1085                 .flags  = IORESOURCE_DMA
1086         },
1087         [2] = {
1088                 .start  = TEGRA_SPDIF_BASE,
1089                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1090                 .flags  = IORESOURCE_MEM
1091         }
1092 };
1093
1094 struct platform_device tegra_spdif_device = {
1095         .name           = "tegra20-spdif",
1096         .id             = -1,
1097         .resource       = spdif_resource,
1098         .num_resources  = ARRAY_SIZE(spdif_resource),
1099 };
1100 #else
1101 static struct resource spdif_resource[] = {
1102         [0] = {
1103                 .start  = TEGRA_SPDIF_BASE,
1104                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1105                 .flags  = IORESOURCE_MEM
1106         }
1107 };
1108
1109 struct platform_device tegra_spdif_device = {
1110         .name           = "tegra30-spdif",
1111         .id             = -1,
1112         .resource       = spdif_resource,
1113         .num_resources  = ARRAY_SIZE(spdif_resource),
1114 };
1115 #endif
1116
1117 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1118 static struct resource ahub_resource[] = {
1119         [0] = {
1120                 .start  = TEGRA_APBIF0_BASE,
1121                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1122                 .flags  = IORESOURCE_MEM
1123         },
1124         [1] = {
1125                 .start  = TEGRA_AHUB_BASE,
1126                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1127                 .flags  = IORESOURCE_MEM
1128         }
1129 };
1130
1131 struct platform_device tegra_ahub_device = {
1132         .name   = "tegra30-ahub",
1133         .id     = -1,
1134         .resource       = ahub_resource,
1135         .num_resources  = ARRAY_SIZE(ahub_resource),
1136 };
1137
1138 static struct resource dam_resource0[] = {
1139         [0] = {
1140                 .start = TEGRA_DAM0_BASE,
1141                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1142                 .flags = IORESOURCE_MEM
1143         }
1144 };
1145
1146 struct platform_device tegra_dam_device0 = {
1147         .name = "tegra30-dam",
1148         .id = 0,
1149         .resource      = dam_resource0,
1150         .num_resources = ARRAY_SIZE(dam_resource0),
1151 };
1152
1153 static struct resource dam_resource1[] = {
1154         [0] = {
1155                 .start = TEGRA_DAM1_BASE,
1156                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1157                 .flags = IORESOURCE_MEM
1158         }
1159 };
1160
1161 struct platform_device tegra_dam_device1 = {
1162         .name = "tegra30-dam",
1163         .id = 1,
1164         .resource      = dam_resource1,
1165         .num_resources = ARRAY_SIZE(dam_resource1),
1166 };
1167
1168 static struct resource dam_resource2[] = {
1169         [0] = {
1170                 .start = TEGRA_DAM2_BASE,
1171                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1172                 .flags = IORESOURCE_MEM
1173         }
1174 };
1175
1176 struct platform_device tegra_dam_device2 = {
1177         .name = "tegra30-dam",
1178         .id = 2,
1179         .resource      = dam_resource2,
1180         .num_resources = ARRAY_SIZE(dam_resource2),
1181 };
1182 #endif
1183
1184 struct platform_device spdif_dit_device = {
1185         .name = "spdif-dit",
1186         .id = 0,
1187 };
1188
1189 struct platform_device bluetooth_dit_device = {
1190         .name = "spdif-dit",
1191         .id = 1,
1192 };
1193
1194 struct platform_device baseband_dit_device = {
1195         .name = "spdif-dit",
1196         .id = 2,
1197 };
1198
1199 #if defined(CONFIG_SND_HDA_TEGRA)
1200 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1201
1202 static struct resource tegra_hda_resources[] = {
1203         [0] = {
1204                 .start  = TEGRA_HDA_BASE,
1205                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1 ,
1206                 .flags  = IORESOURCE_MEM
1207         },
1208         [1] = {
1209                 .start  = INT_HDA,
1210                 .end    = INT_HDA,
1211                 .flags  = IORESOURCE_IRQ
1212         },
1213 };
1214
1215 struct platform_device tegra_hda_device = {
1216         .name           = "tegra-hda",
1217         .id             = 0,
1218         .dev = {
1219                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1220                 .dma_mask               = &tegra_hda_dma_mask,
1221         },
1222         .resource       = tegra_hda_resources,
1223         .num_resources  = ARRAY_SIZE(tegra_hda_resources),
1224 };
1225 #endif
1226
1227 static struct resource w1_resources[] = {
1228         [0] = {
1229                 .start = INT_OWR,
1230                 .end   = INT_OWR,
1231                 .flags = IORESOURCE_IRQ
1232         },
1233         [1] = {
1234                 .start = TEGRA_OWR_BASE,
1235                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1236                 .flags = IORESOURCE_MEM
1237         }
1238 };
1239
1240 struct platform_device tegra_w1_device = {
1241         .name          = "tegra_w1",
1242         .id            = -1,
1243         .resource      = w1_resources,
1244         .num_resources = ARRAY_SIZE(w1_resources),
1245 };
1246
1247 static struct resource tegra_udc_resources[] = {
1248         [0] = {
1249                 .start  = TEGRA_USB_BASE,
1250                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1251                 .flags  = IORESOURCE_MEM,
1252         },
1253         [1] = {
1254                 .start  = INT_USB,
1255                 .end    = INT_USB,
1256                 .flags  = IORESOURCE_IRQ,
1257         },
1258 };
1259
1260 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1261
1262 static struct fsl_usb2_platform_data tegra_udc_pdata = {
1263         .operating_mode = FSL_USB2_DR_DEVICE,
1264         .phy_mode       = FSL_USB2_PHY_UTMI,
1265 };
1266
1267 struct platform_device tegra_udc_device = {
1268         .name   = "fsl-tegra-udc",
1269         .id     = -1,
1270         .dev    = {
1271                 .dma_mask       = &tegra_udc_dmamask,
1272                 .coherent_dma_mask = DMA_BIT_MASK(32),
1273                 .platform_data  = &tegra_udc_pdata,
1274         },
1275         .resource = tegra_udc_resources,
1276         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1277 };
1278
1279 static struct resource tegra_otg_resources[] = {
1280         [0] = {
1281                 .start  = TEGRA_USB_BASE,
1282                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1283                 .flags  = IORESOURCE_MEM,
1284         },
1285         [1] = {
1286                 .start  = INT_USB,
1287                 .end    = INT_USB,
1288                 .flags  = IORESOURCE_IRQ,
1289         },
1290 };
1291
1292 struct platform_device tegra_otg_device = {
1293         .name           = "tegra-otg",
1294         .id             = -1,
1295         .resource       = tegra_otg_resources,
1296         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1297 };
1298
1299 #ifdef CONFIG_SATA_AHCI_TEGRA
1300 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1301
1302 static struct resource tegra_sata_resources[] = {
1303         [0] = {
1304                 .start = TEGRA_SATA_BAR5_BASE,
1305                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1306                 .flags = IORESOURCE_MEM,
1307         },
1308         [1] = {
1309                 .start = TEGRA_SATA_CONFIG_BASE,
1310                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1311                 .flags = IORESOURCE_MEM,
1312         },
1313         [2] = {
1314                 .start = INT_SATA_CTL,
1315                 .end = INT_SATA_CTL,
1316                 .flags = IORESOURCE_IRQ,
1317         },
1318 };
1319
1320 struct platform_device tegra_sata_device = {
1321         .name   = "tegra-sata",
1322         .id     = 0,
1323         .dev    = {
1324                 .platform_data = 0,
1325                 .coherent_dma_mask = DMA_BIT_MASK(32),
1326                 .dma_mask = &tegra_sata_dma_mask,
1327         },
1328         .resource = tegra_sata_resources,
1329         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1330 };
1331 #endif
1332
1333 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1334 static struct resource das_resource[] = {
1335         [0] = {
1336                 .start  = TEGRA_APB_MISC_DAS_BASE,
1337                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1338                 .flags  = IORESOURCE_MEM
1339         }
1340 };
1341
1342 struct platform_device tegra_das_device = {
1343         .name           = "tegra20-das",
1344         .id             = -1,
1345         .resource       = das_resource,
1346         .num_resources  = ARRAY_SIZE(das_resource),
1347 };
1348 #endif
1349
1350 #if defined(CONFIG_TEGRA_IOVMM_GART)
1351 static struct resource tegra_gart_resources[] = {
1352         [0] = {
1353                 .name   = "mc",
1354                 .flags  = IORESOURCE_MEM,
1355                 .start  = TEGRA_MC_BASE,
1356                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1357         },
1358         [1] = {
1359                 .name   = "gart",
1360                 .flags  = IORESOURCE_MEM,
1361                 .start  = TEGRA_GART_BASE,
1362                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1363         }
1364 };
1365
1366 struct platform_device tegra_gart_device = {
1367         .name           = "tegra_gart",
1368         .id             = -1,
1369         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1370         .resource       = tegra_gart_resources
1371 };
1372 #endif
1373
1374 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
1375 static struct resource tegra_smmu_resources[] = {
1376         [0] = {
1377                 .name   = "mc",
1378                 .flags  = IORESOURCE_MEM,
1379                 .start  = TEGRA_MC_BASE,
1380                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1381         },
1382         [1] = {
1383                 .name   = "ahbarb",
1384                 .flags  = IORESOURCE_MEM,
1385                 .start  = TEGRA_AHB_ARB_BASE,
1386                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1387         }
1388 };
1389
1390 struct platform_device tegra_smmu_device = {
1391         .name           = "tegra_smmu",
1392         .id             = -1,
1393         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1394         .resource       = tegra_smmu_resources
1395 };
1396
1397
1398 static struct tegra_smmu_window tegra_smmu[] = {
1399         [0] = {
1400                 .start  = TEGRA_SMMU_BASE,
1401                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1402         },
1403 };
1404
1405 struct tegra_smmu_window *tegra_smmu_window(int wnum)
1406 {
1407         return &tegra_smmu[wnum];
1408 }
1409
1410 int tegra_smmu_window_count(void)
1411 {
1412         return ARRAY_SIZE(tegra_smmu);
1413 }
1414 #endif
1415
1416 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1417 #define CLK_RESET_RST_SOURCE    0x0
1418 static struct resource tegra_wdt_resources[] = {
1419         [0] = {
1420                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1421                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1422                 .flags  = IORESOURCE_MEM,
1423         },
1424         [1] = {
1425                 .start  = TEGRA_TMR1_BASE,
1426                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1427                 .flags  = IORESOURCE_MEM,
1428         },
1429         [2] = {
1430                 .start  = INT_TMR1,
1431                 .end    = INT_TMR1,
1432                 .flags  = IORESOURCE_IRQ,
1433         },
1434 };
1435 #else
1436 static struct resource tegra_wdt_resources[] = {
1437         [0] = {
1438                 .start  = TEGRA_WDT0_BASE,
1439                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1440                 .flags  = IORESOURCE_MEM,
1441         },
1442         [1] = {
1443                 .start  = TEGRA_TMR10_BASE,
1444                 .end    = TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
1445                 .flags  = IORESOURCE_MEM,
1446         },
1447         [2] = {
1448                 .start  = INT_WDT_CPU,
1449                 .end    = INT_WDT_CPU,
1450                 .flags  = IORESOURCE_IRQ,
1451         },
1452 };
1453 #endif
1454
1455 struct platform_device tegra_wdt_device = {
1456         .name           = "tegra_wdt",
1457         .id             = -1,
1458         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1459         .resource       = tegra_wdt_resources,
1460 };
1461
1462 static struct resource tegra_pwfm_resource = {
1463         .start  = TEGRA_PWFM_BASE,
1464         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
1465         .flags  = IORESOURCE_MEM,
1466 };
1467
1468 struct platform_device tegra_pwfm_device = {
1469         .name           = "tegra-pwm",
1470         .id             = 0,
1471         .num_resources  = 1,
1472         .resource       = &tegra_pwfm_resource,
1473 };
1474
1475 static struct resource tegra_grhost_resources[] = {
1476         {
1477                 .start = TEGRA_HOST1X_BASE,
1478                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
1479                 .flags = IORESOURCE_MEM,
1480         },
1481         {
1482                 .start = TEGRA_DISPLAY_BASE,
1483                 .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
1484                 .flags = IORESOURCE_MEM,
1485         },
1486         {
1487                 .start = TEGRA_DISPLAY2_BASE,
1488                 .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
1489                 .flags = IORESOURCE_MEM,
1490         },
1491         {
1492                 .start = TEGRA_VI_BASE,
1493                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
1494                 .flags = IORESOURCE_MEM,
1495         },
1496         {
1497                 .start = TEGRA_ISP_BASE,
1498                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
1499                 .flags = IORESOURCE_MEM,
1500         },
1501         {
1502                 .start = TEGRA_MPE_BASE,
1503                 .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
1504                 .flags = IORESOURCE_MEM,
1505         },
1506         {
1507                 .start = INT_SYNCPT_THRESH_BASE,
1508                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
1509                 .flags = IORESOURCE_IRQ,
1510         },
1511         {
1512                 .start = INT_HOST1X_MPCORE_GENERAL,
1513                 .end = INT_HOST1X_MPCORE_GENERAL,
1514                 .flags = IORESOURCE_IRQ,
1515         },
1516 };
1517
1518 struct platform_device tegra_grhost_device = {
1519         .name = "tegra_grhost",
1520         .id = -1,
1521         .resource = tegra_grhost_resources,
1522         .num_resources = ARRAY_SIZE(tegra_grhost_resources),
1523 };
1524
1525 static struct tegra_avp_platform_data tegra_avp_pdata = {
1526 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1527         .emc_clk_rate = ULONG_MAX,
1528 #else
1529         .emc_clk_rate = 200000000,
1530 #endif
1531 };
1532
1533 struct resource tegra_nvavp_resources[] = {
1534         [0] = {
1535                 .start  = INT_SHR_SEM_INBOX_IBF,
1536                 .end    = INT_SHR_SEM_INBOX_IBF,
1537                 .flags  = IORESOURCE_IRQ,
1538                 .name   = "mbox_from_nvavp_pending",
1539         },
1540 };
1541
1542 struct nvhost_device nvavp_device = {
1543         .name           = "nvavp",
1544         .id             = -1,
1545         .resource       = tegra_nvavp_resources,
1546         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
1547 };
1548
1549 static struct resource tegra_avp_resources[] = {
1550         [0] = {
1551                 .start  = INT_SHR_SEM_INBOX_IBF,
1552                 .end    = INT_SHR_SEM_INBOX_IBF,
1553                 .flags  = IORESOURCE_IRQ,
1554                 .name   = "mbox_from_avp_pending",
1555         },
1556 };
1557
1558 struct platform_device tegra_avp_device = {
1559         .name           = "tegra-avp",
1560         .id             = -1,
1561         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1562         .resource       = tegra_avp_resources,
1563         .dev  = {
1564                 .coherent_dma_mask      = 0xffffffffULL,
1565                 .platform_data          = &tegra_avp_pdata,
1566         },
1567 };
1568
1569 static struct resource tegra_aes_resources[] = {
1570         {
1571                 .start  = TEGRA_VDE_BASE,
1572                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1573                 .flags  = IORESOURCE_MEM,
1574         },
1575         {
1576                 .start  = TEGRA_BSEA_BASE,
1577                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1578                 .flags  = IORESOURCE_MEM,
1579         },
1580 };
1581
1582 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1583
1584 struct platform_device tegra_aes_device = {
1585         .name           = "tegra-aes",
1586         .id             = -1,
1587         .resource       = tegra_aes_resources,
1588         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1589         .dev    = {
1590                 .dma_mask = &tegra_aes_dma_mask,
1591                 .coherent_dma_mask = DMA_BIT_MASK(32),
1592         },
1593 };
1594
1595 static struct resource tegra_kbc_resources[] = {
1596         [0] = {
1597                 .start = TEGRA_KBC_BASE,
1598                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1599                 .flags = IORESOURCE_MEM,
1600         },
1601         [1] = {
1602                 .start = INT_KBC,
1603                 .end   = INT_KBC,
1604                 .flags = IORESOURCE_IRQ,
1605         },
1606 };
1607
1608 struct platform_device tegra_kbc_device = {
1609         .name = "tegra-kbc",
1610         .id = -1,
1611         .resource = tegra_kbc_resources,
1612         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1613         .dev = {
1614                 .platform_data = 0,
1615         },
1616 };
1617
1618 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1619 static struct resource tegra_tsensor_resources[]= {
1620         {
1621                 .start  = TEGRA_TSENSOR_BASE,
1622                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1623                 .flags  = IORESOURCE_MEM,
1624         },
1625         {
1626                 .start  = INT_TSENSOR,
1627                 .end    = INT_TSENSOR,
1628                 .flags  = IORESOURCE_IRQ,
1629         },
1630         {
1631                 .start  = TEGRA_PMC_BASE + 0x1B0,
1632                 /* 2 pmc registers mapped */
1633                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
1634                 .flags  = IORESOURCE_MEM,
1635         },
1636 };
1637
1638 struct platform_device tegra_tsensor_device = {
1639         .name   = "tegra-tsensor",
1640         .id     = -1,
1641         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
1642         .resource       = tegra_tsensor_resources,
1643         .dev = {
1644                 .platform_data = 0,
1645         },
1646 };
1647 #endif
1648
1649 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1650 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
1651
1652 struct resource tegra_se_resources[] = {
1653         [0] = {
1654                 .start = TEGRA_SE_BASE,
1655                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
1656                 .flags = IORESOURCE_MEM,
1657         },
1658         [1] = {
1659                 .start  = TEGRA_PMC_BASE,
1660                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
1661                 .flags  = IORESOURCE_MEM,
1662         },
1663         [2] = {
1664                 .start = INT_SE,
1665                 .end = INT_SE,
1666                 .flags = IORESOURCE_IRQ,
1667         },
1668 };
1669
1670 struct platform_device tegra_se_device = {
1671         .name = "tegra-se",
1672         .id = -1,
1673         .dev = {
1674                 .coherent_dma_mask = DMA_BIT_MASK(32),
1675                 .dma_mask = &tegra_se_dma_mask,
1676         },
1677         .resource = tegra_se_resources,
1678         .num_resources = ARRAY_SIZE(tegra_se_resources),
1679 };
1680 #endif
1681