ARM: tegra: add apb dma device for t124 SOC
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/mipi-bif-tegra.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/tegra_avp.h>
30 #include <linux/nvhost.h>
31 #include <linux/clk.h>
32 #include <mach/irqs.h>
33 #include <linux/usb/tegra_usb_phy.h>
34 #include <mach/tegra_smmu.h>
35 #include <mach/tegra-swgid.h>
36
37 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
38 #include <asm/dma-iommu.h>
39 #endif
40
41 #include "gpio-names.h"
42 #include "iomap.h"
43 #include "devices.h"
44
45 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
46 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
47 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
48 #define TEGRA_DMA_REQ_SEL_SPI                   11
49 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
50
51 static struct resource emc_resource[] = {
52         [0] = {
53                 .start  = TEGRA_EMC_BASE,
54                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
55                 .flags  = IORESOURCE_MEM,
56         }
57 };
58
59 struct platform_device tegra_emc_device = {
60         .name           = "tegra-emc",
61         .id             = -1,
62         .resource       = emc_resource,
63         .num_resources  = ARRAY_SIZE(emc_resource),
64 };
65
66 static struct resource gpio_resource[] = {
67         [0] = {
68                 .start  = TEGRA_GPIO_BASE,
69                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
70                 .flags  = IORESOURCE_MEM,
71         },
72         [1] = {
73                 .start  = INT_GPIO1,
74                 .end    = INT_GPIO1,
75                 .flags  = IORESOURCE_IRQ,
76         },
77         [2] = {
78                 .start  = INT_GPIO2,
79                 .end    = INT_GPIO2,
80                 .flags  = IORESOURCE_IRQ,
81         },
82         [3] = {
83                 .start  = INT_GPIO3,
84                 .end    = INT_GPIO3,
85                 .flags  = IORESOURCE_IRQ,
86         },
87         [4] = {
88                 .start  = INT_GPIO4,
89                 .end    = INT_GPIO4,
90                 .flags  = IORESOURCE_IRQ,
91         },
92         [5] = {
93                 .start  = INT_GPIO5,
94                 .end    = INT_GPIO5,
95                 .flags  = IORESOURCE_IRQ,
96         },
97         [6] = {
98                 .start  = INT_GPIO6,
99                 .end    = INT_GPIO6,
100                 .flags  = IORESOURCE_IRQ,
101         },
102         [7] = {
103                 .start  = INT_GPIO7,
104                 .end    = INT_GPIO7,
105                 .flags  = IORESOURCE_IRQ,
106         },
107 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
108         [8] = {
109                 .start  = INT_GPIO8,
110                 .end    = INT_GPIO8,
111                 .flags  = IORESOURCE_IRQ,
112         },
113 #endif
114 };
115
116 struct platform_device tegra_gpio_device = {
117         .name           = "tegra-gpio",
118         .id             = -1,
119         .resource       = gpio_resource,
120         .num_resources  = ARRAY_SIZE(gpio_resource),
121 };
122
123 static struct resource pinmux_resource[] = {
124 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
125         [0] = {
126                 /* Tri-state registers */
127                 .start  = TEGRA_APB_MISC_BASE + 0x14,
128                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
129                 .flags  = IORESOURCE_MEM,
130         },
131         [1] = {
132                 /* Mux registers */
133                 .start  = TEGRA_APB_MISC_BASE + 0x80,
134                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
135                 .flags  = IORESOURCE_MEM,
136         },
137         [2] = {
138                 /* Pull-up/down registers */
139                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
140                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
141                 .flags  = IORESOURCE_MEM,
142         },
143         [3] = {
144                 /* Pad control registers */
145                 .start  = TEGRA_APB_MISC_BASE + 0x868,
146                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
147                 .flags  = IORESOURCE_MEM,
148         },
149 #else
150         [0] = {
151                 /* Drive registers */
152                 .start  = TEGRA_APB_MISC_BASE + 0x868,
153                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
154                 .flags  = IORESOURCE_MEM,
155         },
156         [1] = {
157                 /* Mux registers */
158                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
159 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
160                 .end    = TEGRA_APB_MISC_BASE + 0x3408 + 3,
161 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
162                 .end    = TEGRA_APB_MISC_BASE + 0x3514 + 3,
163 #else
164                 .end    = TEGRA_APB_MISC_BASE + 0x33e0 + 3,
165 #endif
166                 .flags  = IORESOURCE_MEM,
167         },
168 #endif
169 };
170
171 struct platform_device tegra_pinmux_device = {
172 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
173         .name           = "tegra30-pinmux-ctl",
174 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
175         .name           = "tegra20-pinmux-ctl",
176 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
177         .name           = "tegra11x-pinmux-ctl",
178 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
179         .name           = "tegra12x-pinmux",
180 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
181         .name           = "tegra14x-pinmux",
182 #endif
183         .id             = -1,
184         .resource       = pinmux_resource,
185         .num_resources  = ARRAY_SIZE(pinmux_resource),
186 };
187
188 static struct resource apbdma_resource[] = {
189         [0] = {
190                 .start  = TEGRA_APB_DMA_BASE,
191                 .end    = TEGRA_APB_DMA_BASE + TEGRA_APB_DMA_SIZE-1,
192                 .flags  = IORESOURCE_MEM,
193         },
194         [1] = {
195                 .start  = INT_APB_DMA_CH0,
196                 .end    = INT_APB_DMA_CH0,
197                 .flags  = IORESOURCE_IRQ,
198         },
199         [2] = {
200                 .start  = INT_APB_DMA_CH1,
201                 .end    = INT_APB_DMA_CH1,
202                 .flags  = IORESOURCE_IRQ,
203         },
204         [3] = {
205                 .start  = INT_APB_DMA_CH2,
206                 .end    = INT_APB_DMA_CH2,
207                 .flags  = IORESOURCE_IRQ,
208         },
209         [4] = {
210                 .start  = INT_APB_DMA_CH3,
211                 .end    = INT_APB_DMA_CH3,
212                 .flags  = IORESOURCE_IRQ,
213         },
214         [5] = {
215                 .start  = INT_APB_DMA_CH4,
216                 .end    = INT_APB_DMA_CH4,
217                 .flags  = IORESOURCE_IRQ,
218         },
219         [6] = {
220                 .start  = INT_APB_DMA_CH5,
221                 .end    = INT_APB_DMA_CH5,
222                 .flags  = IORESOURCE_IRQ,
223         },
224         [7] = {
225                 .start  = INT_APB_DMA_CH6,
226                 .end    = INT_APB_DMA_CH6,
227                 .flags  = IORESOURCE_IRQ,
228         },
229         [8] = {
230                 .start  = INT_APB_DMA_CH7,
231                 .end    = INT_APB_DMA_CH7,
232                 .flags  = IORESOURCE_IRQ,
233         },
234         [9] = {
235                 .start  = INT_APB_DMA_CH8,
236                 .end    = INT_APB_DMA_CH8,
237                 .flags  = IORESOURCE_IRQ,
238         },
239         [10] = {
240                 .start  = INT_APB_DMA_CH9,
241                 .end    = INT_APB_DMA_CH9,
242                 .flags  = IORESOURCE_IRQ,
243         },
244         [11] = {
245                 .start  = INT_APB_DMA_CH10,
246                 .end    = INT_APB_DMA_CH10,
247                 .flags  = IORESOURCE_IRQ,
248         },
249         [12] = {
250                 .start  = INT_APB_DMA_CH11,
251                 .end    = INT_APB_DMA_CH11,
252                 .flags  = IORESOURCE_IRQ,
253         },
254         [13] = {
255                 .start  = INT_APB_DMA_CH12,
256                 .end    = INT_APB_DMA_CH12,
257                 .flags  = IORESOURCE_IRQ,
258         },
259         [14] = {
260                 .start  = INT_APB_DMA_CH13,
261                 .end    = INT_APB_DMA_CH13,
262                 .flags  = IORESOURCE_IRQ,
263         },
264         [15] = {
265                 .start  = INT_APB_DMA_CH14,
266                 .end    = INT_APB_DMA_CH14,
267                 .flags  = IORESOURCE_IRQ,
268         },
269         [16] = {
270                 .start  = INT_APB_DMA_CH15,
271                 .end    = INT_APB_DMA_CH15,
272                 .flags  = IORESOURCE_IRQ,
273         },
274         [17] = {
275                 .start  = INT_APB_DMA_CH16,
276                 .end    = INT_APB_DMA_CH16,
277                 .flags  = IORESOURCE_IRQ,
278         },
279         [18] = {
280                 .start  = INT_APB_DMA_CH17,
281                 .end    = INT_APB_DMA_CH17,
282                 .flags  = IORESOURCE_IRQ,
283         },
284         [19] = {
285                 .start  = INT_APB_DMA_CH18,
286                 .end    = INT_APB_DMA_CH18,
287                 .flags  = IORESOURCE_IRQ,
288         },
289         [20] = {
290                 .start  = INT_APB_DMA_CH19,
291                 .end    = INT_APB_DMA_CH19,
292                 .flags  = IORESOURCE_IRQ,
293         },
294         [21] = {
295                 .start  = INT_APB_DMA_CH20,
296                 .end    = INT_APB_DMA_CH20,
297                 .flags  = IORESOURCE_IRQ,
298         },
299         [22] = {
300                 .start  = INT_APB_DMA_CH21,
301                 .end    = INT_APB_DMA_CH21,
302                 .flags  = IORESOURCE_IRQ,
303         },
304         [23] = {
305                 .start  = INT_APB_DMA_CH22,
306                 .end    = INT_APB_DMA_CH22,
307                 .flags  = IORESOURCE_IRQ,
308         },
309         [24] = {
310                 .start  = INT_APB_DMA_CH23,
311                 .end    = INT_APB_DMA_CH23,
312                 .flags  = IORESOURCE_IRQ,
313         },
314         [25] = {
315                 .start  = INT_APB_DMA_CH24,
316                 .end    = INT_APB_DMA_CH24,
317                 .flags  = IORESOURCE_IRQ,
318         },
319         [26] = {
320                 .start  = INT_APB_DMA_CH25,
321                 .end    = INT_APB_DMA_CH25,
322                 .flags  = IORESOURCE_IRQ,
323         },
324         [27] = {
325                 .start  = INT_APB_DMA_CH26,
326                 .end    = INT_APB_DMA_CH26,
327                 .flags  = IORESOURCE_IRQ,
328         },
329         [28] = {
330                 .start  = INT_APB_DMA_CH27,
331                 .end    = INT_APB_DMA_CH27,
332                 .flags  = IORESOURCE_IRQ,
333         },
334         [29] = {
335                 .start  = INT_APB_DMA_CH28,
336                 .end    = INT_APB_DMA_CH28,
337                 .flags  = IORESOURCE_IRQ,
338         },
339         [30] = {
340                 .start  = INT_APB_DMA_CH29,
341                 .end    = INT_APB_DMA_CH29,
342                 .flags  = IORESOURCE_IRQ,
343         },
344         [31] = {
345                 .start  = INT_APB_DMA_CH30,
346                 .end    = INT_APB_DMA_CH30,
347                 .flags  = IORESOURCE_IRQ,
348         },
349         [32] = {
350                 .start  = INT_APB_DMA_CH31,
351                 .end    = INT_APB_DMA_CH31,
352                 .flags  = IORESOURCE_IRQ,
353         },
354
355 };
356
357 struct platform_device tegra_apbdma = {
358         .name           = "tegra124-apbdma",
359         .id             = -1,
360         .resource       = apbdma_resource,
361         .num_resources  = ARRAY_SIZE(apbdma_resource),
362 };
363
364 static struct resource i2c_resource1[] = {
365         [0] = {
366                 .start  = INT_I2C,
367                 .end    = INT_I2C,
368                 .flags  = IORESOURCE_IRQ,
369         },
370         [1] = {
371                 .start  = TEGRA_I2C_BASE,
372                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
373                 .flags  = IORESOURCE_MEM,
374         },
375 };
376
377 static struct resource i2c_resource2[] = {
378         [0] = {
379                 .start  = INT_I2C2,
380                 .end    = INT_I2C2,
381                 .flags  = IORESOURCE_IRQ,
382         },
383         [1] = {
384                 .start  = TEGRA_I2C2_BASE,
385                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
386                 .flags  = IORESOURCE_MEM,
387         },
388 };
389
390 static struct resource i2c_resource3[] = {
391         [0] = {
392                 .start  = INT_I2C3,
393                 .end    = INT_I2C3,
394                 .flags  = IORESOURCE_IRQ,
395         },
396         [1] = {
397                 .start  = TEGRA_I2C3_BASE,
398                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
399                 .flags  = IORESOURCE_MEM,
400         },
401 };
402
403 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
404 static struct resource i2c_resource4[] = {
405         [0] = {
406                 .start  = INT_DVC,
407                 .end    = INT_DVC,
408                 .flags  = IORESOURCE_IRQ,
409         },
410         [1] = {
411                 .start  = TEGRA_DVC_BASE,
412                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
413                 .flags  = IORESOURCE_MEM,
414         },
415 };
416
417 #else
418 static struct resource i2c_resource4[] = {
419         [0] = {
420                 .start  = INT_I2C4,
421                 .end    = INT_I2C4,
422                 .flags  = IORESOURCE_IRQ,
423         },
424         [1] = {
425                 .start  = TEGRA_I2C4_BASE,
426                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
427                 .flags  = IORESOURCE_MEM,
428         },
429 };
430
431 static struct resource i2c_resource5[] = {
432         [0] = {
433                 .start  = INT_I2C5,
434                 .end    = INT_I2C5,
435                 .flags  = IORESOURCE_IRQ,
436         },
437         [1] = {
438                 .start  = TEGRA_I2C5_BASE,
439                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
440                 .flags  = IORESOURCE_MEM,
441         },
442 };
443 #endif
444
445 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
446 static struct resource i2c_resource6[] = {
447         [0] = {
448                 .start  = INT_I2C6,
449                 .end    = INT_I2C6,
450                 .flags  = IORESOURCE_IRQ,
451         },
452         [1] = {
453                 .start  = TEGRA_I2C6_BASE,
454                 .end    = TEGRA_I2C6_BASE + TEGRA_I2C6_SIZE-1,
455                 .flags  = IORESOURCE_MEM,
456         },
457 };
458 #endif
459
460 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
461         .bus_clk_rate   = 400000,
462 };
463
464 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
465         .bus_clk_rate   = 400000,
466 };
467
468 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
469         .bus_clk_rate   = 400000,
470 };
471
472 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
473         .bus_clk_rate   = 400000,
474 };
475
476 struct platform_device tegra_i2c_device1 = {
477         .name           = "tegra-i2c",
478         .id             = 0,
479         .resource       = i2c_resource1,
480         .num_resources  = ARRAY_SIZE(i2c_resource1),
481         .dev = {
482                 .platform_data = &tegra_i2c1_platform_data,
483         },
484 };
485
486 struct platform_device tegra_i2c_device2 = {
487         .name           = "tegra-i2c",
488         .id             = 1,
489         .resource       = i2c_resource2,
490         .num_resources  = ARRAY_SIZE(i2c_resource2),
491         .dev = {
492                 .platform_data = &tegra_i2c2_platform_data,
493         },
494 };
495
496 struct platform_device tegra_i2c_device3 = {
497         .name           = "tegra-i2c",
498         .id             = 2,
499         .resource       = i2c_resource3,
500         .num_resources  = ARRAY_SIZE(i2c_resource3),
501         .dev = {
502                 .platform_data = &tegra_i2c3_platform_data,
503         },
504 };
505
506 struct platform_device tegra_i2c_device4 = {
507         .name           = "tegra-i2c",
508         .id             = 3,
509         .resource       = i2c_resource4,
510         .num_resources  = ARRAY_SIZE(i2c_resource4),
511         .dev = {
512                 .platform_data = &tegra_dvc_platform_data,
513         },
514 };
515
516 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
517 struct platform_device tegra_i2c_device5 = {
518         .name           = "tegra-i2c",
519         .id             = 4,
520         .resource       = i2c_resource5,
521         .num_resources  = ARRAY_SIZE(i2c_resource5),
522         .dev = {
523                 .platform_data = 0,
524         },
525 };
526 #endif
527
528 struct platform_device tegra11_i2c_device1 = {
529         .name           = "tegra11-i2c",
530         .id             = 0,
531         .resource       = i2c_resource1,
532         .num_resources  = ARRAY_SIZE(i2c_resource1),
533         .dev = {
534                 .platform_data = 0,
535         },
536 };
537
538 struct platform_device tegra11_i2c_device2 = {
539         .name           = "tegra11-i2c",
540         .id             = 1,
541         .resource       = i2c_resource2,
542         .num_resources  = ARRAY_SIZE(i2c_resource2),
543         .dev = {
544                 .platform_data = 0,
545         },
546 };
547
548 struct platform_device tegra11_i2c_device3 = {
549         .name           = "tegra11-i2c",
550         .id             = 2,
551         .resource       = i2c_resource3,
552         .num_resources  = ARRAY_SIZE(i2c_resource3),
553         .dev = {
554                 .platform_data = 0,
555         },
556 };
557
558 struct platform_device tegra11_i2c_device4 = {
559         .name           = "tegra11-i2c",
560         .id             = 3,
561         .resource       = i2c_resource4,
562         .num_resources  = ARRAY_SIZE(i2c_resource4),
563         .dev = {
564                 .platform_data = 0,
565         },
566 };
567
568 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
569 struct platform_device tegra11_i2c_device5 = {
570         .name           = "tegra11-i2c",
571         .id             = 4,
572         .resource       = i2c_resource5,
573         .num_resources  = ARRAY_SIZE(i2c_resource5),
574         .dev = {
575                 .platform_data = 0,
576         },
577 };
578 #endif
579
580 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
581
582 struct platform_device tegra14_i2c_device1 = {
583         .name           = "tegra14-i2c",
584         .id             = 0,
585         .resource       = i2c_resource1,
586         .num_resources  = ARRAY_SIZE(i2c_resource1),
587         .dev = {
588                 .platform_data = 0,
589         },
590 };
591
592 struct platform_device tegra14_i2c_device2 = {
593         .name           = "tegra14-i2c",
594         .id             = 1,
595         .resource       = i2c_resource2,
596         .num_resources  = ARRAY_SIZE(i2c_resource2),
597         .dev = {
598                 .platform_data = 0,
599         },
600 };
601
602 struct platform_device tegra14_i2c_device3 = {
603         .name           = "tegra14-i2c",
604         .id             = 2,
605         .resource       = i2c_resource3,
606         .num_resources  = ARRAY_SIZE(i2c_resource3),
607         .dev = {
608                 .platform_data = 0,
609         },
610 };
611
612 struct platform_device tegra14_i2c_device4 = {
613         .name           = "tegra14-i2c",
614         .id             = 3,
615         .resource       = i2c_resource4,
616         .num_resources  = ARRAY_SIZE(i2c_resource4),
617         .dev = {
618                 .platform_data = 0,
619         },
620 };
621
622 struct platform_device tegra14_i2c_device5 = {
623         .name           = "tegra14-i2c",
624         .id             = 4,
625         .resource       = i2c_resource5,
626         .num_resources  = ARRAY_SIZE(i2c_resource5),
627         .dev = {
628                 .platform_data = 0,
629         },
630 };
631
632 struct platform_device tegra14_i2c_device6 = {
633         .name           = "tegra14-i2c",
634         .id             = 5,
635         .resource       = i2c_resource6,
636         .num_resources  = ARRAY_SIZE(i2c_resource6),
637         .dev = {
638                 .platform_data = 0,
639         },
640 };
641
642 #endif
643
644 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
645
646 static struct tegra_mipi_bif_platform_data mipi_bif_pdata = {
647         .adapter_nr     = -1,
648         .tauBIF         = 2,
649         .bus_clk_rate   = 13,
650 };
651
652 static struct resource mipi_bif_resource[] = {
653         [0] = {
654                 .start  = INT_MIPI_BIF,
655                 .end    = INT_MIPI_BIF,
656                 .flags  = IORESOURCE_IRQ,
657         },
658         [1] = {
659                 .start  = TEGRA_MIPI_BIF_BASE,
660                 .end    = TEGRA_MIPI_BIF_BASE + TEGRA_MIPI_BIF_SIZE - 1,
661                 .flags  = IORESOURCE_MEM,
662         },
663 };
664
665 struct platform_device tegra_mipi_bif_device = {
666         .name           = "tegra-mipi-bif",
667         .id             = -1,
668         .resource       = mipi_bif_resource,
669         .num_resources  = ARRAY_SIZE(mipi_bif_resource),
670         .dev = {
671                 .platform_data = &mipi_bif_pdata,
672         },
673 };
674
675 #endif
676
677 static struct resource spi_resource1[] = {
678         [0] = {
679                 .start  = INT_SPI_1,
680                 .end    = INT_SPI_1,
681                 .flags  = IORESOURCE_IRQ,
682         },
683         [1] = {
684                 .start  = TEGRA_SPI1_BASE,
685                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
686                 .flags  = IORESOURCE_MEM,
687         },
688 };
689
690 static struct resource spi_resource2[] = {
691         [0] = {
692                 .start  = INT_SPI_2,
693                 .end    = INT_SPI_2,
694                 .flags  = IORESOURCE_IRQ,
695         },
696         [1] = {
697                 .start  = TEGRA_SPI2_BASE,
698                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
699                 .flags  = IORESOURCE_MEM,
700         },
701 };
702
703 static struct resource spi_resource3[] = {
704         [0] = {
705                 .start  = INT_SPI_3,
706                 .end    = INT_SPI_3,
707                 .flags  = IORESOURCE_IRQ,
708         },
709         [1] = {
710                 .start  = TEGRA_SPI3_BASE,
711                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
712                 .flags  = IORESOURCE_MEM,
713         },
714 };
715
716 static struct resource spi_resource4[] = {
717         [0] = {
718                 .start  = INT_SPI_4,
719                 .end    = INT_SPI_4,
720                 .flags  = IORESOURCE_IRQ,
721         },
722         [1] = {
723                 .start  = TEGRA_SPI4_BASE,
724                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
725                 .flags  = IORESOURCE_MEM,
726         },
727 };
728 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
729 static struct resource spi_resource5[] = {
730         [0] = {
731                 .start  = INT_SPI_5,
732                 .end    = INT_SPI_5,
733                 .flags  = IORESOURCE_IRQ,
734         },
735         [1] = {
736                 .start  = TEGRA_SPI5_BASE,
737                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
738                 .flags  = IORESOURCE_MEM,
739         },
740 };
741
742 static struct resource spi_resource6[] = {
743         [0] = {
744                 .start  = INT_SPI_6,
745                 .end    = INT_SPI_6,
746                 .flags  = IORESOURCE_IRQ,
747         },
748         [1] = {
749                 .start  = TEGRA_SPI6_BASE,
750                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
751                 .flags  = IORESOURCE_MEM,
752         },
753 };
754 #endif
755
756 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
757 static struct resource dtv_resource[] = {
758         [0] = {
759                 .start  = INT_DTV,
760                 .end    = INT_DTV,
761                 .flags  = IORESOURCE_IRQ,
762         },
763         [1] = {
764                 .start  = TEGRA_DTV_BASE,
765                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
766                 .flags  = IORESOURCE_MEM,
767         },
768         [2] = {
769                 .start  = TEGRA_DMA_REQ_SEL_DTV,
770                 .end    = TEGRA_DMA_REQ_SEL_DTV,
771                 .flags  = IORESOURCE_DMA
772         },
773 };
774 #endif
775
776
777 struct platform_device tegra_spi_device1 = {
778         .name           = "spi_tegra",
779         .id             = 0,
780         .resource       = spi_resource1,
781         .num_resources  = ARRAY_SIZE(spi_resource1),
782         .dev            = {
783                 .coherent_dma_mask      = 0xffffffff,
784         },
785 };
786
787 struct platform_device tegra_spi_device2 = {
788         .name           = "spi_tegra",
789         .id             = 1,
790         .resource       = spi_resource2,
791         .num_resources  = ARRAY_SIZE(spi_resource2),
792         .dev            = {
793                 .coherent_dma_mask      = 0xffffffff,
794         },
795 };
796
797 struct platform_device tegra_spi_device3 = {
798         .name           = "spi_tegra",
799         .id             = 2,
800         .resource       = spi_resource3,
801         .num_resources  = ARRAY_SIZE(spi_resource3),
802         .dev            = {
803                 .coherent_dma_mask      = 0xffffffff,
804         },
805 };
806
807 struct platform_device tegra_spi_device4 = {
808         .name           = "spi_tegra",
809         .id             = 3,
810         .resource       = spi_resource4,
811         .num_resources  = ARRAY_SIZE(spi_resource4),
812         .dev            = {
813                 .coherent_dma_mask      = 0xffffffff,
814         },
815 };
816 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
817 struct platform_device tegra_spi_device5 = {
818         .name           = "spi_tegra",
819         .id             = 4,
820         .resource       = spi_resource5,
821         .num_resources  = ARRAY_SIZE(spi_resource5),
822         .dev  = {
823                 .coherent_dma_mask      = 0xffffffff,
824         },
825 };
826
827 struct platform_device tegra_spi_device6 = {
828         .name           = "spi_tegra",
829         .id             = 5,
830         .resource       = spi_resource6,
831         .num_resources  = ARRAY_SIZE(spi_resource6),
832         .dev  = {
833                 .coherent_dma_mask      = 0xffffffff,
834         },
835 };
836 #endif
837
838 struct platform_device tegra11_spi_device1 = {
839         .name           = "spi-tegra114",
840         .id             = 0,
841         .resource       = spi_resource1,
842         .num_resources  = ARRAY_SIZE(spi_resource1),
843         .dev            = {
844                 .coherent_dma_mask      = 0xffffffff,
845         },
846 };
847
848 struct platform_device tegra11_spi_device2 = {
849         .name           = "spi-tegra114",
850         .id             = 1,
851         .resource       = spi_resource2,
852         .num_resources  = ARRAY_SIZE(spi_resource2),
853         .dev            = {
854                 .coherent_dma_mask      = 0xffffffff,
855         },
856 };
857
858 struct platform_device tegra11_spi_device3 = {
859         .name           = "spi-tegra114",
860         .id             = 2,
861         .resource       = spi_resource3,
862         .num_resources  = ARRAY_SIZE(spi_resource3),
863         .dev            = {
864                 .coherent_dma_mask      = 0xffffffff,
865         },
866 };
867
868 struct platform_device tegra11_spi_device4 = {
869         .name           = "spi-tegra114",
870         .id             = 3,
871         .resource       = spi_resource4,
872         .num_resources  = ARRAY_SIZE(spi_resource4),
873         .dev            = {
874                 .coherent_dma_mask      = 0xffffffff,
875         },
876 };
877
878 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
879 struct platform_device tegra11_spi_device5 = {
880         .name           = "spi-tegra114",
881         .id             = 4,
882         .resource       = spi_resource5,
883         .num_resources  = ARRAY_SIZE(spi_resource5),
884         .dev  = {
885                 .coherent_dma_mask      = 0xffffffff,
886         },
887 };
888
889 struct platform_device tegra11_spi_device6 = {
890         .name           = "spi-tegra114",
891         .id             = 5,
892         .resource       = spi_resource6,
893         .num_resources  = ARRAY_SIZE(spi_resource6),
894         .dev  = {
895                 .coherent_dma_mask      = 0xffffffff,
896         },
897 };
898 #endif
899
900 struct platform_device tegra_spi_slave_device1 = {
901         .name           = "spi_slave_tegra",
902         .id             = 0,
903         .resource       = spi_resource1,
904         .num_resources  = ARRAY_SIZE(spi_resource1),
905         .dev  = {
906                 .coherent_dma_mask      = 0xffffffff,
907         },
908 };
909
910 struct platform_device tegra_spi_slave_device2 = {
911         .name           = "spi_slave_tegra",
912         .id             = 1,
913         .resource       = spi_resource2,
914         .num_resources  = ARRAY_SIZE(spi_resource2),
915         .dev  = {
916                 .coherent_dma_mask      = 0xffffffff,
917         },
918 };
919
920 struct platform_device tegra_spi_slave_device3 = {
921         .name           = "spi_slave_tegra",
922         .id             = 2,
923         .resource       = spi_resource3,
924         .num_resources  = ARRAY_SIZE(spi_resource3),
925         .dev  = {
926                 .coherent_dma_mask      = 0xffffffff,
927         },
928 };
929
930 struct platform_device tegra_spi_slave_device4 = {
931         .name           = "spi_slave_tegra",
932         .id             = 3,
933         .resource       = spi_resource4,
934         .num_resources  = ARRAY_SIZE(spi_resource4),
935         .dev  = {
936                 .coherent_dma_mask      = 0xffffffff,
937         },
938 };
939 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
940 struct platform_device tegra_spi_slave_device5 = {
941         .name           = "spi_slave_tegra",
942         .id             = 4,
943         .resource       = spi_resource5,
944         .num_resources  = ARRAY_SIZE(spi_resource5),
945         .dev  = {
946                 .coherent_dma_mask      = 0xffffffff,
947         },
948 };
949
950 struct platform_device tegra_spi_slave_device6 = {
951         .name           = "spi_slave_tegra",
952         .id             = 5,
953         .resource       = spi_resource6,
954         .num_resources  = ARRAY_SIZE(spi_resource6),
955         .dev  = {
956                 .coherent_dma_mask      = 0xffffffff,
957         },
958 };
959 #endif
960
961 struct platform_device tegra11_spi_slave_device1 = {
962         .name           = "tegra11-spi-slave",
963         .id             = 0,
964         .resource       = spi_resource1,
965         .num_resources  = ARRAY_SIZE(spi_resource1),
966         .dev  = {
967                 .coherent_dma_mask      = 0xffffffff,
968         },
969 };
970
971 struct platform_device tegra11_spi_slave_device2 = {
972         .name           = "tegra11-spi-slave",
973         .id             = 1,
974         .resource       = spi_resource2,
975         .num_resources  = ARRAY_SIZE(spi_resource2),
976         .dev  = {
977                 .coherent_dma_mask      = 0xffffffff,
978         },
979 };
980
981 struct platform_device tegra11_spi_slave_device3 = {
982         .name           = "tegra11-spi-slave",
983         .id             = 2,
984         .resource       = spi_resource3,
985         .num_resources  = ARRAY_SIZE(spi_resource3),
986         .dev  = {
987                 .coherent_dma_mask      = 0xffffffff,
988         },
989 };
990
991 struct platform_device tegra11_spi_slave_device4 = {
992         .name           = "tegra11-spi-slave",
993         .id             = 3,
994         .resource       = spi_resource4,
995         .num_resources  = ARRAY_SIZE(spi_resource4),
996         .dev  = {
997                 .coherent_dma_mask      = 0xffffffff,
998         },
999 };
1000 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1001 struct platform_device tegra11_spi_slave_device5 = {
1002         .name           = "tegra11-spi-slave",
1003         .id             = 4,
1004         .resource       = spi_resource5,
1005         .num_resources  = ARRAY_SIZE(spi_resource5),
1006         .dev  = {
1007                 .coherent_dma_mask      = 0xffffffff,
1008         },
1009 };
1010
1011 struct platform_device tegra11_spi_slave_device6 = {
1012         .name           = "tegra11-spi-slave",
1013         .id             = 5,
1014         .resource       = spi_resource6,
1015         .num_resources  = ARRAY_SIZE(spi_resource6),
1016         .dev  = {
1017                 .coherent_dma_mask      = 0xffffffff,
1018         },
1019 };
1020 #endif
1021
1022 static struct resource resources_nor[] = {
1023         [0] = {
1024                 .start = INT_SNOR,
1025                 .end = INT_SNOR,
1026                 .flags = IORESOURCE_IRQ,
1027         },
1028         [1] = {
1029                 /* Map SNOR Controller */
1030                 .start = TEGRA_SNOR_BASE,
1031                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
1032                 .flags = IORESOURCE_MEM,
1033         },
1034         [2] = {
1035                 /* Map the size of flash */
1036                 .start = TEGRA_NOR_FLASH_BASE,
1037                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
1038                 .flags = IORESOURCE_MEM,
1039         }
1040 };
1041
1042 struct platform_device tegra_nor_device = {
1043         .name = "tegra-nor",
1044         .id = -1,
1045         .num_resources = ARRAY_SIZE(resources_nor),
1046         .resource = resources_nor,
1047         .dev = {
1048                 .coherent_dma_mask = 0xffffffff,
1049         },
1050 };
1051
1052 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1053 struct platform_device tegra_dtv_device = {
1054         .name           = "tegra_dtv",
1055         .id             = -1,
1056         .resource       = dtv_resource,
1057         .num_resources  = ARRAY_SIZE(dtv_resource),
1058         .dev = {
1059                 .init_name = "dtv",
1060                 .coherent_dma_mask = 0xffffffff,
1061         },
1062 };
1063 #endif
1064
1065
1066 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1067
1068 static struct resource dtv_resource[] = {
1069         [0] = {
1070                 .start  = TEGRA_DTV_BASE,
1071                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
1072                 .flags  = IORESOURCE_MEM,
1073         },
1074         [1] = {
1075                 .start  = TEGRA_DMA_REQ_SEL_DTV,
1076                 .end    = TEGRA_DMA_REQ_SEL_DTV,
1077                 .flags  = IORESOURCE_DMA
1078         },
1079 };
1080
1081 struct platform_device tegra_dtv_device = {
1082         .name           = "tegra_dtv",
1083         .id             = -1,
1084         .resource       = dtv_resource,
1085         .num_resources  = ARRAY_SIZE(dtv_resource),
1086         .dev = {
1087                 .init_name = "dtv",
1088                 .coherent_dma_mask = 0xffffffff,
1089         },
1090 };
1091 #endif
1092
1093 static struct resource sdhci_resource1[] = {
1094         [0] = {
1095                 .start  = INT_SDMMC1,
1096                 .end    = INT_SDMMC1,
1097                 .flags  = IORESOURCE_IRQ,
1098         },
1099         [1] = {
1100                 .start  = TEGRA_SDMMC1_BASE,
1101                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
1102                 .flags  = IORESOURCE_MEM,
1103         },
1104 };
1105
1106 static struct resource sdhci_resource2[] = {
1107         [0] = {
1108                 .start  = INT_SDMMC2,
1109                 .end    = INT_SDMMC2,
1110                 .flags  = IORESOURCE_IRQ,
1111         },
1112         [1] = {
1113                 .start  = TEGRA_SDMMC2_BASE,
1114                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
1115                 .flags  = IORESOURCE_MEM,
1116         },
1117 };
1118
1119 static struct resource sdhci_resource3[] = {
1120         [0] = {
1121                 .start  = INT_SDMMC3,
1122                 .end    = INT_SDMMC3,
1123                 .flags  = IORESOURCE_IRQ,
1124         },
1125         [1] = {
1126                 .start  = TEGRA_SDMMC3_BASE,
1127                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
1128                 .flags  = IORESOURCE_MEM,
1129         },
1130 };
1131
1132 static struct resource sdhci_resource4[] = {
1133         [0] = {
1134                 .start  = INT_SDMMC4,
1135                 .end    = INT_SDMMC4,
1136                 .flags  = IORESOURCE_IRQ,
1137         },
1138         [1] = {
1139                 .start  = TEGRA_SDMMC4_BASE,
1140                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
1141                 .flags  = IORESOURCE_MEM,
1142         },
1143 };
1144
1145 struct platform_device tegra_pci_device = {
1146         .name           = "tegra-pcie",
1147         .id             = 0,
1148         .resource       = 0,
1149         .num_resources  = 0,
1150         .dev = {
1151                 .platform_data = 0,
1152         },
1153 };
1154
1155 /* board files should fill in platform_data register the devices themselvs.
1156  * See board-harmony.c for an example
1157  */
1158 struct platform_device tegra_sdhci_device1 = {
1159         .name           = "sdhci-tegra",
1160         .id             = 0,
1161         .resource       = sdhci_resource1,
1162         .num_resources  = ARRAY_SIZE(sdhci_resource1),
1163 };
1164
1165 struct platform_device tegra_sdhci_device2 = {
1166         .name           = "sdhci-tegra",
1167         .id             = 1,
1168         .resource       = sdhci_resource2,
1169         .num_resources  = ARRAY_SIZE(sdhci_resource2),
1170 };
1171
1172 struct platform_device tegra_sdhci_device3 = {
1173         .name           = "sdhci-tegra",
1174         .id             = 2,
1175         .resource       = sdhci_resource3,
1176         .num_resources  = ARRAY_SIZE(sdhci_resource3),
1177 };
1178
1179 struct platform_device tegra_sdhci_device4 = {
1180         .name           = "sdhci-tegra",
1181         .id             = 3,
1182         .resource       = sdhci_resource4,
1183         .num_resources  = ARRAY_SIZE(sdhci_resource4),
1184 };
1185
1186 static struct resource tegra_usb1_resources[] = {
1187         [0] = {
1188                 .start  = TEGRA_USB_BASE,
1189                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1190                 .flags  = IORESOURCE_MEM,
1191         },
1192         [1] = {
1193                 .start  = INT_USB,
1194                 .end    = INT_USB,
1195                 .flags  = IORESOURCE_IRQ,
1196         },
1197 };
1198
1199 static struct resource tegra_usb2_resources[] = {
1200         [0] = {
1201                 .start  = TEGRA_USB2_BASE,
1202                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
1203                 .flags  = IORESOURCE_MEM,
1204         },
1205         [1] = {
1206                 .start  = INT_USB2,
1207                 .end    = INT_USB2,
1208                 .flags  = IORESOURCE_IRQ,
1209         },
1210 };
1211
1212 static struct resource tegra_usb3_resources[] = {
1213         [0] = {
1214                 .start  = TEGRA_USB3_BASE,
1215                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
1216                 .flags  = IORESOURCE_MEM,
1217         },
1218         [1] = {
1219                 .start  = INT_USB3,
1220                 .end    = INT_USB3,
1221                 .flags  = IORESOURCE_IRQ,
1222         },
1223 };
1224
1225 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1226 static struct resource tegra_xusb_resources[] = {
1227         [0] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_HOST_BASE, TEGRA_XUSB_HOST_SIZE,
1228                         "host"),
1229         [1] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_FPCI_BASE, TEGRA_XUSB_FPCI_SIZE,
1230                         "fpci"),
1231         [2] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_IPFS_BASE, TEGRA_XUSB_IPFS_SIZE,
1232                         "ipfs"),
1233         [3] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_PADCTL_BASE,
1234                         TEGRA_XUSB_PADCTL_SIZE, "padctl"),
1235         [4] = DEFINE_RES_MEM_NAMED(TEGRA_PMC_BASE, TEGRA_PMC_SIZE, "pmc"),
1236         [5] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_INT, "host"),
1237         [6] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_SMI, "host-smi"),
1238         [7] = DEFINE_RES_IRQ_NAMED(INT_XUSB_PADCTL, "padctl"),
1239         [8] = DEFINE_RES_IRQ_NAMED(INT_USB3, "usb3"),
1240 };
1241
1242 static u64 tegra_xusb_dmamask = DMA_BIT_MASK(64);
1243
1244 struct platform_device tegra_xhci_device = {
1245         .name = "tegra-xhci",
1246         .id = -1,
1247         .dev = {
1248                 .dma_mask = &tegra_xusb_dmamask,
1249                 .coherent_dma_mask = DMA_BIT_MASK(64),
1250         },
1251         .resource = tegra_xusb_resources,
1252         .num_resources = ARRAY_SIZE(tegra_xusb_resources),
1253 };
1254 #endif
1255
1256 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(64);
1257
1258 struct platform_device tegra_ehci1_device = {
1259         .name   = "tegra-ehci",
1260         .id     = 0,
1261         .dev    = {
1262                 .dma_mask       = &tegra_ehci_dmamask,
1263                 .coherent_dma_mask = DMA_BIT_MASK(64),
1264         },
1265         .resource = tegra_usb1_resources,
1266         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
1267 };
1268
1269 struct platform_device tegra_ehci2_device = {
1270         .name   = "tegra-ehci",
1271         .id     = 1,
1272         .dev    = {
1273                 .dma_mask       = &tegra_ehci_dmamask,
1274                 .coherent_dma_mask = DMA_BIT_MASK(64),
1275         },
1276         .resource = tegra_usb2_resources,
1277         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
1278 };
1279
1280 struct platform_device tegra_ehci3_device = {
1281         .name   = "tegra-ehci",
1282         .id     = 2,
1283         .dev    = {
1284                 .dma_mask       = &tegra_ehci_dmamask,
1285                 .coherent_dma_mask = DMA_BIT_MASK(64),
1286         },
1287         .resource = tegra_usb3_resources,
1288         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
1289 };
1290
1291 static struct resource tegra_pmu_resources[] = {
1292         [0] = {
1293                 .start  = INT_CPU0_PMU_INTR,
1294                 .end    = INT_CPU0_PMU_INTR,
1295                 .flags  = IORESOURCE_IRQ,
1296         },
1297         [1] = {
1298                 .start  = INT_CPU1_PMU_INTR,
1299                 .end    = INT_CPU1_PMU_INTR,
1300                 .flags  = IORESOURCE_IRQ,
1301         },
1302 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1303         [2] = {
1304                 .start  = INT_CPU2_PMU_INTR,
1305                 .end    = INT_CPU2_PMU_INTR,
1306                 .flags  = IORESOURCE_IRQ,
1307         },
1308         [3] = {
1309                 .start  = INT_CPU3_PMU_INTR,
1310                 .end    = INT_CPU3_PMU_INTR,
1311                 .flags  = IORESOURCE_IRQ,
1312         },
1313 #endif
1314 };
1315
1316 struct platform_device tegra_pmu_device = {
1317         .name           = "arm-pmu",
1318         .id             = -1,
1319         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
1320         .resource       = tegra_pmu_resources,
1321 };
1322
1323 static struct resource tegra_uarta_resources[] = {
1324         [0] = {
1325                 .start  = TEGRA_UARTA_BASE,
1326                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
1327                 .flags  = IORESOURCE_MEM,
1328         },
1329         [1] = {
1330                 .start  = INT_UARTA,
1331                 .end    = INT_UARTA,
1332                 .flags  = IORESOURCE_IRQ,
1333         },
1334 };
1335
1336 static struct resource tegra_uartb_resources[] = {
1337         [0] = {
1338                 .start  = TEGRA_UARTB_BASE,
1339                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
1340                 .flags  = IORESOURCE_MEM,
1341         },
1342         [1] = {
1343                 .start  = INT_UARTB,
1344                 .end    = INT_UARTB,
1345                 .flags  = IORESOURCE_IRQ,
1346         },
1347 };
1348
1349 static struct resource tegra_uartc_resources[] = {
1350         [0] = {
1351                 .start  = TEGRA_UARTC_BASE,
1352                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
1353                 .flags  = IORESOURCE_MEM,
1354         },
1355         [1] = {
1356                 .start  = INT_UARTC,
1357                 .end    = INT_UARTC,
1358                 .flags  = IORESOURCE_IRQ,
1359         },
1360 };
1361
1362 static struct resource tegra_uartd_resources[] = {
1363         [0] = {
1364                 .start  = TEGRA_UARTD_BASE,
1365                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
1366                 .flags  = IORESOURCE_MEM,
1367         },
1368         [1] = {
1369                 .start  = INT_UARTD,
1370                 .end    = INT_UARTD,
1371                 .flags  = IORESOURCE_IRQ,
1372         },
1373 };
1374
1375 static struct resource tegra_uarte_resources[] = {
1376         [0] = {
1377                 .start  = TEGRA_UARTE_BASE,
1378                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
1379                 .flags  = IORESOURCE_MEM,
1380         },
1381         [1] = {
1382                 .start  = INT_UARTE,
1383                 .end    = INT_UARTE,
1384                 .flags  = IORESOURCE_IRQ,
1385         },
1386 };
1387
1388 #define TEGRA_UART_NAME "serial-tegra"
1389
1390 struct platform_device tegra_uarta_device = {
1391         .name   = TEGRA_UART_NAME,
1392         .id     = 0,
1393         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
1394         .resource       = tegra_uarta_resources,
1395         .dev    = {
1396                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1397         },
1398 };
1399
1400 struct platform_device tegra_uartb_device = {
1401         .name   = TEGRA_UART_NAME,
1402         .id     = 1,
1403         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
1404         .resource       = tegra_uartb_resources,
1405         .dev    = {
1406                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1407         },
1408 };
1409
1410 struct platform_device tegra_uartc_device = {
1411         .name   = TEGRA_UART_NAME,
1412         .id     = 2,
1413         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
1414         .resource       = tegra_uartc_resources,
1415         .dev    = {
1416                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1417         },
1418 };
1419
1420 struct platform_device tegra_uartd_device = {
1421         .name   = TEGRA_UART_NAME,
1422         .id     = 3,
1423         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
1424         .resource       = tegra_uartd_resources,
1425         .dev    = {
1426                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1427         },
1428 };
1429
1430 struct platform_device tegra_uarte_device = {
1431         .name   = "tegra_uart",
1432         .id     = 4,
1433         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
1434         .resource       = tegra_uarte_resources,
1435         .dev    = {
1436                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1437         },
1438 };
1439
1440 static struct plat_serial8250_port debug_uarta_platform_data[] = {
1441         {
1442                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
1443                 .mapbase        = TEGRA_UARTA_BASE,
1444                 .irq            = INT_UARTA,
1445                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1446                 .type           = PORT_TEGRA,
1447                 .iotype         = UPIO_MEM,
1448                 .regshift       = 2,
1449         },
1450         {
1451                 .flags          = 0,
1452         },
1453 };
1454
1455 static struct plat_serial8250_port debug_uartb_platform_data[] = {
1456         {
1457                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
1458                 .mapbase        = TEGRA_UARTB_BASE,
1459                 .irq            = INT_UARTB,
1460                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1461                 .type           = PORT_TEGRA,
1462                 .iotype         = UPIO_MEM,
1463                 .regshift       = 2,
1464         },
1465         {
1466                 .flags          = 0,
1467         },
1468 };
1469
1470 static struct plat_serial8250_port debug_uartc_platform_data[] = {
1471         {
1472                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
1473                 .mapbase        = TEGRA_UARTC_BASE,
1474                 .irq            = INT_UARTC,
1475                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1476                 .type           = PORT_TEGRA,
1477                 .iotype         = UPIO_MEM,
1478                 .regshift       = 2,
1479         },
1480         {
1481                 .flags          = 0,
1482         },
1483 };
1484
1485 static struct plat_serial8250_port debug_uartd_platform_data[] = {
1486         {
1487                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
1488                 .mapbase        = TEGRA_UARTD_BASE,
1489                 .irq            = INT_UARTD,
1490                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1491                 .type           = PORT_TEGRA,
1492                 .iotype         = UPIO_MEM,
1493                 .regshift       = 2,
1494         },
1495         {
1496                 .flags          = 0,
1497         },
1498 };
1499
1500 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1501 static struct plat_serial8250_port debug_uarte_platform_data[] = {
1502         {
1503                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
1504                 .mapbase        = TEGRA_UARTE_BASE,
1505                 .irq            = INT_UARTE,
1506                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1507                 .type           = PORT_TEGRA,
1508                 .iotype         = UPIO_MEM,
1509                 .regshift       = 2,
1510         },
1511         {
1512                 .flags          = 0,
1513         },
1514 };
1515 #endif
1516
1517 struct platform_device debug_uarta_device = {
1518         .name = "serial8250",
1519         .id = PLAT8250_DEV_PLATFORM,
1520         .dev = {
1521                 .platform_data = debug_uarta_platform_data,
1522         },
1523 };
1524
1525 struct platform_device debug_uartb_device = {
1526         .name = "serial8250",
1527         .id = PLAT8250_DEV_PLATFORM,
1528         .dev = {
1529                 .platform_data = debug_uartb_platform_data,
1530         },
1531 };
1532
1533 struct platform_device debug_uartc_device = {
1534         .name = "serial8250",
1535         .id = PLAT8250_DEV_PLATFORM,
1536         .dev = {
1537                 .platform_data = debug_uartc_platform_data,
1538         },
1539 };
1540
1541 struct platform_device debug_uartd_device = {
1542         .name = "serial8250",
1543         .id = PLAT8250_DEV_PLATFORM,
1544         .dev = {
1545                 .platform_data = debug_uartd_platform_data,
1546         },
1547 };
1548
1549 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1550 struct platform_device debug_uarte_device = {
1551         .name = "serial8250",
1552         .id = PLAT8250_DEV_PLATFORM,
1553         .dev = {
1554                 .platform_data = debug_uarte_platform_data,
1555         },
1556 };
1557 #endif
1558
1559 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1560 static struct resource i2s_resource1[] = {
1561         [0] = {
1562                 .start  = INT_I2S1,
1563                 .end    = INT_I2S1,
1564                 .flags  = IORESOURCE_IRQ
1565         },
1566         [1] = {
1567                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1568                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1569                 .flags  = IORESOURCE_DMA
1570         },
1571         [2] = {
1572                 .start  = TEGRA_I2S1_BASE,
1573                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1574                 .flags  = IORESOURCE_MEM
1575         }
1576 };
1577
1578 struct platform_device tegra_i2s_device1 = {
1579         .name           = "tegra20-i2s",
1580         .id             = 0,
1581         .resource       = i2s_resource1,
1582         .num_resources  = ARRAY_SIZE(i2s_resource1),
1583 };
1584
1585 static struct resource i2s_resource2[] = {
1586         [0] = {
1587                 .start  = INT_I2S2,
1588                 .end    = INT_I2S2,
1589                 .flags  = IORESOURCE_IRQ
1590         },
1591         [1] = {
1592                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1593                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1594                 .flags  = IORESOURCE_DMA
1595         },
1596         [2] = {
1597                 .start  = TEGRA_I2S2_BASE,
1598                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1599                 .flags  = IORESOURCE_MEM
1600         }
1601 };
1602
1603 struct platform_device tegra_i2s_device2 = {
1604         .name           = "tegra20-i2s",
1605         .id             = 1,
1606         .resource       = i2s_resource2,
1607         .num_resources  = ARRAY_SIZE(i2s_resource2),
1608 };
1609 #else
1610 static struct resource i2s_resource0[] = {
1611         [0] = {
1612                 .start  = TEGRA_I2S0_BASE,
1613                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1614                 .flags  = IORESOURCE_MEM
1615         }
1616 };
1617
1618 struct platform_device tegra_i2s_device0 = {
1619         .name           = "tegra30-i2s",
1620         .id             = 0,
1621         .resource       = i2s_resource0,
1622         .num_resources  = ARRAY_SIZE(i2s_resource0),
1623 };
1624
1625 static struct resource i2s_resource1[] = {
1626         [0] = {
1627                 .start  = TEGRA_I2S1_BASE,
1628                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1629                 .flags  = IORESOURCE_MEM
1630         }
1631 };
1632
1633 struct platform_device tegra_i2s_device1 = {
1634         .name           = "tegra30-i2s",
1635         .id             = 1,
1636         .resource       = i2s_resource1,
1637         .num_resources  = ARRAY_SIZE(i2s_resource1),
1638 };
1639
1640 static struct resource i2s_resource2[] = {
1641         [0] = {
1642                 .start  = TEGRA_I2S2_BASE,
1643                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1644                 .flags  = IORESOURCE_MEM
1645         }
1646 };
1647
1648 struct platform_device tegra_i2s_device2 = {
1649         .name           = "tegra30-i2s",
1650         .id             = 2,
1651         .resource       = i2s_resource2,
1652         .num_resources  = ARRAY_SIZE(i2s_resource2),
1653 };
1654
1655 static struct resource i2s_resource3[] = {
1656         [0] = {
1657                 .start  = TEGRA_I2S3_BASE,
1658                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1659                 .flags  = IORESOURCE_MEM
1660         }
1661 };
1662
1663 struct platform_device tegra_i2s_device3 = {
1664         .name           = "tegra30-i2s",
1665         .id             = 3,
1666         .resource       = i2s_resource3,
1667         .num_resources  = ARRAY_SIZE(i2s_resource3),
1668 };
1669
1670 static struct resource i2s_resource4[] = {
1671         [0] = {
1672                 .start  = TEGRA_I2S4_BASE,
1673                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1674                 .flags  = IORESOURCE_MEM
1675         }
1676 };
1677
1678 struct platform_device tegra_i2s_device4 = {
1679         .name           = "tegra30-i2s",
1680         .id             = 4,
1681         .resource       = i2s_resource4,
1682         .num_resources  = ARRAY_SIZE(i2s_resource4),
1683 };
1684 #endif
1685
1686 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1687 static struct resource spdif_resource[] = {
1688         [0] = {
1689                 .start  = INT_SPDIF,
1690                 .end    = INT_SPDIF,
1691                 .flags  = IORESOURCE_IRQ
1692         },
1693         [1] = {
1694                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1695                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1696                 .flags  = IORESOURCE_DMA
1697         },
1698         [2] = {
1699                 .start  = TEGRA_SPDIF_BASE,
1700                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1701                 .flags  = IORESOURCE_MEM
1702         }
1703 };
1704
1705 struct platform_device tegra_spdif_device = {
1706         .name           = "tegra20-spdif",
1707         .id             = -1,
1708         .resource       = spdif_resource,
1709         .num_resources  = ARRAY_SIZE(spdif_resource),
1710 };
1711 #else
1712 static struct resource spdif_resource[] = {
1713         [0] = {
1714                 .start  = TEGRA_SPDIF_BASE,
1715                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1716                 .flags  = IORESOURCE_MEM
1717         }
1718 };
1719
1720 struct platform_device tegra_spdif_device = {
1721         .name           = "tegra30-spdif",
1722         .id             = -1,
1723         .resource       = spdif_resource,
1724         .num_resources  = ARRAY_SIZE(spdif_resource),
1725 };
1726 #endif
1727
1728 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1729 static struct resource ahub_resource[] = {
1730         [0] = {
1731                 .start  = TEGRA_APBIF0_BASE,
1732                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1733                 .flags  = IORESOURCE_MEM
1734         },
1735         [1] = {
1736                 .start  = TEGRA_AHUB_BASE,
1737                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1738                 .flags  = IORESOURCE_MEM
1739         }
1740 };
1741
1742 struct platform_device tegra_ahub_device = {
1743         .name   = "tegra30-ahub",
1744         .id     = -1,
1745         .resource       = ahub_resource,
1746         .num_resources  = ARRAY_SIZE(ahub_resource),
1747 };
1748
1749 static struct resource dam_resource0[] = {
1750         [0] = {
1751                 .start = TEGRA_DAM0_BASE,
1752                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1753                 .flags = IORESOURCE_MEM
1754         }
1755 };
1756
1757 struct platform_device tegra_dam_device0 = {
1758         .name = "tegra30-dam",
1759         .id = 0,
1760         .resource      = dam_resource0,
1761         .num_resources = ARRAY_SIZE(dam_resource0),
1762 };
1763
1764 static struct resource dam_resource1[] = {
1765         [0] = {
1766                 .start = TEGRA_DAM1_BASE,
1767                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1768                 .flags = IORESOURCE_MEM
1769         }
1770 };
1771
1772 struct platform_device tegra_dam_device1 = {
1773         .name = "tegra30-dam",
1774         .id = 1,
1775         .resource      = dam_resource1,
1776         .num_resources = ARRAY_SIZE(dam_resource1),
1777 };
1778
1779 static struct resource dam_resource2[] = {
1780         [0] = {
1781                 .start = TEGRA_DAM2_BASE,
1782                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1783                 .flags = IORESOURCE_MEM
1784         }
1785 };
1786
1787 struct platform_device tegra_dam_device2 = {
1788         .name = "tegra30-dam",
1789         .id = 2,
1790         .resource      = dam_resource2,
1791         .num_resources = ARRAY_SIZE(dam_resource2),
1792 };
1793
1794 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1795 static struct resource hda_platform_resources[] = {
1796         [0] = {
1797                 .start  = TEGRA_HDA_BASE,
1798                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1799                 .flags  = IORESOURCE_MEM
1800         },
1801         [1] = {
1802                 .start  = INT_HDA,
1803                 .end    = INT_HDA,
1804                 .flags  = IORESOURCE_IRQ
1805         },
1806 };
1807
1808 struct platform_device tegra_hda_device = {
1809         .name           = "tegra30-hda",
1810         .id             = -1,
1811         .dev = {
1812                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1813                 .dma_mask               = &tegra_hda_dma_mask,
1814         },
1815         .resource       = hda_platform_resources,
1816         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1817 };
1818 #endif
1819
1820 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1821 static struct resource dmic_resource0[] = {
1822         [0] = {
1823                 .start = TEGRA_DMIC0_BASE,
1824                 .end   = TEGRA_DMIC0_BASE + TEGRA_DMIC0_SIZE - 1,
1825                 .flags = IORESOURCE_MEM
1826         }
1827 };
1828
1829 struct platform_device tegra_dmic_device0 = {
1830         .name = "tegra-dmic",
1831         .id = 0,
1832         .resource      = dmic_resource0,
1833         .num_resources = ARRAY_SIZE(dmic_resource0),
1834 };
1835
1836 static struct resource dmic_resource1[] = {
1837         [0] = {
1838                 .start = TEGRA_DMIC1_BASE,
1839                 .end   = TEGRA_DMIC1_BASE + TEGRA_DMIC1_SIZE - 1,
1840                 .flags = IORESOURCE_MEM
1841         }
1842 };
1843
1844 struct platform_device tegra_dmic_device1 = {
1845         .name = "tegra-dmic",
1846         .id = 1,
1847         .resource      = dmic_resource1,
1848         .num_resources = ARRAY_SIZE(dmic_resource1),
1849 };
1850 #endif
1851
1852 struct platform_device spdif_dit_device = {
1853         .name = "spdif-dit",
1854         .id = 0,
1855 };
1856
1857 struct platform_device bluetooth_dit_device = {
1858         .name = "spdif-dit",
1859         .id = 1,
1860 };
1861
1862 struct platform_device baseband_dit_device = {
1863         .name = "spdif-dit",
1864         .id = 2,
1865 };
1866
1867 struct platform_device tegra_tdm_pcm_device = {
1868         .name = "tegra-tdm-pcm-audio",
1869         .id = -1,
1870 };
1871
1872 static struct resource w1_resources[] = {
1873         [0] = {
1874                 .start = INT_OWR,
1875                 .end   = INT_OWR,
1876                 .flags = IORESOURCE_IRQ
1877         },
1878         [1] = {
1879                 .start = TEGRA_OWR_BASE,
1880                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1881                 .flags = IORESOURCE_MEM
1882         }
1883 };
1884
1885 struct platform_device tegra_w1_device = {
1886         .name          = "tegra_w1",
1887         .id            = -1,
1888         .resource      = w1_resources,
1889         .num_resources = ARRAY_SIZE(w1_resources),
1890 };
1891
1892 static struct resource tegra_udc_resources[] = {
1893         [0] = {
1894                 .start  = TEGRA_USB_BASE,
1895                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1896                 .flags  = IORESOURCE_MEM,
1897         },
1898         [1] = {
1899                 .start  = INT_USB,
1900                 .end    = INT_USB,
1901                 .flags  = IORESOURCE_IRQ,
1902         },
1903 };
1904
1905 static u64 tegra_udc_dmamask = DMA_BIT_MASK(64);
1906
1907 struct platform_device tegra_udc_device = {
1908         .name   = "tegra-udc",
1909         .id     = 0,
1910         .dev    = {
1911                 .dma_mask       = &tegra_udc_dmamask,
1912                 .coherent_dma_mask = DMA_BIT_MASK(64),
1913         },
1914         .resource = tegra_udc_resources,
1915         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1916 };
1917
1918 static struct resource tegra_otg_resources[] = {
1919         [0] = {
1920                 .start  = TEGRA_USB_BASE,
1921                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1922                 .flags  = IORESOURCE_MEM,
1923         },
1924         [1] = {
1925                 .start  = INT_USB,
1926                 .end    = INT_USB,
1927                 .flags  = IORESOURCE_IRQ,
1928         },
1929 };
1930
1931 struct platform_device tegra_otg_device = {
1932         .name           = "tegra-otg",
1933         .id             = -1,
1934         .resource       = tegra_otg_resources,
1935         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1936 };
1937
1938 #ifdef CONFIG_SATA_AHCI_TEGRA
1939 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1940
1941 static struct resource tegra_sata_resources[] = {
1942         [0] = {
1943                 .start = TEGRA_SATA_BAR5_BASE,
1944                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1945                 .flags = IORESOURCE_MEM,
1946         },
1947         [1] = {
1948                 .start = TEGRA_SATA_CONFIG_BASE,
1949                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1950                 .flags = IORESOURCE_MEM,
1951         },
1952         [2] = {
1953                 .start = INT_SATA_CTL,
1954                 .end = INT_SATA_CTL,
1955                 .flags = IORESOURCE_IRQ,
1956         },
1957 };
1958
1959 struct platform_device tegra_sata_device = {
1960         .name   = "tegra-sata",
1961         .id     = 0,
1962         .dev    = {
1963                 .platform_data = 0,
1964                 .coherent_dma_mask = DMA_BIT_MASK(32),
1965                 .dma_mask = &tegra_sata_dma_mask,
1966         },
1967         .resource = tegra_sata_resources,
1968         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1969 };
1970 #endif
1971
1972 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1973 static struct resource das_resource[] = {
1974         [0] = {
1975                 .start  = TEGRA_APB_MISC_DAS_BASE,
1976                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1977                 .flags  = IORESOURCE_MEM
1978         }
1979 };
1980
1981 struct platform_device tegra_das_device = {
1982         .name           = "tegra20-das",
1983         .id             = -1,
1984         .resource       = das_resource,
1985         .num_resources  = ARRAY_SIZE(das_resource),
1986 };
1987 #endif
1988
1989 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1990 static struct resource tegra_gart_resources[] = {
1991         [0] = {
1992                 .name   = "mc",
1993                 .flags  = IORESOURCE_MEM,
1994                 .start  = TEGRA_MC_BASE,
1995                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1996         },
1997         [1] = {
1998                 .name   = "gart",
1999                 .flags  = IORESOURCE_MEM,
2000                 .start  = TEGRA_GART_BASE,
2001                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
2002         }
2003 };
2004
2005 struct platform_device tegra_gart_device = {
2006         .name           = "tegra_gart",
2007         .id             = -1,
2008         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
2009         .resource       = tegra_gart_resources
2010 };
2011 #endif
2012
2013 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
2014 static struct resource tegra_smmu_resources[] = {
2015         {
2016                 .name   = "mc",
2017                 .flags  = IORESOURCE_MEM,
2018                 .start  = TEGRA_MC_BASE,
2019                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
2020         },
2021         {
2022                 .name   = "ahbarb",
2023                 .flags  = IORESOURCE_MEM,
2024                 .start  = TEGRA_AHB_ARB_BASE,
2025                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
2026         },
2027 };
2028
2029 struct platform_device tegra_smmu_device = {
2030         .name           = "tegra_smmu",
2031         .id             = -1,
2032         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
2033         .resource       = tegra_smmu_resources
2034 };
2035
2036 static struct resource tegra_smmu[] = {
2037         [0] = {
2038                 .start  = TEGRA_SMMU_BASE,
2039                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
2040         },
2041 };
2042
2043 struct resource *tegra_smmu_window(int wnum)
2044 {
2045         return &tegra_smmu[wnum];
2046 }
2047
2048 int tegra_smmu_window_count(void)
2049 {
2050         return ARRAY_SIZE(tegra_smmu);
2051 }
2052
2053 struct swgid_fixup {
2054         const char * const name;
2055         u64 swgids;
2056 };
2057
2058 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2059 #define DUMMY_DEV_NAME "dummy_dev"
2060 #define DUMMY_DEV_MAX_NAME_SIZE 100
2061 static char dummy_name[DUMMY_DEV_MAX_NAME_SIZE] = DUMMY_DEV_NAME;
2062 #endif
2063
2064 /*
2065  * FIXME: They should have a DT entry with swgroup IDs.
2066  */
2067 struct swgid_fixup tegra_swgid_fixup[] = {
2068         { .name = "540c0000.epp",       .swgids = SWGID(EPP), },
2069         { .name = "epp",        .swgids = SWGID(EPP), },
2070         { .name = "54200000.dc",        .swgids = SWGID(DC), },
2071         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
2072         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
2073         { .name = "gr2d",       .swgids = SWGID(G2), },
2074         { .name = "gr3d",       .swgids = SWGID(NV) | SWGID(NV2), },
2075         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |      \
2076           SWGID(EPP) | SWGID(HDA), },
2077         { .name = "isp",        .swgids = SWGID(ISP), },
2078         { .name = "max77660",   .swgids = SWGID(PPCS), },
2079         { .name = "max8831",    .swgids = SWGID(PPCS), },
2080         { .name = "msenc",      .swgids = SWGID(MSENC), },
2081         { .name = "mpe",        .swgids = SWGID(MPE), },
2082         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
2083         { .name = "nvavp",      .swgids = SWGID(AVPC), },
2084         { .name = "sdhci-tegra",        .swgids = SWGID(PPCS), },
2085         { .name = "serial8250", .swgids = SWGID(PPCS), },
2086         { .name = "serial-tegra",      .swgids = SWGID(PPCS), },
2087         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS), },
2088         { .name = "spdif-dit",  .swgids = SWGID(PPCS), },
2089         { .name = "tegra11-se", .swgids = SWGID(PPCS), },
2090         { .name = "tegra11-spi",        .swgids = SWGID(PPCS), },
2091         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS), },
2092         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS), },
2093         { .name = "tegra30-dam",        .swgids = SWGID(PPCS), },
2094         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
2095         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS), },
2096         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS), },
2097         { .name = "tegradc",    .swgids = SWGID(DC) | SWGID(DCB), },
2098         { .name = "tegra_bb",   .swgids = SWGID(PPCS), },
2099         { .name = "tegra_dma",  .swgids = SWGID(PPCS), },
2100         { .name = "tegra-ehci", .swgids = SWGID(PPCS), },
2101         { .name = "tegra-fuse", .swgids = SWGID(PPCS), },
2102         { .name = "tegra-i2c",  .swgids = SWGID(PPCS), },
2103         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
2104         { .name = "tegra-otg",  .swgids = SWGID(PPCS), },
2105         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS), },
2106         { .name = "tegra-rtc",  .swgids = SWGID(PPCS), },
2107         { .name = "tegra-sata", .swgids = SWGID(SATA), },
2108         { .name = "tegra-se",   .swgids = SWGID(PPCS), },
2109         { .name = "tegra-snd",  .swgids = SWGID(PPCS), },
2110         { .name = "tegra-tzram",        .swgids = SWGID(VDE), },
2111         { .name = "tegra_uart", .swgids = SWGID(PPCS), },
2112         { .name = "tegra-udc",  .swgids = SWGID(PPCS), },
2113         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS), },
2114         { .name = "tsec",       .swgids = SWGID(TSEC), },
2115         { .name = "vi", .swgids = SWGID(VI), },
2116         { .name = "therm_est",  .swgids = SWGID(PPCS), },
2117 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2118         { .name = dummy_name,   .swgids = SWGID(PPCS) },
2119 #endif
2120         {},
2121 };
2122
2123 u64 tegra_smmu_fixup_swgids(struct device *dev)
2124 {
2125         const char *s;
2126         struct swgid_fixup *table = tegra_swgid_fixup;
2127
2128         while ((s = table->name) != NULL) {
2129                 if (!strncmp(s, dev_name(dev), strlen(s)))
2130                         return table->swgids;
2131                 table++;
2132         }
2133
2134         return 0;
2135 }
2136
2137 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
2138
2139 /*
2140  * ASID[0] for the system default
2141  * ASID[1] for PPCS, which has SDMMC
2142  * ASID[3][4] open for drivers, first come, first served.
2143  */
2144 enum {
2145         SYSTEM_DEFAULT,
2146         SYSTEM_PROTECTED,
2147 };
2148
2149 static struct dma_iommu_mapping *smmu_default_map[2];
2150
2151 static void tegra_smmu_map_init(struct platform_device *pdev)
2152 {
2153         int i;
2154
2155         for (i = 0; i < ARRAY_SIZE(smmu_default_map); i++) {
2156                 struct dma_iommu_mapping *map;
2157                 int order = 0;
2158
2159                 if (IS_ENABLED(CONFIG_TEGRA_ERRATA_1053704))
2160                         order = get_order(SZ_16K);
2161
2162                 map = arm_iommu_create_mapping(&platform_bus_type,
2163                                                TEGRA_IOMMU_BASE,
2164                                                TEGRA_IOMMU_SIZE, order);
2165                 if (IS_ERR(map))
2166                         dev_err(&pdev->dev,
2167                                 "Failed create IOVA map for ASID[%d]\n", i);
2168
2169                 smmu_default_map[i] = map;
2170         }
2171 }
2172
2173 void tegra_smmu_map_misc_device(struct device *dev)
2174 {
2175         struct dma_iommu_mapping *map = smmu_default_map[SYSTEM_PROTECTED];
2176         if (!strncmp(dummy_name, DUMMY_DEV_NAME, strlen(dummy_name))) {
2177                 strncpy(dummy_name, dev_name(dev),
2178                         DUMMY_DEV_MAX_NAME_SIZE);
2179                 arm_iommu_attach_device(dev, map);
2180                 dev_info(dev, "Mapped the misc device\n");
2181                 return;
2182         }
2183         dev_err(dev, "Can't Map device\n");
2184 }
2185 EXPORT_SYMBOL(tegra_smmu_map_misc_device);
2186
2187 void tegra_smmu_unmap_misc_device(struct device *dev)
2188 {
2189         if (!strncmp(dummy_name, dev_name(dev), strlen(dummy_name))) {
2190                 arm_iommu_detach_device(dev);
2191                 strncpy(dummy_name, DUMMY_DEV_NAME,
2192                         DUMMY_DEV_MAX_NAME_SIZE);
2193                 dev_info(dev, "Un-mapped the misc device\n");
2194                 return;
2195         }
2196         dev_err(dev, "Can't Unmap device\n");
2197 }
2198 EXPORT_SYMBOL(tegra_smmu_unmap_misc_device);
2199
2200 struct dma_iommu_mapping *tegra_smmu_get_map(struct device *dev, u64 swgids)
2201 {
2202         if (!swgids)
2203                 swgids = tegra_smmu_fixup_swgids(dev);
2204
2205         if (!swgids)
2206                 return NULL;
2207
2208         if (swgids & SWGID(PPCS))
2209                 return smmu_default_map[SYSTEM_PROTECTED];
2210
2211         return smmu_default_map[SYSTEM_DEFAULT];
2212 }
2213 #else
2214 static inline void tegra_smmu_map_init(struct platform_device *pdev)
2215 {
2216 }
2217 #endif
2218
2219 static int __init tegra_smmu_init(void)
2220 {
2221         platform_device_register(&tegra_smmu_device);
2222         tegra_smmu_map_init(&tegra_smmu_device);
2223         return 0;
2224 }
2225 postcore_initcall(tegra_smmu_init);
2226 #endif
2227
2228 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
2229 #define CLK_RESET_RST_SOURCE    0x0
2230 static struct resource tegra_wdt_resources[] = {
2231         [0] = {
2232                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
2233                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
2234                 .flags  = IORESOURCE_MEM,
2235         },
2236         [1] = {
2237                 .start  = TEGRA_TMR1_BASE,
2238                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
2239                 .flags  = IORESOURCE_MEM,
2240         },
2241         [2] = {
2242                 .start  = INT_TMR1,
2243                 .end    = INT_TMR1,
2244                 .flags  = IORESOURCE_IRQ,
2245         },
2246 };
2247
2248 struct platform_device tegra_wdt_device = {
2249         .name           = "tegra_wdt",
2250         .id             = -1,
2251         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
2252         .resource       = tegra_wdt_resources,
2253 };
2254 #else
2255 static struct resource tegra_wdt0_resources[] = {
2256         [0] = {
2257                 .start  = TEGRA_WDT0_BASE,
2258                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
2259                 .flags  = IORESOURCE_MEM,
2260         },
2261         [1] = {
2262                 .start  = TEGRA_TMR7_BASE,
2263                 .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
2264                 .flags  = IORESOURCE_MEM,
2265         },
2266         [2] = {
2267                 .start  = INT_WDT_CPU,
2268                 .end    = INT_WDT_CPU,
2269                 .flags  = IORESOURCE_IRQ,
2270         },
2271 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
2272         [3] = {
2273                 .start  = TEGRA_QUATERNARY_ICTLR_BASE,
2274                 .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
2275                                 TEGRA_QUATERNARY_ICTLR_SIZE -1,
2276                 .flags  = IORESOURCE_MEM,
2277         },
2278 #endif
2279 };
2280
2281 struct platform_device tegra_wdt0_device = {
2282         .name           = "tegra_wdt",
2283         .id             = 0,
2284         .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
2285         .resource       = tegra_wdt0_resources,
2286 };
2287
2288 #endif
2289
2290 static struct resource tegra_pwfm_resource = {
2291         .start  = TEGRA_PWFM_BASE,
2292         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
2293         .flags  = IORESOURCE_MEM,
2294 };
2295
2296 struct platform_device tegra_pwfm_device = {
2297         .name           = "tegra-pwm",
2298         .id             = -1,
2299         .num_resources  = 1,
2300         .resource       = &tegra_pwfm_resource,
2301 };
2302
2303 static struct tegra_avp_platform_data tegra_avp_pdata = {
2304 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2305         .emc_clk_rate = ULONG_MAX,
2306 #else
2307         .emc_clk_rate = 200000000,
2308 #endif
2309 };
2310
2311 struct resource tegra_nvavp_resources[] = {
2312         [0] = {
2313                 .start  = INT_SHR_SEM_INBOX_IBF,
2314                 .end    = INT_SHR_SEM_INBOX_IBF,
2315                 .flags  = IORESOURCE_IRQ,
2316                 .name   = "mbox_from_nvavp_pending",
2317         },
2318 };
2319
2320 struct platform_device nvavp_device = {
2321         .name           = "nvavp",
2322         .id             = -1,
2323         .resource       = tegra_nvavp_resources,
2324         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
2325         .dev  = {
2326                 .coherent_dma_mask      = 0xffffffffULL,
2327                 .platform_data          = &tegra_avp_pdata,
2328         },
2329 };
2330
2331 static struct resource tegra_avp_resources[] = {
2332         [0] = {
2333                 .start  = INT_SHR_SEM_INBOX_IBF,
2334                 .end    = INT_SHR_SEM_INBOX_IBF,
2335                 .flags  = IORESOURCE_IRQ,
2336                 .name   = "mbox_from_avp_pending",
2337         },
2338 };
2339
2340 struct platform_device tegra_avp_device = {
2341         .name           = "tegra-avp",
2342         .id             = -1,
2343         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
2344         .resource       = tegra_avp_resources,
2345         .dev  = {
2346                 .coherent_dma_mask      = 0xffffffffULL,
2347                 .platform_data          = &tegra_avp_pdata,
2348         },
2349 };
2350
2351 static struct resource tegra_aes_resources[] = {
2352         {
2353                 .start  = TEGRA_VDE_BASE,
2354                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
2355                 .flags  = IORESOURCE_MEM,
2356         },
2357         {
2358                 .start  = TEGRA_BSEA_BASE,
2359                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
2360                 .flags  = IORESOURCE_MEM,
2361         },
2362         {
2363                 .start  = INT_VDE_BSE_V,
2364                 .end    = INT_VDE_BSE_V,
2365                 .flags  = IORESOURCE_IRQ,
2366         },
2367         {
2368                 .start  = INT_VDE_BSE_A,
2369                 .end    = INT_VDE_BSE_A,
2370                 .flags  = IORESOURCE_IRQ,
2371         },
2372 };
2373
2374 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
2375
2376 struct platform_device tegra_aes_device = {
2377         .name           = "tegra-aes",
2378         .id             = -1,
2379         .resource       = tegra_aes_resources,
2380         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
2381         .dev    = {
2382                 .dma_mask = &tegra_aes_dma_mask,
2383                 .coherent_dma_mask = DMA_BIT_MASK(32),
2384         },
2385 };
2386
2387 static struct resource tegra_kbc_resources[] = {
2388         [0] = {
2389                 .start = TEGRA_KBC_BASE,
2390                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
2391                 .flags = IORESOURCE_MEM,
2392         },
2393         [1] = {
2394                 .start = INT_KBC,
2395                 .end   = INT_KBC,
2396                 .flags = IORESOURCE_IRQ,
2397         },
2398 };
2399
2400 struct platform_device tegra_kbc_device = {
2401         .name = "tegra-kbc",
2402         .id = -1,
2403         .resource = tegra_kbc_resources,
2404         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
2405         .dev = {
2406                 .platform_data = 0,
2407         },
2408 };
2409
2410 #if defined(CONFIG_TEGRA_SKIN_THROTTLE)
2411 struct platform_device tegra_skin_therm_est_device = {
2412         .name   = "therm_est",
2413         .id     = -1,
2414         .num_resources  = 0,
2415         .dev = {
2416                 .platform_data = 0,
2417         },
2418 };
2419 #endif
2420
2421 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
2422 static struct resource tegra_tsensor_resources[]= {
2423         {
2424                 .start  = TEGRA_TSENSOR_BASE,
2425                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
2426                 .flags  = IORESOURCE_MEM,
2427         },
2428         {
2429                 .start  = INT_TSENSOR,
2430                 .end    = INT_TSENSOR,
2431                 .flags  = IORESOURCE_IRQ,
2432         },
2433         {
2434                 .start  = TEGRA_PMC_BASE + 0x1B0,
2435                 /* 2 pmc registers mapped */
2436                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
2437                 .flags  = IORESOURCE_MEM,
2438         },
2439 };
2440
2441 struct platform_device tegra_tsensor_device = {
2442         .name   = "tegra-tsensor",
2443         .id     = -1,
2444         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
2445         .resource       = tegra_tsensor_resources,
2446         .dev = {
2447                 .platform_data = 0,
2448         },
2449 };
2450 #endif
2451
2452 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2453 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
2454
2455 struct resource tegra_se_resources[] = {
2456         [0] = {
2457                 .start = TEGRA_SE_BASE,
2458                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
2459                 .flags = IORESOURCE_MEM,
2460         },
2461         [1] = {
2462                 .start  = TEGRA_PMC_BASE,
2463                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
2464                 .flags  = IORESOURCE_MEM,
2465         },
2466         [2] = {
2467                 .start = INT_SE,
2468                 .end = INT_SE,
2469                 .flags = IORESOURCE_IRQ,
2470         },
2471 };
2472
2473 struct platform_device tegra_se_device = {
2474         .name = "tegra-se",
2475         .id = -1,
2476         .dev = {
2477                 .coherent_dma_mask = DMA_BIT_MASK(32),
2478                 .dma_mask = &tegra_se_dma_mask,
2479         },
2480         .resource = tegra_se_resources,
2481         .num_resources = ARRAY_SIZE(tegra_se_resources),
2482 };
2483
2484 struct platform_device tegra11_se_device = {
2485         .name = "tegra11-se",
2486         .id = -1,
2487         .dev = {
2488                 .coherent_dma_mask = DMA_BIT_MASK(32),
2489                 .dma_mask = &tegra_se_dma_mask,
2490         },
2491         .resource = tegra_se_resources,
2492         .num_resources = ARRAY_SIZE(tegra_se_resources),
2493 };
2494 #endif
2495
2496 static struct resource tegra_disp1_resources[] = {
2497         {
2498                 .name   = "irq",
2499                 .start  = INT_DISPLAY_GENERAL,
2500                 .end    = INT_DISPLAY_GENERAL,
2501                 .flags  = IORESOURCE_IRQ,
2502         },
2503         {
2504                 .name   = "regs",
2505                 .start  = TEGRA_DISPLAY_BASE,
2506                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
2507                 .flags  = IORESOURCE_MEM,
2508         },
2509         {
2510                 .name   = "fbmem",
2511                 .start  = 0,
2512                 .end    = 0,
2513                 .flags  = IORESOURCE_MEM,
2514         },
2515         {
2516                 .name   = "dsi_regs",
2517                 .start  = TEGRA_DSI_BASE,
2518                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
2519                 .flags  = IORESOURCE_MEM,
2520         },
2521 };
2522
2523 struct platform_device tegra_disp1_device = {
2524         .name           = "tegradc",
2525         .id             = 0,
2526         .resource       = tegra_disp1_resources,
2527         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
2528 };
2529
2530 static struct resource tegra_disp2_resources[] = {
2531         {
2532                 .name   = "irq",
2533                 .start  = INT_DISPLAY_B_GENERAL,
2534                 .end    = INT_DISPLAY_B_GENERAL,
2535                 .flags  = IORESOURCE_IRQ,
2536         },
2537         {
2538                 .name   = "regs",
2539                 .start  = TEGRA_DISPLAY2_BASE,
2540                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
2541                 .flags  = IORESOURCE_MEM,
2542         },
2543         {
2544                 .name   = "fbmem",
2545                 .flags  = IORESOURCE_MEM,
2546                 .start  = 0,
2547                 .end    = 0,
2548         },
2549         {
2550                 .name   = "hdmi_regs",
2551                 .start  = TEGRA_HDMI_BASE,
2552                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
2553                 .flags  = IORESOURCE_MEM,
2554         },
2555 };
2556
2557 struct platform_device tegra_disp2_device = {
2558         .name           = "tegradc",
2559         .id             = 1,
2560         .resource       = tegra_disp2_resources,
2561         .num_resources  = ARRAY_SIZE(tegra_disp2_resources),
2562         .dev = {
2563                 .platform_data = 0,
2564         },
2565 };
2566
2567 struct platform_device tegra_nvmap_device = {
2568         .name   = "tegra-nvmap",
2569         .id     = -1,
2570 };
2571
2572 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2573 static struct resource tegra_cec_resources[] = {
2574         [0] = {
2575                 .start = TEGRA_CEC_BASE,
2576                 .end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
2577                 .flags = IORESOURCE_MEM,
2578         },
2579         [1] = {
2580                 .start = INT_CEC,
2581                 .end = INT_CEC,
2582                 .flags = IORESOURCE_IRQ,
2583         },
2584 };
2585
2586 struct platform_device tegra_cec_device = {
2587         .name = "tegra_cec",
2588         .id   = -1,
2589         .resource = tegra_cec_resources,
2590         .num_resources = ARRAY_SIZE(tegra_cec_resources),
2591 };
2592 #endif
2593
2594 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
2595 static struct resource cl_dvfs_resource[] = {
2596         [0] = {
2597                 .start  = TEGRA_CL_DVFS_BASE,
2598                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2599                 .flags  = IORESOURCE_MEM,
2600         }
2601 };
2602
2603 struct platform_device tegra_cl_dvfs_device = {
2604         .name           = "tegra_cl_dvfs",
2605         .id             = -1,
2606         .resource       = cl_dvfs_resource,
2607         .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
2608 };
2609 #endif
2610
2611 struct platform_device tegra_fuse_device = {
2612         .name   = "tegra-fuse",
2613         .id     = -1,
2614 };
2615
2616 void __init tegra_init_debug_uart_rate(void)
2617 {
2618         unsigned int uartclk;
2619         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
2620
2621         BUG_ON(IS_ERR(debug_uart_parent));
2622         uartclk = clk_get_rate(debug_uart_parent);
2623
2624         debug_uarta_platform_data[0].uartclk = uartclk;
2625         debug_uartb_platform_data[0].uartclk = uartclk;
2626         debug_uartc_platform_data[0].uartclk = uartclk;
2627         debug_uartd_platform_data[0].uartclk = uartclk;
2628 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2629         debug_uarte_platform_data[0].uartclk = uartclk;
2630 #endif
2631 }