18fbff4abeb746d221db006ff3c386b918e83bef
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/serial_8250.h>
26 #include <linux/i2c-tegra.h>
27 #include <linux/mipi-bif-tegra.h>
28 #include <linux/platform_data/tegra_usb.h>
29 #include <linux/tegra_avp.h>
30 #include <linux/nvhost.h>
31 #include <linux/clk.h>
32 #include <mach/irqs.h>
33 #include <linux/usb/tegra_usb_phy.h>
34 #include <mach/tegra_smmu.h>
35 #include <mach/tegra-swgid.h>
36
37 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
38 #include <asm/dma-iommu.h>
39 #endif
40
41 #include "gpio-names.h"
42 #include "iomap.h"
43 #include "devices.h"
44
45 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
46 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
47 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
48 #define TEGRA_DMA_REQ_SEL_SPI                   11
49 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
50
51 static struct resource emc_resource[] = {
52         [0] = {
53                 .start  = TEGRA_EMC_BASE,
54                 .end    = TEGRA_EMC_BASE + TEGRA_EMC_SIZE-1,
55                 .flags  = IORESOURCE_MEM,
56         }
57 };
58
59 struct platform_device tegra_emc_device = {
60         .name           = "tegra-emc",
61         .id             = -1,
62         .resource       = emc_resource,
63         .num_resources  = ARRAY_SIZE(emc_resource),
64 };
65
66 static struct resource gpio_resource[] = {
67         [0] = {
68                 .start  = TEGRA_GPIO_BASE,
69                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
70                 .flags  = IORESOURCE_MEM,
71         },
72         [1] = {
73                 .start  = INT_GPIO1,
74                 .end    = INT_GPIO1,
75                 .flags  = IORESOURCE_IRQ,
76         },
77         [2] = {
78                 .start  = INT_GPIO2,
79                 .end    = INT_GPIO2,
80                 .flags  = IORESOURCE_IRQ,
81         },
82         [3] = {
83                 .start  = INT_GPIO3,
84                 .end    = INT_GPIO3,
85                 .flags  = IORESOURCE_IRQ,
86         },
87         [4] = {
88                 .start  = INT_GPIO4,
89                 .end    = INT_GPIO4,
90                 .flags  = IORESOURCE_IRQ,
91         },
92         [5] = {
93                 .start  = INT_GPIO5,
94                 .end    = INT_GPIO5,
95                 .flags  = IORESOURCE_IRQ,
96         },
97         [6] = {
98                 .start  = INT_GPIO6,
99                 .end    = INT_GPIO6,
100                 .flags  = IORESOURCE_IRQ,
101         },
102         [7] = {
103                 .start  = INT_GPIO7,
104                 .end    = INT_GPIO7,
105                 .flags  = IORESOURCE_IRQ,
106         },
107 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
108         [8] = {
109                 .start  = INT_GPIO8,
110                 .end    = INT_GPIO8,
111                 .flags  = IORESOURCE_IRQ,
112         },
113 #endif
114 };
115
116 struct platform_device tegra_gpio_device = {
117         .name           = "tegra-gpio",
118         .id             = -1,
119         .resource       = gpio_resource,
120         .num_resources  = ARRAY_SIZE(gpio_resource),
121 };
122
123 static struct resource pinmux_resource[] = {
124 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
125         [0] = {
126                 /* Tri-state registers */
127                 .start  = TEGRA_APB_MISC_BASE + 0x14,
128                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
129                 .flags  = IORESOURCE_MEM,
130         },
131         [1] = {
132                 /* Mux registers */
133                 .start  = TEGRA_APB_MISC_BASE + 0x80,
134                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
135                 .flags  = IORESOURCE_MEM,
136         },
137         [2] = {
138                 /* Pull-up/down registers */
139                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
140                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
141                 .flags  = IORESOURCE_MEM,
142         },
143         [3] = {
144                 /* Pad control registers */
145                 .start  = TEGRA_APB_MISC_BASE + 0x868,
146                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
147                 .flags  = IORESOURCE_MEM,
148         },
149 #else
150         [0] = {
151                 /* Drive registers */
152                 .start  = TEGRA_APB_MISC_BASE + 0x868,
153                 .end    = TEGRA_APB_MISC_BASE + 0x938 + 3,
154                 .flags  = IORESOURCE_MEM,
155         },
156         [1] = {
157                 /* Mux registers */
158                 .start  = TEGRA_APB_MISC_BASE + 0x3000,
159 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
160                 .end    = TEGRA_APB_MISC_BASE + 0x3408 + 3,
161 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
162                 .end    = TEGRA_APB_MISC_BASE + 0x3514 + 3,
163 #else
164                 .end    = TEGRA_APB_MISC_BASE + 0x33e0 + 3,
165 #endif
166                 .flags  = IORESOURCE_MEM,
167         },
168 #endif
169 };
170
171 struct platform_device tegra_pinmux_device = {
172 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
173         .name           = "tegra30-pinmux-ctl",
174 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
175         .name           = "tegra20-pinmux-ctl",
176 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
177         .name           = "tegra11x-pinmux-ctl",
178 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
179         .name           = "tegra14x-pinmux",
180 #endif
181         .id             = -1,
182         .resource       = pinmux_resource,
183         .num_resources  = ARRAY_SIZE(pinmux_resource),
184 };
185
186 static struct resource i2c_resource1[] = {
187         [0] = {
188                 .start  = INT_I2C,
189                 .end    = INT_I2C,
190                 .flags  = IORESOURCE_IRQ,
191         },
192         [1] = {
193                 .start  = TEGRA_I2C_BASE,
194                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
195                 .flags  = IORESOURCE_MEM,
196         },
197 };
198
199 static struct resource i2c_resource2[] = {
200         [0] = {
201                 .start  = INT_I2C2,
202                 .end    = INT_I2C2,
203                 .flags  = IORESOURCE_IRQ,
204         },
205         [1] = {
206                 .start  = TEGRA_I2C2_BASE,
207                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
208                 .flags  = IORESOURCE_MEM,
209         },
210 };
211
212 static struct resource i2c_resource3[] = {
213         [0] = {
214                 .start  = INT_I2C3,
215                 .end    = INT_I2C3,
216                 .flags  = IORESOURCE_IRQ,
217         },
218         [1] = {
219                 .start  = TEGRA_I2C3_BASE,
220                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
221                 .flags  = IORESOURCE_MEM,
222         },
223 };
224
225 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
226 static struct resource i2c_resource4[] = {
227         [0] = {
228                 .start  = INT_DVC,
229                 .end    = INT_DVC,
230                 .flags  = IORESOURCE_IRQ,
231         },
232         [1] = {
233                 .start  = TEGRA_DVC_BASE,
234                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
235                 .flags  = IORESOURCE_MEM,
236         },
237 };
238
239 #else
240 static struct resource i2c_resource4[] = {
241         [0] = {
242                 .start  = INT_I2C4,
243                 .end    = INT_I2C4,
244                 .flags  = IORESOURCE_IRQ,
245         },
246         [1] = {
247                 .start  = TEGRA_I2C4_BASE,
248                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
249                 .flags  = IORESOURCE_MEM,
250         },
251 };
252
253 static struct resource i2c_resource5[] = {
254         [0] = {
255                 .start  = INT_I2C5,
256                 .end    = INT_I2C5,
257                 .flags  = IORESOURCE_IRQ,
258         },
259         [1] = {
260                 .start  = TEGRA_I2C5_BASE,
261                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
262                 .flags  = IORESOURCE_MEM,
263         },
264 };
265 #endif
266
267 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
268 static struct resource i2c_resource6[] = {
269         [0] = {
270                 .start  = INT_I2C6,
271                 .end    = INT_I2C6,
272                 .flags  = IORESOURCE_IRQ,
273         },
274         [1] = {
275                 .start  = TEGRA_I2C6_BASE,
276                 .end    = TEGRA_I2C6_BASE + TEGRA_I2C6_SIZE-1,
277                 .flags  = IORESOURCE_MEM,
278         },
279 };
280 #endif
281
282 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
283         .bus_clk_rate   = 400000,
284 };
285
286 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
287         .bus_clk_rate   = 400000,
288 };
289
290 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
291         .bus_clk_rate   = 400000,
292 };
293
294 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
295         .bus_clk_rate   = 400000,
296 };
297
298 struct platform_device tegra_i2c_device1 = {
299         .name           = "tegra-i2c",
300         .id             = 0,
301         .resource       = i2c_resource1,
302         .num_resources  = ARRAY_SIZE(i2c_resource1),
303         .dev = {
304                 .platform_data = &tegra_i2c1_platform_data,
305         },
306 };
307
308 struct platform_device tegra_i2c_device2 = {
309         .name           = "tegra-i2c",
310         .id             = 1,
311         .resource       = i2c_resource2,
312         .num_resources  = ARRAY_SIZE(i2c_resource2),
313         .dev = {
314                 .platform_data = &tegra_i2c2_platform_data,
315         },
316 };
317
318 struct platform_device tegra_i2c_device3 = {
319         .name           = "tegra-i2c",
320         .id             = 2,
321         .resource       = i2c_resource3,
322         .num_resources  = ARRAY_SIZE(i2c_resource3),
323         .dev = {
324                 .platform_data = &tegra_i2c3_platform_data,
325         },
326 };
327
328 struct platform_device tegra_i2c_device4 = {
329         .name           = "tegra-i2c",
330         .id             = 3,
331         .resource       = i2c_resource4,
332         .num_resources  = ARRAY_SIZE(i2c_resource4),
333         .dev = {
334                 .platform_data = &tegra_dvc_platform_data,
335         },
336 };
337
338 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
339 struct platform_device tegra_i2c_device5 = {
340         .name           = "tegra-i2c",
341         .id             = 4,
342         .resource       = i2c_resource5,
343         .num_resources  = ARRAY_SIZE(i2c_resource5),
344         .dev = {
345                 .platform_data = 0,
346         },
347 };
348 #endif
349
350 struct platform_device tegra11_i2c_device1 = {
351         .name           = "tegra11-i2c",
352         .id             = 0,
353         .resource       = i2c_resource1,
354         .num_resources  = ARRAY_SIZE(i2c_resource1),
355         .dev = {
356                 .platform_data = 0,
357         },
358 };
359
360 struct platform_device tegra11_i2c_device2 = {
361         .name           = "tegra11-i2c",
362         .id             = 1,
363         .resource       = i2c_resource2,
364         .num_resources  = ARRAY_SIZE(i2c_resource2),
365         .dev = {
366                 .platform_data = 0,
367         },
368 };
369
370 struct platform_device tegra11_i2c_device3 = {
371         .name           = "tegra11-i2c",
372         .id             = 2,
373         .resource       = i2c_resource3,
374         .num_resources  = ARRAY_SIZE(i2c_resource3),
375         .dev = {
376                 .platform_data = 0,
377         },
378 };
379
380 struct platform_device tegra11_i2c_device4 = {
381         .name           = "tegra11-i2c",
382         .id             = 3,
383         .resource       = i2c_resource4,
384         .num_resources  = ARRAY_SIZE(i2c_resource4),
385         .dev = {
386                 .platform_data = 0,
387         },
388 };
389
390 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
391 struct platform_device tegra11_i2c_device5 = {
392         .name           = "tegra11-i2c",
393         .id             = 4,
394         .resource       = i2c_resource5,
395         .num_resources  = ARRAY_SIZE(i2c_resource5),
396         .dev = {
397                 .platform_data = 0,
398         },
399 };
400 #endif
401
402 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
403
404 struct platform_device tegra14_i2c_device1 = {
405         .name           = "tegra14-i2c",
406         .id             = 0,
407         .resource       = i2c_resource1,
408         .num_resources  = ARRAY_SIZE(i2c_resource1),
409         .dev = {
410                 .platform_data = 0,
411         },
412 };
413
414 struct platform_device tegra14_i2c_device2 = {
415         .name           = "tegra14-i2c",
416         .id             = 1,
417         .resource       = i2c_resource2,
418         .num_resources  = ARRAY_SIZE(i2c_resource2),
419         .dev = {
420                 .platform_data = 0,
421         },
422 };
423
424 struct platform_device tegra14_i2c_device3 = {
425         .name           = "tegra14-i2c",
426         .id             = 2,
427         .resource       = i2c_resource3,
428         .num_resources  = ARRAY_SIZE(i2c_resource3),
429         .dev = {
430                 .platform_data = 0,
431         },
432 };
433
434 struct platform_device tegra14_i2c_device4 = {
435         .name           = "tegra14-i2c",
436         .id             = 3,
437         .resource       = i2c_resource4,
438         .num_resources  = ARRAY_SIZE(i2c_resource4),
439         .dev = {
440                 .platform_data = 0,
441         },
442 };
443
444 struct platform_device tegra14_i2c_device5 = {
445         .name           = "tegra14-i2c",
446         .id             = 4,
447         .resource       = i2c_resource5,
448         .num_resources  = ARRAY_SIZE(i2c_resource5),
449         .dev = {
450                 .platform_data = 0,
451         },
452 };
453
454 struct platform_device tegra14_i2c_device6 = {
455         .name           = "tegra14-i2c",
456         .id             = 5,
457         .resource       = i2c_resource6,
458         .num_resources  = ARRAY_SIZE(i2c_resource6),
459         .dev = {
460                 .platform_data = 0,
461         },
462 };
463
464 static struct tegra_mipi_bif_platform_data mipi_bif_pdata = {
465         .adapter_nr     = -1,
466         .tauBIF         = 2,
467         .bus_clk_rate   = 13,
468 };
469
470 static struct resource mipi_bif_resource[] = {
471         [0] = {
472                 .start  = INT_MIPI_BIF,
473                 .end    = INT_MIPI_BIF,
474                 .flags  = IORESOURCE_IRQ,
475         },
476         [1] = {
477                 .start  = TEGRA_MIPI_BIF_BASE,
478                 .end    = TEGRA_MIPI_BIF_BASE + TEGRA_MIPI_BIF_SIZE - 1,
479                 .flags  = IORESOURCE_MEM,
480         },
481 };
482
483 struct platform_device tegra_mipi_bif_device = {
484         .name           = "tegra-mipi-bif",
485         .id             = -1,
486         .resource       = mipi_bif_resource,
487         .num_resources  = ARRAY_SIZE(mipi_bif_resource),
488         .dev = {
489                 .platform_data = &mipi_bif_pdata,
490         },
491 };
492
493 #endif
494
495 static struct resource spi_resource1[] = {
496         [0] = {
497                 .start  = INT_SPI_1,
498                 .end    = INT_SPI_1,
499                 .flags  = IORESOURCE_IRQ,
500         },
501         [1] = {
502                 .start  = TEGRA_SPI1_BASE,
503                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
504                 .flags  = IORESOURCE_MEM,
505         },
506 };
507
508 static struct resource spi_resource2[] = {
509         [0] = {
510                 .start  = INT_SPI_2,
511                 .end    = INT_SPI_2,
512                 .flags  = IORESOURCE_IRQ,
513         },
514         [1] = {
515                 .start  = TEGRA_SPI2_BASE,
516                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
517                 .flags  = IORESOURCE_MEM,
518         },
519 };
520
521 static struct resource spi_resource3[] = {
522         [0] = {
523                 .start  = INT_SPI_3,
524                 .end    = INT_SPI_3,
525                 .flags  = IORESOURCE_IRQ,
526         },
527         [1] = {
528                 .start  = TEGRA_SPI3_BASE,
529                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
530                 .flags  = IORESOURCE_MEM,
531         },
532 };
533
534 static struct resource spi_resource4[] = {
535         [0] = {
536                 .start  = INT_SPI_4,
537                 .end    = INT_SPI_4,
538                 .flags  = IORESOURCE_IRQ,
539         },
540         [1] = {
541                 .start  = TEGRA_SPI4_BASE,
542                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
543                 .flags  = IORESOURCE_MEM,
544         },
545 };
546 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
547 static struct resource spi_resource5[] = {
548         [0] = {
549                 .start  = INT_SPI_5,
550                 .end    = INT_SPI_5,
551                 .flags  = IORESOURCE_IRQ,
552         },
553         [1] = {
554                 .start  = TEGRA_SPI5_BASE,
555                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
556                 .flags  = IORESOURCE_MEM,
557         },
558 };
559
560 static struct resource spi_resource6[] = {
561         [0] = {
562                 .start  = INT_SPI_6,
563                 .end    = INT_SPI_6,
564                 .flags  = IORESOURCE_IRQ,
565         },
566         [1] = {
567                 .start  = TEGRA_SPI6_BASE,
568                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
569                 .flags  = IORESOURCE_MEM,
570         },
571 };
572 #endif
573
574 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
575 static struct resource dtv_resource[] = {
576         [0] = {
577                 .start  = INT_DTV,
578                 .end    = INT_DTV,
579                 .flags  = IORESOURCE_IRQ,
580         },
581         [1] = {
582                 .start  = TEGRA_DTV_BASE,
583                 .end    = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
584                 .flags  = IORESOURCE_MEM,
585         },
586         [2] = {
587                 .start  = TEGRA_DMA_REQ_SEL_DTV,
588                 .end    = TEGRA_DMA_REQ_SEL_DTV,
589                 .flags  = IORESOURCE_DMA
590         },
591 };
592 #endif
593
594
595 struct platform_device tegra_spi_device1 = {
596         .name           = "spi_tegra",
597         .id             = 0,
598         .resource       = spi_resource1,
599         .num_resources  = ARRAY_SIZE(spi_resource1),
600         .dev            = {
601                 .coherent_dma_mask      = 0xffffffff,
602         },
603 };
604
605 struct platform_device tegra_spi_device2 = {
606         .name           = "spi_tegra",
607         .id             = 1,
608         .resource       = spi_resource2,
609         .num_resources  = ARRAY_SIZE(spi_resource2),
610         .dev            = {
611                 .coherent_dma_mask      = 0xffffffff,
612         },
613 };
614
615 struct platform_device tegra_spi_device3 = {
616         .name           = "spi_tegra",
617         .id             = 2,
618         .resource       = spi_resource3,
619         .num_resources  = ARRAY_SIZE(spi_resource3),
620         .dev            = {
621                 .coherent_dma_mask      = 0xffffffff,
622         },
623 };
624
625 struct platform_device tegra_spi_device4 = {
626         .name           = "spi_tegra",
627         .id             = 3,
628         .resource       = spi_resource4,
629         .num_resources  = ARRAY_SIZE(spi_resource4),
630         .dev            = {
631                 .coherent_dma_mask      = 0xffffffff,
632         },
633 };
634 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
635 struct platform_device tegra_spi_device5 = {
636         .name           = "spi_tegra",
637         .id             = 4,
638         .resource       = spi_resource5,
639         .num_resources  = ARRAY_SIZE(spi_resource5),
640         .dev  = {
641                 .coherent_dma_mask      = 0xffffffff,
642         },
643 };
644
645 struct platform_device tegra_spi_device6 = {
646         .name           = "spi_tegra",
647         .id             = 5,
648         .resource       = spi_resource6,
649         .num_resources  = ARRAY_SIZE(spi_resource6),
650         .dev  = {
651                 .coherent_dma_mask      = 0xffffffff,
652         },
653 };
654 #endif
655
656 struct platform_device tegra11_spi_device1 = {
657         .name           = "spi-tegra114",
658         .id             = 0,
659         .resource       = spi_resource1,
660         .num_resources  = ARRAY_SIZE(spi_resource1),
661         .dev            = {
662                 .coherent_dma_mask      = 0xffffffff,
663         },
664 };
665
666 struct platform_device tegra11_spi_device2 = {
667         .name           = "spi-tegra114",
668         .id             = 1,
669         .resource       = spi_resource2,
670         .num_resources  = ARRAY_SIZE(spi_resource2),
671         .dev            = {
672                 .coherent_dma_mask      = 0xffffffff,
673         },
674 };
675
676 struct platform_device tegra11_spi_device3 = {
677         .name           = "spi-tegra114",
678         .id             = 2,
679         .resource       = spi_resource3,
680         .num_resources  = ARRAY_SIZE(spi_resource3),
681         .dev            = {
682                 .coherent_dma_mask      = 0xffffffff,
683         },
684 };
685
686 struct platform_device tegra11_spi_device4 = {
687         .name           = "spi-tegra114",
688         .id             = 3,
689         .resource       = spi_resource4,
690         .num_resources  = ARRAY_SIZE(spi_resource4),
691         .dev            = {
692                 .coherent_dma_mask      = 0xffffffff,
693         },
694 };
695
696 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
697 struct platform_device tegra11_spi_device5 = {
698         .name           = "spi-tegra114",
699         .id             = 4,
700         .resource       = spi_resource5,
701         .num_resources  = ARRAY_SIZE(spi_resource5),
702         .dev  = {
703                 .coherent_dma_mask      = 0xffffffff,
704         },
705 };
706
707 struct platform_device tegra11_spi_device6 = {
708         .name           = "spi-tegra114",
709         .id             = 5,
710         .resource       = spi_resource6,
711         .num_resources  = ARRAY_SIZE(spi_resource6),
712         .dev  = {
713                 .coherent_dma_mask      = 0xffffffff,
714         },
715 };
716 #endif
717
718 struct platform_device tegra_spi_slave_device1 = {
719         .name           = "spi_slave_tegra",
720         .id             = 0,
721         .resource       = spi_resource1,
722         .num_resources  = ARRAY_SIZE(spi_resource1),
723         .dev  = {
724                 .coherent_dma_mask      = 0xffffffff,
725         },
726 };
727
728 struct platform_device tegra_spi_slave_device2 = {
729         .name           = "spi_slave_tegra",
730         .id             = 1,
731         .resource       = spi_resource2,
732         .num_resources  = ARRAY_SIZE(spi_resource2),
733         .dev  = {
734                 .coherent_dma_mask      = 0xffffffff,
735         },
736 };
737
738 struct platform_device tegra_spi_slave_device3 = {
739         .name           = "spi_slave_tegra",
740         .id             = 2,
741         .resource       = spi_resource3,
742         .num_resources  = ARRAY_SIZE(spi_resource3),
743         .dev  = {
744                 .coherent_dma_mask      = 0xffffffff,
745         },
746 };
747
748 struct platform_device tegra_spi_slave_device4 = {
749         .name           = "spi_slave_tegra",
750         .id             = 3,
751         .resource       = spi_resource4,
752         .num_resources  = ARRAY_SIZE(spi_resource4),
753         .dev  = {
754                 .coherent_dma_mask      = 0xffffffff,
755         },
756 };
757 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
758 struct platform_device tegra_spi_slave_device5 = {
759         .name           = "spi_slave_tegra",
760         .id             = 4,
761         .resource       = spi_resource5,
762         .num_resources  = ARRAY_SIZE(spi_resource5),
763         .dev  = {
764                 .coherent_dma_mask      = 0xffffffff,
765         },
766 };
767
768 struct platform_device tegra_spi_slave_device6 = {
769         .name           = "spi_slave_tegra",
770         .id             = 5,
771         .resource       = spi_resource6,
772         .num_resources  = ARRAY_SIZE(spi_resource6),
773         .dev  = {
774                 .coherent_dma_mask      = 0xffffffff,
775         },
776 };
777 #endif
778
779 struct platform_device tegra11_spi_slave_device1 = {
780         .name           = "tegra11-spi-slave",
781         .id             = 0,
782         .resource       = spi_resource1,
783         .num_resources  = ARRAY_SIZE(spi_resource1),
784         .dev  = {
785                 .coherent_dma_mask      = 0xffffffff,
786         },
787 };
788
789 struct platform_device tegra11_spi_slave_device2 = {
790         .name           = "tegra11-spi-slave",
791         .id             = 1,
792         .resource       = spi_resource2,
793         .num_resources  = ARRAY_SIZE(spi_resource2),
794         .dev  = {
795                 .coherent_dma_mask      = 0xffffffff,
796         },
797 };
798
799 struct platform_device tegra11_spi_slave_device3 = {
800         .name           = "tegra11-spi-slave",
801         .id             = 2,
802         .resource       = spi_resource3,
803         .num_resources  = ARRAY_SIZE(spi_resource3),
804         .dev  = {
805                 .coherent_dma_mask      = 0xffffffff,
806         },
807 };
808
809 struct platform_device tegra11_spi_slave_device4 = {
810         .name           = "tegra11-spi-slave",
811         .id             = 3,
812         .resource       = spi_resource4,
813         .num_resources  = ARRAY_SIZE(spi_resource4),
814         .dev  = {
815                 .coherent_dma_mask      = 0xffffffff,
816         },
817 };
818 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
819 struct platform_device tegra11_spi_slave_device5 = {
820         .name           = "tegra11-spi-slave",
821         .id             = 4,
822         .resource       = spi_resource5,
823         .num_resources  = ARRAY_SIZE(spi_resource5),
824         .dev  = {
825                 .coherent_dma_mask      = 0xffffffff,
826         },
827 };
828
829 struct platform_device tegra11_spi_slave_device6 = {
830         .name           = "tegra11-spi-slave",
831         .id             = 5,
832         .resource       = spi_resource6,
833         .num_resources  = ARRAY_SIZE(spi_resource6),
834         .dev  = {
835                 .coherent_dma_mask      = 0xffffffff,
836         },
837 };
838 #endif
839
840 static struct resource resources_nor[] = {
841         [0] = {
842                 .start = INT_SNOR,
843                 .end = INT_SNOR,
844                 .flags = IORESOURCE_IRQ,
845         },
846         [1] = {
847                 /* Map SNOR Controller */
848                 .start = TEGRA_SNOR_BASE,
849                 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
850                 .flags = IORESOURCE_MEM,
851         },
852         [2] = {
853                 /* Map the size of flash */
854                 .start = TEGRA_NOR_FLASH_BASE,
855                 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
856                 .flags = IORESOURCE_MEM,
857         }
858 };
859
860 struct platform_device tegra_nor_device = {
861         .name = "tegra-nor",
862         .id = -1,
863         .num_resources = ARRAY_SIZE(resources_nor),
864         .resource = resources_nor,
865         .dev = {
866                 .coherent_dma_mask = 0xffffffff,
867         },
868 };
869
870 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
871 struct platform_device tegra_dtv_device = {
872         .name           = "tegra_dtv",
873         .id             = -1,
874         .resource       = dtv_resource,
875         .num_resources  = ARRAY_SIZE(dtv_resource),
876         .dev = {
877                 .init_name = "dtv",
878                 .coherent_dma_mask = 0xffffffff,
879         },
880 };
881 #endif
882
883 static struct resource sdhci_resource1[] = {
884         [0] = {
885                 .start  = INT_SDMMC1,
886                 .end    = INT_SDMMC1,
887                 .flags  = IORESOURCE_IRQ,
888         },
889         [1] = {
890                 .start  = TEGRA_SDMMC1_BASE,
891                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
892                 .flags  = IORESOURCE_MEM,
893         },
894 };
895
896 static struct resource sdhci_resource2[] = {
897         [0] = {
898                 .start  = INT_SDMMC2,
899                 .end    = INT_SDMMC2,
900                 .flags  = IORESOURCE_IRQ,
901         },
902         [1] = {
903                 .start  = TEGRA_SDMMC2_BASE,
904                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
905                 .flags  = IORESOURCE_MEM,
906         },
907 };
908
909 static struct resource sdhci_resource3[] = {
910         [0] = {
911                 .start  = INT_SDMMC3,
912                 .end    = INT_SDMMC3,
913                 .flags  = IORESOURCE_IRQ,
914         },
915         [1] = {
916                 .start  = TEGRA_SDMMC3_BASE,
917                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
918                 .flags  = IORESOURCE_MEM,
919         },
920 };
921
922 static struct resource sdhci_resource4[] = {
923         [0] = {
924                 .start  = INT_SDMMC4,
925                 .end    = INT_SDMMC4,
926                 .flags  = IORESOURCE_IRQ,
927         },
928         [1] = {
929                 .start  = TEGRA_SDMMC4_BASE,
930                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
931                 .flags  = IORESOURCE_MEM,
932         },
933 };
934
935 struct platform_device tegra_pci_device = {
936         .name           = "tegra-pcie",
937         .id             = 0,
938         .resource       = 0,
939         .num_resources  = 0,
940         .dev = {
941                 .platform_data = 0,
942         },
943 };
944
945 /* board files should fill in platform_data register the devices themselvs.
946  * See board-harmony.c for an example
947  */
948 struct platform_device tegra_sdhci_device1 = {
949         .name           = "sdhci-tegra",
950         .id             = 0,
951         .resource       = sdhci_resource1,
952         .num_resources  = ARRAY_SIZE(sdhci_resource1),
953 };
954
955 struct platform_device tegra_sdhci_device2 = {
956         .name           = "sdhci-tegra",
957         .id             = 1,
958         .resource       = sdhci_resource2,
959         .num_resources  = ARRAY_SIZE(sdhci_resource2),
960 };
961
962 struct platform_device tegra_sdhci_device3 = {
963         .name           = "sdhci-tegra",
964         .id             = 2,
965         .resource       = sdhci_resource3,
966         .num_resources  = ARRAY_SIZE(sdhci_resource3),
967 };
968
969 struct platform_device tegra_sdhci_device4 = {
970         .name           = "sdhci-tegra",
971         .id             = 3,
972         .resource       = sdhci_resource4,
973         .num_resources  = ARRAY_SIZE(sdhci_resource4),
974 };
975
976 static struct resource tegra_usb1_resources[] = {
977         [0] = {
978                 .start  = TEGRA_USB_BASE,
979                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
980                 .flags  = IORESOURCE_MEM,
981         },
982         [1] = {
983                 .start  = INT_USB,
984                 .end    = INT_USB,
985                 .flags  = IORESOURCE_IRQ,
986         },
987 };
988
989 static struct resource tegra_usb2_resources[] = {
990         [0] = {
991                 .start  = TEGRA_USB2_BASE,
992                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
993                 .flags  = IORESOURCE_MEM,
994         },
995         [1] = {
996                 .start  = INT_USB2,
997                 .end    = INT_USB2,
998                 .flags  = IORESOURCE_IRQ,
999         },
1000 };
1001
1002 static struct resource tegra_usb3_resources[] = {
1003         [0] = {
1004                 .start  = TEGRA_USB3_BASE,
1005                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
1006                 .flags  = IORESOURCE_MEM,
1007         },
1008         [1] = {
1009                 .start  = INT_USB3,
1010                 .end    = INT_USB3,
1011                 .flags  = IORESOURCE_IRQ,
1012         },
1013 };
1014
1015 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1016 static struct resource tegra_xusb_resources[] = {
1017         [0] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_HOST_BASE, TEGRA_XUSB_HOST_SIZE,
1018                         "host"),
1019         [1] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_FPCI_BASE, TEGRA_XUSB_FPCI_SIZE,
1020                         "fpci"),
1021         [2] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_IPFS_BASE, TEGRA_XUSB_IPFS_SIZE,
1022                         "ipfs"),
1023         [3] = DEFINE_RES_MEM_NAMED(TEGRA_XUSB_PADCTL_BASE,
1024                         TEGRA_XUSB_PADCTL_SIZE, "padctl"),
1025         [4] = DEFINE_RES_MEM_NAMED(TEGRA_PMC_BASE, TEGRA_PMC_SIZE, "pmc"),
1026         [5] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_INT, "host"),
1027         [6] = DEFINE_RES_IRQ_NAMED(INT_XUSB_HOST_SMI, "host-smi"),
1028         [7] = DEFINE_RES_IRQ_NAMED(INT_XUSB_PADCTL, "padctl"),
1029         [8] = DEFINE_RES_IRQ_NAMED(INT_USB3, "usb3"),
1030 };
1031
1032 static u64 tegra_xusb_dmamask = DMA_BIT_MASK(64);
1033
1034 struct platform_device tegra_xhci_device = {
1035         .name = "tegra-xhci",
1036         .id = -1,
1037         .dev = {
1038                 .dma_mask = &tegra_xusb_dmamask,
1039                 .coherent_dma_mask = DMA_BIT_MASK(64),
1040         },
1041         .resource = tegra_xusb_resources,
1042         .num_resources = ARRAY_SIZE(tegra_xusb_resources),
1043 };
1044 #endif
1045
1046 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
1047
1048 struct platform_device tegra_ehci1_device = {
1049         .name   = "tegra-ehci",
1050         .id     = 0,
1051         .dev    = {
1052                 .dma_mask       = &tegra_ehci_dmamask,
1053                 .coherent_dma_mask = DMA_BIT_MASK(32),
1054         },
1055         .resource = tegra_usb1_resources,
1056         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
1057 };
1058
1059 struct platform_device tegra_ehci2_device = {
1060         .name   = "tegra-ehci",
1061         .id     = 1,
1062         .dev    = {
1063                 .dma_mask       = &tegra_ehci_dmamask,
1064                 .coherent_dma_mask = DMA_BIT_MASK(32),
1065         },
1066         .resource = tegra_usb2_resources,
1067         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
1068 };
1069
1070 struct platform_device tegra_ehci3_device = {
1071         .name   = "tegra-ehci",
1072         .id     = 2,
1073         .dev    = {
1074                 .dma_mask       = &tegra_ehci_dmamask,
1075                 .coherent_dma_mask = DMA_BIT_MASK(32),
1076         },
1077         .resource = tegra_usb3_resources,
1078         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
1079 };
1080
1081 static struct resource tegra_pmu_resources[] = {
1082         [0] = {
1083                 .start  = INT_CPU0_PMU_INTR,
1084                 .end    = INT_CPU0_PMU_INTR,
1085                 .flags  = IORESOURCE_IRQ,
1086         },
1087         [1] = {
1088                 .start  = INT_CPU1_PMU_INTR,
1089                 .end    = INT_CPU1_PMU_INTR,
1090                 .flags  = IORESOURCE_IRQ,
1091         },
1092 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1093         [2] = {
1094                 .start  = INT_CPU2_PMU_INTR,
1095                 .end    = INT_CPU2_PMU_INTR,
1096                 .flags  = IORESOURCE_IRQ,
1097         },
1098         [3] = {
1099                 .start  = INT_CPU3_PMU_INTR,
1100                 .end    = INT_CPU3_PMU_INTR,
1101                 .flags  = IORESOURCE_IRQ,
1102         },
1103 #endif
1104 };
1105
1106 struct platform_device tegra_pmu_device = {
1107         .name           = "arm-pmu",
1108         .id             = -1,
1109         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
1110         .resource       = tegra_pmu_resources,
1111 };
1112
1113 static struct resource tegra_uarta_resources[] = {
1114         [0] = {
1115                 .start  = TEGRA_UARTA_BASE,
1116                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
1117                 .flags  = IORESOURCE_MEM,
1118         },
1119         [1] = {
1120                 .start  = INT_UARTA,
1121                 .end    = INT_UARTA,
1122                 .flags  = IORESOURCE_IRQ,
1123         },
1124 };
1125
1126 static struct resource tegra_uartb_resources[] = {
1127         [0] = {
1128                 .start  = TEGRA_UARTB_BASE,
1129                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
1130                 .flags  = IORESOURCE_MEM,
1131         },
1132         [1] = {
1133                 .start  = INT_UARTB,
1134                 .end    = INT_UARTB,
1135                 .flags  = IORESOURCE_IRQ,
1136         },
1137 };
1138
1139 static struct resource tegra_uartc_resources[] = {
1140         [0] = {
1141                 .start  = TEGRA_UARTC_BASE,
1142                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
1143                 .flags  = IORESOURCE_MEM,
1144         },
1145         [1] = {
1146                 .start  = INT_UARTC,
1147                 .end    = INT_UARTC,
1148                 .flags  = IORESOURCE_IRQ,
1149         },
1150 };
1151
1152 static struct resource tegra_uartd_resources[] = {
1153         [0] = {
1154                 .start  = TEGRA_UARTD_BASE,
1155                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
1156                 .flags  = IORESOURCE_MEM,
1157         },
1158         [1] = {
1159                 .start  = INT_UARTD,
1160                 .end    = INT_UARTD,
1161                 .flags  = IORESOURCE_IRQ,
1162         },
1163 };
1164
1165 static struct resource tegra_uarte_resources[] = {
1166         [0] = {
1167                 .start  = TEGRA_UARTE_BASE,
1168                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
1169                 .flags  = IORESOURCE_MEM,
1170         },
1171         [1] = {
1172                 .start  = INT_UARTE,
1173                 .end    = INT_UARTE,
1174                 .flags  = IORESOURCE_IRQ,
1175         },
1176 };
1177
1178 struct platform_device tegra_uarta_device = {
1179         .name   = "tegra_uart",
1180         .id     = 0,
1181         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
1182         .resource       = tegra_uarta_resources,
1183         .dev    = {
1184                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1185         },
1186 };
1187
1188 struct platform_device tegra_uartb_device = {
1189         .name   = "tegra_uart",
1190         .id     = 1,
1191         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
1192         .resource       = tegra_uartb_resources,
1193         .dev    = {
1194                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1195         },
1196 };
1197
1198 struct platform_device tegra_uartc_device = {
1199         .name   = "tegra_uart",
1200         .id     = 2,
1201         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
1202         .resource       = tegra_uartc_resources,
1203         .dev    = {
1204                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1205         },
1206 };
1207
1208 struct platform_device tegra_uartd_device = {
1209         .name   = "tegra_uart",
1210         .id     = 3,
1211         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
1212         .resource       = tegra_uartd_resources,
1213         .dev    = {
1214                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1215         },
1216 };
1217
1218 struct platform_device tegra_uarte_device = {
1219         .name   = "tegra_uart",
1220         .id     = 4,
1221         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
1222         .resource       = tegra_uarte_resources,
1223         .dev    = {
1224                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1225         },
1226 };
1227
1228 static struct plat_serial8250_port debug_uarta_platform_data[] = {
1229         {
1230                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
1231                 .mapbase        = TEGRA_UARTA_BASE,
1232                 .irq            = INT_UARTA,
1233                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1234                 .type           = PORT_TEGRA,
1235                 .iotype         = UPIO_MEM,
1236                 .regshift       = 2,
1237         },
1238         {
1239                 .flags          = 0,
1240         },
1241 };
1242
1243 static struct plat_serial8250_port debug_uartb_platform_data[] = {
1244         {
1245                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
1246                 .mapbase        = TEGRA_UARTB_BASE,
1247                 .irq            = INT_UARTB,
1248                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1249                 .type           = PORT_TEGRA,
1250                 .iotype         = UPIO_MEM,
1251                 .regshift       = 2,
1252         },
1253         {
1254                 .flags          = 0,
1255         },
1256 };
1257
1258 static struct plat_serial8250_port debug_uartc_platform_data[] = {
1259         {
1260                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
1261                 .mapbase        = TEGRA_UARTC_BASE,
1262                 .irq            = INT_UARTC,
1263                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1264                 .type           = PORT_TEGRA,
1265                 .iotype         = UPIO_MEM,
1266                 .regshift       = 2,
1267         },
1268         {
1269                 .flags          = 0,
1270         },
1271 };
1272
1273 static struct plat_serial8250_port debug_uartd_platform_data[] = {
1274         {
1275                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
1276                 .mapbase        = TEGRA_UARTD_BASE,
1277                 .irq            = INT_UARTD,
1278                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1279                 .type           = PORT_TEGRA,
1280                 .iotype         = UPIO_MEM,
1281                 .regshift       = 2,
1282         },
1283         {
1284                 .flags          = 0,
1285         },
1286 };
1287
1288 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1289 static struct plat_serial8250_port debug_uarte_platform_data[] = {
1290         {
1291                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
1292                 .mapbase        = TEGRA_UARTE_BASE,
1293                 .irq            = INT_UARTE,
1294                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
1295                 .type           = PORT_TEGRA,
1296                 .iotype         = UPIO_MEM,
1297                 .regshift       = 2,
1298         },
1299         {
1300                 .flags          = 0,
1301         },
1302 };
1303 #endif
1304
1305 struct platform_device debug_uarta_device = {
1306         .name = "serial8250",
1307         .id = PLAT8250_DEV_PLATFORM,
1308         .dev = {
1309                 .platform_data = debug_uarta_platform_data,
1310         },
1311 };
1312
1313 struct platform_device debug_uartb_device = {
1314         .name = "serial8250",
1315         .id = PLAT8250_DEV_PLATFORM,
1316         .dev = {
1317                 .platform_data = debug_uartb_platform_data,
1318         },
1319 };
1320
1321 struct platform_device debug_uartc_device = {
1322         .name = "serial8250",
1323         .id = PLAT8250_DEV_PLATFORM,
1324         .dev = {
1325                 .platform_data = debug_uartc_platform_data,
1326         },
1327 };
1328
1329 struct platform_device debug_uartd_device = {
1330         .name = "serial8250",
1331         .id = PLAT8250_DEV_PLATFORM,
1332         .dev = {
1333                 .platform_data = debug_uartd_platform_data,
1334         },
1335 };
1336
1337 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1338 struct platform_device debug_uarte_device = {
1339         .name = "serial8250",
1340         .id = PLAT8250_DEV_PLATFORM,
1341         .dev = {
1342                 .platform_data = debug_uarte_platform_data,
1343         },
1344 };
1345 #endif
1346
1347 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1348 static struct resource i2s_resource1[] = {
1349         [0] = {
1350                 .start  = INT_I2S1,
1351                 .end    = INT_I2S1,
1352                 .flags  = IORESOURCE_IRQ
1353         },
1354         [1] = {
1355                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
1356                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
1357                 .flags  = IORESOURCE_DMA
1358         },
1359         [2] = {
1360                 .start  = TEGRA_I2S1_BASE,
1361                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1362                 .flags  = IORESOURCE_MEM
1363         }
1364 };
1365
1366 struct platform_device tegra_i2s_device1 = {
1367         .name           = "tegra20-i2s",
1368         .id             = 0,
1369         .resource       = i2s_resource1,
1370         .num_resources  = ARRAY_SIZE(i2s_resource1),
1371 };
1372
1373 static struct resource i2s_resource2[] = {
1374         [0] = {
1375                 .start  = INT_I2S2,
1376                 .end    = INT_I2S2,
1377                 .flags  = IORESOURCE_IRQ
1378         },
1379         [1] = {
1380                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
1381                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
1382                 .flags  = IORESOURCE_DMA
1383         },
1384         [2] = {
1385                 .start  = TEGRA_I2S2_BASE,
1386                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1387                 .flags  = IORESOURCE_MEM
1388         }
1389 };
1390
1391 struct platform_device tegra_i2s_device2 = {
1392         .name           = "tegra20-i2s",
1393         .id             = 1,
1394         .resource       = i2s_resource2,
1395         .num_resources  = ARRAY_SIZE(i2s_resource2),
1396 };
1397 #else
1398 static struct resource i2s_resource0[] = {
1399         [0] = {
1400                 .start  = TEGRA_I2S0_BASE,
1401                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1402                 .flags  = IORESOURCE_MEM
1403         }
1404 };
1405
1406 struct platform_device tegra_i2s_device0 = {
1407         .name           = "tegra30-i2s",
1408         .id             = 0,
1409         .resource       = i2s_resource0,
1410         .num_resources  = ARRAY_SIZE(i2s_resource0),
1411 };
1412
1413 static struct resource i2s_resource1[] = {
1414         [0] = {
1415                 .start  = TEGRA_I2S1_BASE,
1416                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1417                 .flags  = IORESOURCE_MEM
1418         }
1419 };
1420
1421 struct platform_device tegra_i2s_device1 = {
1422         .name           = "tegra30-i2s",
1423         .id             = 1,
1424         .resource       = i2s_resource1,
1425         .num_resources  = ARRAY_SIZE(i2s_resource1),
1426 };
1427
1428 static struct resource i2s_resource2[] = {
1429         [0] = {
1430                 .start  = TEGRA_I2S2_BASE,
1431                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1432                 .flags  = IORESOURCE_MEM
1433         }
1434 };
1435
1436 struct platform_device tegra_i2s_device2 = {
1437         .name           = "tegra30-i2s",
1438         .id             = 2,
1439         .resource       = i2s_resource2,
1440         .num_resources  = ARRAY_SIZE(i2s_resource2),
1441 };
1442
1443 static struct resource i2s_resource3[] = {
1444         [0] = {
1445                 .start  = TEGRA_I2S3_BASE,
1446                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1447                 .flags  = IORESOURCE_MEM
1448         }
1449 };
1450
1451 struct platform_device tegra_i2s_device3 = {
1452         .name           = "tegra30-i2s",
1453         .id             = 3,
1454         .resource       = i2s_resource3,
1455         .num_resources  = ARRAY_SIZE(i2s_resource3),
1456 };
1457
1458 static struct resource i2s_resource4[] = {
1459         [0] = {
1460                 .start  = TEGRA_I2S4_BASE,
1461                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1462                 .flags  = IORESOURCE_MEM
1463         }
1464 };
1465
1466 struct platform_device tegra_i2s_device4 = {
1467         .name           = "tegra30-i2s",
1468         .id             = 4,
1469         .resource       = i2s_resource4,
1470         .num_resources  = ARRAY_SIZE(i2s_resource4),
1471 };
1472 #endif
1473
1474 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1475 static struct resource spdif_resource[] = {
1476         [0] = {
1477                 .start  = INT_SPDIF,
1478                 .end    = INT_SPDIF,
1479                 .flags  = IORESOURCE_IRQ
1480         },
1481         [1] = {
1482                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1483                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1484                 .flags  = IORESOURCE_DMA
1485         },
1486         [2] = {
1487                 .start  = TEGRA_SPDIF_BASE,
1488                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1489                 .flags  = IORESOURCE_MEM
1490         }
1491 };
1492
1493 struct platform_device tegra_spdif_device = {
1494         .name           = "tegra20-spdif",
1495         .id             = -1,
1496         .resource       = spdif_resource,
1497         .num_resources  = ARRAY_SIZE(spdif_resource),
1498 };
1499 #else
1500 static struct resource spdif_resource[] = {
1501         [0] = {
1502                 .start  = TEGRA_SPDIF_BASE,
1503                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1504                 .flags  = IORESOURCE_MEM
1505         }
1506 };
1507
1508 struct platform_device tegra_spdif_device = {
1509         .name           = "tegra30-spdif",
1510         .id             = -1,
1511         .resource       = spdif_resource,
1512         .num_resources  = ARRAY_SIZE(spdif_resource),
1513 };
1514 #endif
1515
1516 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1517 static struct resource ahub_resource[] = {
1518         [0] = {
1519                 .start  = TEGRA_APBIF0_BASE,
1520                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1521                 .flags  = IORESOURCE_MEM
1522         },
1523         [1] = {
1524                 .start  = TEGRA_AHUB_BASE,
1525                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1526                 .flags  = IORESOURCE_MEM
1527         }
1528 };
1529
1530 struct platform_device tegra_ahub_device = {
1531         .name   = "tegra30-ahub",
1532         .id     = -1,
1533         .resource       = ahub_resource,
1534         .num_resources  = ARRAY_SIZE(ahub_resource),
1535 };
1536
1537 static struct resource dam_resource0[] = {
1538         [0] = {
1539                 .start = TEGRA_DAM0_BASE,
1540                 .end   = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1541                 .flags = IORESOURCE_MEM
1542         }
1543 };
1544
1545 struct platform_device tegra_dam_device0 = {
1546         .name = "tegra30-dam",
1547         .id = 0,
1548         .resource      = dam_resource0,
1549         .num_resources = ARRAY_SIZE(dam_resource0),
1550 };
1551
1552 static struct resource dam_resource1[] = {
1553         [0] = {
1554                 .start = TEGRA_DAM1_BASE,
1555                 .end   = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1556                 .flags = IORESOURCE_MEM
1557         }
1558 };
1559
1560 struct platform_device tegra_dam_device1 = {
1561         .name = "tegra30-dam",
1562         .id = 1,
1563         .resource      = dam_resource1,
1564         .num_resources = ARRAY_SIZE(dam_resource1),
1565 };
1566
1567 static struct resource dam_resource2[] = {
1568         [0] = {
1569                 .start = TEGRA_DAM2_BASE,
1570                 .end   = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1571                 .flags = IORESOURCE_MEM
1572         }
1573 };
1574
1575 struct platform_device tegra_dam_device2 = {
1576         .name = "tegra30-dam",
1577         .id = 2,
1578         .resource      = dam_resource2,
1579         .num_resources = ARRAY_SIZE(dam_resource2),
1580 };
1581
1582 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1583 static struct resource hda_platform_resources[] = {
1584         [0] = {
1585                 .start  = TEGRA_HDA_BASE,
1586                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1587                 .flags  = IORESOURCE_MEM
1588         },
1589         [1] = {
1590                 .start  = INT_HDA,
1591                 .end    = INT_HDA,
1592                 .flags  = IORESOURCE_IRQ
1593         },
1594 };
1595
1596 struct platform_device tegra_hda_device = {
1597         .name           = "tegra30-hda",
1598         .id             = -1,
1599         .dev = {
1600                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1601                 .dma_mask               = &tegra_hda_dma_mask,
1602         },
1603         .resource       = hda_platform_resources,
1604         .num_resources  = ARRAY_SIZE(hda_platform_resources),
1605 };
1606 #endif
1607
1608 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1609 static struct resource dmic_resource0[] = {
1610         [0] = {
1611                 .start = TEGRA_DMIC0_BASE,
1612                 .end   = TEGRA_DMIC0_BASE + TEGRA_DMIC0_SIZE - 1,
1613                 .flags = IORESOURCE_MEM
1614         }
1615 };
1616
1617 struct platform_device tegra_dmic_device0 = {
1618         .name = "tegra-dmic",
1619         .id = 0,
1620         .resource      = dmic_resource0,
1621         .num_resources = ARRAY_SIZE(dmic_resource0),
1622 };
1623
1624 static struct resource dmic_resource1[] = {
1625         [0] = {
1626                 .start = TEGRA_DMIC1_BASE,
1627                 .end   = TEGRA_DMIC1_BASE + TEGRA_DMIC1_SIZE - 1,
1628                 .flags = IORESOURCE_MEM
1629         }
1630 };
1631
1632 struct platform_device tegra_dmic_device1 = {
1633         .name = "tegra-dmic",
1634         .id = 1,
1635         .resource      = dmic_resource1,
1636         .num_resources = ARRAY_SIZE(dmic_resource1),
1637 };
1638 #endif
1639
1640 struct platform_device spdif_dit_device = {
1641         .name = "spdif-dit",
1642         .id = 0,
1643 };
1644
1645 struct platform_device bluetooth_dit_device = {
1646         .name = "spdif-dit",
1647         .id = 1,
1648 };
1649
1650 struct platform_device baseband_dit_device = {
1651         .name = "spdif-dit",
1652         .id = 2,
1653 };
1654
1655 struct platform_device tegra_tdm_pcm_device = {
1656         .name = "tegra-tdm-pcm-audio",
1657         .id = -1,
1658 };
1659
1660 static struct resource w1_resources[] = {
1661         [0] = {
1662                 .start = INT_OWR,
1663                 .end   = INT_OWR,
1664                 .flags = IORESOURCE_IRQ
1665         },
1666         [1] = {
1667                 .start = TEGRA_OWR_BASE,
1668                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1669                 .flags = IORESOURCE_MEM
1670         }
1671 };
1672
1673 struct platform_device tegra_w1_device = {
1674         .name          = "tegra_w1",
1675         .id            = -1,
1676         .resource      = w1_resources,
1677         .num_resources = ARRAY_SIZE(w1_resources),
1678 };
1679
1680 static struct resource tegra_udc_resources[] = {
1681         [0] = {
1682                 .start  = TEGRA_USB_BASE,
1683                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1684                 .flags  = IORESOURCE_MEM,
1685         },
1686         [1] = {
1687                 .start  = INT_USB,
1688                 .end    = INT_USB,
1689                 .flags  = IORESOURCE_IRQ,
1690         },
1691 };
1692
1693 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1694
1695 struct platform_device tegra_udc_device = {
1696         .name   = "tegra-udc",
1697         .id     = 0,
1698         .dev    = {
1699                 .dma_mask       = &tegra_udc_dmamask,
1700                 .coherent_dma_mask = DMA_BIT_MASK(32),
1701         },
1702         .resource = tegra_udc_resources,
1703         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1704 };
1705
1706 static struct resource tegra_otg_resources[] = {
1707         [0] = {
1708                 .start  = TEGRA_USB_BASE,
1709                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1710                 .flags  = IORESOURCE_MEM,
1711         },
1712         [1] = {
1713                 .start  = INT_USB,
1714                 .end    = INT_USB,
1715                 .flags  = IORESOURCE_IRQ,
1716         },
1717 };
1718
1719 struct platform_device tegra_otg_device = {
1720         .name           = "tegra-otg",
1721         .id             = -1,
1722         .resource       = tegra_otg_resources,
1723         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1724 };
1725
1726 #ifdef CONFIG_SATA_AHCI_TEGRA
1727 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1728
1729 static struct resource tegra_sata_resources[] = {
1730         [0] = {
1731                 .start = TEGRA_SATA_BAR5_BASE,
1732                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1733                 .flags = IORESOURCE_MEM,
1734         },
1735         [1] = {
1736                 .start = TEGRA_SATA_CONFIG_BASE,
1737                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1738                 .flags = IORESOURCE_MEM,
1739         },
1740         [2] = {
1741                 .start = INT_SATA_CTL,
1742                 .end = INT_SATA_CTL,
1743                 .flags = IORESOURCE_IRQ,
1744         },
1745 };
1746
1747 struct platform_device tegra_sata_device = {
1748         .name   = "tegra-sata",
1749         .id     = 0,
1750         .dev    = {
1751                 .platform_data = 0,
1752                 .coherent_dma_mask = DMA_BIT_MASK(32),
1753                 .dma_mask = &tegra_sata_dma_mask,
1754         },
1755         .resource = tegra_sata_resources,
1756         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1757 };
1758 #endif
1759
1760 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1761 static struct resource das_resource[] = {
1762         [0] = {
1763                 .start  = TEGRA_APB_MISC_DAS_BASE,
1764                 .end    = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1765                 .flags  = IORESOURCE_MEM
1766         }
1767 };
1768
1769 struct platform_device tegra_das_device = {
1770         .name           = "tegra20-das",
1771         .id             = -1,
1772         .resource       = das_resource,
1773         .num_resources  = ARRAY_SIZE(das_resource),
1774 };
1775 #endif
1776
1777 #if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1778 static struct resource tegra_gart_resources[] = {
1779         [0] = {
1780                 .name   = "mc",
1781                 .flags  = IORESOURCE_MEM,
1782                 .start  = TEGRA_MC_BASE,
1783                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1784         },
1785         [1] = {
1786                 .name   = "gart",
1787                 .flags  = IORESOURCE_MEM,
1788                 .start  = TEGRA_GART_BASE,
1789                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1790         }
1791 };
1792
1793 struct platform_device tegra_gart_device = {
1794         .name           = "tegra_gart",
1795         .id             = -1,
1796         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1797         .resource       = tegra_gart_resources
1798 };
1799 #endif
1800
1801 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
1802 static struct resource tegra_smmu_resources[] = {
1803         {
1804                 .name   = "mc",
1805                 .flags  = IORESOURCE_MEM,
1806                 .start  = TEGRA_MC_BASE,
1807                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1808         },
1809         {
1810                 .name   = "ahbarb",
1811                 .flags  = IORESOURCE_MEM,
1812                 .start  = TEGRA_AHB_ARB_BASE,
1813                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1814         },
1815 };
1816
1817 struct platform_device tegra_smmu_device = {
1818         .name           = "tegra_smmu",
1819         .id             = -1,
1820         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1821         .resource       = tegra_smmu_resources
1822 };
1823
1824 static struct resource tegra_smmu[] = {
1825         [0] = {
1826                 .start  = TEGRA_SMMU_BASE,
1827                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1828         },
1829 };
1830
1831 struct resource *tegra_smmu_window(int wnum)
1832 {
1833         return &tegra_smmu[wnum];
1834 }
1835
1836 int tegra_smmu_window_count(void)
1837 {
1838         return ARRAY_SIZE(tegra_smmu);
1839 }
1840
1841 struct swgid_fixup {
1842         const char * const name;
1843         u64 swgids;
1844 };
1845
1846 /*
1847  * FIXME: They should have a DT entry with swgroup IDs.
1848  */
1849 struct swgid_fixup tegra_swgid_fixup[] = {
1850         { .name = "540c0000.epp",       .swgids = SWGID(EPP), },
1851         { .name = "epp",        .swgids = SWGID(EPP), },
1852         { .name = "54200000.dc",        .swgids = SWGID(DC), },
1853         { .name = "54240000.dc",        .swgids = SWGID(DCB), },
1854         { .name = "dc", .swgids = SWGID(DC) | SWGID(DCB) },
1855         { .name = "gr2d",       .swgids = SWGID(G2), },
1856         { .name = "gr3d",       .swgids = SWGID(NV) | SWGID(NV2), },
1857         { .name = "host1x",     .swgids = SWGID(HC) | SWGID(VDE) |      \
1858           SWGID(EPP) | SWGID(HDA), },
1859         { .name = "isp",        .swgids = SWGID(ISP), },
1860         { .name = "max77660",   .swgids = SWGID(PPCS), },
1861         { .name = "max8831",    .swgids = SWGID(PPCS), },
1862         { .name = "msenc",      .swgids = SWGID(MSENC), },
1863         { .name = "mpe",        .swgids = SWGID(MPE), },
1864         { .name = "tegra-aes",  .swgids = SWGID(VDE), },
1865         { .name = "nvavp",      .swgids = SWGID(AVPC), },
1866         { .name = "sdhci-tegra",        .swgids = SWGID(PPCS), },
1867         { .name = "serial8250", .swgids = SWGID(PPCS), },
1868         { .name = "snd-soc-dummy",      .swgids = SWGID(PPCS), },
1869         { .name = "spdif-dit",  .swgids = SWGID(PPCS), },
1870         { .name = "tegra11-se", .swgids = SWGID(PPCS), },
1871         { .name = "tegra11-spi",        .swgids = SWGID(PPCS), },
1872         { .name = "tegra14-i2c",        .swgids = SWGID(PPCS), },
1873         { .name = "tegra30-ahub",       .swgids = SWGID(PPCS), },
1874         { .name = "tegra30-dam",        .swgids = SWGID(PPCS), },
1875         { .name = "tegra30-hda",        .swgids = SWGID(HDA), },
1876         { .name = "tegra30-i2s",        .swgids = SWGID(PPCS), },
1877         { .name = "tegra30-spdif",      .swgids = SWGID(PPCS), },
1878         { .name = "tegradc",    .swgids = SWGID(DC) | SWGID(DCB), },
1879         { .name = "tegra_bb",   .swgids = SWGID(PPCS), },
1880         { .name = "tegra_dma",  .swgids = SWGID(PPCS), },
1881         { .name = "tegra-ehci", .swgids = SWGID(PPCS), },
1882         { .name = "tegra-fuse", .swgids = SWGID(PPCS), },
1883         { .name = "tegra-i2c",  .swgids = SWGID(PPCS), },
1884         { .name = "tegra-nvmap",        .swgids = SWGID(HC) | SWGID(AVPC), },
1885         { .name = "tegra-otg",  .swgids = SWGID(PPCS), },
1886         { .name = "tegra-pcm-audio",    .swgids = SWGID(PPCS), },
1887         { .name = "tegra-rtc",  .swgids = SWGID(PPCS), },
1888         { .name = "tegra-sata", .swgids = SWGID(SATA), },
1889         { .name = "tegra-se",   .swgids = SWGID(PPCS), },
1890         { .name = "tegra-snd",  .swgids = SWGID(PPCS), },
1891         { .name = "tegra-tzram",        .swgids = SWGID(VDE), },
1892         { .name = "tegra_uart", .swgids = SWGID(PPCS), },
1893         { .name = "tegra-udc",  .swgids = SWGID(PPCS), },
1894         { .name = "tegra_usb_modem_power",      .swgids = SWGID(PPCS), },
1895         { .name = "tsec",       .swgids = SWGID(TSEC), },
1896         { .name = "vi", .swgids = SWGID(VI), },
1897         { .name = "therm_est",  .swgids = SWGID(PPCS), },
1898         {},
1899 };
1900
1901 u64 tegra_smmu_fixup_swgids(struct device *dev)
1902 {
1903         const char *s;
1904         struct swgid_fixup *table = tegra_swgid_fixup;
1905
1906         while ((s = table->name) != NULL) {
1907                 if (!strncmp(s, dev_name(dev), strlen(s)))
1908                         return table->swgids;
1909                 table++;
1910         }
1911
1912         return 0;
1913 }
1914
1915 #ifdef CONFIG_PLATFORM_ENABLE_IOMMU
1916
1917 /*
1918  * ASID[0] for the system default
1919  * ASID[1] for PPCS, which has SDMMC
1920  * ASID[3][4] open for drivers, first come, first served.
1921  */
1922 enum {
1923         SYSTEM_DEFAULT,
1924         SYSTEM_PROTECTED,
1925 };
1926
1927 static struct dma_iommu_mapping *smmu_default_map[2];
1928
1929 static void tegra_smmu_map_init(struct platform_device *pdev)
1930 {
1931         int i;
1932
1933         for (i = 0; i < ARRAY_SIZE(smmu_default_map); i++) {
1934                 struct dma_iommu_mapping *map;
1935
1936                 map = arm_iommu_create_mapping(&platform_bus_type,
1937                                                TEGRA_IOMMU_BASE,
1938                                                TEGRA_IOMMU_SIZE, 0);
1939                 if (IS_ERR(map))
1940                         dev_err(&pdev->dev,
1941                                 "Failed create IOVA map for ASID[%d]\n", i);
1942
1943                 smmu_default_map[i] = map;
1944         }
1945 }
1946
1947 struct dma_iommu_mapping *tegra_smmu_get_map(struct device *dev, u64 swgids)
1948 {
1949         if (!swgids)
1950                 swgids = tegra_smmu_fixup_swgids(dev);
1951
1952         if (!swgids)
1953                 return NULL;
1954
1955         if (swgids & SWGID(PPCS))
1956                 return smmu_default_map[SYSTEM_PROTECTED];
1957
1958         return smmu_default_map[SYSTEM_DEFAULT];
1959 }
1960 #else
1961 static inline void tegra_smmu_map_init(struct platform_device *pdev)
1962 {
1963 }
1964 #endif
1965
1966 static int __init tegra_smmu_init(void)
1967 {
1968         platform_device_register(&tegra_smmu_device);
1969         tegra_smmu_map_init(&tegra_smmu_device);
1970         return 0;
1971 }
1972 postcore_initcall(tegra_smmu_init);
1973 #endif
1974
1975 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1976 #define CLK_RESET_RST_SOURCE    0x0
1977 static struct resource tegra_wdt_resources[] = {
1978         [0] = {
1979                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1980                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1981                 .flags  = IORESOURCE_MEM,
1982         },
1983         [1] = {
1984                 .start  = TEGRA_TMR1_BASE,
1985                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1986                 .flags  = IORESOURCE_MEM,
1987         },
1988         [2] = {
1989                 .start  = INT_TMR1,
1990                 .end    = INT_TMR1,
1991                 .flags  = IORESOURCE_IRQ,
1992         },
1993 };
1994
1995 struct platform_device tegra_wdt_device = {
1996         .name           = "tegra_wdt",
1997         .id             = -1,
1998         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1999         .resource       = tegra_wdt_resources,
2000 };
2001 #else
2002 static struct resource tegra_wdt0_resources[] = {
2003         [0] = {
2004                 .start  = TEGRA_WDT0_BASE,
2005                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
2006                 .flags  = IORESOURCE_MEM,
2007         },
2008         [1] = {
2009                 .start  = TEGRA_TMR7_BASE,
2010                 .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
2011                 .flags  = IORESOURCE_MEM,
2012         },
2013         [2] = {
2014                 .start  = INT_WDT_CPU,
2015                 .end    = INT_WDT_CPU,
2016                 .flags  = IORESOURCE_IRQ,
2017         },
2018 #ifdef CONFIG_TEGRA_FIQ_DEBUGGER
2019         [3] = {
2020                 .start  = TEGRA_QUATERNARY_ICTLR_BASE,
2021                 .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
2022                                 TEGRA_QUATERNARY_ICTLR_SIZE -1,
2023                 .flags  = IORESOURCE_MEM,
2024         },
2025 #endif
2026 };
2027
2028 struct platform_device tegra_wdt0_device = {
2029         .name           = "tegra_wdt",
2030         .id             = 0,
2031         .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
2032         .resource       = tegra_wdt0_resources,
2033 };
2034
2035 #endif
2036
2037 static struct resource tegra_pwfm_resource = {
2038         .start  = TEGRA_PWFM_BASE,
2039         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
2040         .flags  = IORESOURCE_MEM,
2041 };
2042
2043 struct platform_device tegra_pwfm_device = {
2044         .name           = "tegra-pwm",
2045         .id             = -1,
2046         .num_resources  = 1,
2047         .resource       = &tegra_pwfm_resource,
2048 };
2049
2050 static struct tegra_avp_platform_data tegra_avp_pdata = {
2051 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2052         .emc_clk_rate = ULONG_MAX,
2053 #else
2054         .emc_clk_rate = 200000000,
2055 #endif
2056 };
2057
2058 struct resource tegra_nvavp_resources[] = {
2059         [0] = {
2060                 .start  = INT_SHR_SEM_INBOX_IBF,
2061                 .end    = INT_SHR_SEM_INBOX_IBF,
2062                 .flags  = IORESOURCE_IRQ,
2063                 .name   = "mbox_from_nvavp_pending",
2064         },
2065 };
2066
2067 struct platform_device nvavp_device = {
2068         .name           = "nvavp",
2069         .id             = -1,
2070         .resource       = tegra_nvavp_resources,
2071         .num_resources  = ARRAY_SIZE(tegra_nvavp_resources),
2072 };
2073
2074 static struct resource tegra_avp_resources[] = {
2075         [0] = {
2076                 .start  = INT_SHR_SEM_INBOX_IBF,
2077                 .end    = INT_SHR_SEM_INBOX_IBF,
2078                 .flags  = IORESOURCE_IRQ,
2079                 .name   = "mbox_from_avp_pending",
2080         },
2081 };
2082
2083 struct platform_device tegra_avp_device = {
2084         .name           = "tegra-avp",
2085         .id             = -1,
2086         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
2087         .resource       = tegra_avp_resources,
2088         .dev  = {
2089                 .coherent_dma_mask      = 0xffffffffULL,
2090                 .platform_data          = &tegra_avp_pdata,
2091         },
2092 };
2093
2094 static struct resource tegra_aes_resources[] = {
2095         {
2096                 .start  = TEGRA_VDE_BASE,
2097                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
2098                 .flags  = IORESOURCE_MEM,
2099         },
2100         {
2101                 .start  = TEGRA_BSEA_BASE,
2102                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
2103                 .flags  = IORESOURCE_MEM,
2104         },
2105         {
2106                 .start  = INT_VDE_BSE_V,
2107                 .end    = INT_VDE_BSE_V,
2108                 .flags  = IORESOURCE_IRQ,
2109         },
2110         {
2111                 .start  = INT_VDE_BSE_A,
2112                 .end    = INT_VDE_BSE_A,
2113                 .flags  = IORESOURCE_IRQ,
2114         },
2115 };
2116
2117 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
2118
2119 struct platform_device tegra_aes_device = {
2120         .name           = "tegra-aes",
2121         .id             = -1,
2122         .resource       = tegra_aes_resources,
2123         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
2124         .dev    = {
2125                 .dma_mask = &tegra_aes_dma_mask,
2126                 .coherent_dma_mask = DMA_BIT_MASK(32),
2127         },
2128 };
2129
2130 static struct resource tegra_kbc_resources[] = {
2131         [0] = {
2132                 .start = TEGRA_KBC_BASE,
2133                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
2134                 .flags = IORESOURCE_MEM,
2135         },
2136         [1] = {
2137                 .start = INT_KBC,
2138                 .end   = INT_KBC,
2139                 .flags = IORESOURCE_IRQ,
2140         },
2141 };
2142
2143 struct platform_device tegra_kbc_device = {
2144         .name = "tegra-kbc",
2145         .id = -1,
2146         .resource = tegra_kbc_resources,
2147         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
2148         .dev = {
2149                 .platform_data = 0,
2150         },
2151 };
2152
2153 #if defined(CONFIG_TEGRA_SKIN_THROTTLE)
2154 struct platform_device tegra_skin_therm_est_device = {
2155         .name   = "therm_est",
2156         .id     = -1,
2157         .num_resources  = 0,
2158         .dev = {
2159                 .platform_data = 0,
2160         },
2161 };
2162 #endif
2163
2164 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
2165 static struct resource tegra_tsensor_resources[]= {
2166         {
2167                 .start  = TEGRA_TSENSOR_BASE,
2168                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
2169                 .flags  = IORESOURCE_MEM,
2170         },
2171         {
2172                 .start  = INT_TSENSOR,
2173                 .end    = INT_TSENSOR,
2174                 .flags  = IORESOURCE_IRQ,
2175         },
2176         {
2177                 .start  = TEGRA_PMC_BASE + 0x1B0,
2178                 /* 2 pmc registers mapped */
2179                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
2180                 .flags  = IORESOURCE_MEM,
2181         },
2182 };
2183
2184 struct platform_device tegra_tsensor_device = {
2185         .name   = "tegra-tsensor",
2186         .id     = -1,
2187         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
2188         .resource       = tegra_tsensor_resources,
2189         .dev = {
2190                 .platform_data = 0,
2191         },
2192 };
2193 #endif
2194
2195 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2196 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
2197
2198 struct resource tegra_se_resources[] = {
2199         [0] = {
2200                 .start = TEGRA_SE_BASE,
2201                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
2202                 .flags = IORESOURCE_MEM,
2203         },
2204         [1] = {
2205                 .start  = TEGRA_PMC_BASE,
2206                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
2207                 .flags  = IORESOURCE_MEM,
2208         },
2209         [2] = {
2210                 .start = INT_SE,
2211                 .end = INT_SE,
2212                 .flags = IORESOURCE_IRQ,
2213         },
2214 };
2215
2216 struct platform_device tegra_se_device = {
2217         .name = "tegra-se",
2218         .id = -1,
2219         .dev = {
2220                 .coherent_dma_mask = DMA_BIT_MASK(32),
2221                 .dma_mask = &tegra_se_dma_mask,
2222         },
2223         .resource = tegra_se_resources,
2224         .num_resources = ARRAY_SIZE(tegra_se_resources),
2225 };
2226
2227 struct platform_device tegra11_se_device = {
2228         .name = "tegra11-se",
2229         .id = -1,
2230         .dev = {
2231                 .coherent_dma_mask = DMA_BIT_MASK(32),
2232                 .dma_mask = &tegra_se_dma_mask,
2233         },
2234         .resource = tegra_se_resources,
2235         .num_resources = ARRAY_SIZE(tegra_se_resources),
2236 };
2237 #endif
2238
2239 static struct resource tegra_disp1_resources[] = {
2240         {
2241                 .name   = "irq",
2242                 .start  = INT_DISPLAY_GENERAL,
2243                 .end    = INT_DISPLAY_GENERAL,
2244                 .flags  = IORESOURCE_IRQ,
2245         },
2246         {
2247                 .name   = "regs",
2248                 .start  = TEGRA_DISPLAY_BASE,
2249                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
2250                 .flags  = IORESOURCE_MEM,
2251         },
2252         {
2253                 .name   = "fbmem",
2254                 .start  = 0,
2255                 .end    = 0,
2256                 .flags  = IORESOURCE_MEM,
2257         },
2258         {
2259                 .name   = "dsi_regs",
2260                 .start  = TEGRA_DSI_BASE,
2261                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
2262                 .flags  = IORESOURCE_MEM,
2263         },
2264 };
2265
2266 struct platform_device tegra_disp1_device = {
2267         .name           = "tegradc",
2268         .id             = 0,
2269         .resource       = tegra_disp1_resources,
2270         .num_resources  = ARRAY_SIZE(tegra_disp1_resources),
2271 };
2272
2273 static struct resource tegra_disp2_resources[] = {
2274         {
2275                 .name   = "irq",
2276                 .start  = INT_DISPLAY_B_GENERAL,
2277                 .end    = INT_DISPLAY_B_GENERAL,
2278                 .flags  = IORESOURCE_IRQ,
2279         },
2280         {
2281                 .name   = "regs",
2282                 .start  = TEGRA_DISPLAY2_BASE,
2283                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
2284                 .flags  = IORESOURCE_MEM,
2285         },
2286         {
2287                 .name   = "fbmem",
2288                 .flags  = IORESOURCE_MEM,
2289                 .start  = 0,
2290                 .end    = 0,
2291         },
2292         {
2293                 .name   = "hdmi_regs",
2294                 .start  = TEGRA_HDMI_BASE,
2295                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
2296                 .flags  = IORESOURCE_MEM,
2297         },
2298 };
2299
2300 struct platform_device tegra_disp2_device = {
2301         .name           = "tegradc",
2302         .id             = 1,
2303         .resource       = tegra_disp2_resources,
2304         .num_resources  = ARRAY_SIZE(tegra_disp2_resources),
2305         .dev = {
2306                 .platform_data = 0,
2307         },
2308 };
2309
2310 struct platform_device tegra_nvmap_device = {
2311         .name   = "tegra-nvmap",
2312         .id     = -1,
2313 };
2314
2315 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
2316 static struct resource tegra_cec_resources[] = {
2317         [0] = {
2318                 .start = TEGRA_CEC_BASE,
2319                 .end = TEGRA_CEC_BASE + TEGRA_CEC_SIZE - 1,
2320                 .flags = IORESOURCE_MEM,
2321         },
2322         [1] = {
2323                 .start = INT_CEC,
2324                 .end = INT_CEC,
2325                 .flags = IORESOURCE_IRQ,
2326         },
2327 };
2328
2329 struct platform_device tegra_cec_device = {
2330         .name = "tegra_cec",
2331         .id   = -1,
2332         .resource = tegra_cec_resources,
2333         .num_resources = ARRAY_SIZE(tegra_cec_resources),
2334 };
2335 #endif
2336
2337 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
2338 static struct resource cl_dvfs_resource[] = {
2339         [0] = {
2340                 .start  = TEGRA_CL_DVFS_BASE,
2341                 .end    = TEGRA_CL_DVFS_BASE + TEGRA_CL_DVFS_SIZE-1,
2342                 .flags  = IORESOURCE_MEM,
2343         }
2344 };
2345
2346 struct platform_device tegra_cl_dvfs_device = {
2347         .name           = "tegra_cl_dvfs",
2348         .id             = -1,
2349         .resource       = cl_dvfs_resource,
2350         .num_resources  = ARRAY_SIZE(cl_dvfs_resource),
2351 };
2352 #endif
2353
2354 struct platform_device tegra_fuse_device = {
2355         .name   = "tegra-fuse",
2356         .id     = -1,
2357 };
2358
2359 void __init tegra_init_debug_uart_rate(void)
2360 {
2361         unsigned int uartclk;
2362         struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
2363
2364         BUG_ON(IS_ERR(debug_uart_parent));
2365         uartclk = clk_get_rate(debug_uart_parent);
2366
2367         debug_uarta_platform_data[0].uartclk = uartclk;
2368         debug_uartb_platform_data[0].uartclk = uartclk;
2369         debug_uartc_platform_data[0].uartclk = uartclk;
2370         debug_uartd_platform_data[0].uartclk = uartclk;
2371 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2372         debug_uarte_platform_data[0].uartclk = uartclk;
2373 #endif
2374 }