ARM: tegra: Only Tegra3 has TSENSOR
[linux-3.10.git] / arch / arm / mach-tegra / devices.c
1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *      Colin Cross <ccross@android.com>
6  *      Erik Gilling <ccross@android.com>
7  *
8  * Copyright (C) 2010-2011 NVIDIA Corporation.
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21
22 #include <linux/resource.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/fsl_devices.h>
26 #include <linux/serial_8250.h>
27 #include <linux/i2c-tegra.h>
28 #include <linux/tegra_avp.h>
29 #include <mach/irqs.h>
30 #include <linux/usb/tegra_usb_phy.h>
31
32 #include "gpio-names.h"
33 #include "iomap.h"
34 #include "devices.h"
35
36 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
37 #define TEGRA_DMA_REQ_SEL_SPD_I                 3
38 #define TEGRA_DMA_REQ_SEL_I2S2_1                7
39 #define TEGRA_DMA_REQ_SEL_SPI                   11
40 #define TEGRA_DMA_REQ_SEL_DTV                   TEGRA_DMA_REQ_SEL_SPI
41
42 static struct resource gpio_resource[] = {
43         [0] = {
44                 .start  = TEGRA_GPIO_BASE,
45                 .end    = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
46                 .flags  = IORESOURCE_MEM,
47         },
48         [1] = {
49                 .start  = INT_GPIO1,
50                 .end    = INT_GPIO1,
51                 .flags  = IORESOURCE_IRQ,
52         },
53         [2] = {
54                 .start  = INT_GPIO2,
55                 .end    = INT_GPIO2,
56                 .flags  = IORESOURCE_IRQ,
57         },
58         [3] = {
59                 .start  = INT_GPIO3,
60                 .end    = INT_GPIO3,
61                 .flags  = IORESOURCE_IRQ,
62         },
63         [4] = {
64                 .start  = INT_GPIO4,
65                 .end    = INT_GPIO4,
66                 .flags  = IORESOURCE_IRQ,
67         },
68         [5] = {
69                 .start  = INT_GPIO5,
70                 .end    = INT_GPIO5,
71                 .flags  = IORESOURCE_IRQ,
72         },
73         [6] = {
74                 .start  = INT_GPIO6,
75                 .end    = INT_GPIO6,
76                 .flags  = IORESOURCE_IRQ,
77         },
78         [7] = {
79                 .start  = INT_GPIO7,
80                 .end    = INT_GPIO7,
81                 .flags  = IORESOURCE_IRQ,
82         },
83 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
84         [8] = {
85                 .start  = INT_GPIO8,
86                 .end    = INT_GPIO8,
87                 .flags  = IORESOURCE_IRQ,
88         },
89 #endif
90 };
91
92 struct platform_device tegra_gpio_device = {
93         .name           = "tegra-gpio",
94         .id             = -1,
95         .resource       = gpio_resource,
96         .num_resources  = ARRAY_SIZE(gpio_resource),
97 };
98
99 static struct resource pinmux_resource[] = {
100         [0] = {
101                 /* Tri-state registers */
102                 .start  = TEGRA_APB_MISC_BASE + 0x14,
103                 .end    = TEGRA_APB_MISC_BASE + 0x20 + 3,
104                 .flags  = IORESOURCE_MEM,
105         },
106         [1] = {
107                 /* Mux registers */
108                 .start  = TEGRA_APB_MISC_BASE + 0x80,
109                 .end    = TEGRA_APB_MISC_BASE + 0x9c + 3,
110                 .flags  = IORESOURCE_MEM,
111         },
112         [2] = {
113                 /* Pull-up/down registers */
114                 .start  = TEGRA_APB_MISC_BASE + 0xa0,
115                 .end    = TEGRA_APB_MISC_BASE + 0xb0 + 3,
116                 .flags  = IORESOURCE_MEM,
117         },
118         [3] = {
119                 /* Pad control registers */
120                 .start  = TEGRA_APB_MISC_BASE + 0x868,
121                 .end    = TEGRA_APB_MISC_BASE + 0x90c + 3,
122                 .flags  = IORESOURCE_MEM,
123         },
124 };
125
126 struct platform_device tegra_pinmux_device = {
127         .name           = "tegra20-pinctrl",
128         .id             = -1,
129         .resource       = pinmux_resource,
130         .num_resources  = ARRAY_SIZE(pinmux_resource),
131 };
132
133 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
134 #define UART_SOURCE_RATE 408000000
135 #else
136 #define UART_SOURCE_RATE 216000000
137 #endif
138
139 static struct resource i2c_resource1[] = {
140         [0] = {
141                 .start  = INT_I2C,
142                 .end    = INT_I2C,
143                 .flags  = IORESOURCE_IRQ,
144         },
145         [1] = {
146                 .start  = TEGRA_I2C_BASE,
147                 .end    = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
148                 .flags  = IORESOURCE_MEM,
149         },
150 };
151
152 static struct resource i2c_resource2[] = {
153         [0] = {
154                 .start  = INT_I2C2,
155                 .end    = INT_I2C2,
156                 .flags  = IORESOURCE_IRQ,
157         },
158         [1] = {
159                 .start  = TEGRA_I2C2_BASE,
160                 .end    = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
161                 .flags  = IORESOURCE_MEM,
162         },
163 };
164
165 static struct resource i2c_resource3[] = {
166         [0] = {
167                 .start  = INT_I2C3,
168                 .end    = INT_I2C3,
169                 .flags  = IORESOURCE_IRQ,
170         },
171         [1] = {
172                 .start  = TEGRA_I2C3_BASE,
173                 .end    = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
174                 .flags  = IORESOURCE_MEM,
175         },
176 };
177
178 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
179 static struct resource i2c_resource4[] = {
180         [0] = {
181                 .start  = INT_DVC,
182                 .end    = INT_DVC,
183                 .flags  = IORESOURCE_IRQ,
184         },
185         [1] = {
186                 .start  = TEGRA_DVC_BASE,
187                 .end    = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
188                 .flags  = IORESOURCE_MEM,
189         },
190 };
191
192 #else
193 static struct resource i2c_resource4[] = {
194         [0] = {
195                 .start  = INT_I2C4,
196                 .end    = INT_I2C4,
197                 .flags  = IORESOURCE_IRQ,
198         },
199         [1] = {
200                 .start  = TEGRA_I2C4_BASE,
201                 .end    = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
202                 .flags  = IORESOURCE_MEM,
203         },
204 };
205
206 static struct resource i2c_resource5[] = {
207         [0] = {
208                 .start  = INT_I2C5,
209                 .end    = INT_I2C5,
210                 .flags  = IORESOURCE_IRQ,
211         },
212         [1] = {
213                 .start  = TEGRA_I2C5_BASE,
214                 .end    = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
215                 .flags  = IORESOURCE_MEM,
216         },
217 };
218 #endif
219
220 static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
221         .bus_clk_rate   = 400000,
222 };
223
224 static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
225         .bus_clk_rate   = 400000,
226 };
227
228 static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
229         .bus_clk_rate   = 400000,
230 };
231
232 static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
233         .bus_clk_rate   = 400000,
234 };
235
236 struct platform_device tegra_i2c_device1 = {
237         .name           = "tegra-i2c",
238         .id             = 0,
239         .resource       = i2c_resource1,
240         .num_resources  = ARRAY_SIZE(i2c_resource1),
241         .dev = {
242                 .platform_data = &tegra_i2c1_platform_data,
243         },
244 };
245
246 struct platform_device tegra_i2c_device2 = {
247         .name           = "tegra-i2c",
248         .id             = 1,
249         .resource       = i2c_resource2,
250         .num_resources  = ARRAY_SIZE(i2c_resource2),
251         .dev = {
252                 .platform_data = &tegra_i2c2_platform_data,
253         },
254 };
255
256 struct platform_device tegra_i2c_device3 = {
257         .name           = "tegra-i2c",
258         .id             = 2,
259         .resource       = i2c_resource3,
260         .num_resources  = ARRAY_SIZE(i2c_resource3),
261         .dev = {
262                 .platform_data = &tegra_i2c3_platform_data,
263         },
264 };
265
266 struct platform_device tegra_i2c_device4 = {
267         .name           = "tegra-i2c",
268         .id             = 3,
269         .resource       = i2c_resource4,
270         .num_resources  = ARRAY_SIZE(i2c_resource4),
271         .dev = {
272                 .platform_data = &tegra_dvc_platform_data,
273         },
274 };
275
276 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
277 struct platform_device tegra_i2c_device5 = {
278         .name           = "tegra-i2c",
279         .id             = 4,
280         .resource       = i2c_resource5,
281         .num_resources  = ARRAY_SIZE(i2c_resource5),
282         .dev = {
283                 .platform_data = 0,
284         },
285 };
286 #endif
287
288 static struct resource spi_resource1[] = {
289         [0] = {
290                 .start  = INT_SPI_1,
291                 .end    = INT_SPI_1,
292                 .flags  = IORESOURCE_IRQ,
293         },
294         [1] = {
295                 .start  = TEGRA_SPI1_BASE,
296                 .end    = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
297                 .flags  = IORESOURCE_MEM,
298         },
299 };
300
301 static struct resource spi_resource2[] = {
302         [0] = {
303                 .start  = INT_SPI_2,
304                 .end    = INT_SPI_2,
305                 .flags  = IORESOURCE_IRQ,
306         },
307         [1] = {
308                 .start  = TEGRA_SPI2_BASE,
309                 .end    = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
310                 .flags  = IORESOURCE_MEM,
311         },
312 };
313
314 static struct resource spi_resource3[] = {
315         [0] = {
316                 .start  = INT_SPI_3,
317                 .end    = INT_SPI_3,
318                 .flags  = IORESOURCE_IRQ,
319         },
320         [1] = {
321                 .start  = TEGRA_SPI3_BASE,
322                 .end    = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
323                 .flags  = IORESOURCE_MEM,
324         },
325 };
326
327 static struct resource spi_resource4[] = {
328         [0] = {
329                 .start  = INT_SPI_4,
330                 .end    = INT_SPI_4,
331                 .flags  = IORESOURCE_IRQ,
332         },
333         [1] = {
334                 .start  = TEGRA_SPI4_BASE,
335                 .end    = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
336                 .flags  = IORESOURCE_MEM,
337         },
338 };
339 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
340 static struct resource spi_resource5[] = {
341         [0] = {
342                 .start  = INT_SPI_5,
343                 .end    = INT_SPI_5,
344                 .flags  = IORESOURCE_IRQ,
345         },
346         [1] = {
347                 .start  = TEGRA_SPI5_BASE,
348                 .end    = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
349                 .flags  = IORESOURCE_MEM,
350         },
351 };
352
353 static struct resource spi_resource6[] = {
354         [0] = {
355                 .start  = INT_SPI_6,
356                 .end    = INT_SPI_6,
357                 .flags  = IORESOURCE_IRQ,
358         },
359         [1] = {
360                 .start  = TEGRA_SPI6_BASE,
361                 .end    = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
362                 .flags  = IORESOURCE_MEM,
363         },
364 };
365 #endif
366
367 struct platform_device tegra_spi_device1 = {
368         .name           = "spi_tegra",
369         .id             = 0,
370         .resource       = spi_resource1,
371         .num_resources  = ARRAY_SIZE(spi_resource1),
372         .dev            = {
373                 .coherent_dma_mask      = 0xffffffff,
374         },
375 };
376
377 struct platform_device tegra_spi_device2 = {
378         .name           = "spi_tegra",
379         .id             = 1,
380         .resource       = spi_resource2,
381         .num_resources  = ARRAY_SIZE(spi_resource2),
382         .dev            = {
383                 .coherent_dma_mask      = 0xffffffff,
384         },
385 };
386
387 struct platform_device tegra_spi_device3 = {
388         .name           = "spi_tegra",
389         .id             = 2,
390         .resource       = spi_resource3,
391         .num_resources  = ARRAY_SIZE(spi_resource3),
392         .dev            = {
393                 .coherent_dma_mask      = 0xffffffff,
394         },
395 };
396
397 struct platform_device tegra_spi_device4 = {
398         .name           = "spi_tegra",
399         .id             = 3,
400         .resource       = spi_resource4,
401         .num_resources  = ARRAY_SIZE(spi_resource4),
402         .dev            = {
403                 .coherent_dma_mask      = 0xffffffff,
404         },
405 };
406 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
407 struct platform_device tegra_spi_device5 = {
408         .name           = "spi_tegra",
409         .id             = 4,
410         .resource       = spi_resource5,
411         .num_resources  = ARRAY_SIZE(spi_resource5),
412         .dev  = {
413                 .coherent_dma_mask      = 0xffffffff,
414         },
415 };
416
417 struct platform_device tegra_spi_device6 = {
418         .name           = "spi_tegra",
419         .id             = 5,
420         .resource       = spi_resource6,
421         .num_resources  = ARRAY_SIZE(spi_resource6),
422         .dev  = {
423                 .coherent_dma_mask      = 0xffffffff,
424         },
425 };
426 #endif
427
428 struct platform_device tegra_spi_slave_device1 = {
429         .name           = "spi_slave_tegra",
430         .id             = 0,
431         .resource       = spi_resource1,
432         .num_resources  = ARRAY_SIZE(spi_resource1),
433         .dev  = {
434                 .coherent_dma_mask      = 0xffffffff,
435         },
436 };
437
438 struct platform_device tegra_spi_slave_device2 = {
439         .name           = "spi_slave_tegra",
440         .id             = 1,
441         .resource       = spi_resource2,
442         .num_resources  = ARRAY_SIZE(spi_resource2),
443         .dev  = {
444                 .coherent_dma_mask      = 0xffffffff,
445         },
446 };
447
448 struct platform_device tegra_spi_slave_device3 = {
449         .name           = "spi_slave_tegra",
450         .id             = 2,
451         .resource       = spi_resource3,
452         .num_resources  = ARRAY_SIZE(spi_resource3),
453         .dev  = {
454                 .coherent_dma_mask      = 0xffffffff,
455         },
456 };
457
458 struct platform_device tegra_spi_slave_device4 = {
459         .name           = "spi_slave_tegra",
460         .id             = 3,
461         .resource       = spi_resource4,
462         .num_resources  = ARRAY_SIZE(spi_resource4),
463         .dev  = {
464                 .coherent_dma_mask      = 0xffffffff,
465         },
466 };
467 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
468 struct platform_device tegra_spi_slave_device5 = {
469         .name           = "spi_slave_tegra",
470         .id             = 4,
471         .resource       = spi_resource5,
472         .num_resources  = ARRAY_SIZE(spi_resource5),
473         .dev  = {
474                 .coherent_dma_mask      = 0xffffffff,
475         },
476 };
477
478 struct platform_device tegra_spi_slave_device6 = {
479         .name           = "spi_slave_tegra",
480         .id             = 5,
481         .resource       = spi_resource6,
482         .num_resources  = ARRAY_SIZE(spi_resource6),
483         .dev  = {
484                 .coherent_dma_mask      = 0xffffffff,
485         },
486 };
487 #endif
488
489
490
491 static struct resource sdhci_resource1[] = {
492         [0] = {
493                 .start  = INT_SDMMC1,
494                 .end    = INT_SDMMC1,
495                 .flags  = IORESOURCE_IRQ,
496         },
497         [1] = {
498                 .start  = TEGRA_SDMMC1_BASE,
499                 .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
500                 .flags  = IORESOURCE_MEM,
501         },
502 };
503
504 static struct resource sdhci_resource2[] = {
505         [0] = {
506                 .start  = INT_SDMMC2,
507                 .end    = INT_SDMMC2,
508                 .flags  = IORESOURCE_IRQ,
509         },
510         [1] = {
511                 .start  = TEGRA_SDMMC2_BASE,
512                 .end    = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
513                 .flags  = IORESOURCE_MEM,
514         },
515 };
516
517 static struct resource sdhci_resource3[] = {
518         [0] = {
519                 .start  = INT_SDMMC3,
520                 .end    = INT_SDMMC3,
521                 .flags  = IORESOURCE_IRQ,
522         },
523         [1] = {
524                 .start  = TEGRA_SDMMC3_BASE,
525                 .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
526                 .flags  = IORESOURCE_MEM,
527         },
528 };
529
530 static struct resource sdhci_resource4[] = {
531         [0] = {
532                 .start  = INT_SDMMC4,
533                 .end    = INT_SDMMC4,
534                 .flags  = IORESOURCE_IRQ,
535         },
536         [1] = {
537                 .start  = TEGRA_SDMMC4_BASE,
538                 .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
539                 .flags  = IORESOURCE_MEM,
540         },
541 };
542
543 /* board files should fill in platform_data register the devices themselvs.
544  * See board-harmony.c for an example
545  */
546 struct platform_device tegra_sdhci_device1 = {
547         .name           = "sdhci-tegra",
548         .id             = 0,
549         .resource       = sdhci_resource1,
550         .num_resources  = ARRAY_SIZE(sdhci_resource1),
551 };
552
553 struct platform_device tegra_sdhci_device2 = {
554         .name           = "sdhci-tegra",
555         .id             = 1,
556         .resource       = sdhci_resource2,
557         .num_resources  = ARRAY_SIZE(sdhci_resource2),
558 };
559
560 struct platform_device tegra_sdhci_device3 = {
561         .name           = "sdhci-tegra",
562         .id             = 2,
563         .resource       = sdhci_resource3,
564         .num_resources  = ARRAY_SIZE(sdhci_resource3),
565 };
566
567 struct platform_device tegra_sdhci_device4 = {
568         .name           = "sdhci-tegra",
569         .id             = 3,
570         .resource       = sdhci_resource4,
571         .num_resources  = ARRAY_SIZE(sdhci_resource4),
572 };
573
574 static struct resource tegra_usb1_resources[] = {
575         [0] = {
576                 .start  = TEGRA_USB_BASE,
577                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
578                 .flags  = IORESOURCE_MEM,
579         },
580         [1] = {
581                 .start  = INT_USB,
582                 .end    = INT_USB,
583                 .flags  = IORESOURCE_IRQ,
584         },
585 };
586
587 static struct resource tegra_usb2_resources[] = {
588         [0] = {
589                 .start  = TEGRA_USB2_BASE,
590                 .end    = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
591                 .flags  = IORESOURCE_MEM,
592         },
593         [1] = {
594                 .start  = INT_USB2,
595                 .end    = INT_USB2,
596                 .flags  = IORESOURCE_IRQ,
597         },
598 };
599
600 static struct resource tegra_usb3_resources[] = {
601         [0] = {
602                 .start  = TEGRA_USB3_BASE,
603                 .end    = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
604                 .flags  = IORESOURCE_MEM,
605         },
606         [1] = {
607                 .start  = INT_USB3,
608                 .end    = INT_USB3,
609                 .flags  = IORESOURCE_IRQ,
610         },
611 };
612
613 struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
614         .reset_gpio = -1,
615         .clk = "cdev2",
616 };
617
618 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
619         .operating_mode = TEGRA_USB_OTG,
620         .power_down_on_bus_suspend = 1,
621         .vbus_gpio = -1,
622 };
623
624 struct tegra_ehci_platform_data tegra_ehci2_pdata = {
625         .phy_config = &tegra_ehci2_ulpi_phy_config,
626         .operating_mode = TEGRA_USB_HOST,
627         .power_down_on_bus_suspend = 1,
628         .vbus_gpio = -1,
629 };
630
631 struct tegra_ehci_platform_data tegra_ehci3_pdata = {
632         .operating_mode = TEGRA_USB_HOST,
633         .power_down_on_bus_suspend = 1,
634         .vbus_gpio = -1,
635 };
636
637 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
638
639 struct platform_device tegra_ehci1_device = {
640         .name   = "tegra-ehci",
641         .id     = 0,
642         .dev    = {
643                 .dma_mask       = &tegra_ehci_dmamask,
644                 .coherent_dma_mask = DMA_BIT_MASK(32),
645                 .platform_data = &tegra_ehci1_pdata,
646         },
647         .resource = tegra_usb1_resources,
648         .num_resources = ARRAY_SIZE(tegra_usb1_resources),
649 };
650
651 struct platform_device tegra_ehci2_device = {
652         .name   = "tegra-ehci",
653         .id     = 1,
654         .dev    = {
655                 .dma_mask       = &tegra_ehci_dmamask,
656                 .coherent_dma_mask = DMA_BIT_MASK(32),
657                 .platform_data = &tegra_ehci2_pdata,
658         },
659         .resource = tegra_usb2_resources,
660         .num_resources = ARRAY_SIZE(tegra_usb2_resources),
661 };
662
663 struct platform_device tegra_ehci3_device = {
664         .name   = "tegra-ehci",
665         .id     = 2,
666         .dev    = {
667                 .dma_mask       = &tegra_ehci_dmamask,
668                 .coherent_dma_mask = DMA_BIT_MASK(32),
669                 .platform_data = &tegra_ehci3_pdata,
670         },
671         .resource = tegra_usb3_resources,
672         .num_resources = ARRAY_SIZE(tegra_usb3_resources),
673 };
674
675 static struct resource tegra_pmu_resources[] = {
676         [0] = {
677                 .start  = INT_CPU0_PMU_INTR,
678                 .end    = INT_CPU0_PMU_INTR,
679                 .flags  = IORESOURCE_IRQ,
680         },
681         [1] = {
682                 .start  = INT_CPU1_PMU_INTR,
683                 .end    = INT_CPU1_PMU_INTR,
684                 .flags  = IORESOURCE_IRQ,
685         },
686 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
687         [2] = {
688                 .start  = INT_CPU2_PMU_INTR,
689                 .end    = INT_CPU2_PMU_INTR,
690                 .flags  = IORESOURCE_IRQ,
691         },
692         [3] = {
693                 .start  = INT_CPU3_PMU_INTR,
694                 .end    = INT_CPU3_PMU_INTR,
695                 .flags  = IORESOURCE_IRQ,
696         },
697 #endif
698 };
699
700 struct platform_device tegra_pmu_device = {
701         .name           = "arm-pmu",
702         .id             = -1,
703         .num_resources  = ARRAY_SIZE(tegra_pmu_resources),
704         .resource       = tegra_pmu_resources,
705 };
706
707 static struct resource tegra_uarta_resources[] = {
708         [0] = {
709                 .start  = TEGRA_UARTA_BASE,
710                 .end    = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
711                 .flags  = IORESOURCE_MEM,
712         },
713         [1] = {
714                 .start  = INT_UARTA,
715                 .end    = INT_UARTA,
716                 .flags  = IORESOURCE_IRQ,
717         },
718 };
719
720 static struct resource tegra_uartb_resources[] = {
721         [0] = {
722                 .start  = TEGRA_UARTB_BASE,
723                 .end    = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
724                 .flags  = IORESOURCE_MEM,
725         },
726         [1] = {
727                 .start  = INT_UARTB,
728                 .end    = INT_UARTB,
729                 .flags  = IORESOURCE_IRQ,
730         },
731 };
732
733 static struct resource tegra_uartc_resources[] = {
734         [0] = {
735                 .start  = TEGRA_UARTC_BASE,
736                 .end    = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
737                 .flags  = IORESOURCE_MEM,
738         },
739         [1] = {
740                 .start  = INT_UARTC,
741                 .end    = INT_UARTC,
742                 .flags  = IORESOURCE_IRQ,
743         },
744 };
745
746 static struct resource tegra_uartd_resources[] = {
747         [0] = {
748                 .start  = TEGRA_UARTD_BASE,
749                 .end    = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
750                 .flags  = IORESOURCE_MEM,
751         },
752         [1] = {
753                 .start  = INT_UARTD,
754                 .end    = INT_UARTD,
755                 .flags  = IORESOURCE_IRQ,
756         },
757 };
758
759 static struct resource tegra_uarte_resources[] = {
760         [0] = {
761                 .start  = TEGRA_UARTE_BASE,
762                 .end    = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
763                 .flags  = IORESOURCE_MEM,
764         },
765         [1] = {
766                 .start  = INT_UARTE,
767                 .end    = INT_UARTE,
768                 .flags  = IORESOURCE_IRQ,
769         },
770 };
771
772 struct platform_device tegra_uarta_device = {
773         .name   = "tegra_uart",
774         .id     = 0,
775         .num_resources  = ARRAY_SIZE(tegra_uarta_resources),
776         .resource       = tegra_uarta_resources,
777         .dev    = {
778                 .coherent_dma_mask      = DMA_BIT_MASK(32),
779         },
780 };
781
782 struct platform_device tegra_uartb_device = {
783         .name   = "tegra_uart",
784         .id     = 1,
785         .num_resources  = ARRAY_SIZE(tegra_uartb_resources),
786         .resource       = tegra_uartb_resources,
787         .dev    = {
788                 .coherent_dma_mask      = DMA_BIT_MASK(32),
789         },
790 };
791
792 struct platform_device tegra_uartc_device = {
793         .name   = "tegra_uart",
794         .id     = 2,
795         .num_resources  = ARRAY_SIZE(tegra_uartc_resources),
796         .resource       = tegra_uartc_resources,
797         .dev    = {
798                 .coherent_dma_mask      = DMA_BIT_MASK(32),
799         },
800 };
801
802 struct platform_device tegra_uartd_device = {
803         .name   = "tegra_uart",
804         .id     = 3,
805         .num_resources  = ARRAY_SIZE(tegra_uartd_resources),
806         .resource       = tegra_uartd_resources,
807         .dev    = {
808                 .coherent_dma_mask      = DMA_BIT_MASK(32),
809         },
810 };
811
812 struct platform_device tegra_uarte_device = {
813         .name   = "tegra_uart",
814         .id     = 4,
815         .num_resources  = ARRAY_SIZE(tegra_uarte_resources),
816         .resource       = tegra_uarte_resources,
817         .dev    = {
818                 .coherent_dma_mask      = DMA_BIT_MASK(32),
819         },
820 };
821
822 static struct plat_serial8250_port debug_uarta_platform_data[] = {
823         {
824                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
825                 .mapbase        = TEGRA_UARTA_BASE,
826                 .irq            = INT_UARTA,
827                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
828                 .type           = PORT_TEGRA,
829                 .iotype         = UPIO_MEM,
830                 .regshift       = 2,
831                 .uartclk        = UART_SOURCE_RATE,
832         },
833         {
834                 .flags          = 0,
835         },
836 };
837
838 static struct plat_serial8250_port debug_uartb_platform_data[] = {
839         {
840                 .membase        = IO_ADDRESS(TEGRA_UARTB_BASE),
841                 .mapbase        = TEGRA_UARTB_BASE,
842                 .irq            = INT_UARTB,
843                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
844                 .type           = PORT_TEGRA,
845                 .iotype         = UPIO_MEM,
846                 .regshift       = 2,
847                 .uartclk        = UART_SOURCE_RATE,
848         },
849         {
850                 .flags          = 0,
851         },
852 };
853
854 static struct plat_serial8250_port debug_uartc_platform_data[] = {
855         {
856                 .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
857                 .mapbase        = TEGRA_UARTC_BASE,
858                 .irq            = INT_UARTC,
859                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
860                 .type           = PORT_TEGRA,
861                 .iotype         = UPIO_MEM,
862                 .regshift       = 2,
863                 .uartclk        = UART_SOURCE_RATE,
864         },
865         {
866                 .flags          = 0,
867         },
868 };
869
870 static struct plat_serial8250_port debug_uartd_platform_data[] = {
871         {
872                 .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
873                 .mapbase        = TEGRA_UARTD_BASE,
874                 .irq            = INT_UARTD,
875                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
876                 .type           = PORT_TEGRA,
877                 .iotype         = UPIO_MEM,
878                 .regshift       = 2,
879                 .uartclk        = UART_SOURCE_RATE,
880         },
881         {
882                 .flags          = 0,
883         },
884 };
885
886 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
887 static struct plat_serial8250_port debug_uarte_platform_data[] = {
888         {
889                 .membase        = IO_ADDRESS(TEGRA_UARTE_BASE),
890                 .mapbase        = TEGRA_UARTE_BASE,
891                 .irq            = INT_UARTE,
892                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
893                 .type           = PORT_TEGRA,
894                 .iotype         = UPIO_MEM,
895                 .regshift       = 2,
896                 .uartclk        = UART_SOURCE_RATE,
897         },
898         {
899                 .flags          = 0,
900         },
901 };
902 #endif
903
904 struct platform_device debug_uarta_device = {
905         .name = "serial8250",
906         .id = PLAT8250_DEV_PLATFORM,
907         .dev = {
908                 .platform_data = debug_uarta_platform_data,
909         },
910 };
911
912 struct platform_device debug_uartb_device = {
913         .name = "serial8250",
914         .id = PLAT8250_DEV_PLATFORM,
915         .dev = {
916                 .platform_data = debug_uartb_platform_data,
917         },
918 };
919
920 struct platform_device debug_uartc_device = {
921         .name = "serial8250",
922         .id = PLAT8250_DEV_PLATFORM,
923         .dev = {
924                 .platform_data = debug_uartc_platform_data,
925         },
926 };
927
928 struct platform_device debug_uartd_device = {
929         .name = "serial8250",
930         .id = PLAT8250_DEV_PLATFORM,
931         .dev = {
932                 .platform_data = debug_uartd_platform_data,
933         },
934 };
935
936 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
937 struct platform_device debug_uarte_device = {
938         .name = "serial8250",
939         .id = PLAT8250_DEV_PLATFORM,
940         .dev = {
941                 .platform_data = debug_uarte_platform_data,
942         },
943 };
944 #endif
945
946 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
947 static struct resource i2s_resource1[] = {
948         [0] = {
949                 .start  = INT_I2S1,
950                 .end    = INT_I2S1,
951                 .flags  = IORESOURCE_IRQ
952         },
953         [1] = {
954                 .start  = TEGRA_DMA_REQ_SEL_I2S_1,
955                 .end    = TEGRA_DMA_REQ_SEL_I2S_1,
956                 .flags  = IORESOURCE_DMA
957         },
958         [2] = {
959                 .start  = TEGRA_I2S1_BASE,
960                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
961                 .flags  = IORESOURCE_MEM
962         }
963 };
964
965 struct platform_device tegra_i2s_device1 = {
966         .name           = "tegra20-i2s",
967         .id             = 0,
968         .resource       = i2s_resource1,
969         .num_resources  = ARRAY_SIZE(i2s_resource1),
970 };
971
972 static struct resource i2s_resource2[] = {
973         [0] = {
974                 .start  = INT_I2S2,
975                 .end    = INT_I2S2,
976                 .flags  = IORESOURCE_IRQ
977         },
978         [1] = {
979                 .start  = TEGRA_DMA_REQ_SEL_I2S2_1,
980                 .end    = TEGRA_DMA_REQ_SEL_I2S2_1,
981                 .flags  = IORESOURCE_DMA
982         },
983         [2] = {
984                 .start  = TEGRA_I2S2_BASE,
985                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
986                 .flags  = IORESOURCE_MEM
987         }
988 };
989
990 struct platform_device tegra_i2s_device2 = {
991         .name           = "tegra20-i2s",
992         .id             = 1,
993         .resource       = i2s_resource2,
994         .num_resources  = ARRAY_SIZE(i2s_resource2),
995 };
996 #else
997 static struct resource i2s_resource0[] = {
998         [0] = {
999                 .start  = TEGRA_I2S0_BASE,
1000                 .end    = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
1001                 .flags  = IORESOURCE_MEM
1002         }
1003 };
1004
1005 struct platform_device tegra_i2s_device0 = {
1006         .name           = "tegra30-i2s",
1007         .id             = 0,
1008         .resource       = i2s_resource0,
1009         .num_resources  = ARRAY_SIZE(i2s_resource0),
1010 };
1011
1012 static struct resource i2s_resource1[] = {
1013         [0] = {
1014                 .start  = TEGRA_I2S1_BASE,
1015                 .end    = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
1016                 .flags  = IORESOURCE_MEM
1017         }
1018 };
1019
1020 struct platform_device tegra_i2s_device1 = {
1021         .name           = "tegra30-i2s",
1022         .id             = 1,
1023         .resource       = i2s_resource1,
1024         .num_resources  = ARRAY_SIZE(i2s_resource1),
1025 };
1026
1027 static struct resource i2s_resource2[] = {
1028         [0] = {
1029                 .start  = TEGRA_I2S2_BASE,
1030                 .end    = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
1031                 .flags  = IORESOURCE_MEM
1032         }
1033 };
1034
1035 struct platform_device tegra_i2s_device2 = {
1036         .name           = "tegra30-i2s",
1037         .id             = 2,
1038         .resource       = i2s_resource2,
1039         .num_resources  = ARRAY_SIZE(i2s_resource2),
1040 };
1041
1042 static struct resource i2s_resource3[] = {
1043         [0] = {
1044                 .start  = TEGRA_I2S3_BASE,
1045                 .end    = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1046                 .flags  = IORESOURCE_MEM
1047         }
1048 };
1049
1050 struct platform_device tegra_i2s_device3 = {
1051         .name           = "tegra30-i2s",
1052         .id             = 3,
1053         .resource       = i2s_resource3,
1054         .num_resources  = ARRAY_SIZE(i2s_resource3),
1055 };
1056
1057 static struct resource i2s_resource4[] = {
1058         [0] = {
1059                 .start  = TEGRA_I2S4_BASE,
1060                 .end    = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1061                 .flags  = IORESOURCE_MEM
1062         }
1063 };
1064
1065 struct platform_device tegra_i2s_device4 = {
1066         .name           = "tegra30-i2s",
1067         .id             = 4,
1068         .resource       = i2s_resource4,
1069         .num_resources  = ARRAY_SIZE(i2s_resource4),
1070 };
1071 #endif
1072
1073 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1074 static struct resource spdif_resource[] = {
1075         [0] = {
1076                 .start  = INT_SPDIF,
1077                 .end    = INT_SPDIF,
1078                 .flags  = IORESOURCE_IRQ
1079         },
1080         [1] = {
1081                 .start  = TEGRA_DMA_REQ_SEL_SPD_I,
1082                 .end    = TEGRA_DMA_REQ_SEL_SPD_I,
1083                 .flags  = IORESOURCE_DMA
1084         },
1085         [2] = {
1086                 .start  = TEGRA_SPDIF_BASE,
1087                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1088                 .flags  = IORESOURCE_MEM
1089         }
1090 };
1091 #else
1092 /* FIXME : Temporarly adding - find the right solution */
1093
1094 static struct resource spdif_resource[] = {
1095         [0] = {
1096                 .start  = TEGRA_DMA_REQ_SEL_APBIF_CH3,
1097                 .end    = TEGRA_DMA_REQ_SEL_APBIF_CH3,
1098                 .flags  = IORESOURCE_DMA
1099         },
1100         [1] = {
1101                 .start  = TEGRA_SPDIF_BASE,
1102                 .end    = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1103                 .flags  = IORESOURCE_MEM
1104         }
1105 };
1106 #endif
1107
1108 struct platform_device tegra_spdif_device = {
1109         .name           = "spdif_out",
1110         .id             = -1,
1111         .resource       = spdif_resource,
1112         .num_resources  = ARRAY_SIZE(spdif_resource),
1113 };
1114
1115 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1116 static struct resource ahub_resource[] = {
1117         [0] = {
1118                 .start  = TEGRA_APBIF0_BASE,
1119                 .end    = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1120                 .flags  = IORESOURCE_MEM
1121         },
1122         [1] = {
1123                 .start  = TEGRA_AHUB_BASE,
1124                 .end    = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1125                 .flags  = IORESOURCE_MEM
1126         }
1127 };
1128
1129 struct platform_device tegra_ahub_device = {
1130         .name   = "tegra30-ahub",
1131         .id     = -1,
1132         .resource       = ahub_resource,
1133         .num_resources  = ARRAY_SIZE(ahub_resource),
1134 };
1135 #endif
1136
1137 #if defined(CONFIG_SND_HDA_TEGRA)
1138 static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1139
1140 static struct resource tegra_hda_resources[] = {
1141         [0] = {
1142                 .start  = TEGRA_HDA_BASE,
1143                 .end    = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1 ,
1144                 .flags  = IORESOURCE_MEM
1145         },
1146         [1] = {
1147                 .start  = INT_HDA,
1148                 .end    = INT_HDA,
1149                 .flags  = IORESOURCE_IRQ
1150         },
1151 };
1152
1153 struct platform_device tegra_hda_device = {
1154         .name           = "tegra-hda",
1155         .id             = 0,
1156         .dev = {
1157                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1158                 .dma_mask               = &tegra_hda_dma_mask,
1159         },
1160         .resource       = tegra_hda_resources,
1161         .num_resources  = ARRAY_SIZE(tegra_hda_resources),
1162 };
1163 #endif
1164
1165 static struct resource w1_resources[] = {
1166         [0] = {
1167                 .start = INT_OWR,
1168                 .end   = INT_OWR,
1169                 .flags = IORESOURCE_IRQ
1170         },
1171         [1] = {
1172                 .start = TEGRA_OWR_BASE,
1173                 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1174                 .flags = IORESOURCE_MEM
1175         }
1176 };
1177
1178 struct platform_device tegra_w1_device = {
1179         .name          = "tegra_w1",
1180         .id            = -1,
1181         .resource      = w1_resources,
1182         .num_resources = ARRAY_SIZE(w1_resources),
1183 };
1184
1185 static struct resource tegra_udc_resources[] = {
1186         [0] = {
1187                 .start  = TEGRA_USB_BASE,
1188                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1189                 .flags  = IORESOURCE_MEM,
1190         },
1191         [1] = {
1192                 .start  = INT_USB,
1193                 .end    = INT_USB,
1194                 .flags  = IORESOURCE_IRQ,
1195         },
1196 };
1197
1198 static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1199
1200 static struct fsl_usb2_platform_data tegra_udc_pdata = {
1201         .operating_mode = FSL_USB2_DR_DEVICE,
1202         .phy_mode       = FSL_USB2_PHY_UTMI,
1203 };
1204
1205 struct platform_device tegra_udc_device = {
1206         .name   = "fsl-tegra-udc",
1207         .id     = -1,
1208         .dev    = {
1209                 .dma_mask       = &tegra_udc_dmamask,
1210                 .coherent_dma_mask = DMA_BIT_MASK(32),
1211                 .platform_data  = &tegra_udc_pdata,
1212         },
1213         .resource = tegra_udc_resources,
1214         .num_resources = ARRAY_SIZE(tegra_udc_resources),
1215 };
1216
1217 static struct resource tegra_otg_resources[] = {
1218         [0] = {
1219                 .start  = TEGRA_USB_BASE,
1220                 .end    = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1221                 .flags  = IORESOURCE_MEM,
1222         },
1223         [1] = {
1224                 .start  = INT_USB,
1225                 .end    = INT_USB,
1226                 .flags  = IORESOURCE_IRQ,
1227         },
1228 };
1229
1230 struct platform_device tegra_otg_device = {
1231         .name           = "tegra-otg",
1232         .id             = -1,
1233         .resource       = tegra_otg_resources,
1234         .num_resources  = ARRAY_SIZE(tegra_otg_resources),
1235 };
1236
1237 #ifdef CONFIG_SATA_AHCI_TEGRA
1238 static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1239
1240 static struct resource tegra_sata_resources[] = {
1241         [0] = {
1242                 .start = TEGRA_SATA_BAR5_BASE,
1243                 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1244                 .flags = IORESOURCE_MEM,
1245         },
1246         [1] = {
1247                 .start = TEGRA_SATA_CONFIG_BASE,
1248                 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1249                 .flags = IORESOURCE_MEM,
1250         },
1251         [2] = {
1252                 .start = INT_SATA_CTL,
1253                 .end = INT_SATA_CTL,
1254                 .flags = IORESOURCE_IRQ,
1255         },
1256 };
1257
1258 struct platform_device tegra_sata_device = {
1259         .name   = "tegra-sata",
1260         .id     = 0,
1261         .dev    = {
1262                 .platform_data = 0,
1263                 .coherent_dma_mask = DMA_BIT_MASK(32),
1264                 .dma_mask = &tegra_sata_dma_mask,
1265         },
1266         .resource = tegra_sata_resources,
1267         .num_resources = ARRAY_SIZE(tegra_sata_resources),
1268 };
1269 #endif
1270
1271 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1272 static struct resource das_resource[] = {
1273         [0] = {
1274                 .start  = TEGRA_APB_MISC_BASE,
1275                 .end    = TEGRA_APB_MISC_BASE + TEGRA_APB_MISC_SIZE - 1,
1276                 .flags  = IORESOURCE_MEM
1277         }
1278 };
1279
1280 struct platform_device tegra_das_device = {
1281         .name           = "tegra20-das",
1282         .id             = -1,
1283         .resource       = das_resource,
1284         .num_resources  = ARRAY_SIZE(das_resource),
1285 };
1286 #endif
1287
1288 #if defined(CONFIG_TEGRA_IOVMM_GART)
1289 static struct resource tegra_gart_resources[] = {
1290         [0] = {
1291                 .name   = "mc",
1292                 .flags  = IORESOURCE_MEM,
1293                 .start  = TEGRA_MC_BASE,
1294                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1295         },
1296         [1] = {
1297                 .name   = "gart",
1298                 .flags  = IORESOURCE_MEM,
1299                 .start  = TEGRA_GART_BASE,
1300                 .end    = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1301         }
1302 };
1303
1304 struct platform_device tegra_gart_device = {
1305         .name           = "tegra_gart",
1306         .id             = -1,
1307         .num_resources  = ARRAY_SIZE(tegra_gart_resources),
1308         .resource       = tegra_gart_resources
1309 };
1310 #endif
1311
1312 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
1313 static struct resource tegra_smmu_resources[] = {
1314         [0] = {
1315                 .name   = "mc",
1316                 .flags  = IORESOURCE_MEM,
1317                 .start  = TEGRA_MC_BASE,
1318                 .end    = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1319         },
1320         [1] = {
1321                 .name   = "smmu",
1322                 .flags  = IORESOURCE_MEM,
1323                 .start  = TEGRA_SMMU_BASE,
1324                 .end    = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1325         },
1326         [2] = {
1327                 .name   = "ahbarb",
1328                 .flags  = IORESOURCE_MEM,
1329                 .start  = TEGRA_AHB_ARB_BASE,
1330                 .end    = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1331         }
1332 };
1333
1334 struct platform_device tegra_smmu_device = {
1335         .name           = "tegra_smmu",
1336         .id             = -1,
1337         .num_resources  = ARRAY_SIZE(tegra_smmu_resources),
1338         .resource       = tegra_smmu_resources
1339 };
1340 #endif
1341
1342 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1343 #define CLK_RESET_RST_SOURCE    0x0
1344 static struct resource tegra_wdt_resources[] = {
1345         [0] = {
1346                 .start  = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1347                 .end    = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1348                 .flags  = IORESOURCE_MEM,
1349         },
1350         [1] = {
1351                 .start  = TEGRA_TMR1_BASE,
1352                 .end    = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1353                 .flags  = IORESOURCE_MEM,
1354         },
1355         [2] = {
1356                 .start  = INT_TMR1,
1357                 .end    = INT_TMR1,
1358                 .flags  = IORESOURCE_IRQ,
1359         },
1360 };
1361 #else
1362 static struct resource tegra_wdt_resources[] = {
1363         [0] = {
1364                 .start  = TEGRA_WDT0_BASE,
1365                 .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1366                 .flags  = IORESOURCE_MEM,
1367         },
1368         [1] = {
1369                 .start  = TEGRA_TMR10_BASE,
1370                 .end    = TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
1371                 .flags  = IORESOURCE_MEM,
1372         },
1373         [2] = {
1374                 .start  = INT_WDT_CPU,
1375                 .end    = INT_WDT_CPU,
1376                 .flags  = IORESOURCE_IRQ,
1377         },
1378 };
1379 #endif
1380
1381 struct platform_device tegra_wdt_device = {
1382         .name           = "tegra_wdt",
1383         .id             = -1,
1384         .num_resources  = ARRAY_SIZE(tegra_wdt_resources),
1385         .resource       = tegra_wdt_resources,
1386 };
1387
1388 static struct resource tegra_pwfm_resource = {
1389         .start  = TEGRA_PWFM_BASE,
1390         .end    = TEGRA_PWFM_BASE + TEGRA_PWFM_SIZE - 1,
1391         .flags  = IORESOURCE_MEM,
1392 };
1393
1394 struct platform_device tegra_pwfm_device = {
1395         .name           = "tegra-pwm",
1396         .id             = 0,
1397         .num_resources  = 1,
1398         .resource       = &tegra_pwfm_resource,
1399 };
1400
1401 static struct resource tegra_grhost_resources[] = {
1402         {
1403                 .start = TEGRA_HOST1X_BASE,
1404                 .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
1405                 .flags = IORESOURCE_MEM,
1406         },
1407         {
1408                 .start = TEGRA_DISPLAY_BASE,
1409                 .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
1410                 .flags = IORESOURCE_MEM,
1411         },
1412         {
1413                 .start = TEGRA_DISPLAY2_BASE,
1414                 .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
1415                 .flags = IORESOURCE_MEM,
1416         },
1417         {
1418                 .start = TEGRA_VI_BASE,
1419                 .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
1420                 .flags = IORESOURCE_MEM,
1421         },
1422         {
1423                 .start = TEGRA_ISP_BASE,
1424                 .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
1425                 .flags = IORESOURCE_MEM,
1426         },
1427         {
1428                 .start = TEGRA_MPE_BASE,
1429                 .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
1430                 .flags = IORESOURCE_MEM,
1431         },
1432         {
1433                 .start = INT_SYNCPT_THRESH_BASE,
1434                 .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
1435                 .flags = IORESOURCE_IRQ,
1436         },
1437         {
1438                 .start = INT_HOST1X_MPCORE_GENERAL,
1439                 .end = INT_HOST1X_MPCORE_GENERAL,
1440                 .flags = IORESOURCE_IRQ,
1441         },
1442 };
1443
1444 struct platform_device tegra_grhost_device = {
1445         .name = "tegra_grhost",
1446         .id = -1,
1447         .resource = tegra_grhost_resources,
1448         .num_resources = ARRAY_SIZE(tegra_grhost_resources),
1449 };
1450
1451 static struct tegra_avp_platform_data tegra_avp_pdata = {
1452 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1453         .emc_clk_rate = ULONG_MAX,
1454 #else
1455         .emc_clk_rate = 200000000,
1456 #endif
1457 };
1458
1459 static struct resource tegra_avp_resources[] = {
1460         [0] = {
1461                 .start  = INT_SHR_SEM_INBOX_IBF,
1462                 .end    = INT_SHR_SEM_INBOX_IBF,
1463                 .flags  = IORESOURCE_IRQ,
1464                 .name   = "mbox_from_avp_pending",
1465         },
1466 };
1467
1468 struct platform_device tegra_avp_device = {
1469         .name           = "tegra-avp",
1470         .id             = -1,
1471         .num_resources  = ARRAY_SIZE(tegra_avp_resources),
1472         .resource       = tegra_avp_resources,
1473         .dev  = {
1474                 .coherent_dma_mask      = 0xffffffffULL,
1475                 .platform_data          = &tegra_avp_pdata,
1476         },
1477 };
1478
1479 static struct resource tegra_aes_resources[] = {
1480         {
1481                 .start  = TEGRA_VDE_BASE,
1482                 .end    = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1483                 .flags  = IORESOURCE_MEM,
1484         },
1485         {
1486                 .start  = TEGRA_BSEA_BASE,
1487                 .end    = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1488                 .flags  = IORESOURCE_MEM,
1489         },
1490 };
1491
1492 static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1493
1494 struct platform_device tegra_aes_device = {
1495         .name           = "tegra-aes",
1496         .id             = -1,
1497         .resource       = tegra_aes_resources,
1498         .num_resources  = ARRAY_SIZE(tegra_aes_resources),
1499         .dev    = {
1500                 .dma_mask = &tegra_aes_dma_mask,
1501                 .coherent_dma_mask = DMA_BIT_MASK(32),
1502         },
1503 };
1504
1505 static struct resource tegra_kbc_resources[] = {
1506         [0] = {
1507                 .start = TEGRA_KBC_BASE,
1508                 .end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1509                 .flags = IORESOURCE_MEM,
1510         },
1511         [1] = {
1512                 .start = INT_KBC,
1513                 .end   = INT_KBC,
1514                 .flags = IORESOURCE_IRQ,
1515         },
1516 };
1517
1518 struct platform_device tegra_kbc_device = {
1519         .name = "tegra-kbc",
1520         .id = -1,
1521         .resource = tegra_kbc_resources,
1522         .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1523         .dev = {
1524                 .platform_data = 0,
1525         },
1526 };
1527
1528 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1529 static struct resource tegra_tsensor_resources[]= {
1530         {
1531                 .start  = TEGRA_TSENSOR_BASE,
1532                 .end    = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1533                 .flags  = IORESOURCE_MEM,
1534         },
1535         {
1536                 .start  = INT_TSENSOR,
1537                 .end    = INT_TSENSOR,
1538                 .flags  = IORESOURCE_IRQ,
1539         },
1540         {
1541                 .start  = TEGRA_PMC_BASE + 0x1B0,
1542                 /* 2 pmc registers mapped */
1543                 .end    = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
1544                 .flags  = IORESOURCE_MEM,
1545         },
1546 };
1547
1548 struct platform_device tegra_tsensor_device = {
1549         .name   = "tegra-tsensor",
1550         .id     = -1,
1551         .num_resources  = ARRAY_SIZE(tegra_tsensor_resources),
1552         .resource       = tegra_tsensor_resources,
1553         .dev = {
1554                 .platform_data = 0,
1555         },
1556 };
1557 #endif
1558
1559 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1560 static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
1561
1562 struct resource tegra_se_resources[] = {
1563         [0] = {
1564                 .start = TEGRA_SE_BASE,
1565                 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
1566                 .flags = IORESOURCE_MEM,
1567         },
1568         [1] = {
1569                 .start  = TEGRA_PMC_BASE,
1570                 .end    = TEGRA_PMC_BASE + SZ_256 - 1,
1571                 .flags  = IORESOURCE_MEM,
1572         },
1573         [2] = {
1574                 .start = INT_SE,
1575                 .end = INT_SE,
1576                 .flags = IORESOURCE_IRQ,
1577         },
1578 };
1579
1580 struct platform_device tegra_se_device = {
1581         .name = "tegra-se",
1582         .id = -1,
1583         .dev = {
1584                 .coherent_dma_mask = DMA_BIT_MASK(32),
1585                 .dma_mask = &tegra_se_dma_mask,
1586         },
1587         .resource = tegra_se_resources,
1588         .num_resources = ARRAY_SIZE(tegra_se_resources),
1589 };
1590 #endif
1591