ARM: tegra12: set CPU rate to 2.2GHz for sku 0x87
[linux-3.10.git] / arch / arm / mach-tegra / cpuidle.c
1 /*
2  * arch/arm/mach-tegra/cpuidle.c
3  *
4  * CPU idle driver for Tegra CPUs
5  *
6  * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
7  * Copyright (c) 2011 Google, Inc.
8  * Author: Colin Cross <ccross@android.com>
9  *         Gary King <gking@nvidia.com>
10  *
11  * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful, but WITHOUT
19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
21  * more details.
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/cpu.h>
26 #include <linux/cpuidle.h>
27 #include <linux/debugfs.h>
28 #include <linux/delay.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/io.h>
33 #include <linux/sched.h>
34 #include <linux/seq_file.h>
35 #include <linux/slab.h>
36 #include <linux/smp.h>
37 #include <linux/suspend.h>
38 #include <linux/tick.h>
39 #include <linux/cpu_pm.h>
40 #include <linux/module.h>
41 #include <linux/hrtimer.h>
42 #include <linux/pm_domain.h>
43 #include <linux/tegra-timer.h>
44 #include <linux/tegra-cpuidle.h>
45
46 #include <asm/proc-fns.h>
47 #include <asm/cpuidle.h>
48
49 #include <mach/irqs.h>
50
51 #include <trace/events/nvpower.h>
52
53 #include "pm.h"
54 #include "sleep.h"
55
56 #define DRAM_SELF_REFRESH_EXIT_LATENCY  3000
57
58 int tegra_pg_exit_latency;
59 static int tegra_pd_power_off_time;
60 static unsigned int tegra_pd_min_residency;
61
62 static const char *driver_name = "tegra_idle";
63 static struct module *owner = THIS_MODULE;
64
65 DEFINE_PER_CPU(struct cpumask, idle_mask);
66 DEFINE_PER_CPU(struct cpuidle_driver, cpuidle_drv);
67
68 static int tegra_idle_enter_clock_gating(struct cpuidle_device *dev,
69         struct cpuidle_driver *drv, int index)
70 {
71         ktime_t enter, exit;
72         s64 us;
73
74         /* cpu_idle calls us with IRQs disabled */
75
76         local_fiq_disable();
77
78         enter = ktime_get();
79
80         cpu_do_idle();
81
82         exit = ktime_sub(ktime_get(), enter);
83         us = ktime_to_us(exit);
84
85         local_fiq_enable();
86
87         /* cpu_idle expects us to return with IRQs enabled */
88         local_irq_enable();
89
90         dev->last_residency = us;
91         return index;
92 }
93
94 static bool power_down_in_idle __read_mostly;
95
96 #ifdef CONFIG_PM_SLEEP
97 static bool pd_in_idle_modifiable __read_mostly = true;
98 static bool pd_disabled_by_suspend;
99 static struct tegra_cpuidle_ops tegra_idle_ops;
100
101 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
102 u32 tegra_force_clkgt_at_vmin;
103 #endif
104
105 void tegra_pd_in_idle(bool enable)
106 {
107         /*
108          * If power down in idle is permanently disabled it can't be
109          * re-enabled.
110          */
111         if (pd_in_idle_modifiable) {
112                 power_down_in_idle = enable;
113                 pd_in_idle_modifiable = enable;
114                 if (!enable)
115                         pr_warn("LP2 in idle disabled\n");
116         }
117 }
118
119 void tegra_pd_update_target_residency(struct cpuidle_state *state)
120 {
121         state->target_residency = state->exit_latency +
122                 tegra_pd_power_off_time;
123         if (state->target_residency < tegra_pd_min_residency)
124                 state->target_residency = tegra_pd_min_residency;
125 }
126
127 static int tegra_idle_enter_pd(struct cpuidle_device *dev,
128         struct cpuidle_driver *drv, int index)
129 {
130         ktime_t enter, exit;
131         s64 us;
132         struct cpuidle_state *state = &drv->states[index];
133         bool powered_down;
134
135         if (!power_down_in_idle || pd_disabled_by_suspend ||
136             !tegra_idle_ops.pd_is_allowed(dev, state)) {
137 #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
138                 return drv->states[dev->safe_state_index].enter(dev,
139                                         drv, dev->safe_state_index);
140 #else
141                 return drv->states[0].enter(dev, drv, 0);
142 #endif
143         }
144
145         /* cpu_idle calls us with IRQs disabled */
146         trace_nvcpu_powergate_rcuidle(NVPOWER_CPU_POWERGATE_ENTRY);
147
148         enter = ktime_get();
149
150         tegra_idle_ops.cpu_idle_stats_pd_ready(dev->cpu);
151         powered_down = tegra_idle_ops.tegra_idle_pd(dev, state);
152
153         trace_nvcpu_powergate_rcuidle(NVPOWER_CPU_POWERGATE_EXIT);
154
155         exit = ktime_sub(ktime_get(), enter);
156         us = ktime_to_us(exit);
157
158         /* cpu_idle expects us to return with IRQs enabled */
159         local_irq_enable();
160
161         smp_rmb();
162
163         /* Update LP2 latency provided no fall back to clock gating */
164         if (powered_down) {
165                 tegra_pd_set_global_latency(state);
166                 tegra_pd_update_target_residency(state);
167         }
168         tegra_idle_ops.cpu_idle_stats_pd_time(dev->cpu, us);
169
170         dev->last_residency = (int)us;
171         return (powered_down) ? index : 0;
172 }
173 #endif
174
175 static void tegra_cpuidle_setup_bctimer(void *arg)
176 {
177         int cpu = smp_processor_id();
178         clockevents_notify((long)(arg), &cpu);
179 }
180
181 static int tegra_cpuidle_register(unsigned int cpu)
182 {
183         struct cpuidle_driver *drv;
184         struct cpuidle_state *state;
185
186         drv = &per_cpu(cpuidle_drv, cpu);
187         drv->name = driver_name;
188         drv->owner = owner;
189         drv->cpumask = &per_cpu(idle_mask, cpu);
190         cpumask_set_cpu(cpu, drv->cpumask);
191         drv->state_count = 0;
192
193         state = &drv->states[0];
194         snprintf(state->name, CPUIDLE_NAME_LEN, "clock-gated");
195         snprintf(state->desc, CPUIDLE_DESC_LEN, "CPU clock gated");
196         state->exit_latency = 10;
197         state->target_residency = 10;
198         state->power_usage = 600;
199         state->flags = CPUIDLE_FLAG_TIME_VALID;
200         state->enter = tegra_idle_enter_clock_gating;
201 #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
202         drv->safe_state_index = 0;
203 #endif
204         drv->state_count++;
205
206 #ifdef CONFIG_PM_SLEEP
207         state = &drv->states[1];
208         snprintf(state->name, CPUIDLE_NAME_LEN, "powered-down");
209         snprintf(state->desc, CPUIDLE_DESC_LEN, "CPU power gated");
210         state->exit_latency = tegra_cpu_power_good_time();
211         state->target_residency = tegra_cpu_power_off_time() +
212                 tegra_cpu_power_good_time();
213         if (state->target_residency < tegra_pd_min_residency)
214                 state->target_residency = tegra_pd_min_residency;
215         state->power_usage = 100;
216         state->flags = CPUIDLE_FLAG_TIME_VALID;
217         state->enter = tegra_idle_enter_pd;
218         drv->state_count++;
219
220         if (cpu == 0) {
221                 state = &drv->states[2];
222                 snprintf(state->name, CPUIDLE_NAME_LEN, "mc-clock");
223                 snprintf(state->desc, CPUIDLE_DESC_LEN, "MC clock stop");
224                 state->exit_latency = tegra_cpu_power_good_time() +
225                         DRAM_SELF_REFRESH_EXIT_LATENCY;
226                 state->target_residency = tegra_cpu_power_off_time() +
227                         tegra_cpu_power_good_time() + DRAM_SELF_REFRESH_EXIT_LATENCY;
228                 if (state->target_residency < tegra_mc_clk_stop_min_residency())
229                         state->target_residency =
230                                         tegra_mc_clk_stop_min_residency();
231                 state->power_usage = 0;
232                 state->flags = CPUIDLE_FLAG_TIME_VALID;
233                 state->enter = tegra_idle_enter_pd;
234                 state->disabled = true;
235                 drv->state_count++;
236         }
237 #endif
238
239         if (cpuidle_register(drv, NULL)) {
240                 pr_err("CPU%u: failed to register driver\n", cpu);
241                 return -EIO;
242         }
243
244         on_each_cpu_mask(drv->cpumask, tegra_cpuidle_setup_bctimer,
245                                 (void *)CLOCK_EVT_NOTIFY_BROADCAST_ON, 1);
246
247         return 0;
248 }
249
250 static int tegra_cpuidle_pm_notify(struct notifier_block *nb,
251         unsigned long event, void *dummy)
252 {
253 #ifdef CONFIG_PM_SLEEP
254         if (event == PM_SUSPEND_PREPARE)
255                 pd_disabled_by_suspend = true;
256         else if (event == PM_POST_SUSPEND)
257                 pd_disabled_by_suspend = false;
258 #endif
259
260         return NOTIFY_OK;
261 }
262
263 static struct notifier_block tegra_cpuidle_pm_notifier = {
264         .notifier_call = tegra_cpuidle_pm_notify,
265 };
266
267 #ifdef CONFIG_TEGRA_MC_DOMAINS
268 static long __init pm_attach_cpuidle_work (void * arg)
269 {
270         pm_genpd_name_attach_cpuidle("tegra_mc_clk", 2);
271         return 0;
272 }
273 #endif
274
275 static int __init tegra_cpuidle_init(void)
276 {
277         unsigned int cpu;
278         int ret;
279
280 #ifdef CONFIG_PM_SLEEP
281         tegra_pd_min_residency = tegra_cpu_lp2_min_residency();
282         tegra_pg_exit_latency = tegra_cpu_power_good_time();
283         tegra_pd_power_off_time = tegra_cpu_power_off_time();
284
285         tegra_cpuidle_init_soc(&tegra_idle_ops);
286 #endif
287         for_each_possible_cpu(cpu) {
288                 ret = tegra_cpuidle_register(cpu);
289                 if (ret) {
290                         pr_err("CPU%u: CPUidle registration failed\n",
291                                 cpu);
292                         return ret;
293                 }
294         }
295
296 #ifdef CONFIG_TEGRA_MC_DOMAINS
297         work_on_cpu(0, pm_attach_cpuidle_work, NULL);
298 #endif
299         register_pm_notifier(&tegra_cpuidle_pm_notifier);
300         return 0;
301 }
302 device_initcall(tegra_cpuidle_init);
303
304 static void __exit tegra_cpuidle_exit(void)
305 {
306         int cpu;
307         struct cpuidle_driver *drv;
308
309         unregister_pm_notifier(&tegra_cpuidle_pm_notifier);
310
311         for_each_possible_cpu(cpu) {
312                 drv = &per_cpu(cpuidle_drv, cpu);
313
314                 on_each_cpu_mask(drv->cpumask, tegra_cpuidle_setup_bctimer,
315                                 (void *)CLOCK_EVT_NOTIFY_BROADCAST_OFF, 1);
316
317                 cpuidle_unregister(drv);
318         }
319 }
320 module_exit(tegra_cpuidle_exit);
321
322 static int pd_in_idle_set(const char *arg, const struct kernel_param *kp)
323 {
324 #ifdef CONFIG_PM_SLEEP
325         int ret;
326
327         /*
328          * If power down in idle is permanently disabled it can't be
329          * re-enabled.
330          */
331         if (pd_in_idle_modifiable) {
332                 ret = param_set_bool(arg, kp);
333                 return ret;
334         }
335 #endif
336         return -ENODEV;
337 }
338
339 static int pd_in_idle_get(char *buffer, const struct kernel_param *kp)
340 {
341         return param_get_bool(buffer, kp);
342 }
343
344 static struct kernel_param_ops pd_in_idle_ops = {
345         .set = pd_in_idle_set,
346         .get = pd_in_idle_get,
347 };
348 module_param_cb(power_down_in_idle, &pd_in_idle_ops, &power_down_in_idle, 0644);
349
350 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_PM_SLEEP)
351 static int tegra_pd_debug_open(struct inode *inode, struct file *file)
352 {
353         return single_open(file, tegra_idle_ops.pd_debug_show,
354                                 inode->i_private);
355 }
356
357 static const struct file_operations tegra_pd_debug_ops = {
358         .open           = tegra_pd_debug_open,
359         .read           = seq_read,
360         .llseek         = seq_lseek,
361         .release        = single_release,
362 };
363
364 static int __init tegra_cpuidle_debug_init(void)
365 {
366         struct dentry *dir;
367         struct dentry *d;
368
369         dir = debugfs_create_dir("cpuidle", NULL);
370         if (!dir)
371                 return -ENOMEM;
372
373         d = debugfs_create_file("power_down_stats", S_IRUGO, dir, NULL,
374                 &tegra_pd_debug_ops);
375         if (!d)
376                 return -ENOMEM;
377
378 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
379         d = debugfs_create_x32("force_clkgt_at_vmin", S_IRUGO | S_IWUSR,
380                 dir, &tegra_force_clkgt_at_vmin);
381         if (!d)
382                 return -ENOMEM;
383 #endif
384
385         return 0;
386 }
387
388 late_initcall(tegra_cpuidle_debug_init);
389 #endif