f76dcfe258c63425ac9c288d146f01569f672352
[linux-3.10.git] / arch / arm / mach-tegra / cpuidle-t2.c
1 /*
2  * arch/arm/mach-tegra/cpuidle-t2.c
3  *
4  * CPU idle driver for Tegra2 CPUs
5  *
6  * Copyright (c) 2010-2011, NVIDIA Corporation.
7  * Copyright (c) 2011 Google, Inc.
8  * Author: Colin Cross <ccross@android.com>
9  *         Gary King <gking@nvidia.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful, but WITHOUT
17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  * more details.
20  *
21  * You should have received a copy of the GNU General Public License along
22  * with this program; if not, write to the Free Software Foundation, Inc.,
23  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
24  */
25
26 #include <linux/kernel.h>
27 #include <linux/cpu.h>
28 #include <linux/cpuidle.h>
29 #include <linux/debugfs.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/io.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
38 #include <linux/smp.h>
39 #include <linux/suspend.h>
40 #include <linux/tick.h>
41 #include <linux/cpu_pm.h>
42
43 #include <asm/suspend.h>
44
45 #include <mach/iomap.h>
46 #include <mach/irqs.h>
47
48 #include "cpuidle.h"
49 #include "flowctrl.h"
50 #include "gic.h"
51 #include "pm.h"
52 #include "sleep.h"
53 #include "timer.h"
54 #include "dvfs.h"
55
56 static struct {
57         unsigned int cpu_ready_count[2];
58         unsigned long long cpu_wants_lp2_time[2];
59         unsigned long long in_lp2_time;
60         unsigned int both_idle_count;
61         unsigned int tear_down_count;
62         unsigned int lp2_count;
63         unsigned int lp2_completed_count;
64         unsigned int lp2_count_bin[32];
65         unsigned int lp2_completed_count_bin[32];
66         unsigned int lp2_int_count[NR_IRQS];
67         unsigned int last_lp2_int_count[NR_IRQS];
68 } idle_stats;
69
70 static inline unsigned int time_to_bin(unsigned int time)
71 {
72         return fls(time);
73 }
74
75 #ifdef CONFIG_SMP
76
77 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX        0x4C
78 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR    0x344
79
80 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
81 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
82 static s64 tegra_cpu1_wake_by_time = LLONG_MAX;
83
84 static int tegra2_reset_sleeping_cpu(int cpu)
85 {
86         int ret = 0;
87
88         BUG_ON(cpu == 0);
89         BUG_ON(cpu == smp_processor_id());
90         tegra_pen_lock();
91
92         if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
93                 tegra2_cpu_reset(cpu);
94         else
95                 ret = -EINVAL;
96
97         tegra_pen_unlock();
98
99         return ret;
100 }
101
102 static void tegra2_wake_reset_cpu(int cpu)
103 {
104         u32 reg;
105
106         BUG_ON(cpu == 0);
107         BUG_ON(cpu == smp_processor_id());
108
109         tegra_pen_lock();
110
111         tegra2_cpu_clear_resettable();
112
113         /* enable cpu clock on cpu */
114         reg = readl(clk_rst + 0x4c);
115         writel(reg & ~(1 << (8 + cpu)),
116                clk_rst + CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
117
118         /* take the CPU out of reset */
119         reg = 0x1111 << cpu;
120         writel(reg, clk_rst +
121                CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
122
123         /* unhalt the cpu */
124         flowctrl_write_cpu_halt(1, 0);
125
126         tegra_pen_unlock();
127 }
128
129 static int tegra2_reset_other_cpus(int cpu)
130 {
131         int i;
132         int ret = 0;
133
134         BUG_ON(cpu != 0);
135
136         for_each_online_cpu(i) {
137                 if (i != cpu) {
138                         if (tegra2_reset_sleeping_cpu(i)) {
139                                 ret = -EBUSY;
140                                 break;
141                         }
142                 }
143         }
144
145         if (ret) {
146                 for_each_online_cpu(i) {
147                         if (i != cpu)
148                                 tegra2_wake_reset_cpu(i);
149                 }
150                 return ret;
151         }
152
153         return 0;
154 }
155 #else
156 static void tegra2_wake_reset_cpu(int cpu)
157 {
158 }
159
160 static int tegra2_reset_other_cpus(int cpu)
161 {
162         return 0;
163 }
164 #endif
165
166 bool tegra2_lp2_is_allowed(struct cpuidle_device *dev,
167                         struct cpuidle_state *state)
168 {
169         s64 request = ktime_to_us(tick_nohz_get_sleep_length());
170
171         if (request < state->target_residency) {
172                 /* Not enough time left to enter LP2 */
173                 return false;
174         }
175
176         return true;
177 }
178
179 static int tegra2_idle_lp2_cpu_0(struct cpuidle_device *dev,
180                            struct cpuidle_state *state, s64 request)
181 {
182         ktime_t entry_time;
183         ktime_t exit_time;
184         s64 wake_time;
185         bool sleep_completed = false;
186         int bin;
187         int i;
188
189         while (tegra2_cpu_is_resettable_soon())
190                 cpu_relax();
191
192         if (tegra2_reset_other_cpus(dev->cpu))
193                 return 0;
194
195         idle_stats.both_idle_count++;
196
197         if (request < state->target_residency) {
198                 tegra_cpu_wfi();
199                 return -EBUSY;
200         }
201
202         /* LP2 entry time */
203         entry_time = ktime_get();
204
205         /* LP2 initial targeted wake time */
206         wake_time = ktime_to_us(entry_time) + request;
207
208         /* CPU0 must wake up before CPU1. */
209         smp_rmb();
210         wake_time = min_t(s64, wake_time, tegra_cpu1_wake_by_time);
211
212         /* LP2 actual targeted wake time */
213         request = wake_time - ktime_to_us(entry_time);
214         BUG_ON(wake_time < 0LL);
215
216         idle_stats.tear_down_count++;
217         entry_time = ktime_get();
218         tegra_dvfs_rail_off(tegra_cpu_rail, entry_time);
219
220         if (request > state->target_residency) {
221                 s64 sleep_time = request - tegra_lp2_exit_latency;
222
223                 bin = time_to_bin((u32)request / 1000);
224                 idle_stats.lp2_count++;
225                 idle_stats.lp2_count_bin[bin]++;
226
227                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
228
229                 if (tegra_idle_lp2_last(sleep_time, 0) == 0)
230                         sleep_completed = true;
231                 else {
232                         int irq = tegra_gic_pending_interrupt();
233                         idle_stats.lp2_int_count[irq]++;
234                 }
235
236                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
237         }
238
239         for_each_online_cpu(i) {
240                 if (i != dev->cpu)
241                         tegra2_wake_reset_cpu(i);
242         }
243
244         exit_time = ktime_get();
245         tegra_dvfs_rail_on(tegra_cpu_rail, exit_time);
246
247         if (sleep_completed) {
248                 /*
249                  * Stayed in LP2 for the full time until the next tick,
250                  * adjust the exit latency based on measurement
251                  */
252                 s64 actual_time = ktime_to_us(ktime_sub(exit_time, entry_time));
253                 long offset = (long)(actual_time - request);
254                 int latency = tegra_lp2_exit_latency + offset / 16;
255                 latency = clamp(latency, 0, 10000);
256                 tegra_lp2_exit_latency = latency;
257                 smp_wmb();
258
259                 idle_stats.lp2_completed_count++;
260                 idle_stats.lp2_completed_count_bin[bin]++;
261                 idle_stats.in_lp2_time += actual_time;
262
263                 pr_debug("%lld %lld %ld %d\n", request, actual_time,
264                         offset, bin);
265         }
266
267         return 0;
268 }
269
270 static bool tegra2_idle_lp2_cpu_1(struct cpuidle_device *dev,
271                            struct cpuidle_state *state, s64 request)
272 {
273 #ifdef CONFIG_SMP
274         struct tegra_twd_context twd_context;
275
276         if (request < tegra_lp2_exit_latency) {
277                 tegra2_cpu_clear_resettable();
278                 tegra_cpu_wfi();
279                 return false;
280         }
281
282         /* Save time this CPU must be awakened by. */
283         tegra_cpu1_wake_by_time = ktime_to_us(ktime_get()) + request;
284         smp_wmb();
285
286         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
287
288         tegra_twd_suspend(&twd_context);
289
290         cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra2_finish_sleep_cpu_secondary);
291
292         tegra2_cpu_clear_resettable();
293
294         tegra_cpu1_wake_by_time = LLONG_MAX;
295
296         tegra_twd_resume(&twd_context);
297
298         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
299 #endif
300
301         /* FIXME: Do we really know whether we went into LP2 here? */
302         return true;
303 }
304
305 bool tegra2_idle_lp2(struct cpuidle_device *dev,
306                         struct cpuidle_state *state)
307 {
308         s64 request = ktime_to_us(tick_nohz_get_sleep_length());
309         bool last_cpu = tegra_set_cpu_in_lp2(dev->cpu);
310         bool entered_lp2 = false;
311
312         cpu_pm_enter();
313
314         if (dev->cpu == 0) {
315                 if (last_cpu) {
316                         if (tegra2_idle_lp2_cpu_0(dev, state, request) < 0) {
317                                 int i;
318                                 for_each_online_cpu(i) {
319                                         if (i != dev->cpu)
320                                                 tegra2_wake_reset_cpu(i);
321                                 }
322                         } else
323                                 entered_lp2 = true;
324                 } else {
325                         tegra_cpu_wfi();
326                 }
327         } else {
328                 BUG_ON(last_cpu);
329                 entered_lp2 = tegra2_idle_lp2_cpu_1(dev, state, request);
330         }
331
332         cpu_pm_exit();
333         tegra_clear_cpu_in_lp2(dev->cpu);
334
335         return entered_lp2;
336 }
337
338 void tegra2_cpu_idle_stats_lp2_ready(unsigned int cpu)
339 {
340         idle_stats.cpu_ready_count[cpu]++;
341 }
342
343 void tegra2_cpu_idle_stats_lp2_time(unsigned int cpu, s64 us)
344 {
345         idle_stats.cpu_wants_lp2_time[cpu] += us;
346 }
347
348 #ifdef CONFIG_DEBUG_FS
349 int tegra2_lp2_debug_show(struct seq_file *s, void *data)
350 {
351         int bin;
352         int i;
353         seq_printf(s, "                                    cpu0     cpu1\n");
354         seq_printf(s, "-------------------------------------------------\n");
355         seq_printf(s, "cpu ready:                      %8u %8u\n",
356                 idle_stats.cpu_ready_count[0],
357                 idle_stats.cpu_ready_count[1]);
358         seq_printf(s, "both idle:      %8u        %7u%% %7u%%\n",
359                 idle_stats.both_idle_count,
360                 idle_stats.both_idle_count * 100 /
361                         (idle_stats.cpu_ready_count[0] ?: 1),
362                 idle_stats.both_idle_count * 100 /
363                         (idle_stats.cpu_ready_count[1] ?: 1));
364         seq_printf(s, "tear down:      %8u %7u%%\n", idle_stats.tear_down_count,
365                 idle_stats.tear_down_count * 100 /
366                         (idle_stats.both_idle_count ?: 1));
367         seq_printf(s, "lp2:            %8u %7u%%\n", idle_stats.lp2_count,
368                 idle_stats.lp2_count * 100 /
369                         (idle_stats.both_idle_count ?: 1));
370         seq_printf(s, "lp2 completed:  %8u %7u%%\n",
371                 idle_stats.lp2_completed_count,
372                 idle_stats.lp2_completed_count * 100 /
373                         (idle_stats.lp2_count ?: 1));
374
375         seq_printf(s, "\n");
376         seq_printf(s, "cpu ready time:                 %8llu %8llu ms\n",
377                 div64_u64(idle_stats.cpu_wants_lp2_time[0], 1000),
378                 div64_u64(idle_stats.cpu_wants_lp2_time[1], 1000));
379         seq_printf(s, "lp2 time:       %8llu ms     %7d%% %7d%%\n",
380                 div64_u64(idle_stats.in_lp2_time, 1000),
381                 (int)div64_u64(idle_stats.in_lp2_time * 100,
382                         idle_stats.cpu_wants_lp2_time[0] ?: 1),
383                 (int)div64_u64(idle_stats.in_lp2_time * 100,
384                         idle_stats.cpu_wants_lp2_time[1] ?: 1));
385
386         seq_printf(s, "\n");
387         seq_printf(s, "%19s %8s %8s %8s\n", "", "lp2", "comp", "%");
388         seq_printf(s, "-------------------------------------------------\n");
389         for (bin = 0; bin < 32; bin++) {
390                 if (idle_stats.lp2_count_bin[bin] == 0)
391                         continue;
392                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
393                         1 << (bin - 1), 1 << bin,
394                         idle_stats.lp2_count_bin[bin],
395                         idle_stats.lp2_completed_count_bin[bin],
396                         idle_stats.lp2_completed_count_bin[bin] * 100 /
397                                 idle_stats.lp2_count_bin[bin]);
398         }
399
400         seq_printf(s, "\n");
401         seq_printf(s, "%3s %20s %6s %10s\n",
402                 "int", "name", "count", "last count");
403         seq_printf(s, "--------------------------------------------\n");
404         for (i = 0; i < NR_IRQS; i++) {
405                 if (idle_stats.lp2_int_count[i] == 0)
406                         continue;
407                 seq_printf(s, "%3d %20s %6d %10d\n",
408                         i, irq_to_desc(i)->action ?
409                                 irq_to_desc(i)->action->name ?: "???" : "???",
410                         idle_stats.lp2_int_count[i],
411                         idle_stats.lp2_int_count[i] -
412                                 idle_stats.last_lp2_int_count[i]);
413                 idle_stats.last_lp2_int_count[i] = idle_stats.lp2_int_count[i];
414         };
415         return 0;
416 }
417 #endif