ARM: tegra: powermon: Fix copyrights from GPLv3 to GPLv2
[linux-3.10.git] / arch / arm / mach-tegra / cpuidle-t2.c
1 /*
2  * arch/arm/mach-tegra/cpuidle-t2.c
3  *
4  * CPU idle driver for Tegra2 CPUs
5  *
6  * Copyright (c) 2010-2011, NVIDIA Corporation.
7  * Copyright (c) 2011 Google, Inc.
8  * Author: Colin Cross <ccross@android.com>
9  *         Gary King <gking@nvidia.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful, but WITHOUT
17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  * more details.
20  *
21  * You should have received a copy of the GNU General Public License along
22  * with this program; if not, write to the Free Software Foundation, Inc.,
23  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
24  */
25
26 #include <linux/kernel.h>
27 #include <linux/cpu.h>
28 #include <linux/cpuidle.h>
29 #include <linux/debugfs.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/io.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
38 #include <linux/smp.h>
39 #include <linux/suspend.h>
40 #include <linux/tick.h>
41 #include <linux/cpu_pm.h>
42
43 #include <asm/suspend.h>
44
45 #include <mach/iomap.h>
46 #include <mach/irqs.h>
47
48 #include "cpuidle.h"
49 #include "gic.h"
50 #include "pm.h"
51 #include "sleep.h"
52 #include "timer.h"
53 #include "dvfs.h"
54
55 static struct {
56         unsigned int cpu_ready_count[2];
57         unsigned long long cpu_wants_lp2_time[2];
58         unsigned long long in_lp2_time;
59         unsigned int both_idle_count;
60         unsigned int tear_down_count;
61         unsigned int lp2_count;
62         unsigned int lp2_completed_count;
63         unsigned int lp2_count_bin[32];
64         unsigned int lp2_completed_count_bin[32];
65         unsigned int lp2_int_count[NR_IRQS];
66         unsigned int last_lp2_int_count[NR_IRQS];
67 } idle_stats;
68
69 static inline unsigned int time_to_bin(unsigned int time)
70 {
71         return fls(time);
72 }
73
74 #ifdef CONFIG_SMP
75
76 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX        0x4C
77 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR    0x344
78
79 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
80 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
81 static s64 tegra_cpu1_wake_by_time = LLONG_MAX;
82
83 static int tegra2_reset_sleeping_cpu(int cpu)
84 {
85         int ret = 0;
86
87         BUG_ON(cpu == 0);
88         BUG_ON(cpu == smp_processor_id());
89         tegra_pen_lock();
90
91         if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
92                 tegra2_cpu_reset(cpu);
93         else
94                 ret = -EINVAL;
95
96         tegra_pen_unlock();
97
98         return ret;
99 }
100
101 static void tegra2_wake_reset_cpu(int cpu)
102 {
103         u32 reg;
104
105         BUG_ON(cpu == 0);
106         BUG_ON(cpu == smp_processor_id());
107
108         tegra_pen_lock();
109
110         tegra2_cpu_clear_resettable();
111
112         /* enable cpu clock on cpu */
113         reg = readl(clk_rst + 0x4c);
114         writel(reg & ~(1 << (8 + cpu)),
115                clk_rst + CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
116
117         /* take the CPU out of reset */
118         reg = 0x1111 << cpu;
119         writel(reg, clk_rst +
120                CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
121
122         /* unhalt the cpu */
123         flowctrl_writel(0, FLOW_CTRL_HALT_CPU(1));
124
125         tegra_pen_unlock();
126 }
127
128 static int tegra2_reset_other_cpus(int cpu)
129 {
130         int i;
131         int ret = 0;
132
133         BUG_ON(cpu != 0);
134
135         for_each_online_cpu(i) {
136                 if (i != cpu) {
137                         if (tegra2_reset_sleeping_cpu(i)) {
138                                 ret = -EBUSY;
139                                 break;
140                         }
141                 }
142         }
143
144         if (ret) {
145                 for_each_online_cpu(i) {
146                         if (i != cpu)
147                                 tegra2_wake_reset_cpu(i);
148                 }
149                 return ret;
150         }
151
152         return 0;
153 }
154 #else
155 static void tegra2_wake_reset_cpu(int cpu)
156 {
157 }
158
159 static int tegra2_reset_other_cpus(int cpu)
160 {
161         return 0;
162 }
163 #endif
164
165 bool tegra2_lp2_is_allowed(struct cpuidle_device *dev,
166                         struct cpuidle_state *state)
167 {
168         s64 request = ktime_to_us(tick_nohz_get_sleep_length());
169
170         if (request < state->target_residency) {
171                 /* Not enough time left to enter LP2 */
172                 return false;
173         }
174
175         return true;
176 }
177
178 static int tegra2_idle_lp2_cpu_0(struct cpuidle_device *dev,
179                            struct cpuidle_state *state, s64 request)
180 {
181         ktime_t entry_time;
182         ktime_t exit_time;
183         s64 wake_time;
184         bool sleep_completed = false;
185         int bin;
186         int i;
187
188         while (tegra2_cpu_is_resettable_soon())
189                 cpu_relax();
190
191         if (tegra2_reset_other_cpus(dev->cpu))
192                 return 0;
193
194         idle_stats.both_idle_count++;
195
196         if (request < state->target_residency) {
197                 cpu_do_idle();
198                 return -EBUSY;
199         }
200
201         /* LP2 entry time */
202         entry_time = ktime_get();
203
204         /* LP2 initial targeted wake time */
205         wake_time = ktime_to_us(entry_time) + request;
206
207         /* CPU0 must wake up before CPU1. */
208         smp_rmb();
209         wake_time = min_t(s64, wake_time, tegra_cpu1_wake_by_time);
210
211         /* LP2 actual targeted wake time */
212         request = wake_time - ktime_to_us(entry_time);
213         BUG_ON(wake_time < 0LL);
214
215         idle_stats.tear_down_count++;
216         entry_time = ktime_get();
217         tegra_dvfs_rail_off(tegra_cpu_rail, entry_time);
218
219         if (request > state->target_residency) {
220                 s64 sleep_time = request - tegra_pg_exit_latency;
221
222                 bin = time_to_bin((u32)request / 1000);
223                 idle_stats.lp2_count++;
224                 idle_stats.lp2_count_bin[bin]++;
225
226                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
227
228                 if (tegra_idle_power_down_last(sleep_time, 0) == 0)
229                         sleep_completed = true;
230                 else {
231                         int irq = tegra_gic_pending_interrupt();
232                         idle_stats.lp2_int_count[irq]++;
233                 }
234
235                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
236         }
237
238         for_each_online_cpu(i) {
239                 if (i != dev->cpu)
240                         tegra2_wake_reset_cpu(i);
241         }
242
243         exit_time = ktime_get();
244         tegra_dvfs_rail_on(tegra_cpu_rail, exit_time);
245
246         if (sleep_completed) {
247                 /*
248                  * Stayed in LP2 for the full time until the next tick,
249                  * adjust the exit latency based on measurement
250                  */
251                 s64 actual_time = ktime_to_us(ktime_sub(exit_time, entry_time));
252                 long offset = (long)(actual_time - request);
253                 int latency = tegra_pg_exit_latency + offset / 16;
254                 latency = clamp(latency, 0, 10000);
255                 tegra_pg_exit_latency = latency;
256                 smp_wmb();
257
258                 idle_stats.lp2_completed_count++;
259                 idle_stats.lp2_completed_count_bin[bin]++;
260                 idle_stats.in_lp2_time += actual_time;
261
262                 pr_debug("%lld %lld %ld %d\n", request, actual_time,
263                         offset, bin);
264         }
265
266         return 0;
267 }
268
269 static bool tegra2_idle_lp2_cpu_1(struct cpuidle_device *dev,
270                            struct cpuidle_state *state, s64 request)
271 {
272 #ifdef CONFIG_SMP
273         struct tegra_twd_context twd_context;
274
275         if (request < tegra_pg_exit_latency) {
276                 tegra2_cpu_clear_resettable();
277                 cpu_do_idle();
278                 return false;
279         }
280
281         /* Save time this CPU must be awakened by. */
282         tegra_cpu1_wake_by_time = ktime_to_us(ktime_get()) + request;
283         smp_wmb();
284
285         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
286
287         tegra_twd_suspend(&twd_context);
288
289         cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra2_finish_sleep_cpu_secondary);
290
291         tegra2_cpu_clear_resettable();
292
293         tegra_cpu1_wake_by_time = LLONG_MAX;
294
295         tegra_twd_resume(&twd_context);
296
297         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
298 #endif
299
300         /* FIXME: Do we really know whether we went into LP2 here? */
301         return true;
302 }
303
304 bool tegra2_idle_lp2(struct cpuidle_device *dev,
305                         struct cpuidle_state *state)
306 {
307         s64 request = ktime_to_us(tick_nohz_get_sleep_length());
308         bool last_cpu = tegra_set_cpu_in_pd(dev->cpu);
309         bool entered_lp2 = false;
310
311         cpu_pm_enter();
312
313         if (dev->cpu == 0) {
314                 if (last_cpu) {
315                         if (tegra2_idle_lp2_cpu_0(dev, state, request) < 0) {
316                                 int i;
317                                 for_each_online_cpu(i) {
318                                         if (i != dev->cpu)
319                                                 tegra2_wake_reset_cpu(i);
320                                 }
321                         } else
322                                 entered_lp2 = true;
323                 } else {
324                         cpu_do_idle();
325                 }
326         } else {
327                 BUG_ON(last_cpu);
328                 entered_lp2 = tegra2_idle_lp2_cpu_1(dev, state, request);
329         }
330
331         cpu_pm_exit();
332         tegra_clear_cpu_in_pd(dev->cpu);
333
334         return entered_lp2;
335 }
336
337 void tegra2_cpu_idle_stats_lp2_ready(unsigned int cpu)
338 {
339         idle_stats.cpu_ready_count[cpu]++;
340 }
341
342 void tegra2_cpu_idle_stats_lp2_time(unsigned int cpu, s64 us)
343 {
344         idle_stats.cpu_wants_lp2_time[cpu] += us;
345 }
346
347 #ifdef CONFIG_DEBUG_FS
348 int tegra2_lp2_debug_show(struct seq_file *s, void *data)
349 {
350         int bin;
351         int i;
352         seq_printf(s, "                                    cpu0     cpu1\n");
353         seq_printf(s, "-------------------------------------------------\n");
354         seq_printf(s, "cpu ready:                      %8u %8u\n",
355                 idle_stats.cpu_ready_count[0],
356                 idle_stats.cpu_ready_count[1]);
357         seq_printf(s, "both idle:      %8u        %7u%% %7u%%\n",
358                 idle_stats.both_idle_count,
359                 idle_stats.both_idle_count * 100 /
360                         (idle_stats.cpu_ready_count[0] ?: 1),
361                 idle_stats.both_idle_count * 100 /
362                         (idle_stats.cpu_ready_count[1] ?: 1));
363         seq_printf(s, "tear down:      %8u %7u%%\n", idle_stats.tear_down_count,
364                 idle_stats.tear_down_count * 100 /
365                         (idle_stats.both_idle_count ?: 1));
366         seq_printf(s, "lp2:            %8u %7u%%\n", idle_stats.lp2_count,
367                 idle_stats.lp2_count * 100 /
368                         (idle_stats.both_idle_count ?: 1));
369         seq_printf(s, "lp2 completed:  %8u %7u%%\n",
370                 idle_stats.lp2_completed_count,
371                 idle_stats.lp2_completed_count * 100 /
372                         (idle_stats.lp2_count ?: 1));
373
374         seq_printf(s, "\n");
375         seq_printf(s, "cpu ready time:                 %8llu %8llu ms\n",
376                 div64_u64(idle_stats.cpu_wants_lp2_time[0], 1000),
377                 div64_u64(idle_stats.cpu_wants_lp2_time[1], 1000));
378         seq_printf(s, "lp2 time:       %8llu ms     %7d%% %7d%%\n",
379                 div64_u64(idle_stats.in_lp2_time, 1000),
380                 (int)div64_u64(idle_stats.in_lp2_time * 100,
381                         idle_stats.cpu_wants_lp2_time[0] ?: 1),
382                 (int)div64_u64(idle_stats.in_lp2_time * 100,
383                         idle_stats.cpu_wants_lp2_time[1] ?: 1));
384
385         seq_printf(s, "\n");
386         seq_printf(s, "%19s %8s %8s %8s\n", "", "lp2", "comp", "%");
387         seq_printf(s, "-------------------------------------------------\n");
388         for (bin = 0; bin < 32; bin++) {
389                 if (idle_stats.lp2_count_bin[bin] == 0)
390                         continue;
391                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
392                         1 << (bin - 1), 1 << bin,
393                         idle_stats.lp2_count_bin[bin],
394                         idle_stats.lp2_completed_count_bin[bin],
395                         idle_stats.lp2_completed_count_bin[bin] * 100 /
396                                 idle_stats.lp2_count_bin[bin]);
397         }
398
399         seq_printf(s, "\n");
400         seq_printf(s, "%3s %20s %6s %10s\n",
401                 "int", "name", "count", "last count");
402         seq_printf(s, "--------------------------------------------\n");
403         for (i = 0; i < NR_IRQS; i++) {
404                 if (idle_stats.lp2_int_count[i] == 0)
405                         continue;
406                 seq_printf(s, "%3d %20s %6d %10d\n",
407                         i, irq_to_desc(i)->action ?
408                                 irq_to_desc(i)->action->name ?: "???" : "???",
409                         idle_stats.lp2_int_count[i],
410                         idle_stats.lp2_int_count[i] -
411                                 idle_stats.last_lp2_int_count[i]);
412                 idle_stats.last_lp2_int_count[i] = idle_stats.lp2_int_count[i];
413         };
414         return 0;
415 }
416 #endif
417
418 int __init tegra2_cpuidle_init_soc(struct tegra_cpuidle_ops *idle_ops)
419 {
420         struct tegra_cpuidle_ops ops = {
421                 tegra2_idle_lp2,
422                 tegra2_cpu_idle_stats_lp2_ready,
423                 tegra2_cpu_idle_stats_lp2_time,
424                 tegra2_lp2_is_allowed,
425 #ifdef CONFIG_DEBUG_FS
426                 tegra2_lp2_debug_show
427 #endif
428         };
429
430         *idle_ops = ops;
431
432         return 0;
433 }