ARM: tegra11x: cpuidle: Implement cluster power down for secure os
[linux-3.10.git] / arch / arm / mach-tegra / cpuidle-t11x.c
1 /*
2  * arch/arm/mach-tegra/cpuidle-t11x.c
3  *
4  * CPU idle driver for Tegra11x CPUs
5  *
6  * Copyright (c) 2012, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/cpu.h>
25 #include <linux/cpuidle.h>
26 #include <linux/debugfs.h>
27 #include <linux/delay.h>
28 #include <linux/hrtimer.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/io.h>
33 #include <linux/ratelimit.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/slab.h>
37 #include <linux/smp.h>
38 #include <linux/suspend.h>
39 #include <linux/tick.h>
40 #include <linux/clk.h>
41 #include <linux/cpu_pm.h>
42 #include <linux/module.h>
43
44 #include <asm/cacheflush.h>
45 #include <asm/hardware/gic.h>
46 #include <asm/localtimer.h>
47 #include <asm/suspend.h>
48 #include <asm/cputype.h>
49
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/hardware.h>
53
54 #include <trace/events/power.h>
55
56 #include "clock.h"
57 #include "cpuidle.h"
58 #include "dvfs.h"
59 #include "fuse.h"
60 #include "gic.h"
61 #include "pm.h"
62 #include "reset.h"
63 #include "sleep.h"
64 #include "timer.h"
65 #include "fuse.h"
66
67 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS \
68         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x470)
69 #define PMC_POWERGATE_STATUS \
70         (IO_ADDRESS(TEGRA_PMC_BASE) + 0x038)
71
72 #define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
73 #define ARCH_TIMER_CTRL_IT_MASK         (1 << 1)
74
75 #ifdef CONFIG_SMP
76 static s64 tegra_cpu_wake_by_time[4] = {
77         LLONG_MAX, LLONG_MAX, LLONG_MAX, LLONG_MAX };
78 #endif
79
80 static ulong cpu_power_gating_in_idle __read_mostly = 0x1f;
81 module_param(cpu_power_gating_in_idle, ulong, 0644);
82
83 static bool slow_cluster_power_gating_noncpu __read_mostly;
84 module_param(slow_cluster_power_gating_noncpu, bool, 0644);
85
86 static uint fast_cluster_power_down_mode __read_mostly;
87 module_param(fast_cluster_power_down_mode, uint, 0644);
88
89 static struct clk *cpu_clk_for_dvfs;
90
91 static int pd_exit_latencies[5];
92
93 static struct {
94         unsigned int cpu_ready_count[5];
95         unsigned int tear_down_count[5];
96         unsigned long long cpu_wants_pd_time[5];
97         unsigned long long cpu_pg_time[5];
98         unsigned long long rail_pd_time;
99         unsigned long long c0nc_pg_time;
100         unsigned long long c1nc_pg_time;
101         unsigned int rail_gating_count;
102         unsigned int rail_gating_bin[32];
103         unsigned int rail_gating_done_count;
104         unsigned int rail_gating_done_count_bin[32];
105         unsigned int c0nc_gating_count;
106         unsigned int c0nc_gating_bin[32];
107         unsigned int c0nc_gating_done_count;
108         unsigned int c0nc_gating_done_count_bin[32];
109         unsigned int c1nc_gating_count;
110         unsigned int c1nc_gating_bin[32];
111         unsigned int c1nc_gating_done_count;
112         unsigned int c1nc_gating_done_count_bin[32];
113         unsigned int pd_int_count[NR_IRQS];
114         unsigned int last_pd_int_count[NR_IRQS];
115 } idle_stats;
116
117 static inline unsigned int time_to_bin(unsigned int time)
118 {
119         return fls(time);
120 }
121
122 static inline void tegra_irq_unmask(int irq)
123 {
124         struct irq_data *data = irq_get_irq_data(irq);
125         data->chip->irq_unmask(data);
126 }
127
128 static inline unsigned int cpu_number(unsigned int n)
129 {
130         return is_lp_cluster() ? 4 : n;
131 }
132
133 void tegra11x_cpu_idle_stats_pd_ready(unsigned int cpu)
134 {
135         idle_stats.cpu_ready_count[cpu_number(cpu)]++;
136 }
137
138 void tegra11x_cpu_idle_stats_pd_time(unsigned int cpu, s64 us)
139 {
140         idle_stats.cpu_wants_pd_time[cpu_number(cpu)] += us;
141 }
142
143 /* Allow rail off only if all secondary CPUs are power gated, and no
144    rail update is in progress */
145 static bool tegra_rail_off_is_allowed(void)
146 {
147         u32 rst = readl(CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
148         u32 pg = readl(PMC_POWERGATE_STATUS) >> 8;
149
150         if (((rst & 0xE) != 0xE) || ((pg & 0xE) != 0))
151                 return false;
152
153         if (tegra_dvfs_rail_updating(cpu_clk_for_dvfs))
154                 return false;
155
156         return true;
157 }
158
159 bool tegra11x_pd_is_allowed(struct cpuidle_device *dev,
160         struct cpuidle_state *state)
161 {
162         s64 request;
163
164         if (!cpumask_test_cpu(cpu_number(dev->cpu),
165                                 to_cpumask(&cpu_power_gating_in_idle)))
166                 return false;
167
168         request = ktime_to_us(tick_nohz_get_sleep_length());
169         if (state->exit_latency != pd_exit_latencies[cpu_number(dev->cpu)]) {
170                 /* possible on the 1st entry after cluster switch*/
171                 state->exit_latency = pd_exit_latencies[cpu_number(dev->cpu)];
172                 tegra_pd_update_target_residency(state);
173         }
174         if (request < state->target_residency) {
175                 /* Not enough time left to enter LP2 */
176                 return false;
177         }
178
179         return true;
180 }
181
182 static inline void tegra11_irq_restore_affinity(void)
183 {
184 #ifdef CONFIG_SMP
185         /* Disable the distributor. */
186         tegra_gic_dist_disable();
187
188         /* Restore the other CPU's interrupt affinity. */
189         tegra_gic_restore_affinity();
190
191         /* Re-enable the distributor. */
192         tegra_gic_dist_enable();
193 #endif
194 }
195
196 static bool tegra_cpu_cluster_power_down(struct cpuidle_device *dev,
197                            struct cpuidle_state *state, s64 request)
198 {
199         ktime_t entry_time;
200         ktime_t exit_time;
201         bool sleep_completed = false;
202         bool multi_cpu_entry = false;
203         int bin;
204         unsigned int flag = 0;
205         s64 sleep_time;
206
207         /* LP2 entry time */
208         entry_time = ktime_get();
209
210         if (request < state->target_residency) {
211                 /* Not enough time left to enter LP2 */
212                 cpu_do_idle();
213                 return false;
214         }
215
216 #ifdef CONFIG_SMP
217         multi_cpu_entry = !is_lp_cluster() && (num_online_cpus() > 1);
218         if (multi_cpu_entry) {
219                 s64 wake_time;
220                 unsigned int i;
221
222                 /* Disable the distributor -- this is the only way to
223                    prevent the other CPUs from responding to interrupts
224                    and potentially fiddling with the distributor
225                    registers while we're fiddling with them. */
226                 tegra_gic_dist_disable();
227
228                 /* Did an interrupt come in for another CPU before we
229                    could disable the distributor? */
230                 if (!tegra_rail_off_is_allowed()) {
231                         /* Yes, re-enable the distributor and clock gating. */
232                         tegra_gic_dist_enable();
233                         cpu_do_idle();
234                         return false;
235                 }
236
237                 /* LP2 initial targeted wake time */
238                 wake_time = ktime_to_us(entry_time) + request;
239
240                 /* CPU0 must wake up before any of the other CPUs. */
241                 smp_rmb();
242                 for (i = 1; i < CONFIG_NR_CPUS; i++)
243                         wake_time = min_t(s64, wake_time,
244                                 tegra_cpu_wake_by_time[i]);
245
246                 /* LP2 actual targeted wake time */
247                 request = wake_time - ktime_to_us(entry_time);
248                 BUG_ON(wake_time < 0LL);
249
250                 if (request < state->target_residency) {
251                         /* Not enough time left to enter LP2 */
252                         tegra_gic_dist_enable();
253                         cpu_do_idle();
254                         return false;
255                 }
256
257                 /* Cancel power gating wake timers for all secondary CPUs */
258                 tegra_pd_timer_cancel_secondary();
259
260                 /* Save and disable the affinity setting for the other
261                    CPUs and route all interrupts to CPU0. */
262                 tegra_gic_disable_affinity();
263
264                 /* Re-enable the distributor. */
265                 tegra_gic_dist_enable();
266         }
267 #endif
268         cpu_pm_enter();
269
270         sleep_time = request -
271                 pd_exit_latencies[cpu_number(dev->cpu)];
272
273         bin = time_to_bin((u32)request / 1000);
274         idle_stats.tear_down_count[cpu_number(dev->cpu)]++;
275
276         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
277         if (is_lp_cluster()) {
278                 /* here we are not supporting emulation mode, for now */
279                 flag = TEGRA_POWER_CLUSTER_PART_NONCPU;
280                 idle_stats.c1nc_gating_count++;
281                 idle_stats.c1nc_gating_bin[bin]++;
282         } else {
283                 tegra_dvfs_rail_off(tegra_cpu_rail, entry_time);
284                 flag = (fast_cluster_power_down_mode
285                         << TEGRA_POWER_CLUSTER_PART_SHIFT)
286                         & TEGRA_POWER_CLUSTER_PART_MASK;
287                 if ((request < tegra_min_residency_crail()) &&
288                         (flag != TEGRA_POWER_CLUSTER_PART_MASK))
289                         flag = TEGRA_POWER_CLUSTER_PART_NONCPU;
290
291                 if (flag == TEGRA_POWER_CLUSTER_PART_CRAIL) {
292                         idle_stats.rail_gating_count++;
293                         idle_stats.rail_gating_bin[bin]++;
294                 } else if (flag == TEGRA_POWER_CLUSTER_PART_NONCPU) {
295                         idle_stats.c0nc_gating_count++;
296                         idle_stats.c0nc_gating_bin[bin]++;
297                 }
298         }
299
300         if (tegra_idle_power_down_last(sleep_time, flag) == 0)
301                 sleep_completed = true;
302         else {
303                 int irq = tegra_gic_pending_interrupt();
304                 idle_stats.pd_int_count[irq]++;
305         }
306
307         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
308         exit_time = ktime_get();
309         if (!is_lp_cluster())
310                 tegra_dvfs_rail_on(tegra_cpu_rail, exit_time);
311
312         if (flag == TEGRA_POWER_CLUSTER_PART_CRAIL)
313                 idle_stats.rail_pd_time +=
314                         ktime_to_us(ktime_sub(exit_time, entry_time));
315         else if (flag == TEGRA_POWER_CLUSTER_PART_NONCPU) {
316                 if (is_lp_cluster())
317                         idle_stats.c1nc_pg_time +=
318                                 ktime_to_us(ktime_sub(exit_time, entry_time));
319                 else
320                         idle_stats.c0nc_pg_time +=
321                                 ktime_to_us(ktime_sub(exit_time, entry_time));
322         }
323
324         if (multi_cpu_entry)
325                 tegra11_irq_restore_affinity();
326
327         if (sleep_completed) {
328                 /*
329                  * Stayed in LP2 for the full time until the next tick,
330                  * adjust the exit latency based on measurement
331                  */
332                 int offset = ktime_to_us(ktime_sub(exit_time, entry_time))
333                         - request;
334                 int latency = pd_exit_latencies[cpu_number(dev->cpu)] +
335                         offset / 16;
336                 latency = clamp(latency, 0, 10000);
337                 pd_exit_latencies[cpu_number(dev->cpu)] = latency;
338                 state->exit_latency = latency;          /* for idle governor */
339                 smp_wmb();
340
341                 if (flag == TEGRA_POWER_CLUSTER_PART_CRAIL) {
342                         idle_stats.rail_gating_done_count++;
343                         idle_stats.rail_gating_done_count_bin[bin]++;
344                 } else if (flag == TEGRA_POWER_CLUSTER_PART_NONCPU) {
345                         if (is_lp_cluster()) {
346                                 idle_stats.c1nc_gating_done_count++;
347                                 idle_stats.c1nc_gating_done_count_bin[bin]++;
348                         } else {
349                                 idle_stats.c0nc_gating_done_count++;
350                                 idle_stats.c0nc_gating_done_count_bin[bin]++;
351                         }
352                 }
353
354                 pr_debug("%lld %lld %d %d\n", request,
355                         ktime_to_us(ktime_sub(exit_time, entry_time)),
356                         offset, bin);
357         }
358
359         cpu_pm_exit();
360
361         return true;
362 }
363
364 static bool tegra_cpu_core_power_down(struct cpuidle_device *dev,
365                            struct cpuidle_state *state, s64 request)
366 {
367 #ifdef CONFIG_SMP
368         s64 sleep_time;
369         ktime_t entry_time;
370         struct arch_timer_context timer_context;
371         bool sleep_completed = false;
372         struct tick_sched *ts = tick_get_tick_sched(dev->cpu);
373
374         if (!arch_timer_get_state(&timer_context)) {
375                 if ((timer_context.cntp_ctl & ARCH_TIMER_CTRL_ENABLE) &&
376                     ~(timer_context.cntp_ctl & ARCH_TIMER_CTRL_IT_MASK)) {
377                         if (timer_context.cntp_tval <= 0) {
378                                 cpu_do_idle();
379                                 return false;
380                         }
381                         request = div_u64((u64)timer_context.cntp_tval *
382                                         1000000, timer_context.cntfrq);
383 #ifdef CONFIG_TEGRA_LP2_CPU_TIMER
384                         if (request >= state->target_residency) {
385                                 timer_context.cntp_tval -= state->exit_latency *
386                                         (timer_context.cntfrq / 1000000);
387                                 __asm__("mcr p15, 0, %0, c14, c2, 0\n"
388                                         :
389                                         :
390                                         "r"(timer_context.cntp_tval));
391                         }
392 #endif
393                 }
394         }
395
396         if (!tegra_is_cpu_wake_timer_ready(dev->cpu) ||
397             (request < state->target_residency) ||
398             (!ts) || (ts->nohz_mode == NOHZ_MODE_INACTIVE)) {
399                 /*
400                  * Not enough time left to enter LP2, or wake timer not ready
401                  */
402                 cpu_do_idle();
403                 return false;
404         }
405
406         cpu_pm_enter();
407
408 #if !defined(CONFIG_TEGRA_LP2_CPU_TIMER)
409         sleep_time = request - state->exit_latency;
410         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
411         arch_timer_suspend(&timer_context);
412         tegra_pd_set_trigger(sleep_time);
413 #endif
414         idle_stats.tear_down_count[cpu_number(dev->cpu)]++;
415
416         entry_time = ktime_get();
417
418         /* Save time this CPU must be awakened by. */
419         tegra_cpu_wake_by_time[dev->cpu] = ktime_to_us(entry_time) + request;
420         smp_wmb();
421
422 #ifdef CONFIG_TRUSTED_FOUNDATIONS
423         tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4,
424                                    (TEGRA_RESET_HANDLER_BASE +
425                                     tegra_cpu_reset_handler_offset));
426 #endif
427         cpu_suspend(0, tegra3_sleep_cpu_secondary_finish);
428
429         tegra_cpu_wake_by_time[dev->cpu] = LLONG_MAX;
430
431 #ifdef CONFIG_TEGRA_LP2_CPU_TIMER
432         if (!arch_timer_get_state(&timer_context))
433                 sleep_completed = (timer_context.cntp_tval <= 0);
434 #else
435         sleep_completed = !tegra_pd_timer_remain();
436         tegra_pd_set_trigger(0);
437         arch_timer_resume(&timer_context);
438         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
439 #endif
440         sleep_time = ktime_to_us(ktime_sub(ktime_get(), entry_time));
441         idle_stats.cpu_pg_time[cpu_number(dev->cpu)] += sleep_time;
442         if (sleep_completed) {
443                 /*
444                  * Stayed in LP2 for the full time until timer expires,
445                  * adjust the exit latency based on measurement
446                  */
447                 int offset = sleep_time - request;
448                 int latency = pd_exit_latencies[cpu_number(dev->cpu)] +
449                         offset / 16;
450                 latency = clamp(latency, 0, 10000);
451                 pd_exit_latencies[cpu_number(dev->cpu)] = latency;
452                 state->exit_latency = latency;          /* for idle governor */
453                 smp_wmb();
454         }
455 #endif
456         cpu_pm_exit();
457
458         return true;
459 }
460
461 bool tegra11x_idle_power_down(struct cpuidle_device *dev,
462                            struct cpuidle_state *state)
463 {
464         bool power_down;
465         bool cpu_gating_only = false;
466         bool power_gating_cpu_only = true;
467         s64 request = ktime_to_us(tick_nohz_get_sleep_length());
468
469         tegra_set_cpu_in_pd(dev->cpu);
470         cpu_gating_only = (((fast_cluster_power_down_mode
471                         << TEGRA_POWER_CLUSTER_PART_SHIFT)
472                         & TEGRA_POWER_CLUSTER_PART_MASK) == 0);
473
474         if (is_lp_cluster()) {
475                 if (slow_cluster_power_gating_noncpu &&
476                         (request > tegra_min_residency_noncpu()))
477                                 power_gating_cpu_only = false;
478                 else
479                         power_gating_cpu_only = true;
480         } else if (!cpu_gating_only &&
481                 (num_online_cpus() == 1) &&
482                 tegra_rail_off_is_allowed() &&
483                 (request > tegra_min_residency_noncpu()))
484                         power_gating_cpu_only = false;
485         else
486                 power_gating_cpu_only = true;
487
488         if (power_gating_cpu_only)
489                 power_down = tegra_cpu_core_power_down(dev, state, request);
490         else
491                 power_down = tegra_cpu_cluster_power_down(dev, state, request);
492
493         tegra_clear_cpu_in_pd(dev->cpu);
494
495         return power_down;
496 }
497
498 #ifdef CONFIG_DEBUG_FS
499 int tegra11x_pd_debug_show(struct seq_file *s, void *data)
500 {
501         int bin;
502         int i;
503         seq_printf(s, "                                    cpu0     cpu1     cpu2     cpu3     cpulp\n");
504         seq_printf(s, "-----------------------------------------------------------------------------\n");
505         seq_printf(s, "cpu ready:                      %8u %8u %8u %8u %8u\n",
506                 idle_stats.cpu_ready_count[0],
507                 idle_stats.cpu_ready_count[1],
508                 idle_stats.cpu_ready_count[2],
509                 idle_stats.cpu_ready_count[3],
510                 idle_stats.cpu_ready_count[4]);
511         seq_printf(s, "tear down:                      %8u %8u %8u %8u %8u\n",
512                 idle_stats.tear_down_count[0],
513                 idle_stats.tear_down_count[1],
514                 idle_stats.tear_down_count[2],
515                 idle_stats.tear_down_count[3],
516                 idle_stats.tear_down_count[4]);
517         seq_printf(s, "rail gating count:      %8u\n",
518                 idle_stats.rail_gating_count);
519         seq_printf(s, "rail gating completed:  %8u %7u%%\n",
520                 idle_stats.rail_gating_done_count,
521                 idle_stats.rail_gating_done_count * 100 /
522                         (idle_stats.rail_gating_count ?: 1));
523
524         seq_printf(s, "c0nc gating count:      %8u\n",
525                 idle_stats.c0nc_gating_count);
526         seq_printf(s, "c0nc gating completed:  %8u %7u%%\n",
527                 idle_stats.c0nc_gating_done_count,
528                 idle_stats.c0nc_gating_done_count * 100 /
529                         (idle_stats.c0nc_gating_count ?: 1));
530
531         seq_printf(s, "c1nc gating count:      %8u\n",
532                 idle_stats.c1nc_gating_count);
533         seq_printf(s, "c1nc gating completed:  %8u %7u%%\n",
534                 idle_stats.c1nc_gating_done_count,
535                 idle_stats.c1nc_gating_done_count * 100 /
536                         (idle_stats.c1nc_gating_count ?: 1));
537
538         seq_printf(s, "\n");
539         seq_printf(s, "cpu ready time:                 " \
540                         "%8llu %8llu %8llu %8llu %8llu ms\n",
541                 div64_u64(idle_stats.cpu_wants_pd_time[0], 1000),
542                 div64_u64(idle_stats.cpu_wants_pd_time[1], 1000),
543                 div64_u64(idle_stats.cpu_wants_pd_time[2], 1000),
544                 div64_u64(idle_stats.cpu_wants_pd_time[3], 1000),
545                 div64_u64(idle_stats.cpu_wants_pd_time[4], 1000));
546
547         seq_printf(s, "cpu power gating time:          " \
548                         "%8llu %8llu %8llu %8llu %8llu ms\n",
549                 div64_u64(idle_stats.cpu_pg_time[0], 1000),
550                 div64_u64(idle_stats.cpu_pg_time[1], 1000),
551                 div64_u64(idle_stats.cpu_pg_time[2], 1000),
552                 div64_u64(idle_stats.cpu_pg_time[3], 1000),
553                 div64_u64(idle_stats.cpu_pg_time[4], 1000));
554
555         seq_printf(s, "power gated %%:                 " \
556                         "%7d%% %7d%% %7d%% %7d%% %7d%%\n",
557                 (int)(idle_stats.cpu_wants_pd_time[0] ?
558                         div64_u64(idle_stats.cpu_pg_time[0] * 100,
559                         idle_stats.cpu_wants_pd_time[0]) : 0),
560                 (int)(idle_stats.cpu_wants_pd_time[1] ?
561                         div64_u64(idle_stats.cpu_pg_time[1] * 100,
562                         idle_stats.cpu_wants_pd_time[1]) : 0),
563                 (int)(idle_stats.cpu_wants_pd_time[2] ?
564                         div64_u64(idle_stats.cpu_pg_time[2] * 100,
565                         idle_stats.cpu_wants_pd_time[2]) : 0),
566                 (int)(idle_stats.cpu_wants_pd_time[3] ?
567                         div64_u64(idle_stats.cpu_pg_time[3] * 100,
568                         idle_stats.cpu_wants_pd_time[3]) : 0),
569                 (int)(idle_stats.cpu_wants_pd_time[4] ?
570                         div64_u64(idle_stats.cpu_pg_time[4] * 100,
571                         idle_stats.cpu_wants_pd_time[4]) : 0));
572
573         seq_printf(s, "\n");
574         seq_printf(s, "rail gating time  c0nc gating time  c1nc gating time\n");
575         seq_printf(s, "%8llu ms          %8llu ms          %8llu ms\n",
576                 div64_u64(idle_stats.rail_pd_time, 1000),
577                 div64_u64(idle_stats.c0nc_pg_time, 1000),
578                 div64_u64(idle_stats.c1nc_pg_time, 1000));
579         seq_printf(s, "%8d%%             %8d%%             %8d%%\n",
580                 (int)(idle_stats.cpu_wants_pd_time[0] ?
581                         div64_u64(idle_stats.rail_pd_time * 100,
582                         idle_stats.cpu_wants_pd_time[0]) : 0),
583                 (int)(idle_stats.cpu_wants_pd_time[0] ?
584                         div64_u64(idle_stats.c0nc_pg_time * 100,
585                         idle_stats.cpu_wants_pd_time[0]) : 0),
586                 (int)(idle_stats.cpu_wants_pd_time[4] ?
587                         div64_u64(idle_stats.c1nc_pg_time * 100,
588                         idle_stats.cpu_wants_pd_time[4]) : 0));
589
590         seq_printf(s, "\n");
591
592         seq_printf(s, "%19s %8s %8s %8s\n", "", "rail gating", "comp", "%");
593         seq_printf(s, "-------------------------------------------------\n");
594         for (bin = 0; bin < 32; bin++) {
595                 if (idle_stats.rail_gating_bin[bin] == 0)
596                         continue;
597                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
598                         1 << (bin - 1), 1 << bin,
599                         idle_stats.rail_gating_bin[bin],
600                         idle_stats.rail_gating_done_count_bin[bin],
601                         idle_stats.rail_gating_done_count_bin[bin] * 100 /
602                                 idle_stats.rail_gating_bin[bin]);
603         }
604         seq_printf(s, "\n");
605
606         seq_printf(s, "%19s %8s %8s %8s\n", "", "c0nc gating", "comp", "%");
607         seq_printf(s, "-------------------------------------------------\n");
608         for (bin = 0; bin < 32; bin++) {
609                 if (idle_stats.c0nc_gating_bin[bin] == 0)
610                         continue;
611                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
612                         1 << (bin - 1), 1 << bin,
613                         idle_stats.c0nc_gating_bin[bin],
614                         idle_stats.c0nc_gating_done_count_bin[bin],
615                         idle_stats.c0nc_gating_done_count_bin[bin] * 100 /
616                                 idle_stats.c0nc_gating_bin[bin]);
617         }
618         seq_printf(s, "\n");
619
620         seq_printf(s, "%19s %8s %8s %8s\n", "", "c1nc gating", "comp", "%");
621         seq_printf(s, "-------------------------------------------------\n");
622         for (bin = 0; bin < 32; bin++) {
623                 if (idle_stats.c1nc_gating_bin[bin] == 0)
624                         continue;
625                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
626                         1 << (bin - 1), 1 << bin,
627                         idle_stats.c1nc_gating_bin[bin],
628                         idle_stats.c1nc_gating_done_count_bin[bin],
629                         idle_stats.c1nc_gating_done_count_bin[bin] * 100 /
630                                 idle_stats.c1nc_gating_bin[bin]);
631         }
632
633         seq_printf(s, "\n");
634         seq_printf(s, "%3s %20s %6s %10s\n",
635                 "int", "name", "count", "last count");
636         seq_printf(s, "--------------------------------------------\n");
637         for (i = 0; i < NR_IRQS; i++) {
638                 if (idle_stats.pd_int_count[i] == 0)
639                         continue;
640                 seq_printf(s, "%3d %20s %6d %10d\n",
641                         i, irq_to_desc(i)->action ?
642                                 irq_to_desc(i)->action->name ?: "???" : "???",
643                         idle_stats.pd_int_count[i],
644                         idle_stats.pd_int_count[i] -
645                                 idle_stats.last_pd_int_count[i]);
646                 idle_stats.last_pd_int_count[i] = idle_stats.pd_int_count[i];
647         };
648         return 0;
649 }
650 #endif
651
652 int __init tegra11x_cpuidle_init_soc(struct tegra_cpuidle_ops *idle_ops)
653 {
654         int i;
655         struct tegra_cpuidle_ops ops = {
656                 tegra11x_idle_power_down,
657                 tegra11x_cpu_idle_stats_pd_ready,
658                 tegra11x_cpu_idle_stats_pd_time,
659                 tegra11x_pd_is_allowed,
660 #ifdef CONFIG_DEBUG_FS
661                 tegra11x_pd_debug_show
662 #endif
663         };
664
665         cpu_clk_for_dvfs = tegra_get_clock_by_name("cpu_g");
666
667         for (i = 0; i < ARRAY_SIZE(pd_exit_latencies); i++)
668                 pd_exit_latencies[i] = tegra_pg_exit_latency;
669
670         *idle_ops = ops;
671         return 0;
672 }