00cf3e0135f6db18f6fc7603781b30534b53ddc0
[linux-3.10.git] / arch / arm / mach-tegra / cpuidle-t11x.c
1 /*
2  * arch/arm/mach-tegra/cpuidle-t11x.c
3  *
4  * CPU idle driver for Tegra11x CPUs
5  *
6  * Copyright (c) 2012-2013, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/cpu.h>
25 #include <linux/cpuidle.h>
26 #include <linux/debugfs.h>
27 #include <linux/delay.h>
28 #include <linux/hrtimer.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/io.h>
33 #include <linux/ratelimit.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/slab.h>
37 #include <linux/smp.h>
38 #include <linux/suspend.h>
39 #include <linux/tick.h>
40 #include <linux/clk.h>
41 #include <linux/cpu_pm.h>
42 #include <linux/module.h>
43
44 #include <asm/cacheflush.h>
45 #include <asm/hardware/gic.h>
46 #include <asm/localtimer.h>
47 #include <asm/suspend.h>
48 #include <asm/cputype.h>
49
50 #include <mach/irqs.h>
51 #include <mach/hardware.h>
52
53 #include <trace/events/power.h>
54
55 #include "clock.h"
56 #include "cpuidle.h"
57 #include "dvfs.h"
58 #include "fuse.h"
59 #include "gic.h"
60 #include "iomap.h"
61 #include "pm.h"
62 #include "reset.h"
63 #include "sleep.h"
64 #include "timer.h"
65 #include "fuse.h"
66
67 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS \
68         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x470)
69 #define PMC_POWERGATE_STATUS \
70         (IO_ADDRESS(TEGRA_PMC_BASE) + 0x038)
71
72 #define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
73 #define ARCH_TIMER_CTRL_IT_MASK         (1 << 1)
74
75 #ifdef CONFIG_SMP
76 static s64 tegra_cpu_wake_by_time[4] = {
77         LLONG_MAX, LLONG_MAX, LLONG_MAX, LLONG_MAX };
78 #endif
79
80 static ulong cpu_power_gating_in_idle __read_mostly = 0x1f;
81 module_param(cpu_power_gating_in_idle, ulong, 0644);
82
83 static bool slow_cluster_power_gating_noncpu __read_mostly;
84 module_param(slow_cluster_power_gating_noncpu, bool, 0644);
85
86 static uint fast_cluster_power_down_mode __read_mostly;
87 module_param(fast_cluster_power_down_mode, uint, 0644);
88
89 static struct clk *cpu_clk_for_dvfs;
90
91 static int pd_exit_latencies[5];
92
93 static struct {
94         unsigned int cpu_ready_count[5];
95         unsigned int tear_down_count[5];
96         unsigned long long cpu_wants_pd_time[5];
97         unsigned long long cpu_pg_time[5];
98         unsigned long long rail_pd_time;
99         unsigned long long c0nc_pg_time;
100         unsigned long long c1nc_pg_time;
101         unsigned int rail_gating_count;
102         unsigned int rail_gating_bin[32];
103         unsigned int rail_gating_done_count;
104         unsigned int rail_gating_done_count_bin[32];
105         unsigned int c0nc_gating_count;
106         unsigned int c0nc_gating_bin[32];
107         unsigned int c0nc_gating_done_count;
108         unsigned int c0nc_gating_done_count_bin[32];
109         unsigned int c1nc_gating_count;
110         unsigned int c1nc_gating_bin[32];
111         unsigned int c1nc_gating_done_count;
112         unsigned int c1nc_gating_done_count_bin[32];
113         unsigned int pd_int_count[NR_IRQS];
114         unsigned int last_pd_int_count[NR_IRQS];
115 } idle_stats;
116
117 static inline unsigned int time_to_bin(unsigned int time)
118 {
119         return fls(time);
120 }
121
122 static inline void tegra_irq_unmask(int irq)
123 {
124         struct irq_data *data = irq_get_irq_data(irq);
125         data->chip->irq_unmask(data);
126 }
127
128 static inline unsigned int cpu_number(unsigned int n)
129 {
130         return is_lp_cluster() ? 4 : n;
131 }
132
133 void tegra11x_cpu_idle_stats_pd_ready(unsigned int cpu)
134 {
135         idle_stats.cpu_ready_count[cpu_number(cpu)]++;
136 }
137
138 void tegra11x_cpu_idle_stats_pd_time(unsigned int cpu, s64 us)
139 {
140         idle_stats.cpu_wants_pd_time[cpu_number(cpu)] += us;
141 }
142
143 /* Allow rail off only if all secondary CPUs are power gated, and no
144    rail update is in progress */
145 static bool tegra_rail_off_is_allowed(void)
146 {
147         u32 rst = readl(CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
148         u32 pg = readl(PMC_POWERGATE_STATUS) >> 8;
149
150         if (((rst & 0xE) != 0xE) || ((pg & 0xE) != 0))
151                 return false;
152
153         if (tegra_dvfs_rail_updating(cpu_clk_for_dvfs))
154                 return false;
155
156         return true;
157 }
158
159 bool tegra11x_pd_is_allowed(struct cpuidle_device *dev,
160         struct cpuidle_state *state)
161 {
162         s64 request;
163
164         if (!cpumask_test_cpu(cpu_number(dev->cpu),
165                                 to_cpumask(&cpu_power_gating_in_idle)))
166                 return false;
167
168         if (tegra_cpu_timer_get_remain(&request))
169                 return false;
170
171         if (state->exit_latency != pd_exit_latencies[cpu_number(dev->cpu)]) {
172                 /* possible on the 1st entry after cluster switch*/
173                 state->exit_latency = pd_exit_latencies[cpu_number(dev->cpu)];
174                 tegra_pd_update_target_residency(state);
175         }
176         if (request < state->target_residency) {
177                 /* Not enough time left to enter LP2 */
178                 return false;
179         }
180
181         return true;
182 }
183
184 static inline void tegra11_irq_restore_affinity(void)
185 {
186 #ifdef CONFIG_SMP
187         /* Disable the distributor. */
188         tegra_gic_dist_disable();
189
190         /* Restore the other CPU's interrupt affinity. */
191         tegra_gic_restore_affinity();
192
193         /* Re-enable the distributor. */
194         tegra_gic_dist_enable();
195 #endif
196 }
197
198 static bool tegra_cpu_cluster_power_down(struct cpuidle_device *dev,
199                            struct cpuidle_state *state, s64 request)
200 {
201         ktime_t entry_time;
202         ktime_t exit_time;
203         bool sleep_completed = false;
204         bool multi_cpu_entry = false;
205         int bin;
206         unsigned int flag = 0;
207         s64 sleep_time;
208
209         /* LP2 entry time */
210         entry_time = ktime_get();
211
212         if (request < state->target_residency) {
213                 /* Not enough time left to enter LP2 */
214                 cpu_do_idle();
215                 return false;
216         }
217
218 #ifdef CONFIG_SMP
219         multi_cpu_entry = !is_lp_cluster() && (num_online_cpus() > 1);
220         if (multi_cpu_entry) {
221                 s64 wake_time;
222                 unsigned int i;
223
224                 /* Disable the distributor -- this is the only way to
225                    prevent the other CPUs from responding to interrupts
226                    and potentially fiddling with the distributor
227                    registers while we're fiddling with them. */
228                 tegra_gic_dist_disable();
229
230                 /* Did an interrupt come in for another CPU before we
231                    could disable the distributor? */
232                 if (!tegra_rail_off_is_allowed()) {
233                         /* Yes, re-enable the distributor and clock gating. */
234                         tegra_gic_dist_enable();
235                         cpu_do_idle();
236                         return false;
237                 }
238
239                 /* LP2 initial targeted wake time */
240                 wake_time = ktime_to_us(entry_time) + request;
241
242                 /* CPU0 must wake up before any of the other CPUs. */
243                 smp_rmb();
244                 for (i = 1; i < CONFIG_NR_CPUS; i++)
245                         wake_time = min_t(s64, wake_time,
246                                 tegra_cpu_wake_by_time[i]);
247
248                 /* LP2 actual targeted wake time */
249                 request = wake_time - ktime_to_us(entry_time);
250                 BUG_ON(wake_time < 0LL);
251
252                 if (request < state->target_residency) {
253                         /* Not enough time left to enter LP2 */
254                         tegra_gic_dist_enable();
255                         cpu_do_idle();
256                         return false;
257                 }
258
259                 /* Cancel power gating wake timers for all secondary CPUs */
260                 tegra_pd_timer_cancel_secondary();
261
262                 /* Save and disable the affinity setting for the other
263                    CPUs and route all interrupts to CPU0. */
264                 tegra_gic_disable_affinity();
265
266                 /* Re-enable the distributor. */
267                 tegra_gic_dist_enable();
268         }
269 #endif
270         cpu_pm_enter();
271
272         sleep_time = request -
273                 pd_exit_latencies[cpu_number(dev->cpu)];
274
275         bin = time_to_bin((u32)request / 1000);
276         idle_stats.tear_down_count[cpu_number(dev->cpu)]++;
277
278         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
279         if (is_lp_cluster()) {
280                 /* here we are not supporting emulation mode, for now */
281                 flag = TEGRA_POWER_CLUSTER_PART_NONCPU;
282                 idle_stats.c1nc_gating_count++;
283                 idle_stats.c1nc_gating_bin[bin]++;
284         } else {
285                 tegra_dvfs_rail_off(tegra_cpu_rail, entry_time);
286                 flag = (fast_cluster_power_down_mode
287                         << TEGRA_POWER_CLUSTER_PART_SHIFT)
288                         & TEGRA_POWER_CLUSTER_PART_MASK;
289
290                 if (((request < tegra_min_residency_crail()) &&
291                         (flag != TEGRA_POWER_CLUSTER_PART_MASK)) &&
292                         ((fast_cluster_power_down_mode &
293                         TEGRA_POWER_CLUSTER_FORCE_MASK) == 0))
294                         flag = TEGRA_POWER_CLUSTER_PART_NONCPU;
295
296                 if (flag == TEGRA_POWER_CLUSTER_PART_CRAIL) {
297                         idle_stats.rail_gating_count++;
298                         idle_stats.rail_gating_bin[bin]++;
299                 } else if (flag == TEGRA_POWER_CLUSTER_PART_NONCPU) {
300                         idle_stats.c0nc_gating_count++;
301                         idle_stats.c0nc_gating_bin[bin]++;
302                 }
303         }
304
305         if (tegra_idle_power_down_last(sleep_time, flag) == 0)
306                 sleep_completed = true;
307         else {
308                 int irq = tegra_gic_pending_interrupt();
309                 idle_stats.pd_int_count[irq]++;
310         }
311
312         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
313         exit_time = ktime_get();
314         if (!is_lp_cluster())
315                 tegra_dvfs_rail_on(tegra_cpu_rail, exit_time);
316
317         if (flag == TEGRA_POWER_CLUSTER_PART_CRAIL)
318                 idle_stats.rail_pd_time +=
319                         ktime_to_us(ktime_sub(exit_time, entry_time));
320         else if (flag == TEGRA_POWER_CLUSTER_PART_NONCPU) {
321                 if (is_lp_cluster())
322                         idle_stats.c1nc_pg_time +=
323                                 ktime_to_us(ktime_sub(exit_time, entry_time));
324                 else
325                         idle_stats.c0nc_pg_time +=
326                                 ktime_to_us(ktime_sub(exit_time, entry_time));
327         }
328
329         if (multi_cpu_entry)
330                 tegra11_irq_restore_affinity();
331
332         if (sleep_completed) {
333                 /*
334                  * Stayed in LP2 for the full time until the next tick,
335                  * adjust the exit latency based on measurement
336                  */
337                 int offset = ktime_to_us(ktime_sub(exit_time, entry_time))
338                         - request;
339                 int latency = pd_exit_latencies[cpu_number(dev->cpu)] +
340                         offset / 16;
341                 latency = clamp(latency, 0, 10000);
342                 pd_exit_latencies[cpu_number(dev->cpu)] = latency;
343                 state->exit_latency = latency;          /* for idle governor */
344                 smp_wmb();
345
346                 if (flag == TEGRA_POWER_CLUSTER_PART_CRAIL) {
347                         idle_stats.rail_gating_done_count++;
348                         idle_stats.rail_gating_done_count_bin[bin]++;
349                 } else if (flag == TEGRA_POWER_CLUSTER_PART_NONCPU) {
350                         if (is_lp_cluster()) {
351                                 idle_stats.c1nc_gating_done_count++;
352                                 idle_stats.c1nc_gating_done_count_bin[bin]++;
353                         } else {
354                                 idle_stats.c0nc_gating_done_count++;
355                                 idle_stats.c0nc_gating_done_count_bin[bin]++;
356                         }
357                 }
358
359                 pr_debug("%lld %lld %d %d\n", request,
360                         ktime_to_us(ktime_sub(exit_time, entry_time)),
361                         offset, bin);
362         }
363
364         cpu_pm_exit();
365
366         return true;
367 }
368
369 static bool tegra_cpu_core_power_down(struct cpuidle_device *dev,
370                            struct cpuidle_state *state, s64 request)
371 {
372 #ifdef CONFIG_SMP
373         s64 sleep_time;
374         u32 cntp_tval;
375         u32 cntfrq;
376         ktime_t entry_time;
377         bool sleep_completed = false;
378         struct tick_sched *ts = tick_get_tick_sched(dev->cpu);
379         unsigned int cpu = cpu_number(dev->cpu);
380
381         if ((tegra_cpu_timer_get_remain(&request) == -ETIME) ||
382                 (request <= state->target_residency) || (!ts) ||
383                 (ts->nohz_mode == NOHZ_MODE_INACTIVE) ||
384                 !tegra_is_cpu_wake_timer_ready(dev->cpu)) {
385                 /*
386                  * Not enough time left to enter LP2, or wake timer not ready
387                  */
388                 cpu_do_idle();
389                 return false;
390         }
391
392 #ifdef CONFIG_TEGRA_LP2_CPU_TIMER
393         asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (cntfrq));
394         cntp_tval = (request - state->exit_latency) * (cntfrq / 1000000);
395         asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r"(cntp_tval));
396 #endif
397         cpu_pm_enter();
398
399 #if !defined(CONFIG_TEGRA_LP2_CPU_TIMER)
400         sleep_time = request - state->exit_latency;
401         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
402         tegra_pd_set_trigger(sleep_time);
403 #endif
404         idle_stats.tear_down_count[cpu]++;
405
406         entry_time = ktime_get();
407
408         /* Save time this CPU must be awakened by. */
409         tegra_cpu_wake_by_time[dev->cpu] = ktime_to_us(entry_time) + request;
410         smp_wmb();
411
412 #ifdef CONFIG_TRUSTED_FOUNDATIONS
413         if ((cpu == 0) || (cpu == 4)) {
414                 tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE7,
415                                 (TEGRA_RESET_HANDLER_BASE +
416                                 tegra_cpu_reset_handler_offset));
417         }
418 #endif
419         cpu_suspend(0, tegra3_sleep_cpu_secondary_finish);
420
421         tegra_cpu_wake_by_time[dev->cpu] = LLONG_MAX;
422
423 #ifdef CONFIG_TEGRA_LP2_CPU_TIMER
424         asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (cntp_tval));
425         if ((s32)cntp_tval <= 0)
426                 sleep_completed = true;
427 #else
428         sleep_completed = !tegra_pd_timer_remain();
429         tegra_pd_set_trigger(0);
430         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
431 #endif
432         sleep_time = ktime_to_us(ktime_sub(ktime_get(), entry_time));
433         idle_stats.cpu_pg_time[cpu] += sleep_time;
434         if (sleep_completed) {
435                 /*
436                  * Stayed in LP2 for the full time until timer expires,
437                  * adjust the exit latency based on measurement
438                  */
439                 int offset = sleep_time - request;
440                 int latency = pd_exit_latencies[cpu] +
441                         offset / 16;
442                 latency = clamp(latency, 0, 10000);
443                 pd_exit_latencies[cpu] = latency;
444                 state->exit_latency = latency;          /* for idle governor */
445                 smp_wmb();
446         }
447 #endif
448         cpu_pm_exit();
449
450         return true;
451 }
452
453 bool tegra11x_idle_power_down(struct cpuidle_device *dev,
454                            struct cpuidle_state *state)
455 {
456         bool power_down;
457         bool cpu_gating_only = false;
458         bool power_gating_cpu_only = true;
459         int status = -1;
460         unsigned long rate = ULONG_MAX;
461         s64 request;
462
463         if (tegra_cpu_timer_get_remain(&request)) {
464                 cpu_do_idle();
465                 return false;
466         }
467
468         tegra_set_cpu_in_pd(dev->cpu);
469         cpu_gating_only = (((fast_cluster_power_down_mode
470                         << TEGRA_POWER_CLUSTER_PART_SHIFT)
471                         & TEGRA_POWER_CLUSTER_PART_MASK) == 0);
472
473         if (is_lp_cluster()) {
474                 if (slow_cluster_power_gating_noncpu &&
475                         (request > tegra_min_residency_noncpu()))
476                                 power_gating_cpu_only = false;
477                 else
478                         power_gating_cpu_only = true;
479         } else if (!cpu_gating_only &&
480                 (num_online_cpus() == 1) &&
481                 tegra_rail_off_is_allowed()) {
482                 if (fast_cluster_power_down_mode &&
483                         TEGRA_POWER_CLUSTER_FORCE_MASK)
484                         power_gating_cpu_only = cpu_gating_only;
485                 else if (request > tegra_min_residency_noncpu())
486                         power_gating_cpu_only = false;
487                 else
488                         power_gating_cpu_only = true;
489         } else
490                 power_gating_cpu_only = true;
491
492         if (power_gating_cpu_only)
493                 power_down = tegra_cpu_core_power_down(dev, state, request);
494         else {
495                 if (is_lp_cluster())
496                         status = tegra_cpu_backup_rate_exchange(&rate);
497
498                 power_down = tegra_cpu_cluster_power_down(dev, state, request);
499
500                 /* restore cpu clock after cluster power ungating */
501                 if (status == 0)
502                         tegra_cpu_backup_rate_exchange(&rate);
503         }
504
505         tegra_clear_cpu_in_pd(dev->cpu);
506
507         return power_down;
508 }
509
510 #ifdef CONFIG_DEBUG_FS
511 int tegra11x_pd_debug_show(struct seq_file *s, void *data)
512 {
513         int bin;
514         int i;
515         seq_printf(s, "                                    cpu0     cpu1     cpu2     cpu3     cpulp\n");
516         seq_printf(s, "-----------------------------------------------------------------------------\n");
517         seq_printf(s, "cpu ready:                      %8u %8u %8u %8u %8u\n",
518                 idle_stats.cpu_ready_count[0],
519                 idle_stats.cpu_ready_count[1],
520                 idle_stats.cpu_ready_count[2],
521                 idle_stats.cpu_ready_count[3],
522                 idle_stats.cpu_ready_count[4]);
523         seq_printf(s, "tear down:                      %8u %8u %8u %8u %8u\n",
524                 idle_stats.tear_down_count[0],
525                 idle_stats.tear_down_count[1],
526                 idle_stats.tear_down_count[2],
527                 idle_stats.tear_down_count[3],
528                 idle_stats.tear_down_count[4]);
529         seq_printf(s, "rail gating count:      %8u\n",
530                 idle_stats.rail_gating_count);
531         seq_printf(s, "rail gating completed:  %8u %7u%%\n",
532                 idle_stats.rail_gating_done_count,
533                 idle_stats.rail_gating_done_count * 100 /
534                         (idle_stats.rail_gating_count ?: 1));
535
536         seq_printf(s, "c0nc gating count:      %8u\n",
537                 idle_stats.c0nc_gating_count);
538         seq_printf(s, "c0nc gating completed:  %8u %7u%%\n",
539                 idle_stats.c0nc_gating_done_count,
540                 idle_stats.c0nc_gating_done_count * 100 /
541                         (idle_stats.c0nc_gating_count ?: 1));
542
543         seq_printf(s, "c1nc gating count:      %8u\n",
544                 idle_stats.c1nc_gating_count);
545         seq_printf(s, "c1nc gating completed:  %8u %7u%%\n",
546                 idle_stats.c1nc_gating_done_count,
547                 idle_stats.c1nc_gating_done_count * 100 /
548                         (idle_stats.c1nc_gating_count ?: 1));
549
550         seq_printf(s, "\n");
551         seq_printf(s, "cpu ready time:                 " \
552                         "%8llu %8llu %8llu %8llu %8llu ms\n",
553                 div64_u64(idle_stats.cpu_wants_pd_time[0], 1000),
554                 div64_u64(idle_stats.cpu_wants_pd_time[1], 1000),
555                 div64_u64(idle_stats.cpu_wants_pd_time[2], 1000),
556                 div64_u64(idle_stats.cpu_wants_pd_time[3], 1000),
557                 div64_u64(idle_stats.cpu_wants_pd_time[4], 1000));
558
559         seq_printf(s, "cpu power gating time:          " \
560                         "%8llu %8llu %8llu %8llu %8llu ms\n",
561                 div64_u64(idle_stats.cpu_pg_time[0], 1000),
562                 div64_u64(idle_stats.cpu_pg_time[1], 1000),
563                 div64_u64(idle_stats.cpu_pg_time[2], 1000),
564                 div64_u64(idle_stats.cpu_pg_time[3], 1000),
565                 div64_u64(idle_stats.cpu_pg_time[4], 1000));
566
567         seq_printf(s, "power gated %%:                 " \
568                         "%7d%% %7d%% %7d%% %7d%% %7d%%\n",
569                 (int)(idle_stats.cpu_wants_pd_time[0] ?
570                         div64_u64(idle_stats.cpu_pg_time[0] * 100,
571                         idle_stats.cpu_wants_pd_time[0]) : 0),
572                 (int)(idle_stats.cpu_wants_pd_time[1] ?
573                         div64_u64(idle_stats.cpu_pg_time[1] * 100,
574                         idle_stats.cpu_wants_pd_time[1]) : 0),
575                 (int)(idle_stats.cpu_wants_pd_time[2] ?
576                         div64_u64(idle_stats.cpu_pg_time[2] * 100,
577                         idle_stats.cpu_wants_pd_time[2]) : 0),
578                 (int)(idle_stats.cpu_wants_pd_time[3] ?
579                         div64_u64(idle_stats.cpu_pg_time[3] * 100,
580                         idle_stats.cpu_wants_pd_time[3]) : 0),
581                 (int)(idle_stats.cpu_wants_pd_time[4] ?
582                         div64_u64(idle_stats.cpu_pg_time[4] * 100,
583                         idle_stats.cpu_wants_pd_time[4]) : 0));
584
585         seq_printf(s, "\n");
586         seq_printf(s, "rail gating time  c0nc gating time  c1nc gating time\n");
587         seq_printf(s, "%8llu ms          %8llu ms          %8llu ms\n",
588                 div64_u64(idle_stats.rail_pd_time, 1000),
589                 div64_u64(idle_stats.c0nc_pg_time, 1000),
590                 div64_u64(idle_stats.c1nc_pg_time, 1000));
591         seq_printf(s, "%8d%%             %8d%%             %8d%%\n",
592                 (int)(idle_stats.cpu_wants_pd_time[0] ?
593                         div64_u64(idle_stats.rail_pd_time * 100,
594                         idle_stats.cpu_wants_pd_time[0]) : 0),
595                 (int)(idle_stats.cpu_wants_pd_time[0] ?
596                         div64_u64(idle_stats.c0nc_pg_time * 100,
597                         idle_stats.cpu_wants_pd_time[0]) : 0),
598                 (int)(idle_stats.cpu_wants_pd_time[4] ?
599                         div64_u64(idle_stats.c1nc_pg_time * 100,
600                         idle_stats.cpu_wants_pd_time[4]) : 0));
601
602         seq_printf(s, "\n");
603
604         seq_printf(s, "%19s %8s %8s %8s\n", "", "rail gating", "comp", "%");
605         seq_printf(s, "-------------------------------------------------\n");
606         for (bin = 0; bin < 32; bin++) {
607                 if (idle_stats.rail_gating_bin[bin] == 0)
608                         continue;
609                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
610                         1 << (bin - 1), 1 << bin,
611                         idle_stats.rail_gating_bin[bin],
612                         idle_stats.rail_gating_done_count_bin[bin],
613                         idle_stats.rail_gating_done_count_bin[bin] * 100 /
614                                 idle_stats.rail_gating_bin[bin]);
615         }
616         seq_printf(s, "\n");
617
618         seq_printf(s, "%19s %8s %8s %8s\n", "", "c0nc gating", "comp", "%");
619         seq_printf(s, "-------------------------------------------------\n");
620         for (bin = 0; bin < 32; bin++) {
621                 if (idle_stats.c0nc_gating_bin[bin] == 0)
622                         continue;
623                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
624                         1 << (bin - 1), 1 << bin,
625                         idle_stats.c0nc_gating_bin[bin],
626                         idle_stats.c0nc_gating_done_count_bin[bin],
627                         idle_stats.c0nc_gating_done_count_bin[bin] * 100 /
628                                 idle_stats.c0nc_gating_bin[bin]);
629         }
630         seq_printf(s, "\n");
631
632         seq_printf(s, "%19s %8s %8s %8s\n", "", "c1nc gating", "comp", "%");
633         seq_printf(s, "-------------------------------------------------\n");
634         for (bin = 0; bin < 32; bin++) {
635                 if (idle_stats.c1nc_gating_bin[bin] == 0)
636                         continue;
637                 seq_printf(s, "%6u - %6u ms: %8u %8u %7u%%\n",
638                         1 << (bin - 1), 1 << bin,
639                         idle_stats.c1nc_gating_bin[bin],
640                         idle_stats.c1nc_gating_done_count_bin[bin],
641                         idle_stats.c1nc_gating_done_count_bin[bin] * 100 /
642                                 idle_stats.c1nc_gating_bin[bin]);
643         }
644
645         seq_printf(s, "\n");
646         seq_printf(s, "%3s %20s %6s %10s\n",
647                 "int", "name", "count", "last count");
648         seq_printf(s, "--------------------------------------------\n");
649         for (i = 0; i < NR_IRQS; i++) {
650                 if (idle_stats.pd_int_count[i] == 0)
651                         continue;
652                 seq_printf(s, "%3d %20s %6d %10d\n",
653                         i, irq_to_desc(i)->action ?
654                                 irq_to_desc(i)->action->name ?: "???" : "???",
655                         idle_stats.pd_int_count[i],
656                         idle_stats.pd_int_count[i] -
657                                 idle_stats.last_pd_int_count[i]);
658                 idle_stats.last_pd_int_count[i] = idle_stats.pd_int_count[i];
659         };
660         return 0;
661 }
662 #endif
663
664 int __init tegra11x_cpuidle_init_soc(struct tegra_cpuidle_ops *idle_ops)
665 {
666         int i;
667         struct tegra_cpuidle_ops ops = {
668                 tegra11x_idle_power_down,
669                 tegra11x_cpu_idle_stats_pd_ready,
670                 tegra11x_cpu_idle_stats_pd_time,
671                 tegra11x_pd_is_allowed,
672 #ifdef CONFIG_DEBUG_FS
673                 tegra11x_pd_debug_show
674 #endif
675         };
676
677         cpu_clk_for_dvfs = tegra_get_clock_by_name("cpu_g");
678
679         for (i = 0; i < ARRAY_SIZE(pd_exit_latencies); i++)
680                 pd_exit_latencies[i] = tegra_pg_exit_latency;
681
682         *idle_ops = ops;
683         return 0;
684 }