ARM: tegra: reserve PSTORE memory
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2014 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_fdt.h>
35 #include <linux/pstore_ram.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/sys_soc.h>
38 #if defined(CONFIG_SMSC911X)
39 #include <linux/smsc911x.h>
40 #endif
41 #include <linux/pm.h>
42 #include <linux/tegra-powergate.h>
43
44 #include <linux/export.h>
45 #include <linux/bootmem.h>
46 #include <linux/tegra-soc.h>
47 #include <linux/dma-contiguous.h>
48 #include <linux/tegra-fuse.h>
49
50 #ifdef CONFIG_ARM64
51 #include <linux/irqchip/gic.h>
52 #else
53 #include <asm/system.h>
54 #include <asm/hardware/cache-l2x0.h>
55 #endif
56 #include <asm/dma-mapping.h>
57
58 #include <mach/tegra_smmu.h>
59 #include <mach/nct.h>
60 #include <mach/dc.h>
61
62 #include "apbio.h"
63 #include "board.h"
64 #include "clock.h"
65 #include "common.h"
66 #include "dvfs.h"
67 #include "iomap.h"
68 #include "pm.h"
69 #include "sleep.h"
70 #include "reset.h"
71 #include "devices.h"
72 #include "pmc.h"
73
74 #define MC_SECURITY_CFG2        0x7c
75
76 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
77 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
78 #define   PRIORITY_SELECT_USB   BIT(6)
79 #define   PRIORITY_SELECT_USB2  BIT(18)
80 #define   PRIORITY_SELECT_USB3  BIT(17)
81 #define   PRIORITY_SELECT_SE BIT(14)
82
83 #define AHB_GIZMO_AHB_MEM               0xc
84 #define   ENB_FAST_REARBITRATE  BIT(2)
85 #define   DONT_SPLIT_AHB_WR     BIT(7)
86 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
87 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
88
89 #define   RECOVERY_MODE BIT(31)
90 #define   BOOTLOADER_MODE       BIT(30)
91 #define   FORCED_RECOVERY_MODE  BIT(1)
92
93 #define AHB_GIZMO_USB           0x1c
94 #define AHB_GIZMO_USB2          0x78
95 #define AHB_GIZMO_USB3          0x7c
96 #define AHB_GIZMO_SE            0x4c
97 #define   IMMEDIATE     BIT(18)
98
99 #define AHB_MEM_PREFETCH_CFG5   0xc8
100 #define AHB_MEM_PREFETCH_CFG3   0xe0
101 #define AHB_MEM_PREFETCH_CFG4   0xe4
102 #define AHB_MEM_PREFETCH_CFG1   0xec
103 #define AHB_MEM_PREFETCH_CFG2   0xf0
104 #define AHB_MEM_PREFETCH_CFG6   0xcc
105 #define   PREFETCH_ENB  BIT(31)
106 #define   MST_ID(x)     (((x) & 0x1f) << 26)
107 #define   AHBDMA_MST_ID MST_ID(5)
108 #define   USB_MST_ID    MST_ID(6)
109 #define SDMMC4_MST_ID   MST_ID(12)
110 #define   USB2_MST_ID   MST_ID(18)
111 #define   USB3_MST_ID   MST_ID(17)
112 #define   SE_MST_ID     MST_ID(14)
113 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
114 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
115
116 #ifdef CONFIG_PSTORE_RAM
117 #define RAMOOPS_MEM_SIZE SZ_2M
118 #define FTRACE_MEM_SIZE SZ_1M
119 #endif
120
121 phys_addr_t tegra_bootloader_fb_start;
122 phys_addr_t tegra_bootloader_fb_size;
123 phys_addr_t tegra_bootloader_fb2_start;
124 phys_addr_t tegra_bootloader_fb2_size;
125 phys_addr_t tegra_fb_start;
126 phys_addr_t tegra_fb_size;
127 phys_addr_t tegra_fb2_start;
128 phys_addr_t tegra_fb2_size;
129 phys_addr_t tegra_carveout_start;
130 phys_addr_t tegra_carveout_size;
131 phys_addr_t tegra_vpr_start;
132 phys_addr_t tegra_vpr_size;
133 phys_addr_t tegra_tsec_start;
134 phys_addr_t tegra_tsec_size;
135 phys_addr_t tegra_lp0_vec_start;
136 phys_addr_t tegra_lp0_vec_size;
137 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
138 phys_addr_t tegra_wb0_params_address;
139 phys_addr_t tegra_wb0_params_instances;
140 phys_addr_t tegra_wb0_params_block_size;
141 #endif
142
143 #ifdef CONFIG_TEGRA_NVDUMPER
144 unsigned long nvdumper_reserved;
145 #endif
146 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
147 unsigned long tegra_tzram_start;
148 unsigned long tegra_tzram_size;
149 #endif
150 bool tegra_lp0_vec_relocate;
151 unsigned long tegra_grhost_aperture = ~0ul;
152 static   bool is_tegra_debug_uart_hsport;
153 static struct board_info main_board_info;
154 static struct board_info pmu_board_info;
155 static struct board_info display_board_info;
156 static int panel_id;
157 static struct board_info camera_board_info;
158 static int touch_vendor_id;
159 static int touch_panel_id;
160 static struct board_info io_board_info;
161 static struct board_info button_board_info;
162 static struct board_info joystick_board_info;
163 static struct board_info rightspeaker_board_info;
164 static struct board_info leftspeaker_board_info;
165 #ifdef CONFIG_TEGRA_USE_NCT
166 unsigned long tegra_nck_start;
167 unsigned long tegra_nck_size;
168 #endif
169
170 static int pmu_core_edp;
171 static int board_panel_type;
172 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
173 static int pwr_i2c_clk = 400;
174 static u8 power_config;
175 static u8 display_config;
176
177 static int tegra_split_mem_set;
178
179 struct device tegra_generic_cma_dev;
180 struct device tegra_vpr_cma_dev;
181
182 #define CREATE_TRACE_POINTS
183 #include <trace/events/nvsecurity.h>
184
185 u32 notrace tegra_read_cycle(void)
186 {
187         u32 cycle_count;
188
189         asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(cycle_count));
190
191         return cycle_count;
192 }
193
194 /*
195  * Storage for debug-macro.S's state.
196  *
197  * This must be in .data not .bss so that it gets initialized each time the
198  * kernel is loaded. The data is declared here rather than debug-macro.S so
199  * that multiple inclusions of debug-macro.S point at the same data.
200  */
201 u32 tegra_uart_config[4] = {
202         /* Debug UART initialization required */
203         1,
204         /* Debug UART physical address */
205         0,
206         /* Debug UART virtual address */
207         0,
208         /* Scratch space for debug macro */
209         0,
210 };
211
212
213 #define NEVER_RESET 0
214 static DEFINE_SPINLOCK(ahb_lock);
215
216 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
217 {
218         unsigned long check;
219         int retry = 10;
220         unsigned long flags;
221
222         /* Read and check if write is successful,
223          * if val doesn't match with read, retry write.
224          */
225         spin_lock_irqsave(&ahb_lock, flags);
226         do {
227                 writel(val, reg);
228                 check = readl(reg);
229                 if (likely(check == val))
230                         break;
231                 else
232                         pr_err("AHB register access fail for reg\n");
233         } while (--retry);
234         spin_unlock_irqrestore(&ahb_lock, flags);
235 }
236
237 void tegra_assert_system_reset(char mode, const char *cmd)
238 {
239         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
240         u32 reg;
241         bool empty_command = false;
242
243         if (tegra_platform_is_fpga() || NEVER_RESET) {
244                 pr_info("tegra_assert_system_reset() ignored.....");
245                 do { } while (1);
246         }
247
248         reg = readl_relaxed(reset + PMC_SCRATCH0);
249         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
250         if (cmd) {
251                 if (!strcmp(cmd, "recovery"))
252                         reg |= RECOVERY_MODE;
253                 else if (!strcmp(cmd, "bootloader"))
254                         reg |= BOOTLOADER_MODE;
255                 else if (!strcmp(cmd, "forced-recovery"))
256                         reg |= FORCED_RECOVERY_MODE;
257                 else {
258                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
259                         empty_command = true;
260                 }
261         }
262         else {
263                 /* Clearing SCRATCH0 31:30:1 on default reboot */
264                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
265         }
266         writel_relaxed(reg, reset + PMC_SCRATCH0);
267         if ((!cmd || empty_command) && pm_power_reset) {
268                 pm_power_reset();
269         } else {
270                 reg = readl_relaxed(reset);
271                 reg |= 0x10;
272                 writel_relaxed(reg, reset);
273         }
274 }
275 static int modem_id;
276 static int commchip_id;
277 static int sku_override;
278 static int debug_uart_port_id;
279 static bool uart_over_sd;
280 static enum audio_codec_type audio_codec_name;
281 static enum image_type board_image_type = system_image;
282 static int max_cpu_current;
283 static int max_core_current;
284 static int emc_max_dvfs;
285 static unsigned int memory_type;
286 static int usb_port_owner_info;
287 static int lane_owner_info;
288
289 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
290 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
291         /* name         parent          rate            enabled */
292         { "clk_m",      NULL,           0,              true },
293         { "emc",        NULL,           0,              true },
294         { "cpu",        NULL,           0,              true },
295         { "kfuse",      NULL,           0,              true },
296         { "fuse",       NULL,           0,              true },
297         { "sclk",       NULL,           0,              true },
298         { "pll_p",      NULL,           0,              true },
299         { "pll_p_out1", "pll_p",        0,              false },
300         { "pll_p_out3", "pll_p",        0,              false },
301 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
302         { "pll_m_out1", "pll_m",        275000000,      false },
303         { "pll_p_out2",  "pll_p",       102000000,      false },
304         { "sclk",        "pll_p_out2",  102000000,      true },
305         { "pll_p_out4",  "pll_p",       204000000,      true },
306         { "hclk",       "sclk",         102000000,      true },
307         { "pclk",       "hclk",         51000000,       true },
308         { "mselect",    "pll_p",        102000000,      true },
309         { "host1x",     "pll_p",        102000000,      false },
310         { "cl_dvfs_ref", "pll_p",       51000000,       true },
311         { "cl_dvfs_soc", "pll_p",       51000000,       true },
312         { "dsialp", "pll_p",    70000000,       false },
313         { "dsiblp", "pll_p",    70000000,       false },
314 #else
315         { "pll_m_out1", "pll_m",        275000000,      true },
316         { "pll_p_out2", "pll_p",        108000000,      false },
317         { "sclk",       "pll_p_out2",   108000000,      true },
318         { "pll_p_out4", "pll_p",        216000000,      true },
319         { "hclk",       "sclk",         108000000,      true },
320         { "pclk",       "hclk",         54000000,       true },
321         { "mselect",    "pll_p",        108000000,      true },
322         { "host1x",     "pll_p",        108000000,      false },
323         { "cl_dvfs_ref", "clk_m",       13000000,       false },
324         { "cl_dvfs_soc", "clk_m",       13000000,       false },
325 #endif
326 #ifdef CONFIG_TEGRA_SLOW_CSITE
327         { "csite",      "clk_m",        1000000,        true },
328 #else
329         { "csite",      NULL,           0,              true },
330 #endif
331         { "pll_u",      NULL,           480000000,      true },
332         { "pll_re_vco", NULL,           612000000,      true },
333         { "xusb_falcon_src",    "pll_p",        204000000,      false},
334         { "xusb_host_src",      "pll_p",        102000000,      false},
335         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
336         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
337         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
338         { "sdmmc1",     "pll_p",        48000000,       false},
339         { "sdmmc3",     "pll_p",        48000000,       false},
340         { "sdmmc4",     "pll_p",        48000000,       false},
341         { "sbc1.sclk",  NULL,           40000000,       false},
342         { "sbc2.sclk",  NULL,           40000000,       false},
343         { "sbc3.sclk",  NULL,           40000000,       false},
344         { "sbc4.sclk",  NULL,           40000000,       false},
345         { "sbc5.sclk",  NULL,           40000000,       false},
346         { "sbc6.sclk",  NULL,           40000000,       false},
347 #ifdef CONFIG_TEGRA_DUAL_CBUS
348         { "c2bus",      "pll_c2",       250000000,      false },
349         { "c3bus",      "pll_c3",       250000000,      false },
350         { "pll_c",      NULL,           624000000,      false },
351 #else
352         { "cbus",       "pll_c",        250000000,      false },
353 #endif
354         { "pll_c_out1", "pll_c",        150000000,      false },
355 #ifdef CONFIG_TEGRA_PLLM_SCALED
356         { "vi",         "pll_p",        0,              false},
357 #endif
358 #ifdef CONFIG_TEGRA_SOCTHERM
359         { "soc_therm",  "pll_p",        136000000,      false },
360         { "tsensor",    "clk_m",        500000,         false },
361 #endif
362         { "csite",      NULL,           0,              true },
363         { NULL,         NULL,           0,              0},
364 };
365 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
366 #ifdef CONFIG_TEGRA_DUAL_CBUS
367         { "c2bus",      "pll_c2",       250000000,      false },
368         { "c3bus",      "pll_c3",       250000000,      false },
369         { "pll_c",      NULL,           624000000,      false },
370 #else
371         { "cbus",       "pll_c",        250000000,      false },
372 #endif
373         { "pll_c_out1", "pll_c",        150000000,      false },
374         { NULL,         NULL,           0,              0},
375 };
376 #endif
377 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
378 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
379         /* name         parent          rate            enabled */
380         { "clk_m",      NULL,           0,              true },
381         { "mc",         NULL,           0,              true },
382         { "cpu",        NULL,           0,              true },
383         { "kfuse",      NULL,           0,              true },
384         { "fuse",       NULL,           0,              true },
385         { "sclk",       NULL,           0,              true },
386         { "pll_p",      NULL,           0,              true,
387                 TEGRA_CLK_INIT_PLATFORM_SI },
388         { "pll_p_out1", "pll_p",        0,              false,
389                 TEGRA_CLK_INIT_PLATFORM_SI },
390         { "pll_p_out3", "pll_p",        0,              true,
391                 TEGRA_CLK_INIT_PLATFORM_SI },
392         { "pll_m_out1", "pll_m",        275000000,      false,
393                 TEGRA_CLK_INIT_PLATFORM_SI },
394         { "pll_p_out2", "pll_p",        102000000,      false,
395                 TEGRA_CLK_INIT_PLATFORM_SI },
396         { "sclk",       "pll_p_out2",   102000000,      true,
397                 TEGRA_CLK_INIT_PLATFORM_SI },
398         { "pll_p_out4", "pll_p",        204000000,      true,
399                 TEGRA_CLK_INIT_PLATFORM_SI },
400         { "host1x",     "pll_p",        102000000,      false,
401                 TEGRA_CLK_INIT_PLATFORM_SI },
402         { "cl_dvfs_ref", "pll_p",       54000000,       true,
403                 TEGRA_CLK_INIT_PLATFORM_SI },
404         { "cl_dvfs_soc", "pll_p",       54000000,       true,
405                 TEGRA_CLK_INIT_PLATFORM_SI },
406         { "hclk",       "sclk",         102000000,      true,
407                 TEGRA_CLK_INIT_PLATFORM_SI },
408         { "pclk",       "hclk",         51000000,       true,
409                 TEGRA_CLK_INIT_PLATFORM_SI },
410         { "wake.sclk",  NULL,           40000000,       true,
411                 TEGRA_CLK_INIT_PLATFORM_SI },
412         { "mselect",    "pll_p",        102000000,      true,
413                 TEGRA_CLK_INIT_PLATFORM_SI },
414         { "pll_p_out5", "pll_p",        102000000,      true,
415                 TEGRA_CLK_INIT_PLATFORM_SI },
416 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
417         { "pll_m_out1", "pll_m",        275000000,      true,
418                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
419         { "pll_p_out2", "pll_p",        108000000,      false,
420                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
421         { "sclk",       "pll_p_out2",   108000000,      true,
422                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
423         { "pll_p_out4", "pll_p",        216000000,      true,
424                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
425         { "hclk",       "sclk",         108000000,      true,
426                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
427         { "pclk",       "hclk",         54000000,       true,
428                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
429         { "mselect",    "pll_p",        108000000,      true,
430                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
431         { "host1x",     "pll_p",        108000000,      false,
432                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
433         { "cl_dvfs_ref", "clk_m",       13000000,       false,
434                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
435         { "cl_dvfs_soc", "clk_m",       13000000,       false,
436                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
437         { "vde",        "pll_c3",       48400000,       true,
438                 TEGRA_CLK_INIT_CPU_ASIM},
439 #endif
440 #ifdef CONFIG_TEGRA_SLOW_CSITE
441         { "csite",      "clk_m",        1000000,        true },
442 #else
443         { "csite",      NULL,           0,              true },
444 #endif
445         { "pll_u",      NULL,           480000000,      true },
446         { "pll_re_vco", NULL,           672000000,      true },
447         { "xusb_falcon_src",    "pll_re_out",   224000000,      false},
448         { "xusb_host_src",      "pll_re_out",   112000000,      false},
449         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
450         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
451         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
452         { "sdmmc1",     "pll_p",        48000000,       false},
453         { "sdmmc3",     "pll_p",        48000000,       false},
454         { "sdmmc4",     "pll_p",        48000000,       false},
455         { "sdmmc1_ddr", "pll_p",        48000000,       false},
456         { "sdmmc3_ddr", "pll_p",        48000000,       false},
457         { "sdmmc4_ddr", "pll_p",        48000000,       false},
458         { "sbc1.sclk",  NULL,           40000000,       false},
459         { "sbc2.sclk",  NULL,           40000000,       false},
460         { "sbc3.sclk",  NULL,           40000000,       false},
461         { "sbc4.sclk",  NULL,           40000000,       false},
462         { "sbc5.sclk",  NULL,           40000000,       false},
463         { "sbc6.sclk",  NULL,           40000000,       false},
464         { "cpu.mselect", NULL,          102000000,      true},
465         { "gpu_ref",    NULL,           0,              true},
466         { "gk20a.gbus", NULL,           252000000,      false},
467 #ifdef CONFIG_TEGRA_PLLM_SCALED
468         { "vi",         "pll_p",        0,              false},
469         { "isp",        "pll_p",        0,              false},
470 #endif
471 #ifdef CONFIG_TEGRA_SOCTHERM
472         { "soc_therm",  "pll_p",        51000000,       false },
473         { "tsensor",    "clk_m",        500000,         false },
474 #endif
475         { NULL,         NULL,           0,              0},
476 };
477 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
478         /* Initialize c2bus, c3bus, or cbus at the end of the list
479          * after all the clocks are moved under the proper parents.
480          */
481 #ifdef CONFIG_TEGRA_DUAL_CBUS
482         { "c2bus",      "pll_c2",       250000000,      false },
483         { "c3bus",      "pll_c3",       250000000,      false },
484         { "pll_c",      NULL,           600000000,      false },
485 #else
486         { "cbus",       "pll_c",        200000000,      false },
487 #endif
488         { "pll_c_out1", "pll_c",        100000000,      false },
489         { "c4bus",      "pll_c4",       200000000,      false },
490         { NULL,         NULL,           0,              0},
491 };
492 #endif
493
494 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
495 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
496         /* name         parent          rate            enabled */
497         { "osc",        NULL,           0,              true },
498         { "clk_m",      "osc",          0,              true },
499         { "emc",        NULL,           0,              true },
500         { "cpu",        NULL,           0,              true },
501         { "kfuse",      NULL,           0,              true },
502         { "fuse",       NULL,           0,              true },
503         { "sclk",       NULL,           0,              true },
504 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
505         { "pll_p",      NULL,           0,              true },
506         { "pll_p_out1", "pll_p",        0,              false },
507         { "pll_p_out3", "pll_p",        0,              true },
508         { "pll_m_out1", "pll_m",        275000000,      false },
509         { "pll_p_out2",  "pll_p",       102000000,      false },
510         { "sclk",        "pll_p_out2",  102000000,      true },
511         { "pll_p_out4",  "pll_p",       204000000,      true },
512         { "hclk",       "sclk",         102000000,      true },
513         { "pclk",       "hclk",         51000000,       true },
514         { "mselect",    "pll_p",        102000000,      true },
515         { "host1x",     "pll_p",        102000000,      false },
516         { "cl_dvfs_ref", "pll_p",       51000000,       true },
517         { "cl_dvfs_soc", "pll_p",       51000000,       true },
518 #else
519         { "pll_p",      NULL,           0,              true },
520         { "pll_p_out1", "pll_p",        0,              false },
521         { "pll_p_out3", "pll_p",        0,              true },
522         { "pll_m_out1", "pll_m",        275000000,      true },
523         { "pll_p_out2", "pll_p",        108000000,      false },
524         { "sclk",       "pll_p_out2",   108000000,      true },
525         { "pll_p_out4", "pll_p",        216000000,      true },
526         { "host1x",     "pll_p",        108000000,      false },
527         { "cl_dvfs_ref", "clk_m",       13000000,       false },
528         { "cl_dvfs_soc", "clk_m",       13000000,       false },
529         { "hclk",       "sclk",         108000000,      true },
530         { "pclk",       "hclk",         54000000,       true },
531         { "wake.sclk",  NULL,           250000000,      true },
532         { "mselect",    "pll_p",        108000000,      true },
533 #endif
534 #ifdef CONFIG_TEGRA_SLOW_CSITE
535         { "csite",      "clk_m",        1000000,        true },
536 #else
537         { "csite",      NULL,           0,              true },
538 #endif
539         { "pll_u",      NULL,           480000000,      false },
540         { "sdmmc1",     "pll_p",        48000000,       false},
541         { "sdmmc3",     "pll_p",        48000000,       false},
542         { "sdmmc4",     "pll_p",        48000000,       false},
543         { "mon.avp",    NULL,           80000000,       true },
544         { "sbc1.sclk",  NULL,           20000000,       false},
545         { "sbc2.sclk",  NULL,           20000000,       false},
546         { "sbc3.sclk",  NULL,           20000000,       false},
547         { "msenc",      "pll_p",        108000000,      false },
548         { "tsec",       "pll_p",        108000000,      false },
549         { "mc_capa",    "emc",          0,              true },
550         { "mc_cbpa",    "emc",          0,              true },
551 #ifdef CONFIG_TEGRA_SOCTHERM
552         { "soc_therm",  "pll_p",        51000000,       false },
553         { "tsensor",    "clk_m",        400000,         false },
554 #endif
555         { NULL,         NULL,           0,              0},
556 };
557 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
558         /* Initialize c2bus, c3bus, or cbus at the end of the list
559          * after all the clocks are moved under the proper parents.
560          */
561 #ifdef CONFIG_TEGRA_DUAL_CBUS
562         { "c2bus",      "pll_c2",       200000000,      false },
563         { "c3bus",      "pll_c3",       200000000,      false },
564         { "pll_c",      NULL,           768000000,      false },
565 #else
566         { "cbus",       "pll_c",        200000000,      false },
567 #endif
568         { "pll_c_out1", "pll_c",        100000000,      false },
569         { NULL,         NULL,           0,              0},
570 };
571 #endif
572
573 #ifdef CONFIG_CACHE_L2X0
574 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
575 static void tegra_cache_smc(bool enable, u32 arg)
576 {
577         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
578         bool need_affinity_switch;
579         bool can_switch_affinity;
580         bool l2x0_enabled;
581         cpumask_t local_cpu_mask;
582         cpumask_t saved_cpu_mask;
583         unsigned long flags;
584         long ret;
585
586         /*
587          * ISSUE : Some registers of PL310 controler must be written
588          *              from Secure context (and from CPU0)!
589          *
590          * When called form Normal we obtain an abort or do nothing.
591          * Instructions that must be called in Secure:
592          *      - Write to Control register (L2X0_CTRL==0x100)
593          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
594          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
595          *              mandatory at boot time.
596          *      - Tag and Data RAM Latency Control Registers
597          *              (0x108 & 0x10C) must be written in Secure.
598          */
599         need_affinity_switch = (smp_processor_id() != 0);
600         can_switch_affinity = !irqs_disabled();
601
602         WARN_ON(need_affinity_switch && !can_switch_affinity);
603         if (need_affinity_switch && can_switch_affinity) {
604                 cpu_set(0, local_cpu_mask);
605                 sched_getaffinity(0, &saved_cpu_mask);
606                 ret = sched_setaffinity(0, &local_cpu_mask);
607                 WARN_ON(ret != 0);
608         }
609
610         local_irq_save(flags);
611         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
612         if (enable && !l2x0_enabled)
613                 tegra_generic_smc(0x82000002, 0x00000001, arg);
614         else if (!enable && l2x0_enabled)
615                 tegra_generic_smc(0x82000002, 0x00000002, arg);
616         local_irq_restore(flags);
617
618         if (need_affinity_switch && can_switch_affinity) {
619                 ret = sched_setaffinity(0, &saved_cpu_mask);
620                 WARN_ON(ret != 0);
621         }
622 }
623
624 static void tegra_l2x0_disable(void)
625 {
626         unsigned long flags;
627         static u32 l2x0_way_mask;
628
629         if (!l2x0_way_mask) {
630                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
631                 u32 aux_ctrl;
632                 u32 ways;
633
634                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
635                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
636                 l2x0_way_mask = (1 << ways) - 1;
637         }
638
639         local_irq_save(flags);
640         tegra_cache_smc(false, l2x0_way_mask);
641         local_irq_restore(flags);
642 }
643 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
644
645 void tegra_init_cache(bool init)
646 {
647         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
648         u32 aux_ctrl;
649 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
650         u32 cache_type;
651         u32 tag_latency, data_latency;
652 #endif
653
654 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
655         /* issue the SMC to enable the L2 */
656         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
657         trace_smc_init_cache(NVSEC_SMC_START);
658         tegra_cache_smc(true, aux_ctrl);
659         trace_smc_init_cache(NVSEC_SMC_DONE);
660
661         /* after init, reread aux_ctrl and register handlers */
662         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
663         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
664
665         /* override outer_disable() with our disable */
666         outer_cache.disable = tegra_l2x0_disable;
667 #else
668 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
669         tag_latency = 0x331;
670         data_latency = 0x441;
671 #else
672         if (!tegra_platform_is_silicon()) {
673                 tag_latency = 0x770;
674                 data_latency = 0x770;
675         } else if (is_lp_cluster()) {
676                 tag_latency = tegra_cpu_c1_l2_tag_latency;
677                 data_latency = tegra_cpu_c1_l2_data_latency;
678         } else {
679                 tag_latency = tegra_cpu_c0_l2_tag_latency;
680                 data_latency = tegra_cpu_c0_l2_data_latency;
681         }
682 #endif
683         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
684         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
685
686 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
687         if (!tegra_platform_is_fpga()) {
688 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
689                 /* Enable double line fill */
690                 writel(0x40000007, p + L2X0_PREFETCH_CTRL);
691 #else
692                 writel(0x7, p + L2X0_PREFETCH_CTRL);
693 #endif
694                 writel(0x3, p + L2X0_POWER_CTRL);
695         }
696 #endif
697         cache_type = readl(p + L2X0_CACHE_TYPE);
698         aux_ctrl = (cache_type & 0x700) << (17-8);
699         aux_ctrl |= 0x7C400001;
700         if (init) {
701                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
702         } else {
703                 u32 tmp;
704
705                 tmp = aux_ctrl;
706                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
707                 aux_ctrl &= 0x8200c3fe;
708                 aux_ctrl |= tmp;
709                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
710         }
711         l2x0_enable();
712 #endif
713 }
714 #endif
715
716 static void __init tegra_perf_init(void)
717 {
718         u32 reg;
719
720 #ifdef CONFIG_ARM64
721         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
722         reg >>= 11;
723         reg = (1 << (reg & 0x1f))-1;
724         reg |= 0x80000000;
725         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
726         reg = 1;
727         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
728 #else
729         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
730         reg >>= 11;
731         reg = (1 << (reg & 0x1f))-1;
732         reg |= 0x80000000;
733         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
734         reg = 1;
735         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
736 #endif
737 }
738
739 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
740 static void __init tegra_ramrepair_init(void)
741 {
742 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
743         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
744 #endif
745                 u32 reg;
746                 reg = readl(FLOW_CTRL_RAM_REPAIR);
747                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
748                 writel(reg, FLOW_CTRL_RAM_REPAIR);
749 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
750         }
751 #endif
752 }
753 #endif
754
755 static void __init tegra_init_power(void)
756 {
757 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
758         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
759 #endif
760 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
761         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
762 #endif
763
764 #if defined(CONFIG_TEGRA_XUSB_PLATFORM)
765         /* powergate xusb partitions by default */
766         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
767         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
768         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
769 #endif
770
771 }
772
773 static inline unsigned long gizmo_readl(unsigned long offset)
774 {
775         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
776 }
777
778 static inline void gizmo_writel(unsigned long value, unsigned long offset)
779 {
780         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
781 }
782
783 static void __init tegra_init_ahb_gizmo_settings(void)
784 {
785         unsigned long val;
786
787         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
788         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
789
790         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
791                 val |= WR_WAIT_COMMIT_ON_1K;
792 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
793         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
794 #endif
795         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
796
797         val = gizmo_readl(AHB_GIZMO_USB);
798         val |= IMMEDIATE;
799         gizmo_writel(val, AHB_GIZMO_USB);
800
801         val = gizmo_readl(AHB_GIZMO_USB2);
802         val |= IMMEDIATE;
803         gizmo_writel(val, AHB_GIZMO_USB2);
804
805         val = gizmo_readl(AHB_GIZMO_USB3);
806         val |= IMMEDIATE;
807         gizmo_writel(val, AHB_GIZMO_USB3);
808
809         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
810         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
811                                 | AHB_PRIORITY_WEIGHT(7);
812 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
813         val |= PRIORITY_SELECT_SE;
814 #endif
815
816         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
817
818         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
819         val &= ~MST_ID(~0);
820         val |= PREFETCH_ENB | AHBDMA_MST_ID |
821                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
822         ahb_gizmo_writel(val,
823                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
824
825         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
826         val &= ~MST_ID(~0);
827         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
828                 INACTIVITY_TIMEOUT(0x1000);
829         ahb_gizmo_writel(val,
830                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
831
832         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
833         val &= ~MST_ID(~0);
834         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
835                 INACTIVITY_TIMEOUT(0x1000);
836         ahb_gizmo_writel(val,
837                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
838
839         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
840         val &= ~MST_ID(~0);
841         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
842                 INACTIVITY_TIMEOUT(0x1000);
843         ahb_gizmo_writel(val,
844                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
845
846         /*
847          * SDMMC controller is removed from AHB interface in T124 and
848          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
849          * in T11x and T14x SOCs.
850          */
851 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
852         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
853         val &= ~MST_ID(~0);
854         val |= PREFETCH_ENB | SDMMC4_MST_ID;
855         val &= ~SDMMC4_MST_ID;
856         ahb_gizmo_writel(val,
857                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
858 #endif
859
860 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
861         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
862         val &= ~MST_ID(~0);
863         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
864                 INACTIVITY_TIMEOUT(0x1000);
865         ahb_gizmo_writel(val,
866                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
867 #endif
868 }
869
870 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
871 void __init tegra20_init_early(void)
872 {
873 #ifndef CONFIG_SMP
874         /* For SMP system, initializing the reset handler here is too
875            late. For non-SMP systems, the function that calls the reset
876            handler initializer is not called, so do it here for non-SMP. */
877         tegra_cpu_reset_handler_init();
878 #endif
879         tegra_apb_io_init();
880         tegra_perf_init();
881         tegra_init_fuse();
882         tegra_init_cache(true);
883         tegra_pmc_init();
884         tegra_powergate_init();
885         tegra20_hotplug_init();
886         tegra_init_power();
887         tegra_init_ahb_gizmo_settings();
888         tegra_init_debug_uart_rate();
889 }
890 #endif
891 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
892 void __init tegra30_init_early(void)
893 {
894         u32 speedo;
895         u32 tag_latency, data_latency;
896
897         display_tegra_dt_info();
898 #ifndef CONFIG_SMP
899         /* For SMP system, initializing the reset handler here is too
900            late. For non-SMP systems, the function that calls the reset
901            handler initializer is not called, so do it here for non-SMP. */
902         tegra_cpu_reset_handler_init();
903 #endif
904         tegra_apb_io_init();
905         tegra_perf_init();
906         tegra_init_fuse();
907         /*
908          * Store G/LP cluster L2 latencies to IRAM and DRAM
909          */
910         tegra_cpu_c1_l2_tag_latency = 0x221;
911         tegra_cpu_c1_l2_data_latency = 0x221;
912         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
913         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
914         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
915         speedo = tegra_cpu_speedo_id();
916         if (speedo == 4 || speedo == 5 || speedo == 6 ||
917             speedo == 12 || speedo == 13) {
918                 tag_latency = 0x442;
919                 data_latency = 0x552;
920         } else {
921                 tag_latency = 0x441;
922                 data_latency = 0x551;
923         }
924         tegra_cpu_c0_l2_tag_latency = tag_latency;
925         tegra_cpu_c0_l2_data_latency = data_latency;
926         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
927         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
928         tegra_init_cache(true);
929         tegra_pmc_init();
930         tegra_powergate_init();
931         tegra30_hotplug_init();
932         tegra_init_power();
933         tegra_init_ahb_gizmo_settings();
934         tegra_init_debug_uart_rate();
935
936         init_dma_coherent_pool_size(SZ_1M);
937 }
938 #endif
939 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
940 void __init tegra11x_init_early(void)
941 {
942         display_tegra_dt_info();
943 #ifndef CONFIG_SMP
944         /* For SMP system, initializing the reset handler here is too
945            late. For non-SMP systems, the function that calls the reset
946            handler initializer is not called, so do it here for non-SMP. */
947         tegra_cpu_reset_handler_init();
948 #endif
949         tegra_apb_io_init();
950         tegra_perf_init();
951         tegra_init_fuse();
952         tegra_ramrepair_init();
953         tegra11x_init_clocks();
954         tegra11x_init_dvfs();
955         tegra_common_init_clock();
956         tegra_clk_init_from_table(tegra11x_clk_init_table);
957         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
958         tegra11x_clk_init_la();
959         tegra_pmc_init();
960         tegra_powergate_init();
961         tegra30_hotplug_init();
962         tegra_init_power();
963         tegra_init_ahb_gizmo_settings();
964         tegra_init_debug_uart_rate();
965
966         init_dma_coherent_pool_size(SZ_2M);
967 }
968 #endif
969 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
970 void __init tegra12x_init_early(void)
971 {
972         display_tegra_dt_info();
973 #ifndef CONFIG_SMP
974         /* For SMP system, initializing the reset handler here is too
975            late. For non-SMP systems, the function that calls the reset
976            handler initializer is not called, so do it here for non-SMP. */
977         tegra_cpu_reset_handler_init();
978 #endif
979         tegra_apb_io_init();
980         tegra_perf_init();
981         tegra_init_fuse();
982         tegra_ramrepair_init();
983         tegra12x_init_clocks();
984         tegra12x_init_dvfs();
985         tegra_common_init_clock();
986         tegra_clk_init_from_table(tegra12x_clk_init_table);
987         tegra_clk_init_cbus_plls_from_table(tegra12x_cbus_init_table);
988         tegra_pmc_init();
989         tegra_powergate_init();
990         tegra30_hotplug_init();
991         tegra_init_power();
992         tegra_init_ahb_gizmo_settings();
993         tegra_init_debug_uart_rate();
994 }
995 #endif
996 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
997 void __init tegra14x_init_early(void)
998 {
999         display_tegra_dt_info();
1000 #ifndef CONFIG_SMP
1001         /* For SMP system, initializing the reset handler here is too
1002            late. For non-SMP systems, the function that calls the reset
1003            handler initializer is not called, so do it here for non-SMP. */
1004         tegra_cpu_reset_handler_init();
1005 #endif
1006         tegra_apb_io_init();
1007         tegra_perf_init();
1008         tegra_init_fuse();
1009         tegra_ramrepair_init();
1010         tegra14x_init_clocks();
1011         tegra14x_init_dvfs();
1012         tegra_common_init_clock();
1013         tegra_clk_init_from_table(tegra14x_clk_init_table);
1014         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
1015         tegra_cpu_c1_l2_tag_latency = 0x110;
1016         tegra_cpu_c1_l2_data_latency = 0x331;
1017         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
1018         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
1019         tegra_cpu_c0_l2_tag_latency = 0x111;
1020         tegra_cpu_c0_l2_data_latency = 0x441;
1021         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
1022         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
1023         tegra_init_cache(true);
1024         tegra_pmc_init();
1025         tegra_powergate_init();
1026         tegra30_hotplug_init();
1027         tegra_init_power();
1028         tegra_init_ahb_gizmo_settings();
1029         tegra_init_debug_uart_rate();
1030 }
1031 #endif
1032 static int __init tegra_lp0_vec_arg(char *options)
1033 {
1034         char *p = options;
1035
1036         tegra_lp0_vec_size = memparse(p, &p);
1037         if (*p == '@')
1038                 tegra_lp0_vec_start = memparse(p+1, &p);
1039         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
1040                 tegra_lp0_vec_size = 0;
1041                 tegra_lp0_vec_start = 0;
1042         }
1043
1044         return 0;
1045 }
1046 early_param("lp0_vec", tegra_lp0_vec_arg);
1047
1048 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1049 static int __init tegra_wb0_params_arg(char *options)
1050 {
1051         char *p = options;
1052
1053         tegra_wb0_params_address = memparse(p, &p);
1054         if (*p == ',')
1055                 tegra_wb0_params_instances = memparse(p+1, &p);
1056         if (*p == ',')
1057                 tegra_wb0_params_block_size = memparse(p+1, &p);
1058
1059         return 0;
1060 }
1061 early_param("wb0_params", tegra_wb0_params_arg);
1062 #endif
1063
1064 #ifdef CONFIG_TEGRA_NVDUMPER
1065 static int __init tegra_nvdumper_arg(char *options)
1066 {
1067         char *p = options;
1068
1069         nvdumper_reserved = memparse(p, &p);
1070         return 0;
1071 }
1072 early_param("nvdumper_reserved", tegra_nvdumper_arg);
1073 #endif
1074
1075 static int __init tegra_bootloader_fb_arg(char *options)
1076 {
1077         char *p = options;
1078
1079         tegra_bootloader_fb_size = memparse(p, &p);
1080         if (*p == '@')
1081                 tegra_bootloader_fb_start = memparse(p+1, &p);
1082
1083         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1084                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1085
1086         return 0;
1087 }
1088 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1089
1090 static int __init tegra_bootloader_fb2_arg(char *options)
1091 {
1092         char *p = options;
1093
1094         tegra_bootloader_fb2_size = memparse(p, &p);
1095         if (*p == '@')
1096                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1097
1098         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1099                 (u64)tegra_bootloader_fb2_size,
1100                 (u64)tegra_bootloader_fb2_start);
1101
1102         return 0;
1103 }
1104 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1105
1106 static int __init tegra_sku_override(char *id)
1107 {
1108         char *p = id;
1109
1110         sku_override = memparse(p, &p);
1111
1112         return 0;
1113 }
1114 early_param("sku_override", tegra_sku_override);
1115
1116 int tegra_get_sku_override(void)
1117 {
1118         return sku_override;
1119 }
1120
1121 static int __init tegra_vpr_arg(char *options)
1122 {
1123         char *p = options;
1124
1125         tegra_vpr_size = memparse(p, &p);
1126         if (*p == '@')
1127                 tegra_vpr_start = memparse(p+1, &p);
1128         pr_info("Found vpr, start=0x%llx size=%llx",
1129                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1130         return 0;
1131 }
1132 early_param("vpr", tegra_vpr_arg);
1133
1134 static int __init tegra_tsec_arg(char *options)
1135 {
1136         char *p = options;
1137
1138         tegra_tsec_size = memparse(p, &p);
1139         if (*p == '@')
1140                 tegra_tsec_start = memparse(p+1, &p);
1141         pr_info("Found tsec, start=0x%llx size=%llx",
1142                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1143         return 0;
1144 }
1145 early_param("tsec", tegra_tsec_arg);
1146
1147 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1148 static int __init tegra_tzram_arg(char *options)
1149 {
1150         char *p = options;
1151
1152         tegra_tzram_size = memparse(p, &p);
1153         if (*p == '@')
1154                 tegra_tzram_start = memparse(p + 1, &p);
1155         return 0;
1156 }
1157 early_param("tzram", tegra_tzram_arg);
1158 #endif
1159
1160 #ifdef CONFIG_TEGRA_USE_NCT
1161 static int __init tegra_nck_arg(char *options)
1162 {
1163         char *p = options;
1164
1165         tegra_nck_size = memparse(p, &p);
1166         if (*p == '@')
1167                 tegra_nck_start = memparse(p+1, &p);
1168         if (!tegra_nck_size || !tegra_nck_start) {
1169                 tegra_nck_size = 0;
1170                 tegra_nck_start = 0;
1171         }
1172
1173         return 0;
1174 }
1175 early_param("nck", tegra_nck_arg);
1176 #endif  /* CONFIG_TEGRA_USE_NCT */
1177
1178 enum panel_type get_panel_type(void)
1179 {
1180         return board_panel_type;
1181 }
1182 static int __init tegra_board_panel_type(char *options)
1183 {
1184         if (!strcmp(options, "lvds"))
1185                 board_panel_type = panel_type_lvds;
1186         else if (!strcmp(options, "dsi"))
1187                 board_panel_type = panel_type_dsi;
1188         else
1189                 return 0;
1190         return 1;
1191 }
1192 __setup("panel=", tegra_board_panel_type);
1193
1194 int tegra_get_board_panel_id(void)
1195 {
1196         return panel_id;
1197 }
1198 static int __init tegra_board_panel_id(char *options)
1199 {
1200         char *p = options;
1201         panel_id = memparse(p, &p);
1202         return panel_id;
1203 }
1204 __setup("display_panel=", tegra_board_panel_id);
1205
1206 int tegra_get_touch_vendor_id(void)
1207 {
1208         return touch_vendor_id;
1209 }
1210 int tegra_get_touch_panel_id(void)
1211 {
1212         return touch_panel_id;
1213 }
1214 static int __init tegra_touch_id(char *options)
1215 {
1216         char *p = options;
1217         touch_vendor_id = memparse(p, &p);
1218         if (*p == '@')
1219                 touch_panel_id = memparse(p+1, &p);
1220         return 1;
1221 }
1222 __setup("touch_id=", tegra_touch_id);
1223
1224 u8 get_power_config(void)
1225 {
1226         return power_config;
1227 }
1228 static int __init tegra_board_power_config(char *options)
1229 {
1230         char *p = options;
1231         power_config = memparse(p, &p);
1232         return 1;
1233 }
1234 __setup("power-config=", tegra_board_power_config);
1235
1236 u8 get_display_config(void)
1237 {
1238         return display_config;
1239 }
1240 static int __init tegra_board_display_config(char *options)
1241 {
1242         char *p = options;
1243         display_config = memparse(p, &p);
1244         return 1;
1245 }
1246 __setup("display-config=", tegra_board_display_config);
1247
1248 enum power_supply_type get_power_supply_type(void)
1249 {
1250         return pow_supply_type;
1251 }
1252 static int __init tegra_board_power_supply_type(char *options)
1253 {
1254         if (!strcmp(options, "Adapter"))
1255                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1256         if (!strcmp(options, "Mains"))
1257                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1258         else if (!strcmp(options, "Battery"))
1259                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1260         else
1261                 return 0;
1262         return 1;
1263 }
1264 __setup("power_supply=", tegra_board_power_supply_type);
1265
1266 int get_core_edp(void)
1267 {
1268         return pmu_core_edp;
1269 }
1270 static int __init tegra_pmu_core_edp(char *options)
1271 {
1272         char *p = options;
1273         int core_edp = memparse(p, &p);
1274         if (core_edp != 0)
1275                 pmu_core_edp = core_edp;
1276         return 0;
1277 }
1278 early_param("core_edp_mv", tegra_pmu_core_edp);
1279
1280 int get_maximum_cpu_current_supported(void)
1281 {
1282         return max_cpu_current;
1283 }
1284 static int __init tegra_max_cpu_current(char *options)
1285 {
1286         char *p = options;
1287         max_cpu_current = memparse(p, &p);
1288         return 1;
1289 }
1290 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1291
1292 int get_maximum_core_current_supported(void)
1293 {
1294         return max_core_current;
1295 }
1296 static int __init tegra_max_core_current(char *options)
1297 {
1298         char *p = options;
1299         max_core_current = memparse(p, &p);
1300         return 0;
1301 }
1302 early_param("core_edp_ma", tegra_max_core_current);
1303
1304 int get_emc_max_dvfs(void)
1305 {
1306         return emc_max_dvfs;
1307 }
1308 static int __init tegra_emc_max_dvfs(char *options)
1309 {
1310         char *p = options;
1311         emc_max_dvfs = memparse(p, &p);
1312         return 1;
1313 }
1314 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1315
1316 int tegra_get_memory_type(void)
1317 {
1318         return memory_type;
1319 }
1320 static int __init tegra_memory_type(char *options)
1321 {
1322         char *p = options;
1323         memory_type = memparse(p, &p);
1324         return 1;
1325 }
1326 __setup("memtype=", tegra_memory_type);
1327
1328 static int __init tegra_debug_uartport(char *info)
1329 {
1330         char *p = info;
1331         unsigned long long port_id;
1332         if (!strncmp(p, "hsport", 6))
1333                 is_tegra_debug_uart_hsport = true;
1334         else if (!strncmp(p, "lsport", 6))
1335                 is_tegra_debug_uart_hsport = false;
1336
1337         if (p[6] == ',') {
1338                 if (p[7] == '-') {
1339                         debug_uart_port_id = -1;
1340                 } else {
1341                         port_id = memparse(p + 7, &p);
1342                         debug_uart_port_id = (int) port_id;
1343                         if (debug_uart_port_id == 5)
1344                                 uart_over_sd = true;
1345                 }
1346         } else {
1347                 debug_uart_port_id = -1;
1348         }
1349
1350         return 1;
1351 }
1352
1353 bool is_tegra_debug_uartport_hs(void)
1354 {
1355         return is_tegra_debug_uart_hsport;
1356 }
1357
1358 bool is_uart_over_sd_enabled(void)
1359 {
1360         return uart_over_sd;
1361 }
1362
1363 void set_sd_uart_port_id(int port_id)
1364 {
1365         debug_uart_port_id = port_id;
1366 }
1367
1368 int get_tegra_uart_debug_port_id(void)
1369 {
1370         return debug_uart_port_id;
1371 }
1372 __setup("debug_uartport=", tegra_debug_uartport);
1373
1374 static int __init tegra_image_type(char *options)
1375 {
1376         if (!strcmp(options, "RCK"))
1377                 board_image_type = rck_image;
1378
1379         return 0;
1380 }
1381
1382 enum image_type get_tegra_image_type(void)
1383 {
1384         return board_image_type;
1385 }
1386
1387 __setup("image=", tegra_image_type);
1388
1389 static int __init tegra_audio_codec_type(char *info)
1390 {
1391         char *p = info;
1392         if (!strncmp(p, "wm8903", 6))
1393                 audio_codec_name = audio_codec_wm8903;
1394         else
1395                 audio_codec_name = audio_codec_none;
1396
1397         return 1;
1398 }
1399
1400 enum audio_codec_type get_audio_codec_type(void)
1401 {
1402         return audio_codec_name;
1403 }
1404 __setup("audio_codec=", tegra_audio_codec_type);
1405
1406 static int tegra_get_pwr_i2c_clk_rate(char *options)
1407 {
1408         int clk = simple_strtol(options, NULL, 16);
1409         if (clk != 0)
1410                 pwr_i2c_clk = clk;
1411         return 0;
1412 }
1413
1414 int get_pwr_i2c_clk_rate(void)
1415 {
1416         return pwr_i2c_clk;
1417 }
1418 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1419
1420 static bool pmic_wdt_disable;
1421 bool is_pmic_wdt_disabled_at_boot(void)
1422 {
1423         return pmic_wdt_disable;
1424 }
1425
1426 static int parse_arg_pmic_wdt_disable(char *options)
1427 {
1428         /* no kernel command line argument "watchdog" interpreted as
1429          * watchdog enable
1430          */
1431         pmic_wdt_disable = false;
1432         if (!(strcmp(options, "enable")))
1433                 pmic_wdt_disable = false;
1434         else if (!(strcmp(options, "disable")))
1435                 pmic_wdt_disable = true;
1436         /* kernel command line from fastboot does not support
1437          * other values
1438          */
1439
1440         return 0;
1441 }
1442 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1443
1444 void tegra_get_board_info(struct board_info *bi)
1445 {
1446 #ifdef CONFIG_OF
1447         struct device_node *board_info;
1448         u32 prop_val;
1449         int err;
1450
1451         board_info = of_find_node_by_path("/chosen/board_info");
1452         if (!IS_ERR_OR_NULL(board_info)) {
1453                 memset(bi, 0, sizeof(*bi));
1454
1455                 err = of_property_read_u32(board_info, "id", &prop_val);
1456                 if (err)
1457                         pr_err("failed to read /chosen/board_info/id\n");
1458                 else
1459                         bi->board_id = prop_val;
1460
1461                 err = of_property_read_u32(board_info, "sku", &prop_val);
1462                 if (err)
1463                         pr_err("failed to read /chosen/board_info/sku\n");
1464                 else
1465                         bi->sku = prop_val;
1466
1467                 err = of_property_read_u32(board_info, "fab", &prop_val);
1468                 if (err)
1469                         pr_err("failed to read /chosen/board_info/fab\n");
1470                 else
1471                         bi->fab = prop_val;
1472
1473                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1474                 if (err)
1475                         pr_err("failed to read /chosen/board_info/major_revision\n");
1476                 else
1477                         bi->major_revision = prop_val;
1478
1479                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1480                 if (err)
1481                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1482                 else
1483                         bi->minor_revision = prop_val;
1484 #ifndef CONFIG_ARM64
1485                 system_serial_high = (bi->board_id << 16) | bi->sku;
1486                 system_serial_low = (bi->fab << 24) |
1487                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1488 #endif
1489         } else {
1490 #endif
1491 #ifdef CONFIG_ARM64
1492                 /* FIXME:
1493                  * use dummy values for now as system_serial_high/low
1494                  * are gone in arm64.
1495                  */
1496                 bi->board_id = 0xDEAD;
1497                 bi->sku = 0xDEAD;
1498                 bi->fab = 0xDD;
1499                 bi->major_revision = 0xDD;
1500                 bi->minor_revision = 0xDD;
1501 #else
1502                 if (system_serial_high || system_serial_low) {
1503                         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1504                         bi->sku = (system_serial_high) & 0xFFFF;
1505                         bi->fab = (system_serial_low >> 24) & 0xFF;
1506                         bi->major_revision = (system_serial_low >> 16) & 0xFF;
1507                         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1508                 } else {
1509                         memcpy(bi, &main_board_info, sizeof(struct board_info));
1510                 }
1511 #endif
1512 #ifdef CONFIG_OF
1513         }
1514 #endif
1515 }
1516
1517 #ifdef CONFIG_OF
1518 void find_dc_node(struct device_node **dc1_node,
1519                 struct device_node **dc2_node) {
1520         *dc1_node =
1521                 of_find_node_by_path("/host1x/dc@54200000");
1522         *dc2_node =
1523                 of_find_node_by_path("/host1x/dc@54240000");
1524 }
1525 #else
1526 void find_dc_node(struct device_node *dc1_node,
1527                 struct device_node *dc2_node) {
1528         return;
1529 }
1530 #endif
1531
1532 static int __init tegra_main_board_info(char *info)
1533 {
1534         char *p = info;
1535         main_board_info.board_id = memparse(p, &p);
1536         main_board_info.sku = memparse(p+1, &p);
1537         main_board_info.fab = memparse(p+1, &p);
1538         main_board_info.major_revision = memparse(p+1, &p);
1539         main_board_info.minor_revision = memparse(p+1, &p);
1540         return 1;
1541 }
1542
1543 __setup("board_info=", tegra_main_board_info);
1544
1545 static int __init tegra_pmu_board_info(char *info)
1546 {
1547         char *p = info;
1548         pmu_board_info.board_id = memparse(p, &p);
1549         pmu_board_info.sku = memparse(p+1, &p);
1550         pmu_board_info.fab = memparse(p+1, &p);
1551         pmu_board_info.major_revision = memparse(p+1, &p);
1552         pmu_board_info.minor_revision = memparse(p+1, &p);
1553         return 0;
1554 }
1555
1556 void tegra_get_pmu_board_info(struct board_info *bi)
1557 {
1558         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1559 }
1560
1561 early_param("pmuboard", tegra_pmu_board_info);
1562
1563 static int __init tegra_display_board_info(char *info)
1564 {
1565         char *p = info;
1566         display_board_info.board_id = memparse(p, &p);
1567         display_board_info.sku = memparse(p+1, &p);
1568         display_board_info.fab = memparse(p+1, &p);
1569         display_board_info.major_revision = memparse(p+1, &p);
1570         display_board_info.minor_revision = memparse(p+1, &p);
1571         return 1;
1572 }
1573
1574 void tegra_get_display_board_info(struct board_info *bi)
1575 {
1576         memcpy(bi, &display_board_info, sizeof(struct board_info));
1577 }
1578
1579 __setup("displayboard=", tegra_display_board_info);
1580
1581 static int __init tegra_camera_board_info(char *info)
1582 {
1583         char *p = info;
1584         camera_board_info.board_id = memparse(p, &p);
1585         camera_board_info.sku = memparse(p+1, &p);
1586         camera_board_info.fab = memparse(p+1, &p);
1587         camera_board_info.major_revision = memparse(p+1, &p);
1588         camera_board_info.minor_revision = memparse(p+1, &p);
1589         return 1;
1590 }
1591
1592 void tegra_get_camera_board_info(struct board_info *bi)
1593 {
1594         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1595 }
1596
1597 __setup("cameraboard=", tegra_camera_board_info);
1598
1599 static int __init tegra_leftspeaker_board_info(char *info)
1600 {
1601         char *p = info;
1602         leftspeaker_board_info.board_id = memparse(p, &p);
1603         leftspeaker_board_info.sku = memparse(p+1, &p);
1604         leftspeaker_board_info.fab = memparse(p+1, &p);
1605         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1606         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1607         return 1;
1608 }
1609
1610 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1611 {
1612         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1613 }
1614
1615 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1616
1617 static int __init tegra_rightspeaker_board_info(char *info)
1618 {
1619         char *p = info;
1620         rightspeaker_board_info.board_id = memparse(p, &p);
1621         rightspeaker_board_info.sku = memparse(p+1, &p);
1622         rightspeaker_board_info.fab = memparse(p+1, &p);
1623         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1624         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1625         return 1;
1626 }
1627
1628 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1629 {
1630         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1631 }
1632
1633 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1634
1635 static int __init tegra_joystick_board_info(char *info)
1636 {
1637         char *p = info;
1638         joystick_board_info.board_id = memparse(p, &p);
1639         joystick_board_info.sku = memparse(p+1, &p);
1640         joystick_board_info.fab = memparse(p+1, &p);
1641         joystick_board_info.major_revision = memparse(p+1, &p);
1642         joystick_board_info.minor_revision = memparse(p+1, &p);
1643         return 1;
1644 }
1645
1646 void tegra_get_joystick_board_info(struct board_info *bi)
1647 {
1648         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1649 }
1650
1651 __setup("joystickboard=", tegra_joystick_board_info);
1652
1653 static int __init tegra_button_board_info(char *info)
1654 {
1655         char *p = info;
1656         button_board_info.board_id = memparse(p, &p);
1657         button_board_info.sku = memparse(p+1, &p);
1658         button_board_info.fab = memparse(p+1, &p);
1659         button_board_info.major_revision = memparse(p+1, &p);
1660         button_board_info.minor_revision = memparse(p+1, &p);
1661         return 1;
1662 }
1663
1664 void tegra_get_button_board_info(struct board_info *bi)
1665 {
1666         memcpy(bi, &button_board_info, sizeof(struct board_info));
1667 }
1668
1669 __setup("buttonboard=", tegra_button_board_info);
1670
1671 static int __init tegra_io_board_info(char *info)
1672 {
1673         char *p = info;
1674         io_board_info.board_id = memparse(p, &p);
1675         io_board_info.sku = memparse(p+1, &p);
1676         io_board_info.fab = memparse(p+1, &p);
1677         io_board_info.major_revision = memparse(p+1, &p);
1678         io_board_info.minor_revision = memparse(p+1, &p);
1679         return 1;
1680 }
1681
1682 void tegra_get_io_board_info(struct board_info *bi)
1683 {
1684         memcpy(bi, &io_board_info, sizeof(struct board_info));
1685 }
1686
1687 __setup("ioboard=", tegra_io_board_info);
1688
1689 static int __init tegra_modem_id(char *id)
1690 {
1691         char *p = id;
1692
1693         modem_id = memparse(p, &p);
1694         return 1;
1695 }
1696
1697 int tegra_get_modem_id(void)
1698 {
1699         return modem_id;
1700 }
1701
1702 __setup("modem_id=", tegra_modem_id);
1703
1704 static int __init tegra_usb_port_owner_info(char *id)
1705 {
1706         char *p = id;
1707
1708         usb_port_owner_info = memparse(p, &p);
1709         return 1;
1710 }
1711
1712 int tegra_get_usb_port_owner_info(void)
1713 {
1714         return usb_port_owner_info;
1715 }
1716
1717 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1718
1719 static int __init tegra_lane_owner_info(char *id)
1720 {
1721         char *p = id;
1722
1723         lane_owner_info = memparse(p, &p);
1724         return 1;
1725 }
1726
1727 int tegra_get_lane_owner_info(void)
1728 {
1729         return lane_owner_info;
1730 }
1731
1732 __setup("lane_owner_info=", tegra_lane_owner_info);
1733
1734 static int __init tegra_commchip_id(char *id)
1735 {
1736         char *p = id;
1737
1738         if (get_option(&p, &commchip_id) != 1)
1739                 return 0;
1740         return 1;
1741 }
1742
1743 int tegra_get_commchip_id(void)
1744 {
1745         return commchip_id;
1746 }
1747
1748 __setup("commchip_id=", tegra_commchip_id);
1749
1750 /*
1751  * Tegra has a protected aperture that prevents access by most non-CPU
1752  * memory masters to addresses above the aperture value.  Enabling it
1753  * secures the CPU's memory from the GPU, except through the GART.
1754  */
1755 void __init tegra_protected_aperture_init(unsigned long aperture)
1756 {
1757         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1758         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1759         writel(aperture, mc_base + MC_SECURITY_CFG2);
1760 }
1761
1762 /*
1763  * Due to conflicting restrictions on the placement of the framebuffer,
1764  * the bootloader is likely to leave the framebuffer pointed at a location
1765  * in memory that is outside the grhost aperture.  This function will move
1766  * the framebuffer contents from a physical address that is anywhere (lowmem,
1767  * highmem, or outside the memory map) to a physical address that is outside
1768  * the memory map.
1769  */
1770 void __tegra_move_framebuffer(struct platform_device *pdev,
1771         phys_addr_t to, phys_addr_t from,
1772         size_t size)
1773 {
1774         struct page *page;
1775         void __iomem *to_io;
1776         void *from_virt;
1777         unsigned long i;
1778
1779         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1780         BUG_ON(PAGE_ALIGN(from) != from);
1781         BUG_ON(PAGE_ALIGN(size) != size);
1782
1783         to_io = ioremap(to, size);
1784         if (!to_io) {
1785                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1786                 return;
1787         }
1788
1789         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1790                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1791                         page = phys_to_page(from + i);
1792                         from_virt = kmap(page);
1793                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1794                         kunmap(page);
1795                 }
1796         } else if (from) {
1797                 void __iomem *from_io = ioremap(from, size);
1798                 if (!from_io) {
1799                         pr_err("%s: Failed to map source framebuffer\n",
1800                                 __func__);
1801                         goto out;
1802                 }
1803
1804                 for (i = 0; i < size; i += 4)
1805                         writel(readl(from_io + i), to_io + i);
1806
1807                 iounmap(from_io);
1808         }
1809
1810 out:
1811         iounmap(to_io);
1812 }
1813
1814 void __tegra_clear_framebuffer(struct platform_device *pdev,
1815                                unsigned long to, unsigned long size)
1816 {
1817         void __iomem *to_io;
1818         unsigned long i;
1819
1820         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1821         BUG_ON(PAGE_ALIGN(size) != size);
1822
1823         to_io = ioremap(to, size);
1824         if (!to_io) {
1825                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1826                 return;
1827         }
1828
1829         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1830                 for (i = 0 ; i < size; i += PAGE_SIZE)
1831                         memset(to_io + i, 0, PAGE_SIZE);
1832         } else {
1833                 for (i = 0; i < size; i += 4)
1834                         writel(0, to_io + i);
1835         }
1836
1837         iounmap(to_io);
1838 }
1839
1840 #ifdef CONFIG_PSTORE_RAM
1841 static struct ramoops_platform_data ramoops_data;
1842
1843 static struct platform_device ramoops_dev  = {
1844         .name = "ramoops",
1845         .dev = {
1846                 .platform_data = &ramoops_data,
1847         },
1848 };
1849
1850 static void __init tegra_reserve_ramoops_memory(unsigned long reserve_size)
1851 {
1852         ramoops_data.mem_size = reserve_size;
1853         ramoops_data.mem_address = memblock_end_of_4G() - reserve_size;
1854         ramoops_data.console_size = reserve_size - FTRACE_MEM_SIZE;
1855         ramoops_data.ftrace_size = FTRACE_MEM_SIZE;
1856         ramoops_data.dump_oops = 1;
1857         memblock_reserve(ramoops_data.mem_address, ramoops_data.mem_size);
1858 }
1859
1860 static int __init tegra_register_ramoops_device(void)
1861 {
1862         int ret = platform_device_register(&ramoops_dev);
1863         if (ret) {
1864                 pr_info("Unable to register ramoops platform device\n");
1865                 return ret;
1866         }
1867         return ret;
1868 }
1869 core_initcall(tegra_register_ramoops_device);
1870 #endif
1871
1872 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1873         unsigned long fb2_size)
1874 {
1875         struct iommu_linear_map map[4];
1876
1877 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1878         if (carveout_size) {
1879                 /*
1880                  * Place the carveout below the 4 GB physical address limit
1881                  * because IOVAs are only 32 bit wide.
1882                  */
1883                 BUG_ON(memblock_end_of_4G() == 0);
1884                 tegra_carveout_start = memblock_end_of_4G() - carveout_size;
1885                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1886                         pr_err("Failed to remove carveout %08lx@%08llx "
1887                                 "from memory map\n",
1888                                 carveout_size, (u64)tegra_carveout_start);
1889                         tegra_carveout_start = 0;
1890                         tegra_carveout_size = 0;
1891                 } else
1892                         tegra_carveout_size = carveout_size;
1893         }
1894 #endif
1895
1896         if (fb2_size) {
1897                 /*
1898                  * Place fb2 below the 4 GB physical address limit because
1899                  * IOVAs are only 32 bit wide.
1900                  */
1901                 BUG_ON(memblock_end_of_4G() == 0);
1902                 tegra_fb2_start = memblock_end_of_4G() - fb2_size;
1903                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1904                         pr_err("Failed to remove second framebuffer "
1905                                 "%08lx@%08llx from memory map\n",
1906                                 fb2_size, (u64)tegra_fb2_start);
1907                         tegra_fb2_start = 0;
1908                         tegra_fb2_size = 0;
1909                 } else
1910                         tegra_fb2_size = fb2_size;
1911         }
1912
1913         if (fb_size) {
1914                 /*
1915                  * Place fb below the 4 GB physical address limit because
1916                  * IOVAs are only 32 bit wide.
1917                  */
1918                 BUG_ON(memblock_end_of_4G() == 0);
1919                 tegra_fb_start = memblock_end_of_4G() - fb_size;
1920                 if (memblock_remove(tegra_fb_start, fb_size)) {
1921                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1922                                 "from memory map\n",
1923                                 fb_size, (u64)tegra_fb_start);
1924                         tegra_fb_start = 0;
1925                         tegra_fb_size = 0;
1926                 } else
1927                         tegra_fb_size = fb_size;
1928         }
1929
1930         if (tegra_cpu_is_asim()) {
1931                 if (tegra_split_mem_active()) {
1932                         tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1933                         tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1934
1935                         if (tegra_vpr_size == 0) {
1936                                 tegra_carveout_start =
1937                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1938                                 tegra_carveout_size =
1939                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1940                         } else if (
1941                                     (tegra_vpr_start <
1942                                      TEGRA_ASIM_QT_FB_START +
1943                                      TEGRA_ASIM_QT_FB_SIZE) ||
1944                                      (tegra_vpr_start + tegra_vpr_size - 1 >
1945                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1946                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1947                                 /*
1948                                  * On ASIM/ASIM + QT with
1949                                  * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
1950                                  * the VPR region needs to be within the front
1951                                  * door memory region. Moreover, the VPR region
1952                                  * can't exist where the framebuffer resides.
1953                                  */
1954                                 BUG();
1955                         } else if (
1956                                         (tegra_vpr_start -
1957                                          (TEGRA_ASIM_QT_FB_START +
1958                                           TEGRA_ASIM_QT_FB_SIZE) <
1959                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1960                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1961                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1962                                          (tegra_vpr_start + tegra_vpr_size) <
1963                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1964                                 /*
1965                                  * The tegra ASIM/QT carveout has a min size:-
1966                                  * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
1967                                  * regions in front door mem are smaller than
1968                                  * the min carveout size. Therefore, we can't
1969                                  * fit the carveout in front door mem.
1970                                  */
1971                                 BUG();
1972                         } else if (
1973                                         (tegra_vpr_start -
1974                                          (TEGRA_ASIM_QT_FB_START +
1975                                           TEGRA_ASIM_QT_FB_SIZE)) >=
1976                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1977                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1978                                          (tegra_vpr_start + tegra_vpr_size))) {
1979                                 /*
1980                                  * Place the tegra ASIM/QT carveout between the
1981                                  * framebuffer and VPR.
1982                                  */
1983                                 tegra_carveout_start =
1984                                   TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1985                                 tegra_carveout_size = tegra_vpr_start -
1986                                         (TEGRA_ASIM_QT_FB_START +
1987                                          TEGRA_ASIM_QT_FB_SIZE);
1988                         } else {
1989                                 /*
1990                                  * Place the tegra ASIM/QT carveout after VPR.
1991                                  */
1992                                 tegra_carveout_start = tegra_vpr_start +
1993                                                          tegra_vpr_size;
1994                                 tegra_carveout_size =
1995                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1996                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1997                                         (tegra_vpr_start + tegra_vpr_size);
1998                         }
1999                 } else if (tegra_vpr_size != 0) {
2000                         /*
2001                          * VPR cannot work on ASIM/ASIM + QT if split mem is not
2002                          * enabled.
2003                          */
2004                         BUG();
2005                 }
2006         }
2007
2008         if (tegra_fb_size)
2009                 tegra_grhost_aperture = tegra_fb_start;
2010
2011         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
2012                 tegra_grhost_aperture = tegra_fb2_start;
2013
2014         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
2015                 tegra_grhost_aperture = tegra_carveout_start;
2016
2017         if (tegra_lp0_vec_size &&
2018            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
2019                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
2020                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
2021                                 (u64)tegra_lp0_vec_size,
2022                                 (u64)tegra_lp0_vec_start);
2023                         tegra_lp0_vec_start = 0;
2024                         tegra_lp0_vec_size = 0;
2025                 }
2026                 tegra_lp0_vec_relocate = false;
2027         } else
2028                 tegra_lp0_vec_relocate = true;
2029
2030 #ifdef CONFIG_TEGRA_NVDUMPER
2031         if (nvdumper_reserved) {
2032                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
2033                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
2034                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
2035                         nvdumper_reserved = 0;
2036                 }
2037         }
2038 #endif
2039
2040 #ifdef CONFIG_TEGRA_USE_NCT
2041         if (tegra_nck_size &&
2042            (tegra_nck_start < memblock_end_of_DRAM())) {
2043                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
2044                         pr_err("Failed to reserve nck %08lx@%08lx\n",
2045                                 tegra_nck_size, tegra_nck_start);
2046                         tegra_nck_start = 0;
2047                         tegra_nck_size = 0;
2048                 }
2049         }
2050 #endif
2051
2052         /*
2053          * We copy the bootloader's framebuffer to the framebuffer allocated
2054          * above, and then free this one.
2055          * */
2056         if (tegra_bootloader_fb_size) {
2057                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
2058                 if (memblock_reserve(tegra_bootloader_fb_start,
2059                                 tegra_bootloader_fb_size)) {
2060                         pr_err("Failed to reserve bootloader frame buffer "
2061                                 "%08llx@%08llx\n",
2062                                 (u64)tegra_bootloader_fb_size,
2063                                 (u64)tegra_bootloader_fb_start);
2064                         tegra_bootloader_fb_start = 0;
2065                         tegra_bootloader_fb_size = 0;
2066                 }
2067         }
2068
2069         if (tegra_bootloader_fb2_size) {
2070                 tegra_bootloader_fb2_size =
2071                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
2072                 if (memblock_reserve(tegra_bootloader_fb2_start,
2073                                 tegra_bootloader_fb2_size)) {
2074                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
2075                                 (u64)tegra_bootloader_fb2_size,
2076                                 (u64)tegra_bootloader_fb2_start);
2077                         tegra_bootloader_fb2_start = 0;
2078                         tegra_bootloader_fb2_size = 0;
2079                 }
2080         }
2081
2082         pr_info("Tegra reserved memory:\n"
2083                 "LP0:                    %08llx - %08llx\n"
2084                 "Bootloader framebuffer: %08llx - %08llx\n"
2085                 "Bootloader framebuffer2: %08llx - %08llx\n"
2086                 "Framebuffer:            %08llx - %08llx\n"
2087                 "2nd Framebuffer:        %08llx - %08llx\n"
2088 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2089                 "Carveout:               %08llx - %08llx\n"
2090                 "Vpr:                    %08llx - %08llx\n"
2091 #endif
2092                 "Tsec:                   %08llx - %08llx\n",
2093                 (u64)tegra_lp0_vec_start,
2094                 (u64)(tegra_lp0_vec_size ?
2095                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
2096                 (u64)tegra_bootloader_fb_start,
2097                 (u64)(tegra_bootloader_fb_size ?
2098                         tegra_bootloader_fb_start +
2099                         tegra_bootloader_fb_size - 1 : 0),
2100                 (u64)tegra_bootloader_fb2_start,
2101                 (u64)(tegra_bootloader_fb2_size ?
2102                         tegra_bootloader_fb2_start +
2103                         tegra_bootloader_fb2_size - 1 : 0),
2104                 (u64)tegra_fb_start,
2105                 (u64)(tegra_fb_size ?
2106                         tegra_fb_start + tegra_fb_size - 1 : 0),
2107                 (u64)tegra_fb2_start,
2108                 (u64)(tegra_fb2_size ?
2109                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
2110 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2111                 (u64)tegra_carveout_start,
2112                 (u64)(tegra_carveout_size ?
2113                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
2114                 (u64)tegra_vpr_start,
2115                 (u64)(tegra_vpr_size ?
2116                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
2117 #endif
2118                 (u64)tegra_tsec_start,
2119                 (u64)(tegra_tsec_size ?
2120                         tegra_tsec_start + tegra_tsec_size - 1 : 0));
2121
2122
2123 #ifdef CONFIG_TEGRA_NVDUMPER
2124         if (nvdumper_reserved) {
2125                 pr_info("Nvdumper:               %08lx - %08lx\n",
2126                         nvdumper_reserved,
2127                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2128         }
2129 #endif
2130
2131 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
2132         pr_info("Tzram:               %08lx - %08lx\n",
2133                 tegra_tzram_start,
2134                 tegra_tzram_size ?
2135                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
2136 #endif
2137
2138 #ifdef CONFIG_TEGRA_USE_NCT
2139         if (tegra_nck_size) {
2140                 pr_info("Nck:                    %08lx - %08lx\n",
2141                         tegra_nck_start,
2142                         tegra_nck_size ?
2143                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2144         }
2145 #endif
2146
2147 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2148         /* Keep these at the end */
2149         if (carveout_size) {
2150                 if (dma_declare_contiguous(&tegra_generic_cma_dev,
2151                         carveout_size, 0, memblock_end_of_4G()))
2152                         pr_err("dma_declare_contiguous failed for generic\n");
2153                 tegra_carveout_size = carveout_size;
2154         }
2155
2156         if (tegra_vpr_size)
2157                 if (dma_declare_contiguous(&tegra_vpr_cma_dev,
2158                         tegra_vpr_size, 0, memblock_end_of_4G()))
2159                         pr_err("dma_declare_contiguous failed VPR carveout\n");
2160 #endif
2161
2162         tegra_fb_linear_set(map);
2163 #ifdef CONFIG_PSTORE_RAM
2164         tegra_reserve_ramoops_memory(RAMOOPS_MEM_SIZE);
2165 #endif
2166 }
2167
2168 void tegra_get_fb_resource(struct resource *fb_res)
2169 {
2170         fb_res->start = (resource_size_t) tegra_fb_start;
2171         fb_res->end = fb_res->start +
2172                         (resource_size_t) tegra_fb_size - 1;
2173 }
2174
2175 void tegra_get_fb2_resource(struct resource *fb2_res)
2176 {
2177         fb2_res->start = (resource_size_t) tegra_fb2_start;
2178         fb2_res->end = fb2_res->start +
2179                         (resource_size_t) tegra_fb2_size - 1;
2180 }
2181
2182 int __init tegra_register_fuse(void)
2183 {
2184         return platform_device_register(&tegra_fuse_device);
2185 }
2186
2187 int __init tegra_release_bootloader_fb(void)
2188 {
2189         /* Since bootloader fb is reserved in common.c, it is freed here. */
2190         if (tegra_bootloader_fb_size) {
2191                 if (memblock_free(tegra_bootloader_fb_start,
2192                                                 tegra_bootloader_fb_size))
2193                         pr_err("Failed to free bootloader fb.\n");
2194                 else
2195                         free_bootmem_late(tegra_bootloader_fb_start,
2196                                                 tegra_bootloader_fb_size);
2197         }
2198         if (tegra_bootloader_fb2_size) {
2199                 if (memblock_free(tegra_bootloader_fb2_start,
2200                                                 tegra_bootloader_fb2_size))
2201                         pr_err("Failed to free bootloader fb2.\n");
2202                 else
2203                         free_bootmem_late(tegra_bootloader_fb2_start,
2204                                                 tegra_bootloader_fb2_size);
2205         }
2206         return 0;
2207 }
2208 late_initcall(tegra_release_bootloader_fb);
2209
2210 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2211         [TEGRA_REVISION_UNKNOWN] = "unknown",
2212         [TEGRA_REVISION_A01]     = "A01",
2213         [TEGRA_REVISION_A02]     = "A02",
2214         [TEGRA_REVISION_A03]     = "A03",
2215         [TEGRA_REVISION_A03p]    = "A03 prime",
2216         [TEGRA_REVISION_A04]     = "A04",
2217         [TEGRA_REVISION_A04p]    = "A04 prime",
2218 };
2219
2220 static const char * __init tegra_get_revision(void)
2221 {
2222         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2223 }
2224
2225 static const char * __init tegra_get_family(void)
2226 {
2227         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2228         u32 cid = readl(chip_id);
2229         cid = (cid >> 8) & 0xFF;
2230
2231         switch (cid) {
2232         case TEGRA_CHIPID_TEGRA2:
2233                 cid = 2;
2234                 break;
2235         case TEGRA_CHIPID_TEGRA3:
2236                 cid = 3;
2237                 break;
2238         case TEGRA_CHIPID_TEGRA11:
2239                 cid = 11;
2240                 break;
2241         case TEGRA_CHIPID_TEGRA12:
2242                 cid = 12;
2243                 break;
2244         case TEGRA_CHIPID_TEGRA14:
2245                 cid = 14;
2246                 break;
2247
2248         case TEGRA_CHIPID_UNKNOWN:
2249         default:
2250                 cid = 0;
2251         }
2252         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2253 }
2254
2255 static const char * __init tegra_get_soc_id(void)
2256 {
2257         int package_id = tegra_package_id();
2258
2259         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2260                 tegra_revision_name[tegra_revision],
2261                 tegra_get_sku_id(), package_id);
2262 }
2263
2264 static void __init tegra_soc_info_populate(struct soc_device_attribute
2265         *soc_dev_attr, const char *machine)
2266 {
2267         soc_dev_attr->soc_id = tegra_get_soc_id();
2268         soc_dev_attr->machine  = machine;
2269         soc_dev_attr->family   = tegra_get_family();
2270         soc_dev_attr->revision = tegra_get_revision();
2271 }
2272
2273 int __init tegra_soc_device_init(const char *machine)
2274 {
2275         struct soc_device *soc_dev;
2276         struct soc_device_attribute *soc_dev_attr;
2277
2278         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2279         if (!soc_dev_attr)
2280                 return -ENOMEM;
2281
2282         tegra_soc_info_populate(soc_dev_attr, machine);
2283
2284         soc_dev = soc_device_register(soc_dev_attr);
2285         if (IS_ERR_OR_NULL(soc_dev)) {
2286                 kfree(soc_dev_attr);
2287                 return -1;
2288         }
2289
2290         return 0;
2291 }
2292
2293 void __init tegra_init_late(void)
2294 {
2295 #ifndef CONFIG_COMMON_CLK
2296         tegra_clk_debugfs_init();
2297 #endif
2298         tegra_powergate_debugfs_init();
2299 }
2300
2301 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2302 #define ASIM_SHUTDOWN_REG       0x538f0ffc
2303
2304 static void asim_power_off(void)
2305 {
2306         pr_err("ASIM Powering off the device\n");
2307         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
2308         while (1)
2309                 ;
2310 }
2311
2312 static int __init asim_power_off_init(void)
2313 {
2314         if (tegra_cpu_is_asim())
2315                 pm_power_off = asim_power_off;
2316         return 0;
2317 }
2318
2319 arch_initcall(asim_power_off_init);
2320
2321 #if defined(CONFIG_SMC91X)
2322 static struct resource tegra_asim_smc91x_resources[] = {
2323         [0] = {
2324                 .start          = TEGRA_SIM_ETH_BASE,
2325                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
2326                 .flags          = IORESOURCE_MEM,
2327         },
2328         [1] = {
2329                 .start          = IRQ_ETH,
2330                 .end            = IRQ_ETH,
2331                 .flags          = IORESOURCE_IRQ,
2332         },
2333 };
2334
2335 static struct platform_device tegra_asim_smc91x_device = {
2336         .name           = "smc91x",
2337         .id             = 0,
2338         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
2339         .resource       = tegra_asim_smc91x_resources,
2340 };
2341
2342 static int __init asim_enet_smc91x_init(void)
2343 {
2344         if (tegra_cpu_is_asim() && !tegra_cpu_is_dsim())
2345                 platform_device_register(&tegra_asim_smc91x_device);
2346         return 0;
2347 }
2348
2349 rootfs_initcall(asim_enet_smc91x_init);
2350 #endif
2351 #endif
2352
2353 #if defined(CONFIG_SMSC911X)
2354 static struct resource tegra_smsc911x_resources[] = {
2355         [0] = {
2356                 .start          = 0x4E000000,
2357                 .end            = 0x4E000000 + SZ_64K - 1,
2358                 .flags          = IORESOURCE_MEM,
2359         },
2360         [1] = {
2361                 .start          = IRQ_ETH,
2362                 .end            = IRQ_ETH,
2363                 .flags          = IORESOURCE_IRQ,
2364         },
2365 };
2366
2367 static struct smsc911x_platform_config tegra_smsc911x_config = {
2368         .flags          = SMSC911X_USE_32BIT,
2369         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
2370         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
2371         .phy_interface  = PHY_INTERFACE_MODE_MII,
2372 };
2373
2374 static struct platform_device tegra_smsc911x_device = {
2375         .name              = "smsc911x",
2376         .id                = 0,
2377         .resource          = tegra_smsc911x_resources,
2378         .num_resources     = ARRAY_SIZE(tegra_smsc911x_resources),
2379         .dev.platform_data = &tegra_smsc911x_config,
2380 };
2381
2382 static int __init enet_smsc911x_init(void)
2383 {
2384         if (!tegra_cpu_is_dsim())
2385                 platform_device_register(&tegra_smsc911x_device);
2386         return 0;
2387 }
2388
2389 rootfs_initcall(enet_smsc911x_init);
2390 #endif
2391
2392 int tegra_split_mem_active(void)
2393 {
2394         return tegra_split_mem_set;
2395 }
2396
2397 static int __init set_tegra_split_mem(char *options)
2398 {
2399         tegra_split_mem_set = 1;
2400         return 0;
2401 }
2402 early_param("tegra_split_mem", set_tegra_split_mem);
2403
2404 #define FUSE_SKU_INFO       0x110
2405 #define STRAP_OPT 0x008
2406 #define GMI_AD0 BIT(4)
2407 #define GMI_AD1 BIT(5)
2408 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
2409 #define RAM_CODE_SHIFT 4
2410
2411 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2412 static enum tegra_platform tegra_platform;
2413 static bool cpu_is_asim;
2414 static bool cpu_is_dsim;
2415 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
2416         [TEGRA_PLATFORM_SILICON] = "silicon",
2417         [TEGRA_PLATFORM_QT]      = "quickturn",
2418         [TEGRA_PLATFORM_LINSIM]  = "linsim",
2419         [TEGRA_PLATFORM_FPGA]    = "fpga",
2420 };
2421 #endif
2422
2423 static u32 tegra_chip_sku_id;
2424 static u32 tegra_chip_id;
2425 static u32 tegra_chip_bct_strapping;
2426 enum tegra_revision tegra_revision;
2427
2428 u32 tegra_read_pmc_reg(int offset)
2429 {
2430         return readl(IO_ADDRESS(TEGRA_PMC_BASE) + offset);
2431 }
2432
2433 u32 tegra_read_clk_ctrl_reg(int offset)
2434 {
2435         return readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + offset);
2436 }
2437
2438 u32 tegra_read_apb_misc_reg(int offset)
2439 {
2440         return readl(IO_ADDRESS(TEGRA_APB_MISC_BASE) + offset);
2441 }
2442
2443 u32 tegra_fuse_readl(unsigned long offset)
2444 {
2445         return readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2446 }
2447
2448 void tegra_fuse_writel(u32 val, unsigned long offset)
2449 {
2450         writel(val, IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2451 }
2452
2453 u32 tegra_read_chipid(void)
2454 {
2455         return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE)
2456                         + 0x804);
2457 }
2458
2459 static void tegra_set_sku_id(void)
2460 {
2461         u32 reg;
2462
2463         reg = tegra_fuse_readl(FUSE_SKU_INFO);
2464         tegra_chip_sku_id = reg & 0xFF;
2465 }
2466
2467 static void tegra_set_chip_id(void)
2468 {
2469         u32 id;
2470
2471         id = tegra_read_chipid();
2472         tegra_chip_id = (id >> 8) & 0xff;
2473 }
2474
2475 static void tegra_set_bct_strapping(void)
2476 {
2477         u32 reg;
2478
2479         reg = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + STRAP_OPT));
2480         tegra_chip_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
2481 }
2482
2483 u32 tegra_get_sku_id(void)
2484 {
2485         return tegra_chip_sku_id;
2486 }
2487
2488 u32 tegra_get_chip_id(void)
2489 {
2490         return tegra_chip_id;
2491 }
2492
2493 u32 tegra_get_bct_strapping(void)
2494 {
2495         return tegra_chip_bct_strapping;
2496 }
2497
2498 static void tegra_fuse_cfg_reg_visible(void)
2499 {
2500         /* Make all fuse registers visible */
2501         u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2502         reg |= BIT(28);
2503         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2504 }
2505
2506 void tegra_init_fuse(void)
2507 {
2508         u32 sku_id;
2509
2510         tegra_fuse_cfg_reg_visible();
2511         tegra_set_sku_id();
2512         sku_id = tegra_get_sku_id();
2513         tegra_set_bct_strapping();
2514         tegra_set_chip_id();
2515         tegra_revision = tegra_chip_get_revision();
2516         tegra_init_speedo_data();
2517         pr_info("Tegra Revision: %s SKU: 0x%x CPU Process: %d Core Process: %d\n",
2518                 tegra_revision_name[tegra_revision],
2519                 sku_id, tegra_cpu_process_id(),
2520                 tegra_core_process_id());
2521 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2522         if (!tegra_platform_is_silicon()) {
2523                 pr_info("Tegra Platform: %s%s%s\n",
2524                         tegra_cpu_is_asim() ? "ASIM+" : "",
2525                         tegra_cpu_is_dsim() ? "DSIM+" : "",
2526                         tegra_platform_name[tegra_platform]);
2527         }
2528 #endif
2529 }
2530
2531 void __init display_tegra_dt_info(void)
2532 {
2533         unsigned long dt_root;
2534         const char *dts_fname;
2535
2536
2537         dt_root = of_get_flat_dt_root();
2538
2539         dts_fname = of_get_flat_dt_prop(dt_root, "nvidia,dtsfilename", NULL);
2540         if (dts_fname)
2541                 pr_info("DTS File Name: %s\n", dts_fname);
2542         else
2543                 pr_info("DTS File Name: <unknown>\n");
2544 }
2545
2546 static int __init tegra_get_last_reset_reason(void)
2547 {
2548 #define PMC_RST_STATUS 0x1b4
2549 #define RESET_STR(REASON) "last reset is due to "#REASON"\n"
2550         char *reset_reason[] = {
2551                 RESET_STR(power on reset),
2552                 RESET_STR(watchdog timeout),
2553                 RESET_STR(sensor),
2554                 RESET_STR(software reset),
2555                 RESET_STR(deep sleep reset),
2556         };
2557
2558         u32 val = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_RST_STATUS) & 0x7;
2559         if (val >= ARRAY_SIZE(reset_reason))
2560                 pr_info("last reset value is invalid 0x%x\n", val);
2561         else
2562                 pr_info("%s\n", reset_reason[val]);
2563         return 0;
2564 }
2565 late_initcall(tegra_get_last_reset_reason);