unknown changes from android-tegra-nv-3.4
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2012 NVIDIA Corporation
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/irqchip.h>
28 #include <linux/clk/tegra.h>
29 #include <linux/highmem.h>
30 #include <linux/memblock.h>
31 #include <linux/bitops.h>
32 #include <linux/sched.h>
33
34 #include <asm/hardware/cache-l2x0.h>
35 #include <asm/system.h>
36
37 #include <mach/hardware.h>
38 #include <mach/powergate.h>
39 #include <mach/tegra_smmu.h>
40 #include <mach/gpio-tegra.h>
41
42 #include "apbio.h"
43 #include "board.h"
44 #include "common.h"
45 #include "dvfs.h"
46 #include "fuse.h"
47 #include "iomap.h"
48 #include "pm.h"
49 #include "sleep.h"
50 #include "reset.h"
51 #include "devices.h"
52 #include "pmc.h"
53
54 #define MC_SECURITY_CFG2        0x7c
55
56 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
57 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
58 #define   PRIORITY_SELECT_USB   BIT(6)
59 #define   PRIORITY_SELECT_USB2  BIT(18)
60 #define   PRIORITY_SELECT_USB3  BIT(17)
61
62 #define AHB_GIZMO_AHB_MEM               0xc
63 #define   ENB_FAST_REARBITRATE  BIT(2)
64 #define   DONT_SPLIT_AHB_WR     BIT(7)
65
66 #define   RECOVERY_MODE BIT(31)
67 #define   BOOTLOADER_MODE       BIT(30)
68 #define   FORCED_RECOVERY_MODE  BIT(1)
69
70 #define AHB_GIZMO_USB           0x1c
71 #define AHB_GIZMO_USB2          0x78
72 #define AHB_GIZMO_USB3          0x7c
73 #define   IMMEDIATE     BIT(18)
74
75 #define AHB_MEM_PREFETCH_CFG3   0xe0
76 #define AHB_MEM_PREFETCH_CFG4   0xe4
77 #define AHB_MEM_PREFETCH_CFG1   0xec
78 #define AHB_MEM_PREFETCH_CFG2   0xf0
79 #define   PREFETCH_ENB  BIT(31)
80 #define   MST_ID(x)     (((x) & 0x1f) << 26)
81 #define   AHBDMA_MST_ID MST_ID(5)
82 #define   USB_MST_ID    MST_ID(6)
83 #define   USB2_MST_ID   MST_ID(18)
84 #define   USB3_MST_ID   MST_ID(17)
85 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
86 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
87
88 unsigned long tegra_bootloader_fb_start;
89 unsigned long tegra_bootloader_fb_size;
90 unsigned long tegra_fb_start;
91 unsigned long tegra_fb_size;
92 unsigned long tegra_fb2_start;
93 unsigned long tegra_fb2_size;
94 unsigned long tegra_carveout_start;
95 unsigned long tegra_carveout_size;
96 unsigned long tegra_vpr_start;
97 unsigned long tegra_vpr_size;
98 unsigned long tegra_lp0_vec_start;
99 unsigned long tegra_lp0_vec_size;
100 bool tegra_lp0_vec_relocate;
101 unsigned long tegra_grhost_aperture = ~0ul;
102 static   bool is_tegra_debug_uart_hsport;
103 static struct board_info pmu_board_info;
104 static struct board_info display_board_info;
105 static struct board_info camera_board_info;
106
107 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
108 static int board_panel_type;
109 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
110
111 /*
112  * Storage for debug-macro.S's state.
113  *
114  * This must be in .data not .bss so that it gets initialized each time the
115  * kernel is loaded. The data is declared here rather than debug-macro.S so
116  * that multiple inclusions of debug-macro.S point at the same data.
117  */
118 u32 tegra_uart_config[4] = {
119         /* Debug UART initialization required */
120         1,
121         /* Debug UART physical address */
122         0,
123         /* Debug UART virtual address */
124         0,
125         /* Scratch space for debug macro */
126         0,
127 };
128
129 #ifdef CONFIG_OF
130 void __init tegra_dt_init_irq(void)
131 {
132         tegra_clocks_init();
133         tegra_pmc_init();
134         tegra_init_irq();
135         irqchip_init();
136 }
137 #endif
138
139 #define NEVER_RESET 0
140
141 void tegra_assert_system_reset(char mode, const char *cmd)
142 {
143 #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
144         printk("tegra_assert_system_reset() ignored.....");
145         do { } while (1);
146 #else
147         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
148         u32 reg;
149
150         reg = readl_relaxed(reset + PMC_SCRATCH0);
151         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
152         if (cmd) {
153                 if (!strcmp(cmd, "recovery"))
154                         reg |= RECOVERY_MODE;
155                 else if (!strcmp(cmd, "bootloader"))
156                         reg |= BOOTLOADER_MODE;
157                 else if (!strcmp(cmd, "forced-recovery"))
158                         reg |= FORCED_RECOVERY_MODE;
159                 else
160                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
161         }
162         else {
163                 /* Clearing SCRATCH0 31:30:1 on default reboot */
164                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
165         }
166         writel_relaxed(reg, reset + PMC_SCRATCH0);
167         reg = readl_relaxed(reset);
168         reg |= 0x10;
169         writel_relaxed(reg, reset);
170 #endif
171 }
172 static int modem_id;
173 static int sku_override;
174 static int debug_uart_port_id;
175 static enum audio_codec_type audio_codec_name;
176 static enum image_type board_image_type = system_image;
177 static int max_cpu_current;
178
179 #ifdef CONFIG_CACHE_L2X0
180 #ifdef CONFIG_TRUSTED_FOUNDATIONS
181 static void tegra_cache_smc(bool enable, u32 arg)
182 {
183         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
184         bool need_affinity_switch;
185         bool can_switch_affinity;
186         bool l2x0_enabled;
187         cpumask_t local_cpu_mask;
188         cpumask_t saved_cpu_mask;
189         unsigned long flags;
190         long ret;
191
192         /*
193          * ISSUE : Some registers of PL310 controler must be written
194          *              from Secure context (and from CPU0)!
195          *
196          * When called form Normal we obtain an abort or do nothing.
197          * Instructions that must be called in Secure:
198          *      - Write to Control register (L2X0_CTRL==0x100)
199          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
200          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
201          *              mandatory at boot time.
202          *      - Tag and Data RAM Latency Control Registers
203          *              (0x108 & 0x10C) must be written in Secure.
204          */
205         need_affinity_switch = (smp_processor_id() != 0);
206         can_switch_affinity = !irqs_disabled();
207
208         WARN_ON(need_affinity_switch && !can_switch_affinity);
209         if (need_affinity_switch && can_switch_affinity) {
210                 cpu_set(0, local_cpu_mask);
211                 sched_getaffinity(0, &saved_cpu_mask);
212                 ret = sched_setaffinity(0, &local_cpu_mask);
213                 WARN_ON(ret != 0);
214         }
215
216         local_irq_save(flags);
217         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
218         if (enable && !l2x0_enabled)
219                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
220         else if (!enable && l2x0_enabled)
221                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
222         local_irq_restore(flags);
223
224         if (need_affinity_switch && can_switch_affinity) {
225                 ret = sched_setaffinity(0, &saved_cpu_mask);
226                 WARN_ON(ret != 0);
227         }
228 }
229
230 static void tegra_l2x0_disable(void)
231 {
232         unsigned long flags;
233         static u32 l2x0_way_mask;
234
235         if (!l2x0_way_mask) {
236                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
237                 u32 aux_ctrl;
238                 u32 ways;
239
240                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
241                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
242                 l2x0_way_mask = (1 << ways) - 1;
243         }
244
245         local_irq_save(flags);
246         tegra_cache_smc(false, l2x0_way_mask);
247         local_irq_restore(flags);
248 }
249 #endif  /* CONFIG_TRUSTED_FOUNDATIONS  */
250
251 void tegra_init_cache(bool init)
252 {
253         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
254         u32 aux_ctrl;
255 #ifndef CONFIG_TRUSTED_FOUNDATIONS
256         u32 cache_type;
257         u32 tag_latency, data_latency;
258         u32 speedo;
259         u32 tmp;
260 #endif
261
262 #ifdef CONFIG_TRUSTED_FOUNDATIONS
263         /* issue the SMC to enable the L2 */
264         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
265         tegra_cache_smc(true, aux_ctrl);
266
267         /* after init, reread aux_ctrl and register handlers */
268         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
269         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
270
271         /* override outer_disable() with our disable */
272         outer_cache.disable = tegra_l2x0_disable;
273 #else
274 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
275         tag_latency = 0x331;
276         data_latency = 0x441;
277 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
278 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
279         if (is_lp_cluster()) {
280                 tag_latency = 0x221;
281                 data_latency = 0x221;
282         } else {
283                 u32 speedo;
284
285                 /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
286                 speedo = tegra_cpu_speedo_id();
287                 if (speedo == 4 || speedo == 5 || speedo == 6 ||
288                     speedo == 12 || speedo == 13) {
289                         tag_latency = 0x442;
290                         data_latency = 0x552;
291                 } else {
292                         tag_latency = 0x441;
293                         data_latency = 0x551;
294                 }
295         }
296 #else
297         tag_latency = 0x770;
298         data_latency = 0x770;
299 #endif
300 #endif
301         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
302         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
303
304 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
305 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
306         writel(7, p + L2X0_PREFETCH_CTRL);
307         writel(2, p + L2X0_POWER_CTRL);
308 #endif
309 #endif
310
311         writel(0x3, p + L2X0_POWER_CTRL);
312         cache_type = readl(p + L2X0_CACHE_TYPE);
313         aux_ctrl = (cache_type & 0x700) << (17-8);
314         aux_ctrl |= 0x7C400001;
315         if (init) {
316                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
317         } else {
318                 u32 tmp;
319
320                 tmp = aux_ctrl;
321                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
322                 aux_ctrl &= 0x8200c3fe;
323                 aux_ctrl |= tmp;
324                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
325         }
326         l2x0_enable();
327 #endif
328 }
329 #endif
330
331 static void __init tegra_init_power(void)
332 {
333 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
334         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
335 #endif
336 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
337         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
338 #endif
339 }
340
341 static inline unsigned long gizmo_readl(unsigned long offset)
342 {
343         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
344 }
345
346 static inline void gizmo_writel(unsigned long value, unsigned long offset)
347 {
348         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
349 }
350
351 static void __init tegra_init_ahb_gizmo_settings(void)
352 {
353         unsigned long val;
354
355         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
356         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
357         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
358
359         val = gizmo_readl(AHB_GIZMO_USB);
360         val |= IMMEDIATE;
361         gizmo_writel(val, AHB_GIZMO_USB);
362
363         val = gizmo_readl(AHB_GIZMO_USB2);
364         val |= IMMEDIATE;
365         gizmo_writel(val, AHB_GIZMO_USB2);
366
367         val = gizmo_readl(AHB_GIZMO_USB3);
368         val |= IMMEDIATE;
369         gizmo_writel(val, AHB_GIZMO_USB3);
370
371         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
372         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
373                                 | AHB_PRIORITY_WEIGHT(7);
374         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
375
376         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
377         val &= ~MST_ID(~0);
378         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
379         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
380
381         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
382         val &= ~MST_ID(~0);
383         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
384         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
385
386         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
387         val &= ~MST_ID(~0);
388         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
389         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
390
391         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
392         val &= ~MST_ID(~0);
393         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
394         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
395 }
396
397 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
398 void __init tegra20_init_early(void)
399 {
400 #ifndef CONFIG_SMP
401         /* For SMP system, initializing the reset handler here is too
402            late. For non-SMP systems, the function that calls the reset
403            handler initializer is not called, so do it here for non-SMP. */
404         tegra_cpu_reset_handler_init();
405 #endif
406         tegra_apb_io_init();
407         tegra_init_fuse();
408         tegra_init_cache(true);
409         tegra_powergate_init();
410         tegra20_hotplug_init();
411         tegra_init_power();
412         tegra_init_ahb_gizmo_settings();
413         tegra_init_debug_uart_rate();
414         tegra_gpio_resume_init();
415 }
416 #endif
417 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
418 void __init tegra30_init_early(void)
419 {
420 #ifndef CONFIG_SMP
421         /* For SMP system, initializing the reset handler here is too
422            late. For non-SMP systems, the function that calls the reset
423            handler initializer is not called, so do it here for non-SMP. */
424         tegra_cpu_reset_handler_init();
425 #endif
426         tegra_apb_io_init();
427         tegra_init_fuse();
428         tegra_init_cache(true);
429         tegra_pmc_init();
430         tegra_powergate_init();
431         tegra30_hotplug_init();
432         tegra_init_power();
433         tegra_init_ahb_gizmo_settings();
434         tegra_init_debug_uart_rate();
435         tegra_gpio_resume_init();
436 }
437 #endif
438
439 static int __init tegra_lp0_vec_arg(char *options)
440 {
441         char *p = options;
442
443         tegra_lp0_vec_size = memparse(p, &p);
444         if (*p == '@')
445                 tegra_lp0_vec_start = memparse(p+1, &p);
446         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
447                 tegra_lp0_vec_size = 0;
448                 tegra_lp0_vec_start = 0;
449         }
450
451         return 0;
452 }
453 early_param("lp0_vec", tegra_lp0_vec_arg);
454
455 static int __init tegra_bootloader_fb_arg(char *options)
456 {
457         char *p = options;
458
459         tegra_bootloader_fb_size = memparse(p, &p);
460         if (*p == '@')
461                 tegra_bootloader_fb_start = memparse(p+1, &p);
462
463         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
464                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
465
466         return 0;
467 }
468 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
469
470 static int __init tegra_sku_override(char *id)
471 {
472         char *p = id;
473
474         sku_override = memparse(p, &p);
475
476         return 0;
477 }
478 early_param("sku_override", tegra_sku_override);
479
480 int tegra_get_sku_override(void)
481 {
482         return sku_override;
483 }
484
485 static int __init tegra_vpr_arg(char *options)
486 {
487         char *p = options;
488
489         tegra_vpr_size = memparse(p, &p);
490         if (*p == '@')
491                 tegra_vpr_start = memparse(p+1, &p);
492         pr_info("Found vpr, start=0x%lx size=%lx",
493                 tegra_vpr_start, tegra_vpr_size);
494         return 0;
495 }
496 early_param("vpr", tegra_vpr_arg);
497
498 enum panel_type get_panel_type(void)
499 {
500         return board_panel_type;
501 }
502 static int __init tegra_board_panel_type(char *options)
503 {
504         if (!strcmp(options, "lvds"))
505                 board_panel_type = panel_type_lvds;
506         else if (!strcmp(options, "dsi"))
507                 board_panel_type = panel_type_dsi;
508         else
509                 return 0;
510         return 1;
511 }
512 __setup("panel=", tegra_board_panel_type);
513
514 enum power_supply_type get_power_supply_type(void)
515 {
516         return pow_supply_type;
517 }
518 static int __init tegra_board_power_supply_type(char *options)
519 {
520         if (!strcmp(options, "Adapter"))
521                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
522         if (!strcmp(options, "Mains"))
523                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
524         else if (!strcmp(options, "Battery"))
525                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
526         else
527                 return 0;
528         return 1;
529 }
530 __setup("power_supply=", tegra_board_power_supply_type);
531
532 int get_core_edp(void)
533 {
534         return pmu_core_edp;
535 }
536 static int __init tegra_pmu_core_edp(char *options)
537 {
538         char *p = options;
539         int core_edp = memparse(p, &p);
540         if (core_edp != 0)
541                 pmu_core_edp = core_edp;
542         return 0;
543 }
544 early_param("core_edp_mv", tegra_pmu_core_edp);
545
546 int get_maximum_cpu_current_supported(void)
547 {
548         return max_cpu_current;
549 }
550 static int __init tegra_max_cpu_current(char *options)
551 {
552         char *p = options;
553         max_cpu_current = memparse(p, &p);
554         return 1;
555 }
556 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
557
558 static int __init tegra_debug_uartport(char *info)
559 {
560         char *p = info;
561         unsigned long long port_id;
562         if (!strncmp(p, "hsport", 6))
563                 is_tegra_debug_uart_hsport = true;
564         else if (!strncmp(p, "lsport", 6))
565                 is_tegra_debug_uart_hsport = false;
566
567         if (p[6] == ',') {
568                 if (p[7] == '-') {
569                         debug_uart_port_id = -1;
570                 } else {
571                         port_id = memparse(p + 7, &p);
572                         debug_uart_port_id = (int) port_id;
573                 }
574         } else {
575                 debug_uart_port_id = -1;
576         }
577
578         return 1;
579 }
580
581 bool is_tegra_debug_uartport_hs(void)
582 {
583         return is_tegra_debug_uart_hsport;
584 }
585
586 int get_tegra_uart_debug_port_id(void)
587 {
588         return debug_uart_port_id;
589 }
590 __setup("debug_uartport=", tegra_debug_uartport);
591
592 static int __init tegra_image_type(char *options)
593 {
594         if (!strcmp(options, "RCK"))
595                 board_image_type = rck_image;
596
597         return 0;
598 }
599
600 enum image_type get_tegra_image_type(void)
601 {
602         return board_image_type;
603 }
604
605 __setup("image=", tegra_image_type);
606
607 static int __init tegra_audio_codec_type(char *info)
608 {
609         char *p = info;
610         if (!strncmp(p, "wm8903", 6))
611                 audio_codec_name = audio_codec_wm8903;
612         else
613                 audio_codec_name = audio_codec_none;
614
615         return 1;
616 }
617
618 enum audio_codec_type get_audio_codec_type(void)
619 {
620         return audio_codec_name;
621 }
622 __setup("audio_codec=", tegra_audio_codec_type);
623
624
625 void tegra_get_board_info(struct board_info *bi)
626 {
627         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
628         bi->sku = (system_serial_high) & 0xFFFF;
629         bi->fab = (system_serial_low >> 24) & 0xFF;
630         bi->major_revision = (system_serial_low >> 16) & 0xFF;
631         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
632 }
633
634 static int __init tegra_pmu_board_info(char *info)
635 {
636         char *p = info;
637         pmu_board_info.board_id = memparse(p, &p);
638         pmu_board_info.sku = memparse(p+1, &p);
639         pmu_board_info.fab = memparse(p+1, &p);
640         pmu_board_info.major_revision = memparse(p+1, &p);
641         pmu_board_info.minor_revision = memparse(p+1, &p);
642         return 1;
643 }
644
645 void tegra_get_pmu_board_info(struct board_info *bi)
646 {
647         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
648 }
649
650 __setup("pmuboard=", tegra_pmu_board_info);
651
652 static int __init tegra_display_board_info(char *info)
653 {
654         char *p = info;
655         display_board_info.board_id = memparse(p, &p);
656         display_board_info.sku = memparse(p+1, &p);
657         display_board_info.fab = memparse(p+1, &p);
658         display_board_info.major_revision = memparse(p+1, &p);
659         display_board_info.minor_revision = memparse(p+1, &p);
660         return 1;
661 }
662
663 void tegra_get_display_board_info(struct board_info *bi)
664 {
665         memcpy(bi, &display_board_info, sizeof(struct board_info));
666 }
667
668 __setup("displayboard=", tegra_display_board_info);
669
670 static int __init tegra_camera_board_info(char *info)
671 {
672         char *p = info;
673         camera_board_info.board_id = memparse(p, &p);
674         camera_board_info.sku = memparse(p+1, &p);
675         camera_board_info.fab = memparse(p+1, &p);
676         camera_board_info.major_revision = memparse(p+1, &p);
677         camera_board_info.minor_revision = memparse(p+1, &p);
678         return 1;
679 }
680
681 void tegra_get_camera_board_info(struct board_info *bi)
682 {
683         memcpy(bi, &camera_board_info, sizeof(struct board_info));
684 }
685
686 __setup("cameraboard=", tegra_camera_board_info);
687
688 static int __init tegra_modem_id(char *id)
689 {
690         char *p = id;
691
692         modem_id = memparse(p, &p);
693         return 1;
694 }
695
696 int tegra_get_modem_id(void)
697 {
698         return modem_id;
699 }
700
701 __setup("modem_id=", tegra_modem_id);
702
703 /*
704  * Tegra has a protected aperture that prevents access by most non-CPU
705  * memory masters to addresses above the aperture value.  Enabling it
706  * secures the CPU's memory from the GPU, except through the GART.
707  */
708 void __init tegra_protected_aperture_init(unsigned long aperture)
709 {
710 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
711         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
712         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
713         writel(aperture, mc_base + MC_SECURITY_CFG2);
714 #else
715         pr_err("Tegra protected aperture disabled because nvmap is using "
716                 "system memory\n");
717 #endif
718 }
719
720 /*
721  * Due to conflicting restrictions on the placement of the framebuffer,
722  * the bootloader is likely to leave the framebuffer pointed at a location
723  * in memory that is outside the grhost aperture.  This function will move
724  * the framebuffer contents from a physical address that is anywher (lowmem,
725  * highmem, or outside the memory map) to a physical address that is outside
726  * the memory map.
727  */
728 void tegra_move_framebuffer(unsigned long to, unsigned long from,
729         unsigned long size)
730 {
731         struct page *page;
732         void __iomem *to_io;
733         void *from_virt;
734         unsigned long i;
735
736         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
737         BUG_ON(PAGE_ALIGN(from) != from);
738         BUG_ON(PAGE_ALIGN(size) != size);
739
740         to_io = ioremap(to, size);
741         if (!to_io) {
742                 pr_err("%s: Failed to map target framebuffer\n", __func__);
743                 return;
744         }
745
746         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
747                 for (i = 0 ; i < size; i += PAGE_SIZE) {
748                         page = phys_to_page(from + i);
749                         from_virt = kmap(page);
750                         memcpy(to_io + i, from_virt, PAGE_SIZE);
751                         kunmap(page);
752                 }
753         } else {
754                 void __iomem *from_io = ioremap(from, size);
755                 if (!from_io) {
756                         pr_err("%s: Failed to map source framebuffer\n",
757                                 __func__);
758                         goto out;
759                 }
760
761                 for (i = 0; i < size; i += 4)
762                         writel(readl(from_io + i), to_io + i);
763
764                 iounmap(from_io);
765         }
766 out:
767         iounmap(to_io);
768 }
769
770 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
771         unsigned long fb2_size)
772 {
773         if (carveout_size) {
774                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
775                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
776                         pr_err("Failed to remove carveout %08lx@%08lx "
777                                 "from memory map\n",
778                                 carveout_size, tegra_carveout_start);
779                         tegra_carveout_start = 0;
780                         tegra_carveout_size = 0;
781                 } else
782                         tegra_carveout_size = carveout_size;
783         }
784
785         if (fb2_size) {
786                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
787                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
788                         pr_err("Failed to remove second framebuffer "
789                                 "%08lx@%08lx from memory map\n",
790                                 fb2_size, tegra_fb2_start);
791                         tegra_fb2_start = 0;
792                         tegra_fb2_size = 0;
793                 } else
794                         tegra_fb2_size = fb2_size;
795         }
796
797         if (fb_size) {
798                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
799                 if (memblock_remove(tegra_fb_start, fb_size)) {
800                         pr_err("Failed to remove framebuffer %08lx@%08lx "
801                                 "from memory map\n",
802                                 fb_size, tegra_fb_start);
803                         tegra_fb_start = 0;
804                         tegra_fb_size = 0;
805                 } else
806                         tegra_fb_size = fb_size;
807         }
808
809         if (tegra_fb_size)
810                 tegra_grhost_aperture = tegra_fb_start;
811
812         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
813                 tegra_grhost_aperture = tegra_fb2_start;
814
815         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
816                 tegra_grhost_aperture = tegra_carveout_start;
817
818         if (tegra_lp0_vec_size &&
819            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
820                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
821                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
822                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
823                         tegra_lp0_vec_start = 0;
824                         tegra_lp0_vec_size = 0;
825                 }
826                 tegra_lp0_vec_relocate = false;
827         } else
828                 tegra_lp0_vec_relocate = true;
829
830         /*
831          * We copy the bootloader's framebuffer to the framebuffer allocated
832          * above, and then free this one.
833          * */
834         if (tegra_bootloader_fb_size) {
835                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
836                 if (memblock_reserve(tegra_bootloader_fb_start,
837                                 tegra_bootloader_fb_size)) {
838                         pr_err("Failed to reserve bootloader frame buffer "
839                                 "%08lx@%08lx\n", tegra_bootloader_fb_size,
840                                 tegra_bootloader_fb_start);
841                         tegra_bootloader_fb_start = 0;
842                         tegra_bootloader_fb_size = 0;
843                 }
844         }
845
846         pr_info("Tegra reserved memory:\n"
847                 "LP0:                    %08lx - %08lx\n"
848                 "Bootloader framebuffer: %08lx - %08lx\n"
849                 "Framebuffer:            %08lx - %08lx\n"
850                 "2nd Framebuffer:        %08lx - %08lx\n"
851                 "Carveout:               %08lx - %08lx\n"
852                 "Vpr:                    %08lx - %08lx\n",
853                 tegra_lp0_vec_start,
854                 tegra_lp0_vec_size ?
855                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
856                 tegra_bootloader_fb_start,
857                 tegra_bootloader_fb_size ?
858                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
859                 tegra_fb_start,
860                 tegra_fb_size ?
861                         tegra_fb_start + tegra_fb_size - 1 : 0,
862                 tegra_fb2_start,
863                 tegra_fb2_size ?
864                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
865                 tegra_carveout_start,
866                 tegra_carveout_size ?
867                         tegra_carveout_start + tegra_carveout_size - 1 : 0,
868                 tegra_vpr_start,
869                 tegra_vpr_size ?
870                         tegra_vpr_start + tegra_vpr_size - 1 : 0);
871 }
872
873 static struct resource ram_console_resources[] = {
874         {
875                 .flags = IORESOURCE_MEM,
876         },
877 };
878
879 static struct platform_device ram_console_device = {
880         .name           = "ram_console",
881         .id             = -1,
882         .num_resources  = ARRAY_SIZE(ram_console_resources),
883         .resource       = ram_console_resources,
884 };
885
886 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
887 {
888         struct resource *res;
889         long ret;
890
891         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
892         if (!res)
893                 goto fail;
894         res->start = memblock_end_of_DRAM() - ram_console_size;
895         res->end = res->start + ram_console_size - 1;
896         ret = memblock_remove(res->start, ram_console_size);
897         if (ret)
898                 goto fail;
899
900         return;
901
902 fail:
903         ram_console_device.resource = NULL;
904         ram_console_device.num_resources = 0;
905         pr_err("Failed to reserve memory block for ram console\n");
906 }
907
908 void __init tegra_ram_console_debug_init(void)
909 {
910         int err;
911
912         err = platform_device_register(&ram_console_device);
913         if (err) {
914                 pr_err("%s: ram console registration failed (%d)!\n", __func__, err);
915         }
916 }
917
918 void __init tegra_release_bootloader_fb(void)
919 {
920         /* Since bootloader fb is reserved in common.c, it is freed here. */
921         if (tegra_bootloader_fb_size)
922                 if (memblock_free(tegra_bootloader_fb_start,
923                                                 tegra_bootloader_fb_size))
924                         pr_err("Failed to free bootloader fb.\n");
925 }
926
927 static struct platform_device *pinmux_devices[] = {
928         &tegra_gpio_device,
929         &tegra_pinmux_device,
930 };
931
932 void tegra_enable_pinmux(void)
933 {
934         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
935 }
936
937 void __init tegra_init_late(void)
938 {
939 #ifndef CONFIG_COMMON_CLK
940         tegra_clk_debugfs_init();
941 #endif
942         tegra_powergate_debugfs_init();
943 }