ab008fc8f4f4a269114c6d612e1974be51a8522d
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/pstore_ram.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/sys_soc.h>
36 #if defined(CONFIG_SMSC911X)
37 #include <linux/smsc911x.h>
38 #endif
39 #include <linux/pm.h>
40
41 #include <linux/export.h>
42 #include <linux/bootmem.h>
43 #include <trace/events/nvsecurity.h>
44
45 #ifdef CONFIG_ARM64
46 #include <linux/irqchip/gic.h>
47 #else
48 #include <asm/system.h>
49 #include <asm/hardware/cache-l2x0.h>
50 #endif
51 #include <asm/dma-mapping.h>
52
53 #include <mach/hardware.h>
54 #include <mach/powergate.h>
55 #include <mach/tegra_smmu.h>
56 #include <mach/nct.h>
57
58 #include "apbio.h"
59 #include "board.h"
60 #include "clock.h"
61 #include "common.h"
62 #include "dvfs.h"
63 #include "fuse.h"
64 #include "iomap.h"
65 #include "pm.h"
66 #include "sleep.h"
67 #include "reset.h"
68 #include "devices.h"
69 #include "pmc.h"
70
71 #define MC_SECURITY_CFG2        0x7c
72
73 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
74 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
75 #define   PRIORITY_SELECT_USB   BIT(6)
76 #define   PRIORITY_SELECT_USB2  BIT(18)
77 #define   PRIORITY_SELECT_USB3  BIT(17)
78 #define   PRIORITY_SELECT_SE BIT(14)
79
80 #define AHB_GIZMO_AHB_MEM               0xc
81 #define   ENB_FAST_REARBITRATE  BIT(2)
82 #define   DONT_SPLIT_AHB_WR     BIT(7)
83 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
84 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
85
86 #define   RECOVERY_MODE BIT(31)
87 #define   BOOTLOADER_MODE       BIT(30)
88 #define   FORCED_RECOVERY_MODE  BIT(1)
89
90 #define AHB_GIZMO_USB           0x1c
91 #define AHB_GIZMO_USB2          0x78
92 #define AHB_GIZMO_USB3          0x7c
93 #define AHB_GIZMO_SE            0x4c
94 #define   IMMEDIATE     BIT(18)
95
96 #define AHB_MEM_PREFETCH_CFG5   0xc8
97 #define AHB_MEM_PREFETCH_CFG3   0xe0
98 #define AHB_MEM_PREFETCH_CFG4   0xe4
99 #define AHB_MEM_PREFETCH_CFG1   0xec
100 #define AHB_MEM_PREFETCH_CFG2   0xf0
101 #define AHB_MEM_PREFETCH_CFG6   0xcc
102 #define   PREFETCH_ENB  BIT(31)
103 #define   MST_ID(x)     (((x) & 0x1f) << 26)
104 #define   AHBDMA_MST_ID MST_ID(5)
105 #define   USB_MST_ID    MST_ID(6)
106 #define SDMMC4_MST_ID   MST_ID(12)
107 #define   USB2_MST_ID   MST_ID(18)
108 #define   USB3_MST_ID   MST_ID(17)
109 #define   SE_MST_ID     MST_ID(14)
110 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
111 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
112
113 phys_addr_t tegra_avp_kernel_start;
114 phys_addr_t tegra_avp_kernel_size;
115 phys_addr_t tegra_bootloader_fb_start;
116 phys_addr_t tegra_bootloader_fb_size;
117 phys_addr_t tegra_bootloader_fb2_start;
118 phys_addr_t tegra_bootloader_fb2_size;
119 phys_addr_t tegra_fb_start;
120 phys_addr_t tegra_fb_size;
121 phys_addr_t tegra_fb2_start;
122 phys_addr_t tegra_fb2_size;
123 phys_addr_t tegra_carveout_start;
124 phys_addr_t tegra_carveout_size;
125 phys_addr_t tegra_vpr_start;
126 phys_addr_t tegra_vpr_size;
127 phys_addr_t tegra_tsec_start;
128 phys_addr_t tegra_tsec_size;
129 phys_addr_t tegra_lp0_vec_start;
130 phys_addr_t tegra_lp0_vec_size;
131 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
132 phys_addr_t tegra_wb0_params_address;
133 phys_addr_t tegra_wb0_params_instances;
134 phys_addr_t tegra_wb0_params_block_size;
135 #endif
136
137 #ifdef CONFIG_TEGRA_NVDUMPER
138 unsigned long nvdumper_reserved;
139 #endif
140 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
141 unsigned long tegra_tzram_start;
142 unsigned long tegra_tzram_size;
143 #endif
144 bool tegra_lp0_vec_relocate;
145 unsigned long tegra_grhost_aperture = ~0ul;
146 static   bool is_tegra_debug_uart_hsport;
147 static struct board_info main_board_info;
148 static struct board_info pmu_board_info;
149 static struct board_info display_board_info;
150 static int panel_id;
151 static struct board_info camera_board_info;
152 static int touch_vendor_id;
153 static int touch_panel_id;
154 static struct board_info io_board_info;
155 static struct board_info button_board_info;
156 static struct board_info joystick_board_info;
157 static struct board_info rightspeaker_board_info;
158 static struct board_info leftspeaker_board_info;
159 #ifdef CONFIG_TEGRA_USE_NCT
160 unsigned long tegra_nck_start;
161 unsigned long tegra_nck_size;
162 #endif
163
164 static int pmu_core_edp;
165 static int board_panel_type;
166 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
167 static int pwr_i2c_clk = 400;
168 static u8 power_config;
169 static u8 display_config;
170
171 static int tegra_split_mem_set;
172
173 /*
174  * Storage for debug-macro.S's state.
175  *
176  * This must be in .data not .bss so that it gets initialized each time the
177  * kernel is loaded. The data is declared here rather than debug-macro.S so
178  * that multiple inclusions of debug-macro.S point at the same data.
179  */
180 u32 tegra_uart_config[4] = {
181         /* Debug UART initialization required */
182         1,
183         /* Debug UART physical address */
184         0,
185         /* Debug UART virtual address */
186         0,
187         /* Scratch space for debug macro */
188         0,
189 };
190
191
192 #define NEVER_RESET 0
193 static DEFINE_SPINLOCK(ahb_lock);
194
195 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
196 {
197         unsigned long check;
198         int retry = 10;
199         unsigned long flags;
200
201         /* Read and check if write is successful,
202          * if val doesn't match with read, retry write.
203          */
204         spin_lock_irqsave(&ahb_lock, flags);
205         do {
206                 writel(val, reg);
207                 check = readl(reg);
208                 if (likely(check == val))
209                         break;
210                 else
211                         pr_err("AHB register access fail for reg\n");
212         } while (--retry);
213         spin_unlock_irqrestore(&ahb_lock, flags);
214 }
215
216 void tegra_assert_system_reset(char mode, const char *cmd)
217 {
218         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
219         u32 reg;
220
221         if (tegra_platform_is_fpga() || NEVER_RESET) {
222                 pr_info("tegra_assert_system_reset() ignored.....");
223                 do { } while (1);
224         }
225
226         reg = readl_relaxed(reset + PMC_SCRATCH0);
227         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
228         if (cmd) {
229                 if (!strcmp(cmd, "recovery"))
230                         reg |= RECOVERY_MODE;
231                 else if (!strcmp(cmd, "bootloader"))
232                         reg |= BOOTLOADER_MODE;
233                 else if (!strcmp(cmd, "forced-recovery"))
234                         reg |= FORCED_RECOVERY_MODE;
235                 else
236                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
237         }
238         else {
239                 /* Clearing SCRATCH0 31:30:1 on default reboot */
240                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
241         }
242         writel_relaxed(reg, reset + PMC_SCRATCH0);
243         if (!cmd && pm_power_reset) {
244                 pm_power_reset();
245         } else {
246                 reg = readl_relaxed(reset);
247                 reg |= 0x10;
248                 writel_relaxed(reg, reset);
249         }
250 }
251 static int modem_id;
252 static int commchip_id;
253 static int sku_override;
254 static int debug_uart_port_id;
255 static enum audio_codec_type audio_codec_name;
256 static enum image_type board_image_type = system_image;
257 static int max_cpu_current;
258 static int max_core_current;
259 static int emc_max_dvfs;
260 static unsigned int memory_type;
261 static int usb_port_owner_info;
262 static int lane_owner_info;
263
264 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
265 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
266         /* name         parent          rate            enabled */
267         { "clk_m",      NULL,           0,              true },
268         { "emc",        NULL,           0,              true },
269         { "cpu",        NULL,           0,              true },
270         { "kfuse",      NULL,           0,              true },
271         { "fuse",       NULL,           0,              true },
272         { "sclk",       NULL,           0,              true },
273         { "pll_p",      NULL,           0,              true },
274         { "pll_p_out1", "pll_p",        0,              false },
275         { "pll_p_out3", "pll_p",        0,              false },
276 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
277         { "pll_m_out1", "pll_m",        275000000,      false },
278         { "pll_p_out2",  "pll_p",       102000000,      false },
279         { "sclk",        "pll_p_out2",  102000000,      true },
280         { "pll_p_out4",  "pll_p",       204000000,      true },
281         { "hclk",       "sclk",         102000000,      true },
282         { "pclk",       "hclk",         51000000,       true },
283         { "mselect",    "pll_p",        102000000,      true },
284         { "host1x",     "pll_p",        102000000,      false },
285         { "cl_dvfs_ref", "pll_p",       51000000,       true },
286         { "cl_dvfs_soc", "pll_p",       51000000,       true },
287         { "dsialp", "pll_p",    70000000,       false },
288         { "dsiblp", "pll_p",    70000000,       false },
289 #else
290         { "pll_m_out1", "pll_m",        275000000,      true },
291         { "pll_p_out2", "pll_p",        108000000,      false },
292         { "sclk",       "pll_p_out2",   108000000,      true },
293         { "pll_p_out4", "pll_p",        216000000,      true },
294         { "hclk",       "sclk",         108000000,      true },
295         { "pclk",       "hclk",         54000000,       true },
296         { "mselect",    "pll_p",        108000000,      true },
297         { "host1x",     "pll_p",        108000000,      false },
298         { "cl_dvfs_ref", "clk_m",       13000000,       false },
299         { "cl_dvfs_soc", "clk_m",       13000000,       false },
300 #endif
301 #ifdef CONFIG_TEGRA_SLOW_CSITE
302         { "csite",      "clk_m",        1000000,        true },
303 #else
304         { "csite",      NULL,           0,              true },
305 #endif
306         { "pll_u",      NULL,           480000000,      true },
307         { "pll_re_vco", NULL,           612000000,      true },
308         { "xusb_falcon_src",    "pll_p",        204000000,      false},
309         { "xusb_host_src",      "pll_p",        102000000,      false},
310         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
311         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
312         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
313         { "sdmmc1",     "pll_p",        48000000,       false},
314         { "sdmmc3",     "pll_p",        48000000,       false},
315         { "sdmmc4",     "pll_p",        48000000,       false},
316         { "sbc1.sclk",  NULL,           40000000,       false},
317         { "sbc2.sclk",  NULL,           40000000,       false},
318         { "sbc3.sclk",  NULL,           40000000,       false},
319         { "sbc4.sclk",  NULL,           40000000,       false},
320         { "sbc5.sclk",  NULL,           40000000,       false},
321         { "sbc6.sclk",  NULL,           40000000,       false},
322 #ifdef CONFIG_TEGRA_DUAL_CBUS
323         { "c2bus",      "pll_c2",       250000000,      false },
324         { "c3bus",      "pll_c3",       250000000,      false },
325         { "pll_c",      NULL,           624000000,      false },
326 #else
327         { "cbus",       "pll_c",        250000000,      false },
328 #endif
329         { "pll_c_out1", "pll_c",        150000000,      false },
330 #ifdef CONFIG_TEGRA_PLLM_SCALED
331         { "vi",         "pll_p",        0,              false},
332 #endif
333 #ifdef CONFIG_TEGRA_SOCTHERM
334         { "soc_therm",  "pll_p",        136000000,      false },
335         { "tsensor",    "clk_m",        500000,         false },
336 #endif
337         { "csite",      NULL,           0,              true },
338         { NULL,         NULL,           0,              0},
339 };
340 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
341 #ifdef CONFIG_TEGRA_DUAL_CBUS
342         { "c2bus",      "pll_c2",       250000000,      false },
343         { "c3bus",      "pll_c3",       250000000,      false },
344         { "pll_c",      NULL,           624000000,      false },
345 #else
346         { "cbus",       "pll_c",        250000000,      false },
347 #endif
348         { "pll_c_out1", "pll_c",        150000000,      false },
349         { NULL,         NULL,           0,              0},
350 };
351 #endif
352 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
353 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
354         /* name         parent          rate            enabled */
355         { "clk_m",      NULL,           0,              true },
356         { "emc",        NULL,           0,              true },
357         { "cpu",        NULL,           0,              true },
358         { "kfuse",      NULL,           0,              true },
359         { "fuse",       NULL,           0,              true },
360         { "sclk",       NULL,           0,              true },
361         { "pll_p",      NULL,           0,              true,
362                 TEGRA_CLK_INIT_PLATFORM_SI },
363         { "pll_p_out1", "pll_p",        0,              false,
364                 TEGRA_CLK_INIT_PLATFORM_SI },
365         { "pll_p_out3", "pll_p",        0,              true,
366                 TEGRA_CLK_INIT_PLATFORM_SI },
367         { "pll_m_out1", "pll_m",        275000000,      false,
368                 TEGRA_CLK_INIT_PLATFORM_SI },
369         { "pll_p_out2", "pll_p",        102000000,      false,
370                 TEGRA_CLK_INIT_PLATFORM_SI },
371         { "sclk",       "pll_p_out2",   102000000,      true,
372                 TEGRA_CLK_INIT_PLATFORM_SI },
373         { "pll_p_out4", "pll_p",        204000000,      true,
374                 TEGRA_CLK_INIT_PLATFORM_SI },
375         { "host1x",     "pll_p",        102000000,      false,
376                 TEGRA_CLK_INIT_PLATFORM_SI },
377         { "cl_dvfs_ref", "pll_p",       54000000,       true,
378                 TEGRA_CLK_INIT_PLATFORM_SI },
379         { "cl_dvfs_soc", "pll_p",       54000000,       true,
380                 TEGRA_CLK_INIT_PLATFORM_SI },
381         { "hclk",       "sclk",         102000000,      true,
382                 TEGRA_CLK_INIT_PLATFORM_SI },
383         { "pclk",       "hclk",         51000000,       true,
384                 TEGRA_CLK_INIT_PLATFORM_SI },
385         { "wake.sclk",  NULL,           40000000,       true,
386                 TEGRA_CLK_INIT_PLATFORM_SI },
387         { "mselect",    "pll_p",        102000000,      true,
388                 TEGRA_CLK_INIT_PLATFORM_SI },
389         { "pll_p_out5", "pll_p",        102000000,      true,
390                 TEGRA_CLK_INIT_PLATFORM_SI },
391 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
392         { "pll_m_out1", "pll_m",        275000000,      true,
393                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
394         { "pll_p_out2", "pll_p",        108000000,      false,
395                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
396         { "sclk",       "pll_p_out2",   108000000,      true,
397                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
398         { "pll_p_out4", "pll_p",        216000000,      true,
399                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
400         { "hclk",       "sclk",         108000000,      true,
401                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
402         { "pclk",       "hclk",         54000000,       true,
403                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
404         { "mselect",    "pll_p",        108000000,      true,
405                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
406         { "host1x",     "pll_p",        108000000,      false,
407                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
408         { "cl_dvfs_ref", "clk_m",       13000000,       false,
409                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
410         { "cl_dvfs_soc", "clk_m",       13000000,       false,
411                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
412 #endif
413 #ifdef CONFIG_TEGRA_SLOW_CSITE
414         { "csite",      "clk_m",        1000000,        true },
415 #else
416         { "csite",      NULL,           0,              true },
417 #endif
418         { "pll_u",      NULL,           480000000,      true },
419         { "pll_re_vco", NULL,           672000000,      false },
420         { "xusb_falcon_src",    "pll_re_out",   224000000,      false},
421         { "xusb_host_src",      "pll_re_out",   112000000,      false},
422         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
423         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
424         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
425         { "sdmmc1",     "pll_p",        48000000,       false},
426         { "sdmmc3",     "pll_p",        48000000,       false},
427         { "sdmmc4",     "pll_p",        48000000,       false},
428         { "sbc1.sclk",  NULL,           40000000,       false},
429         { "sbc2.sclk",  NULL,           40000000,       false},
430         { "sbc3.sclk",  NULL,           40000000,       false},
431         { "sbc4.sclk",  NULL,           40000000,       false},
432         { "sbc5.sclk",  NULL,           40000000,       false},
433         { "sbc6.sclk",  NULL,           40000000,       false},
434         { "gpu",        NULL,           0,              true},
435 #ifdef CONFIG_TEGRA_PLLM_SCALED
436         { "vi",         "pll_p",        0,              false},
437         { "isp",        "pll_p",        0,              false},
438 #endif
439 #ifdef CONFIG_TEGRA_SOCTHERM
440         { "soc_therm",  "pll_p",        51000000,       false },
441         { "tsensor",    "clk_m",        500000,         false },
442 #endif
443         { "vde",        "pll_c3",       48400000,       true,
444                 TEGRA_CLK_INIT_CPU_ASIM},
445         { NULL,         NULL,           0,              0},
446 };
447 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
448         /* Initialize c2bus, c3bus, or cbus at the end of the list
449          * after all the clocks are moved under the proper parents.
450          */
451 #ifdef CONFIG_TEGRA_DUAL_CBUS
452         { "c2bus",      "pll_c2",       250000000,      false },
453         { "c3bus",      "pll_c3",       250000000,      false },
454         { "pll_c",      NULL,           768000000,      false },
455 #else
456         { "cbus",       "pll_c",        200000000,      false },
457 #endif
458         { "pll_c_out1", "pll_c",        100000000,      false },
459         { NULL,         NULL,           0,              0},
460 };
461 #endif
462
463 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
464 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
465         /* name         parent          rate            enabled */
466         { "osc",        NULL,           0,              true },
467         { "clk_m",      "osc",          0,              true },
468         { "emc",        NULL,           0,              true },
469         { "cpu",        NULL,           0,              true },
470         { "kfuse",      NULL,           0,              true },
471         { "fuse",       NULL,           0,              true },
472         { "sclk",       NULL,           0,              true },
473 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
474         { "pll_p",      NULL,           0,              true },
475         { "pll_p_out1", "pll_p",        0,              false },
476         { "pll_p_out3", "pll_p",        0,              true },
477         { "pll_m_out1", "pll_m",        275000000,      false },
478         { "pll_p_out2",  "pll_p",       102000000,      false },
479         { "sclk",        "pll_p_out2",  102000000,      true },
480         { "pll_p_out4",  "pll_p",       204000000,      true },
481         { "hclk",       "sclk",         102000000,      true },
482         { "pclk",       "hclk",         51000000,       true },
483         { "mselect",    "pll_p",        102000000,      true },
484         { "host1x",     "pll_p",        102000000,      false },
485         { "cl_dvfs_ref", "pll_p",       51000000,       true },
486         { "cl_dvfs_soc", "pll_p",       51000000,       true },
487 #else
488         { "pll_p",      NULL,           0,              true },
489         { "pll_p_out1", "pll_p",        0,              false },
490         { "pll_p_out3", "pll_p",        0,              true },
491         { "pll_m_out1", "pll_m",        275000000,      true },
492         { "pll_p_out2", "pll_p",        108000000,      false },
493         { "sclk",       "pll_p_out2",   108000000,      true },
494         { "pll_p_out4", "pll_p",        216000000,      true },
495         { "host1x",     "pll_p",        108000000,      false },
496         { "cl_dvfs_ref", "clk_m",       13000000,       false },
497         { "cl_dvfs_soc", "clk_m",       13000000,       false },
498         { "hclk",       "sclk",         108000000,      true },
499         { "pclk",       "hclk",         54000000,       true },
500         { "wake.sclk",  NULL,           250000000,      true },
501         { "mselect",    "pll_p",        108000000,      true },
502 #endif
503 #ifdef CONFIG_TEGRA_SLOW_CSITE
504         { "csite",      "clk_m",        1000000,        true },
505 #else
506         { "csite",      NULL,           0,              true },
507 #endif
508         { "pll_u",      NULL,           480000000,      false },
509         { "sdmmc1",     "pll_p",        48000000,       false},
510         { "sdmmc3",     "pll_p",        48000000,       false},
511         { "sdmmc4",     "pll_p",        48000000,       false},
512         { "mon.avp",    NULL,           80000000,       true },
513         { "sbc1.sclk",  NULL,           20000000,       false},
514         { "sbc2.sclk",  NULL,           20000000,       false},
515         { "sbc3.sclk",  NULL,           20000000,       false},
516         { "msenc",      "pll_p",        108000000,      false },
517         { "tsec",       "pll_p",        108000000,      false },
518         { "mc_capa",    "emc",          0,              true },
519         { "mc_cbpa",    "emc",          0,              true },
520 #ifdef CONFIG_TEGRA_SOCTHERM
521         { "soc_therm",  "pll_p",        51000000,       false },
522         { "tsensor",    "clk_m",        400000,         false },
523 #endif
524         { NULL,         NULL,           0,              0},
525 };
526 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
527         /* Initialize c2bus, c3bus, or cbus at the end of the list
528          * after all the clocks are moved under the proper parents.
529          */
530 #ifdef CONFIG_TEGRA_DUAL_CBUS
531         { "c2bus",      "pll_c2",       200000000,      false },
532         { "c3bus",      "pll_c3",       200000000,      false },
533         { "pll_c",      NULL,           768000000,      false },
534 #else
535         { "cbus",       "pll_c",        200000000,      false },
536 #endif
537         { "pll_c_out1", "pll_c",        100000000,      false },
538         { NULL,         NULL,           0,              0},
539 };
540 #endif
541
542 #ifdef CONFIG_CACHE_L2X0
543 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
544 static void tegra_cache_smc(bool enable, u32 arg)
545 {
546         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
547         bool need_affinity_switch;
548         bool can_switch_affinity;
549         bool l2x0_enabled;
550         cpumask_t local_cpu_mask;
551         cpumask_t saved_cpu_mask;
552         unsigned long flags;
553         long ret;
554
555         /*
556          * ISSUE : Some registers of PL310 controler must be written
557          *              from Secure context (and from CPU0)!
558          *
559          * When called form Normal we obtain an abort or do nothing.
560          * Instructions that must be called in Secure:
561          *      - Write to Control register (L2X0_CTRL==0x100)
562          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
563          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
564          *              mandatory at boot time.
565          *      - Tag and Data RAM Latency Control Registers
566          *              (0x108 & 0x10C) must be written in Secure.
567          */
568         need_affinity_switch = (smp_processor_id() != 0);
569         can_switch_affinity = !irqs_disabled();
570
571         WARN_ON(need_affinity_switch && !can_switch_affinity);
572         if (need_affinity_switch && can_switch_affinity) {
573                 cpu_set(0, local_cpu_mask);
574                 sched_getaffinity(0, &saved_cpu_mask);
575                 ret = sched_setaffinity(0, &local_cpu_mask);
576                 WARN_ON(ret != 0);
577         }
578
579         local_irq_save(flags);
580         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
581         if (enable && !l2x0_enabled)
582                 tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
583         else if (!enable && l2x0_enabled)
584                 tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
585         local_irq_restore(flags);
586
587         if (need_affinity_switch && can_switch_affinity) {
588                 ret = sched_setaffinity(0, &saved_cpu_mask);
589                 WARN_ON(ret != 0);
590         }
591 }
592
593 static void tegra_l2x0_disable(void)
594 {
595         unsigned long flags;
596         static u32 l2x0_way_mask;
597
598         if (!l2x0_way_mask) {
599                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
600                 u32 aux_ctrl;
601                 u32 ways;
602
603                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
604                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
605                 l2x0_way_mask = (1 << ways) - 1;
606         }
607
608         local_irq_save(flags);
609         tegra_cache_smc(false, l2x0_way_mask);
610         local_irq_restore(flags);
611 }
612 #endif  /* CONFIG_TEGRA_USE_SECURE_KERNEL */
613
614 void tegra_init_cache(bool init)
615 {
616         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
617         u32 aux_ctrl;
618 #ifndef CONFIG_TEGRA_USE_SECURE_KERNEL
619         u32 cache_type;
620         u32 tag_latency, data_latency;
621 #endif
622
623 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
624         /* issue the SMC to enable the L2 */
625         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
626         trace_smc_init_cache(NVSEC_SMC_START);
627         tegra_cache_smc(true, aux_ctrl);
628         trace_smc_init_cache(NVSEC_SMC_DONE);
629
630         /* after init, reread aux_ctrl and register handlers */
631         aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
632         l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
633
634         /* override outer_disable() with our disable */
635         outer_cache.disable = tegra_l2x0_disable;
636 #else
637 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
638         tag_latency = 0x331;
639         data_latency = 0x441;
640 #else
641         if (!tegra_platform_is_silicon()) {
642                 tag_latency = 0x770;
643                 data_latency = 0x770;
644         } else if (is_lp_cluster()) {
645                 tag_latency = tegra_cpu_c1_l2_tag_latency;
646                 data_latency = tegra_cpu_c1_l2_data_latency;
647         } else {
648                 tag_latency = tegra_cpu_c0_l2_tag_latency;
649                 data_latency = tegra_cpu_c0_l2_data_latency;
650         }
651 #endif
652         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
653         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
654
655 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
656         if (!tegra_platform_is_fpga()) {
657 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
658                 /* Enable double line fill */
659                 writel(0x40000007, p + L2X0_PREFETCH_CTRL);
660 #else
661                 writel(0x7, p + L2X0_PREFETCH_CTRL);
662 #endif
663                 writel(0x3, p + L2X0_POWER_CTRL);
664         }
665 #endif
666         cache_type = readl(p + L2X0_CACHE_TYPE);
667         aux_ctrl = (cache_type & 0x700) << (17-8);
668         aux_ctrl |= 0x7C400001;
669         if (init) {
670                 l2x0_init(p, aux_ctrl, 0x8200c3fe);
671         } else {
672                 u32 tmp;
673
674                 tmp = aux_ctrl;
675                 aux_ctrl = readl(p + L2X0_AUX_CTRL);
676                 aux_ctrl &= 0x8200c3fe;
677                 aux_ctrl |= tmp;
678                 writel(aux_ctrl, p + L2X0_AUX_CTRL);
679         }
680         l2x0_enable();
681 #endif
682 }
683 #endif
684
685 static void __init tegra_perf_init(void)
686 {
687         u32 reg;
688
689 #ifdef CONFIG_ARM64
690         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
691         reg >>= 11;
692         reg = (1 << (reg & 0x1f))-1;
693         reg |= 0x80000000;
694         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
695         reg = 1;
696         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
697 #else
698         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
699         reg >>= 11;
700         reg = (1 << (reg & 0x1f))-1;
701         reg |= 0x80000000;
702         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
703         reg = 1;
704         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
705 #endif
706 }
707
708 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
709 static void __init tegra_ramrepair_init(void)
710 {
711         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
712                 u32 reg;
713                 reg = readl(FLOW_CTRL_RAM_REPAIR);
714                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
715                 writel(reg, FLOW_CTRL_RAM_REPAIR);
716         }
717 }
718 #endif
719
720 static void __init tegra_init_power(void)
721 {
722 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
723         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
724 #endif
725 #if defined(CONFIG_ARCH_TEGRA_HAS_PCIE) && \
726                         !defined(CONFIG_TEGRA_PCIE_SKIP_POWERGATING)
727         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
728 #endif
729
730 #if defined(CONFIG_TEGRA_XUSB_PLATFORM)
731         /* powergate xusb partitions by default */
732         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
733         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
734         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
735 #endif
736
737 }
738
739 static inline unsigned long gizmo_readl(unsigned long offset)
740 {
741         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
742 }
743
744 static inline void gizmo_writel(unsigned long value, unsigned long offset)
745 {
746         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
747 }
748
749 static void __init tegra_init_ahb_gizmo_settings(void)
750 {
751         unsigned long val;
752
753         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
754         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
755
756         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
757                 val |= WR_WAIT_COMMIT_ON_1K;
758 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
759         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
760 #endif
761         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
762
763         val = gizmo_readl(AHB_GIZMO_USB);
764         val |= IMMEDIATE;
765         gizmo_writel(val, AHB_GIZMO_USB);
766
767         val = gizmo_readl(AHB_GIZMO_USB2);
768         val |= IMMEDIATE;
769         gizmo_writel(val, AHB_GIZMO_USB2);
770
771         val = gizmo_readl(AHB_GIZMO_USB3);
772         val |= IMMEDIATE;
773         gizmo_writel(val, AHB_GIZMO_USB3);
774
775         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
776         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
777                                 | AHB_PRIORITY_WEIGHT(7);
778 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
779         val |= PRIORITY_SELECT_SE;
780 #endif
781
782         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
783
784         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
785         val &= ~MST_ID(~0);
786         val |= PREFETCH_ENB | AHBDMA_MST_ID |
787                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
788         ahb_gizmo_writel(val,
789                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
790
791         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
792         val &= ~MST_ID(~0);
793         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
794                 INACTIVITY_TIMEOUT(0x1000);
795 #if !defined(CONFIG_ANDROID)
796         val &= ~USB_MST_ID;
797 #endif
798         ahb_gizmo_writel(val,
799                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
800
801         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
802         val &= ~MST_ID(~0);
803         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
804                 INACTIVITY_TIMEOUT(0x1000);
805 #if !defined(CONFIG_ANDROID)
806         val &= ~USB3_MST_ID;
807 #endif
808         ahb_gizmo_writel(val,
809                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
810
811         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
812         val &= ~MST_ID(~0);
813         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
814                 INACTIVITY_TIMEOUT(0x1000);
815         ahb_gizmo_writel(val,
816                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
817
818         /*
819          * SDMMC controller is removed from AHB interface in T124 and
820          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
821          * in T11x and T14x SOCs.
822          */
823 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
824         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
825         val &= ~MST_ID(~0);
826         val |= PREFETCH_ENB | SDMMC4_MST_ID;
827         val &= ~SDMMC4_MST_ID;
828         ahb_gizmo_writel(val,
829                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
830 #endif
831
832 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
833         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
834         val &= ~MST_ID(~0);
835         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
836                 INACTIVITY_TIMEOUT(0x1000);
837         ahb_gizmo_writel(val,
838                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
839 #endif
840 }
841
842 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
843 void __init tegra20_init_early(void)
844 {
845 #ifndef CONFIG_SMP
846         /* For SMP system, initializing the reset handler here is too
847            late. For non-SMP systems, the function that calls the reset
848            handler initializer is not called, so do it here for non-SMP. */
849         tegra_cpu_reset_handler_init();
850 #endif
851         tegra_apb_io_init();
852         tegra_perf_init();
853         tegra_init_fuse();
854         tegra_init_cache(true);
855         tegra_pmc_init();
856         tegra_powergate_init();
857         tegra20_hotplug_init();
858         tegra_init_power();
859         tegra_init_ahb_gizmo_settings();
860         tegra_init_debug_uart_rate();
861         tegra_ram_console_debug_reserve(SZ_1M);
862 }
863 #endif
864 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
865 void __init tegra30_init_early(void)
866 {
867         u32 speedo;
868         u32 tag_latency, data_latency;
869
870 #ifndef CONFIG_SMP
871         /* For SMP system, initializing the reset handler here is too
872            late. For non-SMP systems, the function that calls the reset
873            handler initializer is not called, so do it here for non-SMP. */
874         tegra_cpu_reset_handler_init();
875 #endif
876         tegra_apb_io_init();
877         tegra_perf_init();
878         tegra_init_fuse();
879         /*
880          * Store G/LP cluster L2 latencies to IRAM and DRAM
881          */
882         tegra_cpu_c1_l2_tag_latency = 0x221;
883         tegra_cpu_c1_l2_data_latency = 0x221;
884         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
885         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
886         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
887         speedo = tegra_cpu_speedo_id();
888         if (speedo == 4 || speedo == 5 || speedo == 6 ||
889             speedo == 12 || speedo == 13) {
890                 tag_latency = 0x442;
891                 data_latency = 0x552;
892         } else {
893                 tag_latency = 0x441;
894                 data_latency = 0x551;
895         }
896         tegra_cpu_c0_l2_tag_latency = tag_latency;
897         tegra_cpu_c0_l2_data_latency = data_latency;
898         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
899         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
900         tegra_init_cache(true);
901         tegra_pmc_init();
902         tegra_powergate_init();
903         tegra30_hotplug_init();
904         tegra_init_power();
905         tegra_init_ahb_gizmo_settings();
906         tegra_init_debug_uart_rate();
907         tegra_ram_console_debug_reserve(SZ_1M);
908
909         init_dma_coherent_pool_size(SZ_1M);
910 }
911 #endif
912 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
913 void __init tegra11x_init_early(void)
914 {
915 #ifndef CONFIG_SMP
916         /* For SMP system, initializing the reset handler here is too
917            late. For non-SMP systems, the function that calls the reset
918            handler initializer is not called, so do it here for non-SMP. */
919         tegra_cpu_reset_handler_init();
920 #endif
921         tegra_apb_io_init();
922         tegra_perf_init();
923         tegra_init_fuse();
924         tegra_ramrepair_init();
925         tegra11x_init_clocks();
926         tegra11x_init_dvfs();
927         tegra_common_init_clock();
928         tegra_clk_init_from_table(tegra11x_clk_init_table);
929         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
930         tegra11x_clk_init_la();
931         tegra_pmc_init();
932         tegra_powergate_init();
933         tegra30_hotplug_init();
934         tegra_init_power();
935         tegra_init_ahb_gizmo_settings();
936         tegra_init_debug_uart_rate();
937
938         init_dma_coherent_pool_size(SZ_2M);
939 }
940 #endif
941 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
942 void __init tegra12x_init_early(void)
943 {
944 #ifndef CONFIG_SMP
945         /* For SMP system, initializing the reset handler here is too
946            late. For non-SMP systems, the function that calls the reset
947            handler initializer is not called, so do it here for non-SMP. */
948         tegra_cpu_reset_handler_init();
949 #endif
950         tegra_apb_io_init();
951         tegra_perf_init();
952         tegra_init_fuse();
953         tegra_ramrepair_init();
954         tegra12x_init_clocks();
955         tegra12x_init_dvfs();
956         tegra_common_init_clock();
957         tegra_clk_init_from_table(tegra12x_clk_init_table);
958         tegra_clk_init_cbus_plls_from_table(tegra12x_cbus_init_table);
959         tegra_init_cache(true);
960         tegra_pmc_init();
961         tegra_powergate_init();
962         tegra_init_power();
963         tegra_init_ahb_gizmo_settings();
964         tegra_init_debug_uart_rate();
965 }
966 #endif
967 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
968 void __init tegra14x_init_early(void)
969 {
970 #ifndef CONFIG_SMP
971         /* For SMP system, initializing the reset handler here is too
972            late. For non-SMP systems, the function that calls the reset
973            handler initializer is not called, so do it here for non-SMP. */
974         tegra_cpu_reset_handler_init();
975 #endif
976         tegra_apb_io_init();
977         tegra_perf_init();
978         tegra_init_fuse();
979         tegra_ramrepair_init();
980         tegra14x_init_clocks();
981         tegra14x_init_dvfs();
982         tegra_common_init_clock();
983         tegra_clk_init_from_table(tegra14x_clk_init_table);
984         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
985         tegra_cpu_c1_l2_tag_latency = 0x110;
986         tegra_cpu_c1_l2_data_latency = 0x331;
987         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
988         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
989         tegra_cpu_c0_l2_tag_latency = 0x111;
990         tegra_cpu_c0_l2_data_latency = 0x441;
991         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
992         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
993         tegra_init_cache(true);
994         tegra_pmc_init();
995         tegra_powergate_init();
996         tegra30_hotplug_init();
997         tegra_init_power();
998         tegra_init_ahb_gizmo_settings();
999         tegra_init_debug_uart_rate();
1000         tegra_ram_console_debug_reserve(SZ_1M);
1001 }
1002 #endif
1003 static int __init tegra_lp0_vec_arg(char *options)
1004 {
1005         char *p = options;
1006
1007         tegra_lp0_vec_size = memparse(p, &p);
1008         if (*p == '@')
1009                 tegra_lp0_vec_start = memparse(p+1, &p);
1010         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
1011                 tegra_lp0_vec_size = 0;
1012                 tegra_lp0_vec_start = 0;
1013         }
1014
1015         return 0;
1016 }
1017 early_param("lp0_vec", tegra_lp0_vec_arg);
1018
1019 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1020 static int __init tegra_wb0_params_arg(char *options)
1021 {
1022         char *p = options;
1023
1024         tegra_wb0_params_address = memparse(p, &p);
1025         if (*p == ',')
1026                 tegra_wb0_params_instances = memparse(p+1, &p);
1027         if (*p == ',')
1028                 tegra_wb0_params_block_size = memparse(p+1, &p);
1029
1030         return 0;
1031 }
1032 early_param("wb0_params", tegra_wb0_params_arg);
1033 #endif
1034
1035 #ifdef CONFIG_TEGRA_NVDUMPER
1036 static int __init tegra_nvdumper_arg(char *options)
1037 {
1038         char *p = options;
1039
1040         nvdumper_reserved = memparse(p, &p);
1041         return 0;
1042 }
1043 early_param("nvdumper_reserved", tegra_nvdumper_arg);
1044 #endif
1045
1046 static int __init tegra_bootloader_fb_arg(char *options)
1047 {
1048         char *p = options;
1049
1050         tegra_bootloader_fb_size = memparse(p, &p);
1051         if (*p == '@')
1052                 tegra_bootloader_fb_start = memparse(p+1, &p);
1053
1054         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1055                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1056
1057         return 0;
1058 }
1059 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1060
1061 static int __init tegra_bootloader_fb2_arg(char *options)
1062 {
1063         char *p = options;
1064
1065         tegra_bootloader_fb2_size = memparse(p, &p);
1066         if (*p == '@')
1067                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1068
1069         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1070                 (u64)tegra_bootloader_fb2_size,
1071                 (u64)tegra_bootloader_fb2_start);
1072
1073         return 0;
1074 }
1075 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1076
1077 static int __init tegra_sku_override(char *id)
1078 {
1079         char *p = id;
1080
1081         sku_override = memparse(p, &p);
1082
1083         return 0;
1084 }
1085 early_param("sku_override", tegra_sku_override);
1086
1087 int tegra_get_sku_override(void)
1088 {
1089         return sku_override;
1090 }
1091
1092 static int __init tegra_vpr_arg(char *options)
1093 {
1094         char *p = options;
1095
1096         tegra_vpr_size = memparse(p, &p);
1097         if (*p == '@')
1098                 tegra_vpr_start = memparse(p+1, &p);
1099         pr_info("Found vpr, start=0x%llx size=%llx",
1100                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1101         return 0;
1102 }
1103 early_param("vpr", tegra_vpr_arg);
1104
1105 static int __init tegra_tsec_arg(char *options)
1106 {
1107         char *p = options;
1108
1109         tegra_tsec_size = memparse(p, &p);
1110         if (*p == '@')
1111                 tegra_tsec_start = memparse(p+1, &p);
1112         pr_info("Found tsec, start=0x%llx size=%llx",
1113                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1114         return 0;
1115 }
1116 early_param("tsec", tegra_tsec_arg);
1117
1118 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
1119 static int __init tegra_tzram_arg(char *options)
1120 {
1121         char *p = options;
1122
1123         tegra_tzram_size = memparse(p, &p);
1124         if (*p == '@')
1125                 tegra_tzram_start = memparse(p + 1, &p);
1126         return 0;
1127 }
1128 early_param("tzram", tegra_tzram_arg);
1129 #endif
1130
1131 #ifdef CONFIG_TEGRA_USE_NCT
1132 static int __init tegra_nck_arg(char *options)
1133 {
1134         char *p = options;
1135
1136         tegra_nck_size = memparse(p, &p);
1137         if (*p == '@')
1138                 tegra_nck_start = memparse(p+1, &p);
1139         if (!tegra_nck_size || !tegra_nck_start) {
1140                 tegra_nck_size = 0;
1141                 tegra_nck_start = 0;
1142         }
1143
1144         return 0;
1145 }
1146 early_param("nck", tegra_nck_arg);
1147 #endif  /* CONFIG_TEGRA_USE_NCT */
1148
1149 enum panel_type get_panel_type(void)
1150 {
1151         return board_panel_type;
1152 }
1153 static int __init tegra_board_panel_type(char *options)
1154 {
1155         if (!strcmp(options, "lvds"))
1156                 board_panel_type = panel_type_lvds;
1157         else if (!strcmp(options, "dsi"))
1158                 board_panel_type = panel_type_dsi;
1159         else
1160                 return 0;
1161         return 1;
1162 }
1163 __setup("panel=", tegra_board_panel_type);
1164
1165 int tegra_get_board_panel_id(void)
1166 {
1167         return panel_id;
1168 }
1169 static int __init tegra_board_panel_id(char *options)
1170 {
1171         char *p = options;
1172         panel_id = memparse(p, &p);
1173         return panel_id;
1174 }
1175 __setup("display_panel=", tegra_board_panel_id);
1176
1177 int tegra_get_touch_vendor_id(void)
1178 {
1179         return touch_vendor_id;
1180 }
1181 int tegra_get_touch_panel_id(void)
1182 {
1183         return touch_panel_id;
1184 }
1185 static int __init tegra_touch_id(char *options)
1186 {
1187         char *p = options;
1188         touch_vendor_id = memparse(p, &p);
1189         if (*p == '@')
1190                 touch_panel_id = memparse(p+1, &p);
1191         return 1;
1192 }
1193 __setup("touch_id=", tegra_touch_id);
1194
1195 u8 get_power_config(void)
1196 {
1197         return power_config;
1198 }
1199 static int __init tegra_board_power_config(char *options)
1200 {
1201         char *p = options;
1202         power_config = memparse(p, &p);
1203         return 1;
1204 }
1205 __setup("power-config=", tegra_board_power_config);
1206
1207 u8 get_display_config(void)
1208 {
1209         return display_config;
1210 }
1211 static int __init tegra_board_display_config(char *options)
1212 {
1213         char *p = options;
1214         display_config = memparse(p, &p);
1215         return 1;
1216 }
1217 __setup("display-config=", tegra_board_display_config);
1218
1219 enum power_supply_type get_power_supply_type(void)
1220 {
1221         return pow_supply_type;
1222 }
1223 static int __init tegra_board_power_supply_type(char *options)
1224 {
1225         if (!strcmp(options, "Adapter"))
1226                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1227         if (!strcmp(options, "Mains"))
1228                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1229         else if (!strcmp(options, "Battery"))
1230                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1231         else
1232                 return 0;
1233         return 1;
1234 }
1235 __setup("power_supply=", tegra_board_power_supply_type);
1236
1237 int get_core_edp(void)
1238 {
1239         return pmu_core_edp;
1240 }
1241 static int __init tegra_pmu_core_edp(char *options)
1242 {
1243         char *p = options;
1244         int core_edp = memparse(p, &p);
1245         if (core_edp != 0)
1246                 pmu_core_edp = core_edp;
1247         return 0;
1248 }
1249 early_param("core_edp_mv", tegra_pmu_core_edp);
1250
1251 int get_maximum_cpu_current_supported(void)
1252 {
1253         return max_cpu_current;
1254 }
1255 static int __init tegra_max_cpu_current(char *options)
1256 {
1257         char *p = options;
1258         max_cpu_current = memparse(p, &p);
1259         return 1;
1260 }
1261 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1262
1263 int get_maximum_core_current_supported(void)
1264 {
1265         return max_core_current;
1266 }
1267 static int __init tegra_max_core_current(char *options)
1268 {
1269         char *p = options;
1270         max_core_current = memparse(p, &p);
1271         return 1;
1272 }
1273 __setup("core_edp_ma=", tegra_max_core_current);
1274
1275 int get_emc_max_dvfs(void)
1276 {
1277         return emc_max_dvfs;
1278 }
1279 static int __init tegra_emc_max_dvfs(char *options)
1280 {
1281         char *p = options;
1282         emc_max_dvfs = memparse(p, &p);
1283         return 1;
1284 }
1285 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1286
1287 int tegra_get_memory_type(void)
1288 {
1289         return memory_type;
1290 }
1291 static int __init tegra_memory_type(char *options)
1292 {
1293         char *p = options;
1294         memory_type = memparse(p, &p);
1295         return 1;
1296 }
1297 __setup("memtype=", tegra_memory_type);
1298
1299 static int __init tegra_debug_uartport(char *info)
1300 {
1301         char *p = info;
1302         unsigned long long port_id;
1303         if (!strncmp(p, "hsport", 6))
1304                 is_tegra_debug_uart_hsport = true;
1305         else if (!strncmp(p, "lsport", 6))
1306                 is_tegra_debug_uart_hsport = false;
1307
1308         if (p[6] == ',') {
1309                 if (p[7] == '-') {
1310                         debug_uart_port_id = -1;
1311                 } else {
1312                         port_id = memparse(p + 7, &p);
1313                         debug_uart_port_id = (int) port_id;
1314                 }
1315         } else {
1316                 debug_uart_port_id = -1;
1317         }
1318
1319         return 1;
1320 }
1321
1322 bool is_tegra_debug_uartport_hs(void)
1323 {
1324         return is_tegra_debug_uart_hsport;
1325 }
1326
1327 int get_tegra_uart_debug_port_id(void)
1328 {
1329         return debug_uart_port_id;
1330 }
1331 __setup("debug_uartport=", tegra_debug_uartport);
1332
1333 static int __init tegra_image_type(char *options)
1334 {
1335         if (!strcmp(options, "RCK"))
1336                 board_image_type = rck_image;
1337
1338         return 0;
1339 }
1340
1341 enum image_type get_tegra_image_type(void)
1342 {
1343         return board_image_type;
1344 }
1345
1346 __setup("image=", tegra_image_type);
1347
1348 static int __init tegra_audio_codec_type(char *info)
1349 {
1350         char *p = info;
1351         if (!strncmp(p, "wm8903", 6))
1352                 audio_codec_name = audio_codec_wm8903;
1353         else
1354                 audio_codec_name = audio_codec_none;
1355
1356         return 1;
1357 }
1358
1359 enum audio_codec_type get_audio_codec_type(void)
1360 {
1361         return audio_codec_name;
1362 }
1363 __setup("audio_codec=", tegra_audio_codec_type);
1364
1365 static int tegra_get_pwr_i2c_clk_rate(char *options)
1366 {
1367         int clk = simple_strtol(options, NULL, 16);
1368         if (clk != 0)
1369                 pwr_i2c_clk = clk;
1370         return 0;
1371 }
1372
1373 int get_pwr_i2c_clk_rate(void)
1374 {
1375         return pwr_i2c_clk;
1376 }
1377 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1378
1379 static bool pmic_wdt_disable;
1380 bool is_pmic_wdt_disabled_at_boot(void)
1381 {
1382         return pmic_wdt_disable;
1383 }
1384
1385 static int parse_arg_pmic_wdt_disable(char *options)
1386 {
1387         /* no kernel command line argument "watchdog" interpreted as
1388          * watchdog enable
1389          */
1390         pmic_wdt_disable = false;
1391         if (!(strcmp(options, "enable")))
1392                 pmic_wdt_disable = false;
1393         else if (!(strcmp(options, "disable")))
1394                 pmic_wdt_disable = true;
1395         /* kernel command line from fastboot does not support
1396          * other values
1397          */
1398
1399         return 0;
1400 }
1401 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1402
1403 void tegra_get_board_info(struct board_info *bi)
1404 {
1405 #ifdef CONFIG_OF
1406         struct device_node *board_info;
1407         u32 prop_val;
1408         int err;
1409
1410         board_info = of_find_node_by_path("/chosen/board_info");
1411         if (!IS_ERR_OR_NULL(board_info)) {
1412                 memset(bi, 0, sizeof(*bi));
1413
1414                 err = of_property_read_u32(board_info, "id", &prop_val);
1415                 if (err)
1416                         pr_err("failed to read /chosen/board_info/id\n");
1417                 else
1418                         bi->board_id = prop_val;
1419
1420                 err = of_property_read_u32(board_info, "sku", &prop_val);
1421                 if (err)
1422                         pr_err("failed to read /chosen/board_info/sku\n");
1423                 else
1424                         bi->sku = prop_val;
1425
1426                 err = of_property_read_u32(board_info, "fab", &prop_val);
1427                 if (err)
1428                         pr_err("failed to read /chosen/board_info/fab\n");
1429                 else
1430                         bi->fab = prop_val;
1431
1432                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1433                 if (err)
1434                         pr_err("failed to read /chosen/board_info/major_revision\n");
1435                 else
1436                         bi->major_revision = prop_val;
1437
1438                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1439                 if (err)
1440                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1441                 else
1442                         bi->minor_revision = prop_val;
1443 #ifndef CONFIG_ARM64
1444                 system_serial_high = (bi->board_id << 16) | bi->sku;
1445                 system_serial_low = (bi->fab << 24) |
1446                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1447 #endif
1448         } else {
1449 #endif
1450 #ifdef CONFIG_ARM64
1451                 /* FIXME:
1452                  * use dummy values for now as system_serial_high/low
1453                  * are gone in arm64.
1454                  */
1455                 bi->board_id = 0xDEAD;
1456                 bi->sku = 0xDEAD;
1457                 bi->fab = 0xDD;
1458                 bi->major_revision = 0xDD;
1459                 bi->minor_revision = 0xDD;
1460 #else
1461                 if (system_serial_high || system_serial_low) {
1462                         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1463                         bi->sku = (system_serial_high) & 0xFFFF;
1464                         bi->fab = (system_serial_low >> 24) & 0xFF;
1465                         bi->major_revision = (system_serial_low >> 16) & 0xFF;
1466                         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1467                 } else {
1468                         memcpy(bi, &main_board_info, sizeof(struct board_info));
1469                 }
1470 #endif
1471 #ifdef CONFIG_OF
1472         }
1473 #endif
1474 }
1475
1476 static int __init tegra_main_board_info(char *info)
1477 {
1478         char *p = info;
1479         main_board_info.board_id = memparse(p, &p);
1480         main_board_info.sku = memparse(p+1, &p);
1481         main_board_info.fab = memparse(p+1, &p);
1482         main_board_info.major_revision = memparse(p+1, &p);
1483         main_board_info.minor_revision = memparse(p+1, &p);
1484         return 1;
1485 }
1486
1487 __setup("board_info=", tegra_main_board_info);
1488
1489 static int __init tegra_pmu_board_info(char *info)
1490 {
1491         char *p = info;
1492         pmu_board_info.board_id = memparse(p, &p);
1493         pmu_board_info.sku = memparse(p+1, &p);
1494         pmu_board_info.fab = memparse(p+1, &p);
1495         pmu_board_info.major_revision = memparse(p+1, &p);
1496         pmu_board_info.minor_revision = memparse(p+1, &p);
1497         return 0;
1498 }
1499
1500 void tegra_get_pmu_board_info(struct board_info *bi)
1501 {
1502         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1503 }
1504
1505 early_param("pmuboard", tegra_pmu_board_info);
1506
1507 static int __init tegra_display_board_info(char *info)
1508 {
1509         char *p = info;
1510         display_board_info.board_id = memparse(p, &p);
1511         display_board_info.sku = memparse(p+1, &p);
1512         display_board_info.fab = memparse(p+1, &p);
1513         display_board_info.major_revision = memparse(p+1, &p);
1514         display_board_info.minor_revision = memparse(p+1, &p);
1515         return 1;
1516 }
1517
1518 void tegra_get_display_board_info(struct board_info *bi)
1519 {
1520         memcpy(bi, &display_board_info, sizeof(struct board_info));
1521 }
1522
1523 __setup("displayboard=", tegra_display_board_info);
1524
1525 static int __init tegra_camera_board_info(char *info)
1526 {
1527         char *p = info;
1528         camera_board_info.board_id = memparse(p, &p);
1529         camera_board_info.sku = memparse(p+1, &p);
1530         camera_board_info.fab = memparse(p+1, &p);
1531         camera_board_info.major_revision = memparse(p+1, &p);
1532         camera_board_info.minor_revision = memparse(p+1, &p);
1533         return 1;
1534 }
1535
1536 void tegra_get_camera_board_info(struct board_info *bi)
1537 {
1538         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1539 }
1540
1541 __setup("cameraboard=", tegra_camera_board_info);
1542
1543 static int __init tegra_leftspeaker_board_info(char *info)
1544 {
1545         char *p = info;
1546         leftspeaker_board_info.board_id = memparse(p, &p);
1547         leftspeaker_board_info.sku = memparse(p+1, &p);
1548         leftspeaker_board_info.fab = memparse(p+1, &p);
1549         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1550         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1551         return 1;
1552 }
1553
1554 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1555 {
1556         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1557 }
1558
1559 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1560
1561 static int __init tegra_rightspeaker_board_info(char *info)
1562 {
1563         char *p = info;
1564         rightspeaker_board_info.board_id = memparse(p, &p);
1565         rightspeaker_board_info.sku = memparse(p+1, &p);
1566         rightspeaker_board_info.fab = memparse(p+1, &p);
1567         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1568         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1569         return 1;
1570 }
1571
1572 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1573 {
1574         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1575 }
1576
1577 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1578
1579 static int __init tegra_joystick_board_info(char *info)
1580 {
1581         char *p = info;
1582         joystick_board_info.board_id = memparse(p, &p);
1583         joystick_board_info.sku = memparse(p+1, &p);
1584         joystick_board_info.fab = memparse(p+1, &p);
1585         joystick_board_info.major_revision = memparse(p+1, &p);
1586         joystick_board_info.minor_revision = memparse(p+1, &p);
1587         return 1;
1588 }
1589
1590 void tegra_get_joystick_board_info(struct board_info *bi)
1591 {
1592         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1593 }
1594
1595 __setup("joystickboard=", tegra_joystick_board_info);
1596
1597 static int __init tegra_button_board_info(char *info)
1598 {
1599         char *p = info;
1600         button_board_info.board_id = memparse(p, &p);
1601         button_board_info.sku = memparse(p+1, &p);
1602         button_board_info.fab = memparse(p+1, &p);
1603         button_board_info.major_revision = memparse(p+1, &p);
1604         button_board_info.minor_revision = memparse(p+1, &p);
1605         return 1;
1606 }
1607
1608 void tegra_get_button_board_info(struct board_info *bi)
1609 {
1610         memcpy(bi, &button_board_info, sizeof(struct board_info));
1611 }
1612
1613 __setup("buttonboard=", tegra_button_board_info);
1614
1615 static int __init tegra_io_board_info(char *info)
1616 {
1617         char *p = info;
1618         io_board_info.board_id = memparse(p, &p);
1619         io_board_info.sku = memparse(p+1, &p);
1620         io_board_info.fab = memparse(p+1, &p);
1621         io_board_info.major_revision = memparse(p+1, &p);
1622         io_board_info.minor_revision = memparse(p+1, &p);
1623         return 1;
1624 }
1625
1626 void tegra_get_io_board_info(struct board_info *bi)
1627 {
1628         memcpy(bi, &io_board_info, sizeof(struct board_info));
1629 }
1630
1631 __setup("ioboard=", tegra_io_board_info);
1632
1633 static int __init tegra_modem_id(char *id)
1634 {
1635         char *p = id;
1636
1637         modem_id = memparse(p, &p);
1638         return 1;
1639 }
1640
1641 int tegra_get_modem_id(void)
1642 {
1643         return modem_id;
1644 }
1645
1646 __setup("modem_id=", tegra_modem_id);
1647
1648 static int __init tegra_usb_port_owner_info(char *id)
1649 {
1650         char *p = id;
1651
1652         usb_port_owner_info = memparse(p, &p);
1653         return 1;
1654 }
1655
1656 int tegra_get_usb_port_owner_info(void)
1657 {
1658         return usb_port_owner_info;
1659 }
1660
1661 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1662
1663 static int __init tegra_lane_owner_info(char *id)
1664 {
1665         char *p = id;
1666
1667         lane_owner_info = memparse(p, &p);
1668         return 1;
1669 }
1670
1671 int tegra_get_lane_owner_info(void)
1672 {
1673         return lane_owner_info;
1674 }
1675
1676 __setup("lane_owner_info=", tegra_lane_owner_info);
1677
1678 static int __init tegra_commchip_id(char *id)
1679 {
1680         char *p = id;
1681
1682         if (get_option(&p, &commchip_id) != 1)
1683                 return 0;
1684         return 1;
1685 }
1686
1687 int tegra_get_commchip_id(void)
1688 {
1689         return commchip_id;
1690 }
1691
1692 __setup("commchip_id=", tegra_commchip_id);
1693
1694 /*
1695  * Tegra has a protected aperture that prevents access by most non-CPU
1696  * memory masters to addresses above the aperture value.  Enabling it
1697  * secures the CPU's memory from the GPU, except through the GART.
1698  */
1699 void __init tegra_protected_aperture_init(unsigned long aperture)
1700 {
1701         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1702         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1703         writel(aperture, mc_base + MC_SECURITY_CFG2);
1704 }
1705
1706 /*
1707  * Due to conflicting restrictions on the placement of the framebuffer,
1708  * the bootloader is likely to leave the framebuffer pointed at a location
1709  * in memory that is outside the grhost aperture.  This function will move
1710  * the framebuffer contents from a physical address that is anywhere (lowmem,
1711  * highmem, or outside the memory map) to a physical address that is outside
1712  * the memory map.
1713  */
1714 void __tegra_move_framebuffer(struct platform_device *pdev,
1715         phys_addr_t to, phys_addr_t from,
1716         size_t size)
1717 {
1718         struct page *page;
1719         void __iomem *to_io;
1720         void *from_virt;
1721         unsigned long i;
1722         phys_addr_t addr[] = { to, from, };
1723
1724         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1725         BUG_ON(PAGE_ALIGN(from) != from);
1726         BUG_ON(PAGE_ALIGN(size) != size);
1727
1728         to_io = ioremap(to, size);
1729         if (!to_io) {
1730                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1731                 return;
1732         }
1733
1734         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1735                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1736                         page = phys_to_page(from + i);
1737                         from_virt = kmap(page);
1738                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1739                         kunmap(page);
1740                 }
1741         } else if (from) {
1742                 void __iomem *from_io = ioremap(from, size);
1743                 if (!from_io) {
1744                         pr_err("%s: Failed to map source framebuffer\n",
1745                                 __func__);
1746                         goto out;
1747                 }
1748
1749                 for (i = 0; i < size; i += 4)
1750                         writel(readl(from_io + i), to_io + i);
1751
1752                 iounmap(from_io);
1753         }
1754
1755         if (!pdev)
1756                 goto out;
1757
1758 #ifdef CONFIG_ARM64
1759         BUG(); /* ARM64 doesn't support dma_map_linear yet!!! */
1760 #else
1761         for (i = 0; i < ARRAY_SIZE(addr); i++)
1762                 dma_map_linear(&pdev->dev, addr[i], size, DMA_TO_DEVICE);
1763 #endif
1764 out:
1765         iounmap(to_io);
1766 }
1767
1768 void __tegra_clear_framebuffer(struct platform_device *pdev,
1769                                unsigned long to, unsigned long size)
1770 {
1771         void __iomem *to_io;
1772         unsigned long i;
1773
1774         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1775         BUG_ON(PAGE_ALIGN(size) != size);
1776
1777         to_io = ioremap(to, size);
1778         if (!to_io) {
1779                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1780                 return;
1781         }
1782
1783         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1784                 for (i = 0 ; i < size; i += PAGE_SIZE)
1785                         memset(to_io + i, 0, PAGE_SIZE);
1786         } else {
1787                 for (i = 0; i < size; i += 4)
1788                         writel(0, to_io + i);
1789         }
1790
1791         if (!pdev)
1792                 goto out;
1793
1794 #ifndef CONFIG_ARM64 /* FIXME */
1795         dma_map_linear(&pdev->dev, to, size, DMA_TO_DEVICE);
1796 #endif
1797 out:
1798         iounmap(to_io);
1799 }
1800
1801 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1802         unsigned long fb2_size)
1803 {
1804         const size_t avp_kernel_reserve = SZ_32M;
1805         int i = 0;
1806 #if !defined(CONFIG_TEGRA_AVP_KERNEL_ON_MMU) /* Tegra2 with AVP MMU */ && \
1807         !defined(CONFIG_TEGRA_AVP_KERNEL_ON_SMMU) /* Tegra3 & up with SMMU */
1808         /* Reserve hardcoded AVP kernel load area starting at 0xXe000000*/
1809         tegra_avp_kernel_size = SECTION_SIZE;
1810
1811         /*
1812          * Choose a DRAM region in which to allocate the AVP kernel, using the
1813          * following guidelines:
1814          *     - Choose a DRAM region which exists below the 4 GB physical
1815          *       address limit. This is necessary because AVP is a 32 bit
1816          *       processor and it cannot access physical addresses above 4 GB.
1817          *     - Out of the applicable DRAM regions (i.e. those which exist
1818          *       below 4 GB), choose the region with the highest starting
1819          *       physical address.
1820          */
1821         for (i = memblock.memory.cnt - 1; i >= 0; i--) {
1822                 if ((u64)(memblock.memory.regions[i].base) +
1823                         (u64)(memblock.memory.regions[i].size) <
1824                         (u64)(SZ_2G)*(u64)(2)) {
1825                         tegra_avp_kernel_start =
1826                                 memblock.memory.regions[i].base +
1827                                 memblock.memory.regions[i].size -
1828                                 avp_kernel_reserve;
1829                         break;
1830                 }
1831         }
1832         /*
1833          * If tegra_avp_kernel_start is still 0, that means we didn't find any
1834          * DRAM region below the 4 GB physical address limit. This is a problem
1835          * because the AVP kernel must reside below 4 GB.
1836          */
1837         BUG_ON(tegra_avp_kernel_start == 0);
1838
1839         if (memblock_remove(tegra_avp_kernel_start, avp_kernel_reserve)) {
1840                 pr_err("Failed to remove AVP kernel load area %08lx@%08llx "
1841                                 "from memory map\n",
1842                         (unsigned long)avp_kernel_reserve,
1843                         (u64)tegra_avp_kernel_start);
1844                 tegra_avp_kernel_size = 0;
1845         }
1846 #endif
1847
1848         if (carveout_size) {
1849                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
1850                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1851                         pr_err("Failed to remove carveout %08lx@%08llx "
1852                                 "from memory map\n",
1853                                 carveout_size, (u64)tegra_carveout_start);
1854                         tegra_carveout_start = 0;
1855                         tegra_carveout_size = 0;
1856                 } else
1857                         tegra_carveout_size = carveout_size;
1858         }
1859
1860         if (fb2_size) {
1861                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
1862                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1863                         pr_err("Failed to remove second framebuffer "
1864                                 "%08lx@%08llx from memory map\n",
1865                                 fb2_size, (u64)tegra_fb2_start);
1866                         tegra_fb2_start = 0;
1867                         tegra_fb2_size = 0;
1868                 } else
1869                         tegra_fb2_size = fb2_size;
1870         }
1871
1872         if (fb_size) {
1873                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
1874                 if (memblock_remove(tegra_fb_start, fb_size)) {
1875                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1876                                 "from memory map\n",
1877                                 fb_size, (u64)tegra_fb_start);
1878                         tegra_fb_start = 0;
1879                         tegra_fb_size = 0;
1880                 } else
1881                         tegra_fb_size = fb_size;
1882         }
1883
1884         if (tegra_cpu_is_asim()) {
1885                 if (tegra_split_mem_active()) {
1886                         tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1887                         tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1888
1889                         if (tegra_vpr_size == 0) {
1890                                 tegra_carveout_start =
1891                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1892                                 tegra_carveout_size =
1893                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1894                         } else if (
1895                                     (tegra_vpr_start <
1896                                      TEGRA_ASIM_QT_FB_START +
1897                                      TEGRA_ASIM_QT_FB_SIZE) ||
1898                                      (tegra_vpr_start + tegra_vpr_size - 1 >
1899                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1900                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1901                                 /*
1902                                  * On ASIM/ASIM + QT with
1903                                  * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
1904                                  * the VPR region needs to be within the front
1905                                  * door memory region. Moreover, the VPR region
1906                                  * can't exist where the framebuffer resides.
1907                                  */
1908                                 BUG();
1909                         } else if (
1910                                         (tegra_vpr_start -
1911                                          (TEGRA_ASIM_QT_FB_START +
1912                                           TEGRA_ASIM_QT_FB_SIZE) <
1913                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1914                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1915                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1916                                          (tegra_vpr_start + tegra_vpr_size) <
1917                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1918                                 /*
1919                                  * The tegra ASIM/QT carveout has a min size:-
1920                                  * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
1921                                  * regions in front door mem are smaller than
1922                                  * the min carveout size. Therefore, we can't
1923                                  * fit the carveout in front door mem.
1924                                  */
1925                                 BUG();
1926                         } else if (
1927                                         (tegra_vpr_start -
1928                                          (TEGRA_ASIM_QT_FB_START +
1929                                           TEGRA_ASIM_QT_FB_SIZE)) >=
1930                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1931                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1932                                          (tegra_vpr_start + tegra_vpr_size))) {
1933                                 /*
1934                                  * Place the tegra ASIM/QT carveout between the
1935                                  * framebuffer and VPR.
1936                                  */
1937                                 tegra_carveout_start =
1938                                   TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1939                                 tegra_carveout_size = tegra_vpr_start -
1940                                         (TEGRA_ASIM_QT_FB_START +
1941                                          TEGRA_ASIM_QT_FB_SIZE);
1942                         } else {
1943                                 /*
1944                                  * Place the tegra ASIM/QT carveout after VPR.
1945                                  */
1946                                 tegra_carveout_start = tegra_vpr_start +
1947                                                          tegra_vpr_size;
1948                                 tegra_carveout_size =
1949                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1950                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1951                                         (tegra_vpr_start + tegra_vpr_size);
1952                         }
1953                 } else if (tegra_vpr_size != 0) {
1954                         /*
1955                          * VPR cannot work on ASIM/ASIM + QT if split mem is not
1956                          * enabled.
1957                          */
1958                         BUG();
1959                 }
1960         }
1961
1962         if (tegra_fb_size)
1963                 tegra_grhost_aperture = tegra_fb_start;
1964
1965         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
1966                 tegra_grhost_aperture = tegra_fb2_start;
1967
1968         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
1969                 tegra_grhost_aperture = tegra_carveout_start;
1970
1971         if (tegra_lp0_vec_size &&
1972            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
1973                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
1974                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
1975                                 (u64)tegra_lp0_vec_size,
1976                                 (u64)tegra_lp0_vec_start);
1977                         tegra_lp0_vec_start = 0;
1978                         tegra_lp0_vec_size = 0;
1979                 }
1980                 tegra_lp0_vec_relocate = false;
1981         } else
1982                 tegra_lp0_vec_relocate = true;
1983
1984 #ifdef CONFIG_TEGRA_NVDUMPER
1985         if (nvdumper_reserved) {
1986                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
1987                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
1988                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
1989                         nvdumper_reserved = 0;
1990                 }
1991         }
1992 #endif
1993
1994 #ifdef CONFIG_TEGRA_USE_NCT
1995         if (tegra_nck_size &&
1996            (tegra_nck_start < memblock_end_of_DRAM())) {
1997                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
1998                         pr_err("Failed to reserve nck %08lx@%08lx\n",
1999                                 tegra_nck_size, tegra_nck_start);
2000                         tegra_nck_start = 0;
2001                         tegra_nck_size = 0;
2002                 }
2003         }
2004 #endif
2005
2006         /*
2007          * We copy the bootloader's framebuffer to the framebuffer allocated
2008          * above, and then free this one.
2009          * */
2010         if (tegra_bootloader_fb_size) {
2011                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
2012                 if (memblock_reserve(tegra_bootloader_fb_start,
2013                                 tegra_bootloader_fb_size)) {
2014                         pr_err("Failed to reserve bootloader frame buffer "
2015                                 "%08llx@%08llx\n",
2016                                 (u64)tegra_bootloader_fb_size,
2017                                 (u64)tegra_bootloader_fb_start);
2018                         tegra_bootloader_fb_start = 0;
2019                         tegra_bootloader_fb_size = 0;
2020                 }
2021         }
2022
2023         if (tegra_bootloader_fb2_size) {
2024                 tegra_bootloader_fb2_size =
2025                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
2026                 if (memblock_reserve(tegra_bootloader_fb2_start,
2027                                 tegra_bootloader_fb2_size)) {
2028                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
2029                                 (u64)tegra_bootloader_fb2_size,
2030                                 (u64)tegra_bootloader_fb2_start);
2031                         tegra_bootloader_fb2_start = 0;
2032                         tegra_bootloader_fb2_size = 0;
2033                 }
2034         }
2035
2036         pr_info("Tegra reserved memory:\n"
2037                 "LP0:                    %08llx - %08llx\n"
2038                 "Bootloader framebuffer: %08llx - %08llx\n"
2039                 "Bootloader framebuffer2: %08llx - %08llx\n"
2040                 "Framebuffer:            %08llx - %08llx\n"
2041                 "2nd Framebuffer:        %08llx - %08llx\n"
2042                 "Carveout:               %08llx - %08llx\n"
2043                 "Vpr:                    %08llx - %08llx\n"
2044                 "Tsec:                   %08llx - %08llx\n",
2045                 (u64)tegra_lp0_vec_start,
2046                 (u64)(tegra_lp0_vec_size ?
2047                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
2048                 (u64)tegra_bootloader_fb_start,
2049                 (u64)(tegra_bootloader_fb_size ?
2050                         tegra_bootloader_fb_start +
2051                         tegra_bootloader_fb_size - 1 : 0),
2052                 (u64)tegra_bootloader_fb2_start,
2053                 (u64)(tegra_bootloader_fb2_size ?
2054                         tegra_bootloader_fb2_start +
2055                         tegra_bootloader_fb2_size - 1 : 0),
2056                 (u64)tegra_fb_start,
2057                 (u64)(tegra_fb_size ?
2058                         tegra_fb_start + tegra_fb_size - 1 : 0),
2059                 (u64)tegra_fb2_start,
2060                 (u64)(tegra_fb2_size ?
2061                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
2062                 (u64)tegra_carveout_start,
2063                 (u64)(tegra_carveout_size ?
2064                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
2065                 (u64)tegra_vpr_start,
2066                 (u64)(tegra_vpr_size ?
2067                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
2068                 (u64)tegra_tsec_start,
2069                 (u64)(tegra_tsec_size ?
2070                         tegra_tsec_start + tegra_tsec_size - 1 : 0));
2071
2072         if (tegra_avp_kernel_size) {
2073                 /* Return excessive memory reserved for AVP kernel */
2074                 if (tegra_avp_kernel_size < avp_kernel_reserve)
2075                         memblock_add(
2076                                 tegra_avp_kernel_start + tegra_avp_kernel_size,
2077                                 avp_kernel_reserve - tegra_avp_kernel_size);
2078                 /* The AVP kernel should be loaded below the 4 GB physical
2079                    address limit. */
2080                 BUG_ON((u64)(tegra_avp_kernel_start) +
2081                         (u64)(tegra_avp_kernel_size) - (u64)(1) >=
2082                         (u64)(SZ_2G)*(u64)(2));
2083                 pr_info(
2084                 "AVP kernel: %08llx - %08llx\n",
2085                         (u64)tegra_avp_kernel_start,
2086                         (u64)(tegra_avp_kernel_start +
2087                                 tegra_avp_kernel_size - 1));
2088         }
2089
2090 #ifdef CONFIG_TEGRA_NVDUMPER
2091         if (nvdumper_reserved) {
2092                 pr_info("Nvdumper:               %08lx - %08lx\n",
2093                         nvdumper_reserved,
2094                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2095         }
2096 #endif
2097
2098 #ifdef CONFIG_TEGRA_USE_SECURE_KERNEL
2099         pr_info("Tzram:               %08lx - %08lx\n",
2100                 tegra_tzram_start,
2101                 tegra_tzram_size ?
2102                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
2103 #endif
2104
2105 #ifdef CONFIG_TEGRA_USE_NCT
2106         if (tegra_nck_size) {
2107                 pr_info("Nck:                    %08lx - %08lx\n",
2108                         tegra_nck_start,
2109                         tegra_nck_size ?
2110                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2111         }
2112 #endif
2113 }
2114
2115 #ifdef CONFIG_PSTORE_RAM
2116 static struct persistent_ram_descriptor desc = {
2117         .name = "ramoops",
2118 };
2119
2120 static struct persistent_ram ram = {
2121         .descs = &desc,
2122         .num_descs = 1,
2123 };
2124
2125 void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
2126 {
2127         int ret;
2128
2129         ram.start = memblock_end_of_DRAM() - ram_console_size;
2130         ram.size = ram_console_size;
2131         ram.descs->size = ram_console_size;
2132
2133         INIT_LIST_HEAD(&ram.node);
2134
2135         ret = persistent_ram_early_init(&ram);
2136         if (ret)
2137                 goto fail;
2138
2139         return;
2140
2141 fail:
2142         pr_err("Failed to reserve memory block for ram console\n");
2143 }
2144 #endif
2145
2146 int __init tegra_register_fuse(void)
2147 {
2148         return platform_device_register(&tegra_fuse_device);
2149 }
2150
2151 void __init tegra_release_bootloader_fb(void)
2152 {
2153         /* Since bootloader fb is reserved in common.c, it is freed here. */
2154         if (tegra_bootloader_fb_size) {
2155                 if (memblock_free(tegra_bootloader_fb_start,
2156                                                 tegra_bootloader_fb_size))
2157                         pr_err("Failed to free bootloader fb.\n");
2158                 else
2159                         free_bootmem_late(tegra_bootloader_fb_start,
2160                                                 tegra_bootloader_fb_size);
2161         }
2162         if (tegra_bootloader_fb2_size) {
2163                 if (memblock_free(tegra_bootloader_fb2_start,
2164                                                 tegra_bootloader_fb2_size))
2165                         pr_err("Failed to free bootloader fb2.\n");
2166                 else
2167                         free_bootmem_late(tegra_bootloader_fb2_start,
2168                                                 tegra_bootloader_fb2_size);
2169         }
2170 }
2171
2172 static struct platform_device *pinmux_devices[] = {
2173         &tegra_gpio_device,
2174         &tegra_pinmux_device,
2175 };
2176
2177 void tegra_enable_pinmux(void)
2178 {
2179         platform_add_devices(pinmux_devices, ARRAY_SIZE(pinmux_devices));
2180 }
2181
2182 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2183         [TEGRA_REVISION_UNKNOWN] = "unknown",
2184         [TEGRA_REVISION_A01]     = "A01",
2185         [TEGRA_REVISION_A02]     = "A02",
2186         [TEGRA_REVISION_A03]     = "A03",
2187         [TEGRA_REVISION_A03p]    = "A03 prime",
2188         [TEGRA_REVISION_A04]     = "A04",
2189         [TEGRA_REVISION_A04p]    = "A04 prime",
2190 };
2191
2192 static const char * __init tegra_get_revision(void)
2193 {
2194         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2195 }
2196
2197 static const char * __init tegra_get_family(void)
2198 {
2199         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2200         u32 cid = readl(chip_id);
2201         cid = (cid >> 8) & 0xFF;
2202
2203         switch (cid) {
2204         case TEGRA_CHIPID_TEGRA2:
2205                 cid = 2;
2206                 break;
2207         case TEGRA_CHIPID_TEGRA3:
2208                 cid = 3;
2209                 break;
2210         case TEGRA_CHIPID_TEGRA11:
2211                 cid = 11;
2212                 break;
2213         case TEGRA_CHIPID_TEGRA12:
2214                 cid = 12;
2215                 break;
2216         case TEGRA_CHIPID_TEGRA14:
2217                 cid = 14;
2218                 break;
2219
2220         case TEGRA_CHIPID_UNKNOWN:
2221         default:
2222                 cid = 0;
2223         }
2224         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2225 }
2226
2227 static const char * __init tegra_get_soc_id(void)
2228 {
2229         int package_id = tegra_package_id();
2230         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2231                 tegra_revision_name[tegra_revision], tegra_sku_id, package_id);
2232 }
2233
2234 static void __init tegra_soc_info_populate(struct soc_device_attribute
2235         *soc_dev_attr, const char *machine)
2236 {
2237         soc_dev_attr->soc_id = tegra_get_soc_id();
2238         soc_dev_attr->machine  = machine;
2239         soc_dev_attr->family   = tegra_get_family();
2240         soc_dev_attr->revision = tegra_get_revision();
2241 }
2242
2243 int __init tegra_soc_device_init(const char *machine)
2244 {
2245         struct soc_device *soc_dev;
2246         struct soc_device_attribute *soc_dev_attr;
2247
2248         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2249         if (!soc_dev_attr)
2250                 return -ENOMEM;
2251
2252         tegra_soc_info_populate(soc_dev_attr, machine);
2253
2254         soc_dev = soc_device_register(soc_dev_attr);
2255         if (IS_ERR_OR_NULL(soc_dev)) {
2256                 kfree(soc_dev_attr);
2257                 return -1;
2258         }
2259
2260         return 0;
2261 }
2262
2263 void __init tegra_init_late(void)
2264 {
2265 #ifndef CONFIG_COMMON_CLK
2266         tegra_clk_debugfs_init();
2267 #endif
2268         tegra_powergate_debugfs_init();
2269 }
2270
2271 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2272 #define ASIM_SHUTDOWN_REG       0x538f0ffc
2273
2274 static void asim_power_off(void)
2275 {
2276         pr_err("ASIM Powering off the device\n");
2277         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
2278         while (1)
2279                 ;
2280 }
2281
2282 static int __init asim_power_off_init(void)
2283 {
2284         if (tegra_cpu_is_asim())
2285                 pm_power_off = asim_power_off;
2286         return 0;
2287 }
2288
2289 arch_initcall(asim_power_off_init);
2290
2291 #if defined(CONFIG_SMC91X)
2292 static struct resource tegra_asim_smc91x_resources[] = {
2293         [0] = {
2294                 .start          = TEGRA_SIM_ETH_BASE,
2295                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
2296                 .flags          = IORESOURCE_MEM,
2297         },
2298         [1] = {
2299                 .start          = IRQ_ETH,
2300                 .end            = IRQ_ETH,
2301                 .flags          = IORESOURCE_IRQ,
2302         },
2303 };
2304
2305 static struct platform_device tegra_asim_smc91x_device = {
2306         .name           = "smc91x",
2307         .id             = 0,
2308         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
2309         .resource       = tegra_asim_smc91x_resources,
2310 };
2311
2312 static int __init asim_enet_smc91x_init(void)
2313 {
2314         if (tegra_cpu_is_asim() && !tegra_cpu_is_dsim())
2315                 platform_device_register(&tegra_asim_smc91x_device);
2316         return 0;
2317 }
2318
2319 rootfs_initcall(asim_enet_smc91x_init);
2320 #endif
2321 #endif
2322
2323 #if defined(CONFIG_SMSC911X)
2324 static struct resource tegra_smsc911x_resources[] = {
2325         [0] = {
2326                 .start          = 0x4E000000,
2327                 .end            = 0x4E000000 + SZ_64K - 1,
2328                 .flags          = IORESOURCE_MEM,
2329         },
2330         [1] = {
2331                 .start          = IRQ_ETH,
2332                 .end            = IRQ_ETH,
2333                 .flags          = IORESOURCE_IRQ,
2334         },
2335 };
2336
2337 static struct smsc911x_platform_config tegra_smsc911x_config = {
2338         .flags          = SMSC911X_USE_32BIT,
2339         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
2340         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
2341         .phy_interface  = PHY_INTERFACE_MODE_MII,
2342 };
2343
2344 static struct platform_device tegra_smsc911x_device = {
2345         .name              = "smsc911x",
2346         .id                = 0,
2347         .resource          = tegra_smsc911x_resources,
2348         .num_resources     = ARRAY_SIZE(tegra_smsc911x_resources),
2349         .dev.platform_data = &tegra_smsc911x_config,
2350 };
2351
2352 static int __init enet_smsc911x_init(void)
2353 {
2354         if (!tegra_cpu_is_dsim())
2355                 platform_device_register(&tegra_smsc911x_device);
2356         return 0;
2357 }
2358
2359 rootfs_initcall(enet_smsc911x_init);
2360 #endif
2361
2362 int tegra_split_mem_active(void)
2363 {
2364         return tegra_split_mem_set;
2365 }
2366
2367 static int __init set_tegra_split_mem(char *options)
2368 {
2369         tegra_split_mem_set = 1;
2370         return 0;
2371 }
2372 early_param("tegra_split_mem", set_tegra_split_mem);