arm: tegra: remove memory for ramoops in correct order
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Copyright (C) 2010-2014 NVIDIA Corporation. All rights reserved.
6  *
7  * Author:
8  *      Colin Cross <ccross@android.com>
9  *
10  * This software is licensed under the terms of the GNU General Public
11  * License version 2, as published by the Free Software Foundation, and
12  * may be copied, distributed, and modified under those terms.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  */
20
21 #include <linux/platform_device.h>
22 #include <linux/console.h>
23 #include <linux/init.h>
24 #include <linux/io.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/clk/tegra.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_fdt.h>
35 #include <linux/pstore_ram.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/sys_soc.h>
38 #include <linux/tegra-pmc.h>
39 #if defined(CONFIG_SMSC911X)
40 #include <linux/smsc911x.h>
41 #endif
42 #include <linux/pm.h>
43 #include <linux/tegra-powergate.h>
44
45 #include <linux/export.h>
46 #include <linux/bootmem.h>
47 #include <linux/tegra-soc.h>
48 #include <linux/dma-contiguous.h>
49 #include <linux/tegra-fuse.h>
50 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
51 #include <linux/ote_protocol.h>
52 #endif
53 #include <linux/gk20a.h>
54
55 #ifdef CONFIG_ARM64
56 #include <linux/irqchip/arm-gic.h>
57 #include <asm/system_info.h>
58 #else
59 #include <asm/system.h>
60 #include <asm/hardware/cache-l2x0.h>
61 #endif
62 #include <asm/dma-mapping.h>
63
64 #include <mach/tegra_smmu.h>
65 #include <mach/nct.h>
66 #include <mach/dc.h>
67
68 #include "apbio.h"
69 #include "board.h"
70 #include "clock.h"
71 #include "common.h"
72 #include "dvfs.h"
73 #include "iomap.h"
74 #include "pm.h"
75 #include "sleep.h"
76 #include "reset.h"
77 #include "devices.h"
78
79 #define MC_SECURITY_CFG2        0x7c
80
81 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
82 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
83 #define   PRIORITY_SELECT_USB   BIT(6)
84 #define   PRIORITY_SELECT_USB2  BIT(18)
85 #define   PRIORITY_SELECT_USB3  BIT(17)
86 #define   PRIORITY_SELECT_SE BIT(14)
87
88 #define AHB_GIZMO_AHB_MEM               0xc
89 #define   ENB_FAST_REARBITRATE  BIT(2)
90 #define   DONT_SPLIT_AHB_WR     BIT(7)
91 #define   WR_WAIT_COMMIT_ON_1K  BIT(8)
92 #define   EN_USB_WAIT_COMMIT_ON_1K_STALL        BIT(9)
93
94 #define   RECOVERY_MODE BIT(31)
95 #define   BOOTLOADER_MODE       BIT(30)
96 #define   FORCED_RECOVERY_MODE  BIT(1)
97
98 #define AHB_GIZMO_USB           0x1c
99 #define AHB_GIZMO_USB2          0x78
100 #define AHB_GIZMO_USB3          0x7c
101 #define AHB_GIZMO_SE            0x4c
102 #define   IMMEDIATE     BIT(18)
103
104 #define AHB_MEM_PREFETCH_CFG5   0xc8
105 #define AHB_MEM_PREFETCH_CFG3   0xe0
106 #define AHB_MEM_PREFETCH_CFG4   0xe4
107 #define AHB_MEM_PREFETCH_CFG1   0xec
108 #define AHB_MEM_PREFETCH_CFG2   0xf0
109 #define AHB_MEM_PREFETCH_CFG6   0xcc
110 #define   PREFETCH_ENB  BIT(31)
111 #define   MST_ID(x)     (((x) & 0x1f) << 26)
112 #define   AHBDMA_MST_ID MST_ID(5)
113 #define   USB_MST_ID    MST_ID(6)
114 #define SDMMC4_MST_ID   MST_ID(12)
115 #define   USB2_MST_ID   MST_ID(18)
116 #define   USB3_MST_ID   MST_ID(17)
117 #define   SE_MST_ID     MST_ID(14)
118 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
119 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
120
121 #ifdef CONFIG_PSTORE_RAM
122 #define RAMOOPS_MEM_SIZE SZ_2M
123 #define FTRACE_MEM_SIZE SZ_1M
124 #endif
125
126 phys_addr_t tegra_bootloader_fb_start;
127 phys_addr_t tegra_bootloader_fb_size;
128 phys_addr_t tegra_bootloader_fb2_start;
129 phys_addr_t tegra_bootloader_fb2_size;
130 phys_addr_t tegra_fb_start;
131 phys_addr_t tegra_fb_size;
132 phys_addr_t tegra_fb2_start;
133 phys_addr_t tegra_fb2_size;
134 phys_addr_t tegra_carveout_start;
135 phys_addr_t tegra_carveout_size;
136 phys_addr_t tegra_vpr_start;
137 phys_addr_t tegra_vpr_size;
138 phys_addr_t tegra_tsec_start;
139 phys_addr_t tegra_tsec_size;
140 phys_addr_t tegra_lp0_vec_start;
141 phys_addr_t tegra_lp0_vec_size;
142 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
143 phys_addr_t tegra_wb0_params_address;
144 phys_addr_t tegra_wb0_params_instances;
145 phys_addr_t tegra_wb0_params_block_size;
146 #endif
147
148 #ifdef CONFIG_TEGRA_NVDUMPER
149 unsigned long nvdumper_reserved;
150 #endif
151 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
152 unsigned long tegra_tzram_start;
153 unsigned long tegra_tzram_size;
154 #endif
155 bool tegra_lp0_vec_relocate;
156 unsigned long tegra_grhost_aperture = ~0ul;
157 static   bool is_tegra_debug_uart_hsport;
158 static struct board_info main_board_info;
159 static struct board_info pmu_board_info;
160 static struct board_info display_board_info;
161 static int panel_id;
162 static struct board_info camera_board_info;
163 static int touch_vendor_id;
164 static int touch_panel_id;
165 static struct board_info io_board_info;
166 static struct board_info button_board_info;
167 static struct board_info joystick_board_info;
168 static struct board_info rightspeaker_board_info;
169 static struct board_info leftspeaker_board_info;
170 #ifdef CONFIG_TEGRA_USE_NCT
171 unsigned long tegra_nck_start;
172 unsigned long tegra_nck_size;
173 #endif
174
175 int tegra_with_secure_firmware;
176
177 static int pmu_core_edp;
178 static int board_panel_type;
179 static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
180 static int pwr_i2c_clk = 400;
181 static u8 power_config;
182 static u8 display_config;
183
184 static int tegra_split_mem_set;
185
186 struct device tegra_generic_cma_dev;
187 struct device tegra_vpr_cma_dev;
188
189 struct device tegra_generic_dev;
190
191 struct device tegra_vpr_dev;
192 EXPORT_SYMBOL(tegra_vpr_dev);
193
194 struct device tegra_iram_dev;
195 EXPORT_SYMBOL(tegra_iram_dev);
196
197 #define CREATE_TRACE_POINTS
198 #include <trace/events/nvsecurity.h>
199
200 static int tegra_update_resize_cfg(phys_addr_t base , size_t size)
201 {
202         int err = 0;
203 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
204
205         err = gk20a_do_idle();
206         if (!err) {
207                 /* Config VPR_BOM/_SIZE in MC */
208                 err = te_set_vpr_params((void *)(uintptr_t)base, size);
209                 gk20a_do_unidle();
210         }
211 #endif
212         return err;
213 }
214
215 struct dma_resize_notifier_ops vpr_dev_ops = {
216         .resize = tegra_update_resize_cfg
217 };
218
219 u32 notrace tegra_read_cycle(void)
220 {
221         u32 cycle_count;
222
223 #ifdef CONFIG_ARM64
224         asm volatile("mrs %0, pmccntr_el0" : "=r"(cycle_count));
225 #else
226         asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(cycle_count));
227 #endif
228
229         return cycle_count;
230 }
231
232 /*
233  * Storage for debug-macro.S's state.
234  *
235  * This must be in .data not .bss so that it gets initialized each time the
236  * kernel is loaded. The data is declared here rather than debug-macro.S so
237  * that multiple inclusions of debug-macro.S point at the same data.
238  */
239 u32 tegra_uart_config[4] = {
240         /* Debug UART initialization required */
241         1,
242         /* Debug UART physical address */
243         0,
244         /* Debug UART virtual address */
245         0,
246         /* Scratch space for debug macro */
247         0,
248 };
249
250
251 #define NEVER_RESET 0
252 static DEFINE_SPINLOCK(ahb_lock);
253
254 void ahb_gizmo_writel(unsigned long val, void __iomem *reg)
255 {
256         unsigned long check;
257         int retry = 10;
258         unsigned long flags;
259
260         /* Read and check if write is successful,
261          * if val doesn't match with read, retry write.
262          */
263         spin_lock_irqsave(&ahb_lock, flags);
264         do {
265                 writel(val, reg);
266                 check = readl(reg);
267                 if (likely(check == val))
268                         break;
269                 else
270                         pr_err("AHB register access fail for reg\n");
271         } while (--retry);
272         spin_unlock_irqrestore(&ahb_lock, flags);
273 }
274
275 void tegra_assert_system_reset(char mode, const char *cmd)
276 {
277         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
278         u32 reg;
279         bool empty_command = false;
280
281         if (tegra_platform_is_fpga() || NEVER_RESET) {
282                 pr_info("tegra_assert_system_reset() ignored.....");
283                 do { } while (1);
284         }
285
286         reg = readl_relaxed(reset + PMC_SCRATCH0);
287         /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
288         if (cmd) {
289                 if (!strcmp(cmd, "recovery"))
290                         reg |= RECOVERY_MODE;
291                 else if (!strcmp(cmd, "bootloader"))
292                         reg |= BOOTLOADER_MODE;
293                 else if (!strcmp(cmd, "forced-recovery"))
294                         reg |= FORCED_RECOVERY_MODE;
295                 else {
296                         reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
297                         empty_command = true;
298                 }
299         }
300         else {
301                 /* Clearing SCRATCH0 31:30:1 on default reboot */
302                 reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
303         }
304         writel_relaxed(reg, reset + PMC_SCRATCH0);
305         if ((!cmd || empty_command) && pm_power_reset) {
306                 pm_power_reset();
307         } else {
308                 reg = readl_relaxed(reset);
309                 reg |= 0x10;
310                 writel_relaxed(reg, reset);
311         }
312 }
313 static int modem_id;
314 static int commchip_id;
315 static int sku_override;
316 static int debug_uart_port_id;
317 static bool uart_over_sd;
318 static enum audio_codec_type audio_codec_name;
319 static enum image_type board_image_type = system_image;
320 static int max_cpu_current;
321 static int max_core_current;
322 static int emc_max_dvfs;
323 static unsigned int memory_type;
324 static int usb_port_owner_info;
325 static int lane_owner_info;
326
327 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
328 static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
329         /* name         parent          rate            enabled */
330         { "clk_m",      NULL,           0,              true },
331         { "emc",        NULL,           0,              true },
332         { "cpu",        NULL,           0,              true },
333         { "kfuse",      NULL,           0,              true },
334         { "fuse",       NULL,           0,              true },
335         { "sclk",       NULL,           0,              true },
336         { "pll_p",      NULL,           0,              true },
337         { "pll_p_out1", "pll_p",        0,              false },
338         { "pll_p_out3", "pll_p",        0,              false },
339 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
340         { "pll_m_out1", "pll_m",        275000000,      false },
341         { "pll_p_out2",  "pll_p",       102000000,      false },
342         { "sclk",        "pll_p_out2",  102000000,      true },
343         { "pll_p_out4",  "pll_p",       204000000,      true },
344         { "hclk",       "sclk",         102000000,      true },
345         { "pclk",       "hclk",         51000000,       true },
346         { "mselect",    "pll_p",        102000000,      true },
347         { "host1x",     "pll_p",        102000000,      false },
348         { "cl_dvfs_ref", "pll_p",       51000000,       true },
349         { "cl_dvfs_soc", "pll_p",       51000000,       true },
350         { "dsialp", "pll_p",    70000000,       false },
351         { "dsiblp", "pll_p",    70000000,       false },
352 #else
353         { "pll_m_out1", "pll_m",        275000000,      true },
354         { "pll_p_out2", "pll_p",        108000000,      false },
355         { "sclk",       "pll_p_out2",   108000000,      true },
356         { "pll_p_out4", "pll_p",        216000000,      true },
357         { "hclk",       "sclk",         108000000,      true },
358         { "pclk",       "hclk",         54000000,       true },
359         { "mselect",    "pll_p",        108000000,      true },
360         { "host1x",     "pll_p",        108000000,      false },
361         { "cl_dvfs_ref", "clk_m",       13000000,       false },
362         { "cl_dvfs_soc", "clk_m",       13000000,       false },
363 #endif
364 #ifdef CONFIG_TEGRA_SLOW_CSITE
365         { "csite",      "clk_m",        1000000,        true },
366 #else
367         { "csite",      NULL,           0,              true },
368 #endif
369         { "pll_u",      NULL,           480000000,      true },
370         { "pll_re_vco", NULL,           612000000,      true },
371         { "xusb_falcon_src",    "pll_p",        204000000,      false},
372         { "xusb_host_src",      "pll_p",        102000000,      false},
373         { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
374         { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
375         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
376         { "sdmmc1",     "pll_p",        48000000,       false},
377         { "sdmmc3",     "pll_p",        48000000,       false},
378         { "sdmmc4",     "pll_p",        48000000,       false},
379         { "sbc1.sclk",  NULL,           40000000,       false},
380         { "sbc2.sclk",  NULL,           40000000,       false},
381         { "sbc3.sclk",  NULL,           40000000,       false},
382         { "sbc4.sclk",  NULL,           40000000,       false},
383         { "sbc5.sclk",  NULL,           40000000,       false},
384         { "sbc6.sclk",  NULL,           40000000,       false},
385 #ifdef CONFIG_TEGRA_DUAL_CBUS
386         { "c2bus",      "pll_c2",       250000000,      false },
387         { "c3bus",      "pll_c3",       250000000,      false },
388         { "pll_c",      NULL,           624000000,      false },
389 #else
390         { "cbus",       "pll_c",        250000000,      false },
391 #endif
392         { "pll_c_out1", "pll_c",        150000000,      false },
393 #ifdef CONFIG_TEGRA_PLLM_SCALED
394         { "vi",         "pll_p",        0,              false},
395 #endif
396 #ifdef CONFIG_TEGRA_SOCTHERM
397         { "soc_therm",  "pll_p",        136000000,      false },
398         { "tsensor",    "clk_m",        500000,         false },
399 #endif
400         { "csite",      NULL,           0,              true },
401         { NULL,         NULL,           0,              0},
402 };
403 static __initdata struct tegra_clk_init_table tegra11x_cbus_init_table[] = {
404 #ifdef CONFIG_TEGRA_DUAL_CBUS
405         { "c2bus",      "pll_c2",       250000000,      false },
406         { "c3bus",      "pll_c3",       250000000,      false },
407         { "pll_c",      NULL,           624000000,      false },
408 #else
409         { "cbus",       "pll_c",        250000000,      false },
410 #endif
411         { "pll_c_out1", "pll_c",        150000000,      false },
412         { NULL,         NULL,           0,              0},
413 };
414 #endif
415 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
416 static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
417         /* name         parent          rate            enabled */
418         { "clk_m",      NULL,           0,              true },
419         { "mc",         NULL,           0,              true },
420         { "cpu",        NULL,           0,              true },
421         { "kfuse",      NULL,           0,              true },
422         { "fuse",       NULL,           0,              true },
423         { "sclk",       NULL,           0,              true },
424         { "pll_p",      NULL,           0,              true,
425                 TEGRA_CLK_INIT_PLATFORM_SI },
426         { "pll_p_out1", "pll_p",        0,              false,
427                 TEGRA_CLK_INIT_PLATFORM_SI },
428         { "pll_p_out3", "pll_p",        0,              true,
429                 TEGRA_CLK_INIT_PLATFORM_SI },
430         { "pll_m_out1", "pll_m",        275000000,      false,
431                 TEGRA_CLK_INIT_PLATFORM_SI },
432         { "pll_p_out2", "pll_p",        102000000,      false,
433                 TEGRA_CLK_INIT_PLATFORM_SI },
434         { "sclk",       "pll_p_out2",   102000000,      true,
435                 TEGRA_CLK_INIT_PLATFORM_SI },
436         { "pll_p_out4", "pll_p",        204000000,      true,
437                 TEGRA_CLK_INIT_PLATFORM_SI },
438         { "host1x",     "pll_p",        102000000,      false,
439                 TEGRA_CLK_INIT_PLATFORM_SI },
440         { "cl_dvfs_ref", "pll_p",       54000000,       true,
441                 TEGRA_CLK_INIT_PLATFORM_SI },
442         { "cl_dvfs_soc", "pll_p",       54000000,       true,
443                 TEGRA_CLK_INIT_PLATFORM_SI },
444         { "hclk",       "sclk",         102000000,      true,
445                 TEGRA_CLK_INIT_PLATFORM_SI },
446         { "pclk",       "hclk",         51000000,       true,
447                 TEGRA_CLK_INIT_PLATFORM_SI },
448         { "wake.sclk",  NULL,           40000000,       true,
449                 TEGRA_CLK_INIT_PLATFORM_SI },
450         { "mselect",    "pll_p",        102000000,      true,
451                 TEGRA_CLK_INIT_PLATFORM_SI },
452         { "pll_p_out5", "pll_p",        102000000,      true,
453                 TEGRA_CLK_INIT_PLATFORM_SI },
454 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
455         { "pll_m_out1", "pll_m",        275000000,      true,
456                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
457         { "pll_p_out2", "pll_p",        108000000,      false,
458                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
459         { "sclk",       "pll_p_out2",   108000000,      true,
460                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
461         { "pll_p_out4", "pll_p",        216000000,      true,
462                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
463         { "hclk",       "sclk",         108000000,      true,
464                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
465         { "pclk",       "hclk",         54000000,       true,
466                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
467         { "mselect",    "pll_p",        108000000,      true,
468                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
469         { "host1x",     "pll_p",        108000000,      false,
470                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
471         { "cl_dvfs_ref", "clk_m",       13000000,       false,
472                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
473         { "cl_dvfs_soc", "clk_m",       13000000,       false,
474                 TEGRA_CLK_INIT_PLATFORM_NON_SI },
475         { "vde",        "pll_c3",       48400000,       true,
476                 TEGRA_CLK_INIT_CPU_ASIM},
477 #endif
478 #ifdef CONFIG_TEGRA_SLOW_CSITE
479         { "csite",      "clk_m",        1000000,        true },
480 #else
481         { "csite",      NULL,           0,              true },
482 #endif
483         { "pll_u",      NULL,           480000000,      true },
484         { "pll_re_vco", NULL,           672000000,      true },
485         { "xusb_falcon_src",    "pll_re_out",   224000000,      false},
486         { "xusb_host_src",      "pll_re_out",   112000000,      false},
487         { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
488         { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
489         { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
490         { "sdmmc1",     "pll_p",        48000000,       false},
491         { "sdmmc3",     "pll_p",        48000000,       false},
492         { "sdmmc4",     "pll_p",        48000000,       false},
493         { "sdmmc1_ddr", "pll_p",        48000000,       false},
494         { "sdmmc3_ddr", "pll_p",        48000000,       false},
495         { "sdmmc4_ddr", "pll_p",        48000000,       false},
496         { "sbc1.sclk",  NULL,           40000000,       false},
497         { "sbc2.sclk",  NULL,           40000000,       false},
498         { "sbc3.sclk",  NULL,           40000000,       false},
499         { "sbc4.sclk",  NULL,           40000000,       false},
500         { "sbc5.sclk",  NULL,           40000000,       false},
501         { "sbc6.sclk",  NULL,           40000000,       false},
502         { "cpu.mselect", NULL,          102000000,      true},
503         { "gpu_ref",    NULL,           0,              true},
504         { "gk20a.gbus", NULL,           252000000,      false},
505 #ifdef CONFIG_TEGRA_PLLM_SCALED
506         { "vi",         "pll_p",        0,              false},
507         { "isp",        "pll_p",        0,              false},
508 #endif
509 #ifdef CONFIG_TEGRA_SOCTHERM
510         { "soc_therm",  "pll_p",        51000000,       false },
511         { "tsensor",    "clk_m",        500000,         false },
512 #endif
513         { "pll_d",      NULL,           0,              true },
514         { "dsialp",     "pll_p",        70000000,       false },
515         { "dsiblp",     "pll_p",        70000000,       false },
516         { NULL,         NULL,           0,              0},
517 };
518 static __initdata struct tegra_clk_init_table tegra12x_cbus_init_table[] = {
519         /* Initialize c2bus, c3bus, or cbus at the end of the list
520          * after all the clocks are moved under the proper parents.
521          */
522 #ifdef CONFIG_TEGRA_DUAL_CBUS
523         { "c2bus",      "pll_c2",       250000000,      false },
524         { "c3bus",      "pll_c3",       250000000,      false },
525         { "pll_c",      NULL,           600000000,      false },
526 #else
527         { "cbus",       "pll_c",        200000000,      false },
528 #endif
529         { "pll_c_out1", "pll_c",        100000000,      false },
530         { "c4bus",      "pll_c4",       200000000,      false },
531         { NULL,         NULL,           0,              0},
532 };
533 #endif
534
535 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
536 static __initdata struct tegra_clk_init_table tegra14x_clk_init_table[] = {
537         /* name         parent          rate            enabled */
538         { "osc",        NULL,           0,              true },
539         { "clk_m",      "osc",          0,              true },
540         { "emc",        NULL,           0,              true },
541         { "cpu",        NULL,           0,              true },
542         { "kfuse",      NULL,           0,              true },
543         { "fuse",       NULL,           0,              true },
544         { "sclk",       NULL,           0,              true },
545 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
546         { "pll_p",      NULL,           0,              true },
547         { "pll_p_out1", "pll_p",        0,              false },
548         { "pll_p_out3", "pll_p",        0,              true },
549         { "pll_m_out1", "pll_m",        275000000,      false },
550         { "pll_p_out2",  "pll_p",       102000000,      false },
551         { "sclk",        "pll_p_out2",  102000000,      true },
552         { "pll_p_out4",  "pll_p",       204000000,      true },
553         { "hclk",       "sclk",         102000000,      true },
554         { "pclk",       "hclk",         51000000,       true },
555         { "mselect",    "pll_p",        102000000,      true },
556         { "host1x",     "pll_p",        102000000,      false },
557         { "cl_dvfs_ref", "pll_p",       51000000,       true },
558         { "cl_dvfs_soc", "pll_p",       51000000,       true },
559 #else
560         { "pll_p",      NULL,           0,              true },
561         { "pll_p_out1", "pll_p",        0,              false },
562         { "pll_p_out3", "pll_p",        0,              true },
563         { "pll_m_out1", "pll_m",        275000000,      true },
564         { "pll_p_out2", "pll_p",        108000000,      false },
565         { "sclk",       "pll_p_out2",   108000000,      true },
566         { "pll_p_out4", "pll_p",        216000000,      true },
567         { "host1x",     "pll_p",        108000000,      false },
568         { "cl_dvfs_ref", "clk_m",       13000000,       false },
569         { "cl_dvfs_soc", "clk_m",       13000000,       false },
570         { "hclk",       "sclk",         108000000,      true },
571         { "pclk",       "hclk",         54000000,       true },
572         { "wake.sclk",  NULL,           250000000,      true },
573         { "mselect",    "pll_p",        108000000,      true },
574 #endif
575 #ifdef CONFIG_TEGRA_SLOW_CSITE
576         { "csite",      "clk_m",        1000000,        true },
577 #else
578         { "csite",      NULL,           0,              true },
579 #endif
580         { "pll_u",      NULL,           480000000,      false },
581         { "sdmmc1",     "pll_p",        48000000,       false},
582         { "sdmmc3",     "pll_p",        48000000,       false},
583         { "sdmmc4",     "pll_p",        48000000,       false},
584         { "mon.avp",    NULL,           80000000,       true },
585         { "sbc1.sclk",  NULL,           20000000,       false},
586         { "sbc2.sclk",  NULL,           20000000,       false},
587         { "sbc3.sclk",  NULL,           20000000,       false},
588         { "msenc",      "pll_p",        108000000,      false },
589         { "tsec",       "pll_p",        108000000,      false },
590         { "mc_capa",    "emc",          0,              true },
591         { "mc_cbpa",    "emc",          0,              true },
592 #ifdef CONFIG_TEGRA_SOCTHERM
593         { "soc_therm",  "pll_p",        51000000,       false },
594         { "tsensor",    "clk_m",        400000,         false },
595 #endif
596         { NULL,         NULL,           0,              0},
597 };
598 static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = {
599         /* Initialize c2bus, c3bus, or cbus at the end of the list
600          * after all the clocks are moved under the proper parents.
601          */
602 #ifdef CONFIG_TEGRA_DUAL_CBUS
603         { "c2bus",      "pll_c2",       200000000,      false },
604         { "c3bus",      "pll_c3",       200000000,      false },
605         { "pll_c",      NULL,           768000000,      false },
606 #else
607         { "cbus",       "pll_c",        200000000,      false },
608 #endif
609         { "pll_c_out1", "pll_c",        100000000,      false },
610         { NULL,         NULL,           0,              0},
611 };
612 #endif
613
614 #ifdef CONFIG_CACHE_L2X0
615 static void tegra_cache_smc(bool enable, u32 arg)
616 {
617         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
618         bool need_affinity_switch;
619         bool can_switch_affinity;
620         bool l2x0_enabled;
621         cpumask_t local_cpu_mask;
622         cpumask_t saved_cpu_mask;
623         unsigned long flags;
624         long ret;
625
626         /*
627          * ISSUE : Some registers of PL310 controler must be written
628          *              from Secure context (and from CPU0)!
629          *
630          * When called form Normal we obtain an abort or do nothing.
631          * Instructions that must be called in Secure:
632          *      - Write to Control register (L2X0_CTRL==0x100)
633          *      - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
634          *      - Invalidate all entries (L2X0_INV_WAY==0x77C),
635          *              mandatory at boot time.
636          *      - Tag and Data RAM Latency Control Registers
637          *              (0x108 & 0x10C) must be written in Secure.
638          */
639         need_affinity_switch = (smp_processor_id() != 0);
640         can_switch_affinity = !irqs_disabled();
641
642         WARN_ON(need_affinity_switch && !can_switch_affinity);
643         if (need_affinity_switch && can_switch_affinity) {
644                 cpu_set(0, local_cpu_mask);
645                 sched_getaffinity(0, &saved_cpu_mask);
646                 ret = sched_setaffinity(0, &local_cpu_mask);
647                 WARN_ON(ret != 0);
648         }
649
650         local_irq_save(flags);
651         l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
652         if (enable && !l2x0_enabled)
653                 tegra_generic_smc(0x82000002, 0x00000001, arg);
654         else if (!enable && l2x0_enabled)
655                 tegra_generic_smc(0x82000002, 0x00000002, arg);
656         local_irq_restore(flags);
657
658         if (need_affinity_switch && can_switch_affinity) {
659                 ret = sched_setaffinity(0, &saved_cpu_mask);
660                 WARN_ON(ret != 0);
661         }
662 }
663
664 static void tegra_l2x0_disable(void)
665 {
666         unsigned long flags;
667         static u32 l2x0_way_mask;
668
669         if (!l2x0_way_mask) {
670                 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
671                 u32 aux_ctrl;
672                 u32 ways;
673
674                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
675                 ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
676                 l2x0_way_mask = (1 << ways) - 1;
677         }
678
679         local_irq_save(flags);
680         tegra_cache_smc(false, l2x0_way_mask);
681         local_irq_restore(flags);
682 }
683
684 void tegra_init_cache(bool init)
685 {
686         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE);
687         u32 aux_ctrl;
688         u32 cache_type;
689         u32 tag_latency, data_latency;
690
691         if (tegra_cpu_is_secure()) {
692                 /* issue the SMC to enable the L2 */
693                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
694                 trace_smc_init_cache(NVSEC_SMC_START);
695                 tegra_cache_smc(true, aux_ctrl);
696                 trace_smc_init_cache(NVSEC_SMC_DONE);
697
698                 /* after init, reread aux_ctrl and register handlers */
699                 aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
700                 l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
701
702                 /* override outer_disable() with our disable */
703                 outer_cache.disable = tegra_l2x0_disable;
704         } else {
705 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
706                 tag_latency = 0x331;
707                 data_latency = 0x441;
708 #else
709                 if (!tegra_platform_is_silicon()) {
710                         tag_latency = 0x770;
711                         data_latency = 0x770;
712                 } else if (is_lp_cluster()) {
713                         tag_latency = tegra_cpu_c1_l2_tag_latency;
714                         data_latency = tegra_cpu_c1_l2_data_latency;
715                 } else {
716                         tag_latency = tegra_cpu_c0_l2_tag_latency;
717                         data_latency = tegra_cpu_c0_l2_data_latency;
718                 }
719 #endif
720                 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
721                 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
722
723 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
724                 if (!tegra_platform_is_fpga()) {
725 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
726                         /* Enable double line fill */
727                         writel(0x40000007, p + L2X0_PREFETCH_CTRL);
728 #else
729                         writel(0x7, p + L2X0_PREFETCH_CTRL);
730 #endif
731                         writel(0x3, p + L2X0_POWER_CTRL);
732                 }
733 #endif
734                 cache_type = readl(p + L2X0_CACHE_TYPE);
735                 aux_ctrl = (cache_type & 0x700) << (17-8);
736                 aux_ctrl |= 0x7C400001;
737                 if (init) {
738                         l2x0_init(p, aux_ctrl, 0x8200c3fe);
739                 } else {
740                         u32 tmp;
741
742                         tmp = aux_ctrl;
743                         aux_ctrl = readl(p + L2X0_AUX_CTRL);
744                         aux_ctrl &= 0x8200c3fe;
745                         aux_ctrl |= tmp;
746                         writel(aux_ctrl, p + L2X0_AUX_CTRL);
747                 }
748                 l2x0_enable();
749         }
750 }
751 #endif
752
753 static void __init tegra_perf_init(void)
754 {
755         u32 reg;
756
757 #ifdef CONFIG_ARM64
758         asm volatile("mrs %0, PMCR_EL0" : "=r"(reg));
759         reg >>= 11;
760         reg = (1 << (reg & 0x1f))-1;
761         reg |= 0x80000000;
762         asm volatile("msr PMINTENCLR_EL1, %0" : : "r"(reg));
763         reg = 1;
764         asm volatile("msr PMUSERENR_EL0, %0" : : "r"(reg));
765 #else
766         asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
767         reg >>= 11;
768         reg = (1 << (reg & 0x1f))-1;
769         reg |= 0x80000000;
770         asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
771         reg = 1;
772         asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
773 #endif
774 }
775
776 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
777 static void __init tegra_ramrepair_init(void)
778 {
779 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
780         if (tegra_spare_fuse(10)  | tegra_spare_fuse(11)) {
781 #endif
782                 u32 reg;
783                 reg = readl(FLOW_CTRL_RAM_REPAIR);
784                 reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN;
785                 writel(reg, FLOW_CTRL_RAM_REPAIR);
786 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
787         }
788 #endif
789 }
790 #endif
791
792 static void __init tegra_init_power(void)
793 {
794 #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
795         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
796 #endif
797 #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
798         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
799 #endif
800
801 #if defined(CONFIG_TEGRA_XUSB_PLATFORM)
802         /* powergate xusb partitions by default */
803         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
804         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
805         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
806 #endif
807
808 }
809
810 static inline unsigned long gizmo_readl(unsigned long offset)
811 {
812         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
813 }
814
815 static inline void gizmo_writel(unsigned long value, unsigned long offset)
816 {
817         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
818 }
819
820 static void __init tegra_init_ahb_gizmo_settings(void)
821 {
822         unsigned long val;
823
824         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
825         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
826
827         if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA11)
828                 val |= WR_WAIT_COMMIT_ON_1K;
829 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
830         val |= WR_WAIT_COMMIT_ON_1K | EN_USB_WAIT_COMMIT_ON_1K_STALL;
831 #endif
832         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
833
834         val = gizmo_readl(AHB_GIZMO_USB);
835         val |= IMMEDIATE;
836         gizmo_writel(val, AHB_GIZMO_USB);
837
838         val = gizmo_readl(AHB_GIZMO_USB2);
839         val |= IMMEDIATE;
840         gizmo_writel(val, AHB_GIZMO_USB2);
841
842         val = gizmo_readl(AHB_GIZMO_USB3);
843         val |= IMMEDIATE;
844         gizmo_writel(val, AHB_GIZMO_USB3);
845
846         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
847         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
848                                 | AHB_PRIORITY_WEIGHT(7);
849 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
850         val |= PRIORITY_SELECT_SE;
851 #endif
852
853         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
854
855         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
856         val &= ~MST_ID(~0);
857         val |= PREFETCH_ENB | AHBDMA_MST_ID |
858                 ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
859         ahb_gizmo_writel(val,
860                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG1));
861
862         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
863         val &= ~MST_ID(~0);
864         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) |
865                 INACTIVITY_TIMEOUT(0x1000);
866         ahb_gizmo_writel(val,
867                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG2));
868
869         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
870         val &= ~MST_ID(~0);
871         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) |
872                 INACTIVITY_TIMEOUT(0x1000);
873         ahb_gizmo_writel(val,
874                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG3));
875
876         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
877         val &= ~MST_ID(~0);
878         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
879                 INACTIVITY_TIMEOUT(0x1000);
880         ahb_gizmo_writel(val,
881                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG4));
882
883         /*
884          * SDMMC controller is removed from AHB interface in T124 and
885          * later versions of Tegra. Configure AHB prefetcher for SDMMC4
886          * in T11x and T14x SOCs.
887          */
888 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
889         val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
890         val &= ~MST_ID(~0);
891         val |= PREFETCH_ENB | SDMMC4_MST_ID;
892         val &= ~SDMMC4_MST_ID;
893         ahb_gizmo_writel(val,
894                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG5));
895 #endif
896
897 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
898         val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
899         val &= ~MST_ID(~0);
900         val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
901                 INACTIVITY_TIMEOUT(0x1000);
902         ahb_gizmo_writel(val,
903                 IO_ADDRESS(TEGRA_AHB_GIZMO_BASE + AHB_MEM_PREFETCH_CFG6));
904 #endif
905 }
906
907 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
908 void __init tegra20_init_early(void)
909 {
910         tegra_apb_io_init();
911         tegra_perf_init();
912         tegra_init_fuse();
913         tegra_init_cache(true);
914         tegra_powergate_init();
915         tegra20_hotplug_init();
916         tegra_init_power();
917         tegra_init_ahb_gizmo_settings();
918         tegra_init_debug_uart_rate();
919 }
920 #endif
921 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
922 void __init tegra30_init_early(void)
923 {
924         u32 speedo;
925         u32 tag_latency, data_latency;
926
927         display_tegra_dt_info();
928         tegra_apb_io_init();
929         tegra_perf_init();
930         tegra_init_fuse();
931         /*
932          * Store G/LP cluster L2 latencies to IRAM and DRAM
933          */
934         tegra_cpu_c1_l2_tag_latency = 0x221;
935         tegra_cpu_c1_l2_data_latency = 0x221;
936         writel_relaxed(0x221, tegra_cpu_c1_l2_tag_latency_iram);
937         writel_relaxed(0x221, tegra_cpu_c1_l2_data_latency_iram);
938         /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
939         speedo = tegra_cpu_speedo_id();
940         if (speedo == 4 || speedo == 5 || speedo == 6 ||
941             speedo == 12 || speedo == 13) {
942                 tag_latency = 0x442;
943                 data_latency = 0x552;
944         } else {
945                 tag_latency = 0x441;
946                 data_latency = 0x551;
947         }
948         tegra_cpu_c0_l2_tag_latency = tag_latency;
949         tegra_cpu_c0_l2_data_latency = data_latency;
950         writel_relaxed(tag_latency, tegra_cpu_c0_l2_tag_latency_iram);
951         writel_relaxed(data_latency, tegra_cpu_c0_l2_data_latency_iram);
952         tegra_init_cache(true);
953         tegra_powergate_init();
954         tegra30_hotplug_init();
955         tegra_init_power();
956         tegra_init_ahb_gizmo_settings();
957         tegra_init_debug_uart_rate();
958
959         init_dma_coherent_pool_size(SZ_1M);
960 }
961 #endif
962 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
963 void __init tegra11x_init_early(void)
964 {
965         display_tegra_dt_info();
966         tegra_apb_io_init();
967         tegra_perf_init();
968         tegra_init_fuse();
969         tegra_ramrepair_init();
970         tegra11x_init_clocks();
971         tegra11x_init_dvfs();
972         tegra_common_init_clock();
973         tegra_clk_init_from_table(tegra11x_clk_init_table);
974         tegra_clk_init_cbus_plls_from_table(tegra11x_cbus_init_table);
975         tegra11x_clk_init_la();
976         tegra_powergate_init();
977         tegra30_hotplug_init();
978         tegra_init_power();
979         tegra_init_ahb_gizmo_settings();
980         tegra_init_debug_uart_rate();
981
982         init_dma_coherent_pool_size(SZ_2M);
983 }
984 #endif
985 #ifdef CONFIG_ARCH_TEGRA_12x_SOC
986 void __init tegra12x_init_early(void)
987 {
988         if (of_find_compatible_node(NULL, NULL, "arm,psci"))
989                 tegra_with_secure_firmware = 1;
990
991         display_tegra_dt_info();
992         tegra_apb_io_init();
993         tegra_perf_init();
994         tegra_init_fuse();
995         tegra_ramrepair_init();
996         tegra12x_init_clocks();
997 #ifdef CONFIG_ARCH_TEGRA_13x_SOC
998         tegra13x_init_dvfs();
999 #else
1000         tegra12x_init_dvfs();
1001 #endif
1002         tegra_common_init_clock();
1003         tegra_clk_init_from_table(tegra12x_clk_init_table);
1004         tegra_clk_init_cbus_plls_from_table(tegra12x_cbus_init_table);
1005         tegra_powergate_init();
1006 #ifndef CONFIG_ARM64
1007         tegra30_hotplug_init();
1008 #endif
1009         tegra_init_power();
1010         tegra_init_ahb_gizmo_settings();
1011         tegra_init_debug_uart_rate();
1012 }
1013 #endif
1014 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
1015 void __init tegra14x_init_early(void)
1016 {
1017         display_tegra_dt_info();
1018         tegra_apb_io_init();
1019         tegra_perf_init();
1020         tegra_init_fuse();
1021         tegra_ramrepair_init();
1022         tegra14x_init_clocks();
1023         tegra14x_init_dvfs();
1024         tegra_common_init_clock();
1025         tegra_clk_init_from_table(tegra14x_clk_init_table);
1026         tegra_clk_init_cbus_plls_from_table(tegra14x_cbus_init_table);
1027         tegra_cpu_c1_l2_tag_latency = 0x110;
1028         tegra_cpu_c1_l2_data_latency = 0x331;
1029         writel_relaxed(0x110, tegra_cpu_c1_l2_tag_latency_iram);
1030         writel_relaxed(0x331, tegra_cpu_c1_l2_data_latency_iram);
1031         tegra_cpu_c0_l2_tag_latency = 0x111;
1032         tegra_cpu_c0_l2_data_latency = 0x441;
1033         writel_relaxed(0x111, tegra_cpu_c0_l2_tag_latency_iram);
1034         writel_relaxed(0x441, tegra_cpu_c0_l2_data_latency_iram);
1035         tegra_init_cache(true);
1036         tegra_powergate_init();
1037         tegra30_hotplug_init();
1038         tegra_init_power();
1039         tegra_init_ahb_gizmo_settings();
1040         tegra_init_debug_uart_rate();
1041 }
1042 #endif
1043 static int __init tegra_lp0_vec_arg(char *options)
1044 {
1045         char *p = options;
1046
1047         tegra_lp0_vec_size = memparse(p, &p);
1048         if (*p == '@')
1049                 tegra_lp0_vec_start = memparse(p+1, &p);
1050         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
1051                 tegra_lp0_vec_size = 0;
1052                 tegra_lp0_vec_start = 0;
1053         }
1054
1055         return 0;
1056 }
1057 early_param("lp0_vec", tegra_lp0_vec_arg);
1058
1059 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1060 static int __init tegra_wb0_params_arg(char *options)
1061 {
1062         char *p = options;
1063
1064         tegra_wb0_params_address = memparse(p, &p);
1065         if (*p == ',')
1066                 tegra_wb0_params_instances = memparse(p+1, &p);
1067         if (*p == ',')
1068                 tegra_wb0_params_block_size = memparse(p+1, &p);
1069
1070         return 0;
1071 }
1072 early_param("wb0_params", tegra_wb0_params_arg);
1073 #endif
1074
1075 #ifdef CONFIG_TEGRA_NVDUMPER
1076 static int __init tegra_nvdumper_arg(char *options)
1077 {
1078         char *p = options;
1079
1080         nvdumper_reserved = memparse(p, &p);
1081         return 0;
1082 }
1083 early_param("nvdumper_reserved", tegra_nvdumper_arg);
1084 #endif
1085
1086 static int __init tegra_bootloader_fb_arg(char *options)
1087 {
1088         char *p = options;
1089
1090         tegra_bootloader_fb_size = memparse(p, &p);
1091         if (*p == '@')
1092                 tegra_bootloader_fb_start = memparse(p+1, &p);
1093
1094         pr_info("Found tegra_fbmem: %08llx@%08llx\n",
1095                 (u64)tegra_bootloader_fb_size, (u64)tegra_bootloader_fb_start);
1096
1097         return 0;
1098 }
1099 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
1100
1101 static int __init tegra_bootloader_fb2_arg(char *options)
1102 {
1103         char *p = options;
1104
1105         tegra_bootloader_fb2_size = memparse(p, &p);
1106         if (*p == '@')
1107                 tegra_bootloader_fb2_start = memparse(p+1, &p);
1108
1109         pr_info("Found tegra_fbmem2: %08llx@%08llx\n",
1110                 (u64)tegra_bootloader_fb2_size,
1111                 (u64)tegra_bootloader_fb2_start);
1112
1113         return 0;
1114 }
1115 early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
1116
1117 static int __init tegra_sku_override(char *id)
1118 {
1119         char *p = id;
1120
1121         sku_override = memparse(p, &p);
1122
1123         return 0;
1124 }
1125 early_param("sku_override", tegra_sku_override);
1126
1127 int tegra_get_sku_override(void)
1128 {
1129         return sku_override;
1130 }
1131
1132 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1133 static int __init tegra_vpr_arg(char *options)
1134 {
1135         char *p = options;
1136
1137         tegra_vpr_size = memparse(p, &p);
1138         if (*p == '@')
1139                 tegra_vpr_start = memparse(p+1, &p);
1140         pr_info("Found vpr, start=0x%llx size=%llx",
1141                 (u64)tegra_vpr_start, (u64)tegra_vpr_size);
1142         return 0;
1143 }
1144 early_param("vpr", tegra_vpr_arg);
1145 #endif
1146
1147 static int __init tegra_tsec_arg(char *options)
1148 {
1149         char *p = options;
1150
1151         tegra_tsec_size = memparse(p, &p);
1152         if (*p == '@')
1153                 tegra_tsec_start = memparse(p+1, &p);
1154         pr_info("Found tsec, start=0x%llx size=%llx",
1155                 (u64)tegra_tsec_start, (u64)tegra_tsec_size);
1156         return 0;
1157 }
1158 early_param("tsec", tegra_tsec_arg);
1159
1160 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
1161 static int __init tegra_tzram_arg(char *options)
1162 {
1163         char *p = options;
1164
1165         tegra_tzram_size = memparse(p, &p);
1166         if (*p == '@')
1167                 tegra_tzram_start = memparse(p + 1, &p);
1168         return 0;
1169 }
1170 early_param("tzram", tegra_tzram_arg);
1171 #endif
1172
1173 #ifdef CONFIG_TEGRA_USE_NCT
1174 static int __init tegra_nck_arg(char *options)
1175 {
1176         char *p = options;
1177
1178         tegra_nck_size = memparse(p, &p);
1179         if (*p == '@')
1180                 tegra_nck_start = memparse(p+1, &p);
1181         if (!tegra_nck_size || !tegra_nck_start) {
1182                 tegra_nck_size = 0;
1183                 tegra_nck_start = 0;
1184         }
1185
1186         return 0;
1187 }
1188 early_param("nck", tegra_nck_arg);
1189 #endif  /* CONFIG_TEGRA_USE_NCT */
1190
1191 enum panel_type get_panel_type(void)
1192 {
1193         return board_panel_type;
1194 }
1195 static int __init tegra_board_panel_type(char *options)
1196 {
1197         if (!strcmp(options, "lvds"))
1198                 board_panel_type = panel_type_lvds;
1199         else if (!strcmp(options, "dsi"))
1200                 board_panel_type = panel_type_dsi;
1201         else
1202                 return 0;
1203         return 1;
1204 }
1205 __setup("panel=", tegra_board_panel_type);
1206
1207 int tegra_get_board_panel_id(void)
1208 {
1209         return panel_id;
1210 }
1211 static int __init tegra_board_panel_id(char *options)
1212 {
1213         char *p = options;
1214         panel_id = memparse(p, &p);
1215         return panel_id;
1216 }
1217 __setup("display_panel=", tegra_board_panel_id);
1218
1219 int tegra_get_touch_vendor_id(void)
1220 {
1221         return touch_vendor_id;
1222 }
1223 int tegra_get_touch_panel_id(void)
1224 {
1225         return touch_panel_id;
1226 }
1227 static int __init tegra_touch_id(char *options)
1228 {
1229         char *p = options;
1230         touch_vendor_id = memparse(p, &p);
1231         if (*p == '@')
1232                 touch_panel_id = memparse(p+1, &p);
1233         return 1;
1234 }
1235 __setup("touch_id=", tegra_touch_id);
1236
1237 u8 get_power_config(void)
1238 {
1239         return power_config;
1240 }
1241 static int __init tegra_board_power_config(char *options)
1242 {
1243         char *p = options;
1244         power_config = memparse(p, &p);
1245         return 1;
1246 }
1247 __setup("power-config=", tegra_board_power_config);
1248
1249 u8 get_display_config(void)
1250 {
1251         return display_config;
1252 }
1253 static int __init tegra_board_display_config(char *options)
1254 {
1255         char *p = options;
1256         display_config = memparse(p, &p);
1257         return 1;
1258 }
1259 __setup("display-config=", tegra_board_display_config);
1260
1261 enum power_supply_type get_power_supply_type(void)
1262 {
1263         return pow_supply_type;
1264 }
1265 static int __init tegra_board_power_supply_type(char *options)
1266 {
1267         if (!strcmp(options, "Adapter"))
1268                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1269         if (!strcmp(options, "Mains"))
1270                 pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
1271         else if (!strcmp(options, "Battery"))
1272                 pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
1273         else
1274                 return 0;
1275         return 1;
1276 }
1277 __setup("power_supply=", tegra_board_power_supply_type);
1278
1279 int get_core_edp(void)
1280 {
1281         return pmu_core_edp;
1282 }
1283 static int __init tegra_pmu_core_edp(char *options)
1284 {
1285         char *p = options;
1286         int core_edp = memparse(p, &p);
1287         if (core_edp != 0)
1288                 pmu_core_edp = core_edp;
1289         return 0;
1290 }
1291 early_param("core_edp_mv", tegra_pmu_core_edp);
1292
1293 int get_maximum_cpu_current_supported(void)
1294 {
1295         return max_cpu_current;
1296 }
1297 static int __init tegra_max_cpu_current(char *options)
1298 {
1299         char *p = options;
1300         max_cpu_current = memparse(p, &p);
1301         return 1;
1302 }
1303 __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
1304
1305 int get_maximum_core_current_supported(void)
1306 {
1307         return max_core_current;
1308 }
1309 static int __init tegra_max_core_current(char *options)
1310 {
1311         char *p = options;
1312         max_core_current = memparse(p, &p);
1313         return 0;
1314 }
1315 early_param("core_edp_ma", tegra_max_core_current);
1316
1317 int get_emc_max_dvfs(void)
1318 {
1319         return emc_max_dvfs;
1320 }
1321 static int __init tegra_emc_max_dvfs(char *options)
1322 {
1323         char *p = options;
1324         emc_max_dvfs = memparse(p, &p);
1325         return 1;
1326 }
1327 __setup("emc_max_dvfs=", tegra_emc_max_dvfs);
1328
1329 int tegra_get_memory_type(void)
1330 {
1331         return memory_type;
1332 }
1333 static int __init tegra_memory_type(char *options)
1334 {
1335         char *p = options;
1336         memory_type = memparse(p, &p);
1337         return 1;
1338 }
1339 __setup("memtype=", tegra_memory_type);
1340
1341 static int __init tegra_debug_uartport(char *info)
1342 {
1343         char *p = info;
1344         unsigned long long port_id;
1345         if (!strncmp(p, "hsport", 6))
1346                 is_tegra_debug_uart_hsport = true;
1347         else if (!strncmp(p, "lsport", 6))
1348                 is_tegra_debug_uart_hsport = false;
1349
1350         if (p[6] == ',') {
1351                 if (p[7] == '-') {
1352                         debug_uart_port_id = -1;
1353                 } else {
1354                         port_id = memparse(p + 7, &p);
1355                         debug_uart_port_id = (int) port_id;
1356                         if (debug_uart_port_id == 5)
1357                                 uart_over_sd = true;
1358                 }
1359         } else {
1360                 debug_uart_port_id = -1;
1361         }
1362
1363         return 1;
1364 }
1365
1366 bool is_tegra_debug_uartport_hs(void)
1367 {
1368         return is_tegra_debug_uart_hsport;
1369 }
1370
1371 bool is_uart_over_sd_enabled(void)
1372 {
1373         return uart_over_sd;
1374 }
1375
1376 void set_sd_uart_port_id(int port_id)
1377 {
1378         debug_uart_port_id = port_id;
1379 }
1380
1381 int get_tegra_uart_debug_port_id(void)
1382 {
1383         return debug_uart_port_id;
1384 }
1385 __setup("debug_uartport=", tegra_debug_uartport);
1386
1387 static int __init tegra_image_type(char *options)
1388 {
1389         if (!strcmp(options, "RCK"))
1390                 board_image_type = rck_image;
1391
1392         return 0;
1393 }
1394
1395 enum image_type get_tegra_image_type(void)
1396 {
1397         return board_image_type;
1398 }
1399
1400 __setup("image=", tegra_image_type);
1401
1402 static int __init tegra_audio_codec_type(char *info)
1403 {
1404         char *p = info;
1405         if (!strncmp(p, "wm8903", 6))
1406                 audio_codec_name = audio_codec_wm8903;
1407         else
1408                 audio_codec_name = audio_codec_none;
1409
1410         return 1;
1411 }
1412
1413 enum audio_codec_type get_audio_codec_type(void)
1414 {
1415         return audio_codec_name;
1416 }
1417 __setup("audio_codec=", tegra_audio_codec_type);
1418
1419 static int tegra_get_pwr_i2c_clk_rate(char *options)
1420 {
1421         int clk = simple_strtol(options, NULL, 16);
1422         if (clk != 0)
1423                 pwr_i2c_clk = clk;
1424         return 0;
1425 }
1426
1427 int get_pwr_i2c_clk_rate(void)
1428 {
1429         return pwr_i2c_clk;
1430 }
1431 __setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
1432
1433 static bool pmic_wdt_disable;
1434 bool is_pmic_wdt_disabled_at_boot(void)
1435 {
1436         return pmic_wdt_disable;
1437 }
1438
1439 static int parse_arg_pmic_wdt_disable(char *options)
1440 {
1441         /* no kernel command line argument "watchdog" interpreted as
1442          * watchdog enable
1443          */
1444         pmic_wdt_disable = false;
1445         if (!(strcmp(options, "enable")))
1446                 pmic_wdt_disable = false;
1447         else if (!(strcmp(options, "disable")))
1448                 pmic_wdt_disable = true;
1449         /* kernel command line from fastboot does not support
1450          * other values
1451          */
1452
1453         return 0;
1454 }
1455 __setup("watchdog=", parse_arg_pmic_wdt_disable);
1456
1457 void tegra_get_board_info(struct board_info *bi)
1458 {
1459 #ifdef CONFIG_OF
1460         struct device_node *board_info;
1461         u32 prop_val;
1462         int err;
1463
1464         board_info = of_find_node_by_path("/chosen/board_info");
1465         if (!IS_ERR_OR_NULL(board_info)) {
1466                 memset(bi, 0, sizeof(*bi));
1467
1468                 err = of_property_read_u32(board_info, "id", &prop_val);
1469                 if (err)
1470                         pr_err("failed to read /chosen/board_info/id\n");
1471                 else
1472                         bi->board_id = prop_val;
1473
1474                 err = of_property_read_u32(board_info, "sku", &prop_val);
1475                 if (err)
1476                         pr_err("failed to read /chosen/board_info/sku\n");
1477                 else
1478                         bi->sku = prop_val;
1479
1480                 err = of_property_read_u32(board_info, "fab", &prop_val);
1481                 if (err)
1482                         pr_err("failed to read /chosen/board_info/fab\n");
1483                 else
1484                         bi->fab = prop_val;
1485
1486                 err = of_property_read_u32(board_info, "major_revision", &prop_val);
1487                 if (err)
1488                         pr_err("failed to read /chosen/board_info/major_revision\n");
1489                 else
1490                         bi->major_revision = prop_val;
1491
1492                 err = of_property_read_u32(board_info, "minor_revision", &prop_val);
1493                 if (err)
1494                         pr_err("failed to read /chosen/board_info/minor_revision\n");
1495                 else
1496                         bi->minor_revision = prop_val;
1497                 system_serial_high = (bi->board_id << 16) | bi->sku;
1498                 system_serial_low = (bi->fab << 24) |
1499                         (bi->major_revision << 16) | (bi->minor_revision << 8);
1500         } else {
1501 #endif
1502                 if (system_serial_high || system_serial_low) {
1503                         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
1504                         bi->sku = (system_serial_high) & 0xFFFF;
1505                         bi->fab = (system_serial_low >> 24) & 0xFF;
1506                         bi->major_revision = (system_serial_low >> 16) & 0xFF;
1507                         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
1508                 } else {
1509                         memcpy(bi, &main_board_info, sizeof(struct board_info));
1510                 }
1511 #ifdef CONFIG_OF
1512         }
1513 #endif
1514 }
1515
1516 #ifdef CONFIG_OF
1517 void find_dc_node(struct device_node **dc1_node,
1518                 struct device_node **dc2_node) {
1519         *dc1_node =
1520                 of_find_node_by_path("/host1x/dc@54200000");
1521         *dc2_node =
1522                 of_find_node_by_path("/host1x/dc@54240000");
1523 }
1524 #else
1525 void find_dc_node(struct device_node *dc1_node,
1526                 struct device_node *dc2_node) {
1527         return;
1528 }
1529 #endif
1530
1531 static int __init tegra_main_board_info(char *info)
1532 {
1533         char *p = info;
1534         main_board_info.board_id = memparse(p, &p);
1535         main_board_info.sku = memparse(p+1, &p);
1536         main_board_info.fab = memparse(p+1, &p);
1537         main_board_info.major_revision = memparse(p+1, &p);
1538         main_board_info.minor_revision = memparse(p+1, &p);
1539         return 1;
1540 }
1541
1542 __setup("board_info=", tegra_main_board_info);
1543
1544 static int __init tegra_pmu_board_info(char *info)
1545 {
1546         char *p = info;
1547         pmu_board_info.board_id = memparse(p, &p);
1548         pmu_board_info.sku = memparse(p+1, &p);
1549         pmu_board_info.fab = memparse(p+1, &p);
1550         pmu_board_info.major_revision = memparse(p+1, &p);
1551         pmu_board_info.minor_revision = memparse(p+1, &p);
1552         return 0;
1553 }
1554
1555 void tegra_get_pmu_board_info(struct board_info *bi)
1556 {
1557         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
1558 }
1559
1560 early_param("pmuboard", tegra_pmu_board_info);
1561
1562 static int __init tegra_display_board_info(char *info)
1563 {
1564         char *p = info;
1565         display_board_info.board_id = memparse(p, &p);
1566         display_board_info.sku = memparse(p+1, &p);
1567         display_board_info.fab = memparse(p+1, &p);
1568         display_board_info.major_revision = memparse(p+1, &p);
1569         display_board_info.minor_revision = memparse(p+1, &p);
1570         return 1;
1571 }
1572
1573 void tegra_get_display_board_info(struct board_info *bi)
1574 {
1575         memcpy(bi, &display_board_info, sizeof(struct board_info));
1576 }
1577
1578 __setup("displayboard=", tegra_display_board_info);
1579
1580 static int __init tegra_camera_board_info(char *info)
1581 {
1582         char *p = info;
1583         camera_board_info.board_id = memparse(p, &p);
1584         camera_board_info.sku = memparse(p+1, &p);
1585         camera_board_info.fab = memparse(p+1, &p);
1586         camera_board_info.major_revision = memparse(p+1, &p);
1587         camera_board_info.minor_revision = memparse(p+1, &p);
1588         return 1;
1589 }
1590
1591 void tegra_get_camera_board_info(struct board_info *bi)
1592 {
1593         memcpy(bi, &camera_board_info, sizeof(struct board_info));
1594 }
1595
1596 __setup("cameraboard=", tegra_camera_board_info);
1597
1598 static int __init tegra_leftspeaker_board_info(char *info)
1599 {
1600         char *p = info;
1601         leftspeaker_board_info.board_id = memparse(p, &p);
1602         leftspeaker_board_info.sku = memparse(p+1, &p);
1603         leftspeaker_board_info.fab = memparse(p+1, &p);
1604         leftspeaker_board_info.major_revision = memparse(p+1, &p);
1605         leftspeaker_board_info.minor_revision = memparse(p+1, &p);
1606         return 1;
1607 }
1608
1609 void tegra_get_leftspeaker_board_info(struct board_info *bi)
1610 {
1611         memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
1612 }
1613
1614 __setup("leftspeakerboard=", tegra_leftspeaker_board_info);
1615
1616 static int __init tegra_rightspeaker_board_info(char *info)
1617 {
1618         char *p = info;
1619         rightspeaker_board_info.board_id = memparse(p, &p);
1620         rightspeaker_board_info.sku = memparse(p+1, &p);
1621         rightspeaker_board_info.fab = memparse(p+1, &p);
1622         rightspeaker_board_info.major_revision = memparse(p+1, &p);
1623         rightspeaker_board_info.minor_revision = memparse(p+1, &p);
1624         return 1;
1625 }
1626
1627 void tegra_get_rightspeaker_board_info(struct board_info *bi)
1628 {
1629         memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
1630 }
1631
1632 __setup("rightspeakerboard=", tegra_rightspeaker_board_info);
1633
1634 static int __init tegra_joystick_board_info(char *info)
1635 {
1636         char *p = info;
1637         joystick_board_info.board_id = memparse(p, &p);
1638         joystick_board_info.sku = memparse(p+1, &p);
1639         joystick_board_info.fab = memparse(p+1, &p);
1640         joystick_board_info.major_revision = memparse(p+1, &p);
1641         joystick_board_info.minor_revision = memparse(p+1, &p);
1642         return 1;
1643 }
1644
1645 void tegra_get_joystick_board_info(struct board_info *bi)
1646 {
1647         memcpy(bi, &joystick_board_info, sizeof(struct board_info));
1648 }
1649
1650 __setup("joystickboard=", tegra_joystick_board_info);
1651
1652 static int __init tegra_button_board_info(char *info)
1653 {
1654         char *p = info;
1655         button_board_info.board_id = memparse(p, &p);
1656         button_board_info.sku = memparse(p+1, &p);
1657         button_board_info.fab = memparse(p+1, &p);
1658         button_board_info.major_revision = memparse(p+1, &p);
1659         button_board_info.minor_revision = memparse(p+1, &p);
1660         return 1;
1661 }
1662
1663 void tegra_get_button_board_info(struct board_info *bi)
1664 {
1665         memcpy(bi, &button_board_info, sizeof(struct board_info));
1666 }
1667
1668 __setup("buttonboard=", tegra_button_board_info);
1669
1670 static int __init tegra_io_board_info(char *info)
1671 {
1672         char *p = info;
1673         io_board_info.board_id = memparse(p, &p);
1674         io_board_info.sku = memparse(p+1, &p);
1675         io_board_info.fab = memparse(p+1, &p);
1676         io_board_info.major_revision = memparse(p+1, &p);
1677         io_board_info.minor_revision = memparse(p+1, &p);
1678         return 1;
1679 }
1680
1681 void tegra_get_io_board_info(struct board_info *bi)
1682 {
1683         memcpy(bi, &io_board_info, sizeof(struct board_info));
1684 }
1685
1686 __setup("ioboard=", tegra_io_board_info);
1687
1688 static int __init tegra_modem_id(char *id)
1689 {
1690         char *p = id;
1691
1692         modem_id = memparse(p, &p);
1693         return 1;
1694 }
1695
1696 int tegra_get_modem_id(void)
1697 {
1698         return modem_id;
1699 }
1700
1701 __setup("modem_id=", tegra_modem_id);
1702
1703 static int __init tegra_usb_port_owner_info(char *id)
1704 {
1705         char *p = id;
1706
1707         usb_port_owner_info = memparse(p, &p);
1708         return 1;
1709 }
1710
1711 int tegra_get_usb_port_owner_info(void)
1712 {
1713         return usb_port_owner_info;
1714 }
1715
1716 __setup("usb_port_owner_info=", tegra_usb_port_owner_info);
1717
1718 static int __init tegra_lane_owner_info(char *id)
1719 {
1720         char *p = id;
1721
1722         lane_owner_info = memparse(p, &p);
1723         return 1;
1724 }
1725
1726 int tegra_get_lane_owner_info(void)
1727 {
1728         return lane_owner_info;
1729 }
1730
1731 __setup("lane_owner_info=", tegra_lane_owner_info);
1732
1733 static int __init tegra_commchip_id(char *id)
1734 {
1735         char *p = id;
1736
1737         if (get_option(&p, &commchip_id) != 1)
1738                 return 0;
1739         return 1;
1740 }
1741
1742 int tegra_get_commchip_id(void)
1743 {
1744         return commchip_id;
1745 }
1746
1747 __setup("commchip_id=", tegra_commchip_id);
1748
1749 /*
1750  * Tegra has a protected aperture that prevents access by most non-CPU
1751  * memory masters to addresses above the aperture value.  Enabling it
1752  * secures the CPU's memory from the GPU, except through the GART.
1753  */
1754 void __init tegra_protected_aperture_init(unsigned long aperture)
1755 {
1756         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
1757         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
1758         writel(aperture, mc_base + MC_SECURITY_CFG2);
1759 }
1760
1761 /*
1762  * Due to conflicting restrictions on the placement of the framebuffer,
1763  * the bootloader is likely to leave the framebuffer pointed at a location
1764  * in memory that is outside the grhost aperture.  This function will move
1765  * the framebuffer contents from a physical address that is anywhere (lowmem,
1766  * highmem, or outside the memory map) to a physical address that is outside
1767  * the memory map.
1768  */
1769 void __tegra_move_framebuffer(struct platform_device *pdev,
1770         phys_addr_t to, phys_addr_t from,
1771         size_t size)
1772 {
1773         struct page *page;
1774         void __iomem *to_io;
1775         void *from_virt;
1776         unsigned long i;
1777
1778         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1779         BUG_ON(PAGE_ALIGN(from) != from);
1780         BUG_ON(PAGE_ALIGN(size) != size);
1781
1782         to_io = ioremap_wc(to, size);
1783         if (!to_io) {
1784                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1785                 return;
1786         }
1787
1788         if (from && pfn_valid(page_to_pfn(phys_to_page(from)))) {
1789                 for (i = 0 ; i < size; i += PAGE_SIZE) {
1790                         page = phys_to_page(from + i);
1791                         from_virt = kmap(page);
1792                         memcpy(to_io + i, from_virt, PAGE_SIZE);
1793                         kunmap(page);
1794                 }
1795         } else if (from) {
1796                 void __iomem *from_io = ioremap_wc(from, size);
1797                 if (!from_io) {
1798                         pr_err("%s: Failed to map source framebuffer\n",
1799                                 __func__);
1800                         goto out;
1801                 }
1802
1803                 for (i = 0; i < size; i += 4)
1804                         writel_relaxed(readl_relaxed(from_io + i), to_io + i);
1805                 dmb();
1806
1807                 iounmap(from_io);
1808         }
1809
1810 out:
1811         iounmap(to_io);
1812 }
1813
1814 void __tegra_clear_framebuffer(struct platform_device *pdev,
1815                                unsigned long to, unsigned long size)
1816 {
1817         void __iomem *to_io;
1818         unsigned long i;
1819
1820         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
1821         BUG_ON(PAGE_ALIGN(size) != size);
1822
1823         to_io = ioremap_wc(to, size);
1824         if (!to_io) {
1825                 pr_err("%s: Failed to map target framebuffer\n", __func__);
1826                 return;
1827         }
1828
1829         if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
1830                 for (i = 0 ; i < size; i += PAGE_SIZE)
1831                         memset(to_io + i, 0, PAGE_SIZE);
1832         } else {
1833                 for (i = 0; i < size; i += 4)
1834                         writel_relaxed(0, to_io + i);
1835                 dmb();
1836         }
1837
1838         iounmap(to_io);
1839 }
1840
1841 #ifdef CONFIG_PSTORE_RAM
1842 static struct ramoops_platform_data ramoops_data;
1843
1844 static struct platform_device ramoops_dev  = {
1845         .name = "ramoops",
1846         .dev = {
1847                 .platform_data = &ramoops_data,
1848         },
1849 };
1850
1851
1852 static void __init tegra_reserve_ramoops_memory(unsigned long reserve_size)
1853 {
1854         ramoops_data.mem_size = reserve_size;
1855         ramoops_data.mem_address = memblock_end_of_4G() - reserve_size;
1856         ramoops_data.console_size = reserve_size - FTRACE_MEM_SIZE;
1857         ramoops_data.ftrace_size = FTRACE_MEM_SIZE;
1858         ramoops_data.dump_oops = 1;
1859         memblock_remove(ramoops_data.mem_address, ramoops_data.mem_size);
1860 }
1861
1862 static int __init tegra_register_ramoops_device(void)
1863 {
1864         int ret = platform_device_register(&ramoops_dev);
1865         if (ret) {
1866                 pr_info("Unable to register ramoops platform device\n");
1867                 return ret;
1868         }
1869         return ret;
1870 }
1871 core_initcall(tegra_register_ramoops_device);
1872 #endif
1873
1874 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
1875         unsigned long fb2_size)
1876 {
1877         struct iommu_linear_map map[4];
1878
1879 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
1880         if (carveout_size) {
1881                 /*
1882                  * Place the carveout below the 4 GB physical address limit
1883                  * because IOVAs are only 32 bit wide.
1884                  */
1885                 BUG_ON(memblock_end_of_4G() == 0);
1886                 tegra_carveout_start = memblock_end_of_4G() - carveout_size;
1887                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
1888                         pr_err("Failed to remove carveout %08lx@%08llx "
1889                                 "from memory map\n",
1890                                 carveout_size, (u64)tegra_carveout_start);
1891                         tegra_carveout_start = 0;
1892                         tegra_carveout_size = 0;
1893                 } else
1894                         tegra_carveout_size = carveout_size;
1895         }
1896 #endif
1897
1898         if (fb2_size) {
1899                 /*
1900                  * Place fb2 below the 4 GB physical address limit because
1901                  * IOVAs are only 32 bit wide.
1902                  */
1903                 BUG_ON(memblock_end_of_4G() == 0);
1904                 tegra_fb2_start = memblock_end_of_4G() - fb2_size;
1905                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
1906                         pr_err("Failed to remove second framebuffer "
1907                                 "%08lx@%08llx from memory map\n",
1908                                 fb2_size, (u64)tegra_fb2_start);
1909                         tegra_fb2_start = 0;
1910                         tegra_fb2_size = 0;
1911                 } else
1912                         tegra_fb2_size = fb2_size;
1913         }
1914
1915         if (fb_size) {
1916                 /*
1917                  * Place fb below the 4 GB physical address limit because
1918                  * IOVAs are only 32 bit wide.
1919                  */
1920                 BUG_ON(memblock_end_of_4G() == 0);
1921                 tegra_fb_start = memblock_end_of_4G() - fb_size;
1922                 if (memblock_remove(tegra_fb_start, fb_size)) {
1923                         pr_err("Failed to remove framebuffer %08lx@%08llx "
1924                                 "from memory map\n",
1925                                 fb_size, (u64)tegra_fb_start);
1926                         tegra_fb_start = 0;
1927                         tegra_fb_size = 0;
1928                 } else
1929                         tegra_fb_size = fb_size;
1930         }
1931
1932         if (tegra_cpu_is_asim()) {
1933                 if (tegra_split_mem_active()) {
1934                         tegra_fb_start = TEGRA_ASIM_QT_FB_START;
1935                         tegra_fb_size = TEGRA_ASIM_QT_FB_SIZE;
1936
1937                         if (tegra_vpr_size == 0) {
1938                                 tegra_carveout_start =
1939                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1940                                 tegra_carveout_size =
1941                                    TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_SIZE;
1942                         } else if (
1943                                     (tegra_vpr_start <
1944                                      TEGRA_ASIM_QT_FB_START +
1945                                      TEGRA_ASIM_QT_FB_SIZE) ||
1946                                      (tegra_vpr_start + tegra_vpr_size - 1 >
1947                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1948                                      TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE - 1)) {
1949                                 /*
1950                                  * On ASIM/ASIM + QT with
1951                                  * CONFIG_TEGRA_SIMULATION_SPLIT_MEM enabled,
1952                                  * the VPR region needs to be within the front
1953                                  * door memory region. Moreover, the VPR region
1954                                  * can't exist where the framebuffer resides.
1955                                  */
1956                                 BUG();
1957                         } else if (
1958                                         (tegra_vpr_start -
1959                                          (TEGRA_ASIM_QT_FB_START +
1960                                           TEGRA_ASIM_QT_FB_SIZE) <
1961                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE) &&
1962                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1963                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1964                                          (tegra_vpr_start + tegra_vpr_size) <
1965                                          TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE)) {
1966                                 /*
1967                                  * The tegra ASIM/QT carveout has a min size:-
1968                                  * TEGRA_ASIM_QT_CARVEOUT_MIN_SIZE. All free
1969                                  * regions in front door mem are smaller than
1970                                  * the min carveout size. Therefore, we can't
1971                                  * fit the carveout in front door mem.
1972                                  */
1973                                 BUG();
1974                         } else if (
1975                                         (tegra_vpr_start -
1976                                          (TEGRA_ASIM_QT_FB_START +
1977                                           TEGRA_ASIM_QT_FB_SIZE)) >=
1978                                         (TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1979                                          TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1980                                          (tegra_vpr_start + tegra_vpr_size))) {
1981                                 /*
1982                                  * Place the tegra ASIM/QT carveout between the
1983                                  * framebuffer and VPR.
1984                                  */
1985                                 tegra_carveout_start =
1986                                   TEGRA_ASIM_QT_CARVEOUT_VPR_DISABLED_START;
1987                                 tegra_carveout_size = tegra_vpr_start -
1988                                         (TEGRA_ASIM_QT_FB_START +
1989                                          TEGRA_ASIM_QT_FB_SIZE);
1990                         } else {
1991                                 /*
1992                                  * Place the tegra ASIM/QT carveout after VPR.
1993                                  */
1994                                 tegra_carveout_start = tegra_vpr_start +
1995                                                          tegra_vpr_size;
1996                                 tegra_carveout_size =
1997                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_START +
1998                                         TEGRA_ASIM_QT_FRONT_DOOR_MEM_SIZE -
1999                                         (tegra_vpr_start + tegra_vpr_size);
2000                         }
2001                 } else if (tegra_vpr_size != 0) {
2002                         /*
2003                          * VPR cannot work on ASIM/ASIM + QT if split mem is not
2004                          * enabled.
2005                          */
2006                         BUG();
2007                 }
2008         }
2009
2010         if (tegra_fb_size)
2011                 tegra_grhost_aperture = tegra_fb_start;
2012
2013         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
2014                 tegra_grhost_aperture = tegra_fb2_start;
2015
2016         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
2017                 tegra_grhost_aperture = tegra_carveout_start;
2018
2019         if (tegra_lp0_vec_size &&
2020            (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
2021                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
2022                         pr_err("Failed to reserve lp0_vec %08llx@%08llx\n",
2023                                 (u64)tegra_lp0_vec_size,
2024                                 (u64)tegra_lp0_vec_start);
2025                         tegra_lp0_vec_start = 0;
2026                         tegra_lp0_vec_size = 0;
2027                 }
2028                 tegra_lp0_vec_relocate = false;
2029         } else
2030                 tegra_lp0_vec_relocate = true;
2031
2032 #ifdef CONFIG_TEGRA_NVDUMPER
2033         if (nvdumper_reserved) {
2034                 if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
2035                         pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
2036                                nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
2037                         nvdumper_reserved = 0;
2038                 }
2039         }
2040 #endif
2041
2042 #ifdef CONFIG_TEGRA_USE_NCT
2043         if (tegra_nck_size &&
2044            (tegra_nck_start < memblock_end_of_DRAM())) {
2045                 if (memblock_reserve(tegra_nck_start, tegra_nck_size)) {
2046                         pr_err("Failed to reserve nck %08lx@%08lx\n",
2047                                 tegra_nck_size, tegra_nck_start);
2048                         tegra_nck_start = 0;
2049                         tegra_nck_size = 0;
2050                 }
2051         }
2052 #endif
2053
2054         /*
2055          * We copy the bootloader's framebuffer to the framebuffer allocated
2056          * above, and then free this one.
2057          * */
2058         if (tegra_bootloader_fb_size) {
2059                 tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
2060                 if (memblock_reserve(tegra_bootloader_fb_start,
2061                                 tegra_bootloader_fb_size)) {
2062                         pr_err("Failed to reserve bootloader frame buffer "
2063                                 "%08llx@%08llx\n",
2064                                 (u64)tegra_bootloader_fb_size,
2065                                 (u64)tegra_bootloader_fb_start);
2066                         tegra_bootloader_fb_start = 0;
2067                         tegra_bootloader_fb_size = 0;
2068                 }
2069         }
2070
2071         if (tegra_bootloader_fb2_size) {
2072                 tegra_bootloader_fb2_size =
2073                                 PAGE_ALIGN(tegra_bootloader_fb2_size);
2074                 if (memblock_reserve(tegra_bootloader_fb2_start,
2075                                 tegra_bootloader_fb2_size)) {
2076                         pr_err("Failed to reserve bootloader fb2 %08llx@%08llx\n",
2077                                 (u64)tegra_bootloader_fb2_size,
2078                                 (u64)tegra_bootloader_fb2_start);
2079                         tegra_bootloader_fb2_start = 0;
2080                         tegra_bootloader_fb2_size = 0;
2081                 }
2082         }
2083
2084         pr_info("Tegra reserved memory:\n"
2085                 "LP0:                    %08llx - %08llx\n"
2086                 "Bootloader framebuffer: %08llx - %08llx\n"
2087                 "Bootloader framebuffer2: %08llx - %08llx\n"
2088                 "Framebuffer:            %08llx - %08llx\n"
2089                 "2nd Framebuffer:        %08llx - %08llx\n"
2090 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2091                 "Carveout:               %08llx - %08llx\n"
2092                 "Vpr:                    %08llx - %08llx\n"
2093 #endif
2094                 "Tsec:                   %08llx - %08llx\n",
2095                 (u64)tegra_lp0_vec_start,
2096                 (u64)(tegra_lp0_vec_size ?
2097                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0),
2098                 (u64)tegra_bootloader_fb_start,
2099                 (u64)(tegra_bootloader_fb_size ?
2100                         tegra_bootloader_fb_start +
2101                         tegra_bootloader_fb_size - 1 : 0),
2102                 (u64)tegra_bootloader_fb2_start,
2103                 (u64)(tegra_bootloader_fb2_size ?
2104                         tegra_bootloader_fb2_start +
2105                         tegra_bootloader_fb2_size - 1 : 0),
2106                 (u64)tegra_fb_start,
2107                 (u64)(tegra_fb_size ?
2108                         tegra_fb_start + tegra_fb_size - 1 : 0),
2109                 (u64)tegra_fb2_start,
2110                 (u64)(tegra_fb2_size ?
2111                         tegra_fb2_start + tegra_fb2_size - 1 : 0),
2112 #ifndef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2113                 (u64)tegra_carveout_start,
2114                 (u64)(tegra_carveout_size ?
2115                         tegra_carveout_start + tegra_carveout_size - 1 : 0),
2116                 (u64)tegra_vpr_start,
2117                 (u64)(tegra_vpr_size ?
2118                         tegra_vpr_start + tegra_vpr_size - 1 : 0),
2119 #endif
2120                 (u64)tegra_tsec_start,
2121                 (u64)(tegra_tsec_size ?
2122                         tegra_tsec_start + tegra_tsec_size - 1 : 0));
2123
2124
2125 #ifdef CONFIG_TEGRA_NVDUMPER
2126         if (nvdumper_reserved) {
2127                 pr_info("Nvdumper:               %08lx - %08lx\n",
2128                         nvdumper_reserved,
2129                         nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
2130         }
2131 #endif
2132
2133 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
2134         pr_info("Tzram:               %08lx - %08lx\n",
2135                 tegra_tzram_start,
2136                 tegra_tzram_size ?
2137                         tegra_tzram_start + tegra_tzram_size - 1 : 0);
2138 #endif
2139
2140 #ifdef CONFIG_TEGRA_USE_NCT
2141         if (tegra_nck_size) {
2142                 pr_info("Nck:                    %08lx - %08lx\n",
2143                         tegra_nck_start,
2144                         tegra_nck_size ?
2145                                 tegra_nck_start + tegra_nck_size - 1 : 0);
2146         }
2147 #endif
2148
2149 #ifdef CONFIG_PSTORE_RAM
2150         tegra_reserve_ramoops_memory(RAMOOPS_MEM_SIZE);
2151 #endif
2152
2153 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2154         /* Keep these at the end */
2155         if (carveout_size) {
2156                 if (dma_declare_contiguous(&tegra_generic_cma_dev,
2157                         carveout_size, 0, memblock_end_of_4G()))
2158                         pr_err("dma_declare_contiguous failed for generic\n");
2159                 tegra_carveout_size = carveout_size;
2160         }
2161
2162         if (tegra_vpr_size)
2163                 if (dma_declare_contiguous(&tegra_vpr_cma_dev,
2164                         tegra_vpr_size, 0, memblock_end_of_4G()))
2165                         pr_err("dma_declare_contiguous failed VPR carveout\n");
2166 #endif
2167
2168         tegra_fb_linear_set(map);
2169 }
2170
2171 void tegra_reserve4(ulong carveout_size, ulong fb_size,
2172                        ulong fb2_size, ulong vpr_size)
2173 {
2174 #ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
2175         tegra_vpr_start = 0;
2176         tegra_vpr_size = vpr_size;
2177 #endif
2178         tegra_reserve(carveout_size, fb_size, fb2_size);
2179 }
2180
2181 void tegra_get_fb_resource(struct resource *fb_res)
2182 {
2183         fb_res->start = (resource_size_t) tegra_fb_start;
2184         fb_res->end = fb_res->start +
2185                         (resource_size_t) tegra_fb_size - 1;
2186 }
2187
2188 void tegra_get_fb2_resource(struct resource *fb2_res)
2189 {
2190         fb2_res->start = (resource_size_t) tegra_fb2_start;
2191         fb2_res->end = fb2_res->start +
2192                         (resource_size_t) tegra_fb2_size - 1;
2193 }
2194
2195
2196
2197 int __init tegra_register_fuse(void)
2198 {
2199         return platform_device_register(&tegra_fuse_device);
2200 }
2201
2202 int __init tegra_release_bootloader_fb(void)
2203 {
2204         /* Since bootloader fb is reserved in common.c, it is freed here. */
2205         if (tegra_bootloader_fb_size) {
2206                 if (memblock_free(tegra_bootloader_fb_start,
2207                                                 tegra_bootloader_fb_size))
2208                         pr_err("Failed to free bootloader fb.\n");
2209                 else
2210                         free_bootmem_late(tegra_bootloader_fb_start,
2211                                                 tegra_bootloader_fb_size);
2212         }
2213         if (tegra_bootloader_fb2_size) {
2214                 if (memblock_free(tegra_bootloader_fb2_start,
2215                                                 tegra_bootloader_fb2_size))
2216                         pr_err("Failed to free bootloader fb2.\n");
2217                 else
2218                         free_bootmem_late(tegra_bootloader_fb2_start,
2219                                                 tegra_bootloader_fb2_size);
2220         }
2221         return 0;
2222 }
2223 late_initcall(tegra_release_bootloader_fb);
2224
2225 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
2226         [TEGRA_REVISION_UNKNOWN] = "unknown",
2227         [TEGRA_REVISION_A01]     = "A01",
2228         [TEGRA_REVISION_A02]     = "A02",
2229         [TEGRA_REVISION_A03]     = "A03",
2230         [TEGRA_REVISION_A03p]    = "A03 prime",
2231         [TEGRA_REVISION_A04]     = "A04",
2232         [TEGRA_REVISION_A04p]    = "A04 prime",
2233 };
2234
2235 static const char * __init tegra_get_revision(void)
2236 {
2237         return kasprintf(GFP_KERNEL, "%s", tegra_revision_name[tegra_revision]);
2238 }
2239
2240 static const char * __init tegra_get_family(void)
2241 {
2242         void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
2243         u32 cid = readl(chip_id);
2244         cid = (cid >> 8) & 0xFF;
2245
2246         switch (cid) {
2247         case TEGRA_CHIPID_TEGRA2:
2248                 cid = 2;
2249                 break;
2250         case TEGRA_CHIPID_TEGRA3:
2251                 cid = 3;
2252                 break;
2253         case TEGRA_CHIPID_TEGRA11:
2254                 cid = 11;
2255                 break;
2256         case TEGRA_CHIPID_TEGRA12:
2257                 cid = 12;
2258                 break;
2259         case TEGRA_CHIPID_TEGRA13:
2260                 cid = 13;
2261                 break;
2262         case TEGRA_CHIPID_TEGRA14:
2263                 cid = 14;
2264                 break;
2265
2266         case TEGRA_CHIPID_UNKNOWN:
2267         default:
2268                 cid = 0;
2269         }
2270         return kasprintf(GFP_KERNEL, "Tegra%d", cid);
2271 }
2272
2273 static const char * __init tegra_get_soc_id(void)
2274 {
2275         int package_id = tegra_package_id();
2276
2277         return kasprintf(GFP_KERNEL, "REV=%s:SKU=0x%x:PID=0x%x",
2278                 tegra_revision_name[tegra_revision],
2279                 tegra_get_sku_id(), package_id);
2280 }
2281
2282 static void __init tegra_soc_info_populate(struct soc_device_attribute
2283         *soc_dev_attr, const char *machine)
2284 {
2285         soc_dev_attr->soc_id = tegra_get_soc_id();
2286         soc_dev_attr->machine  = machine;
2287         soc_dev_attr->family   = tegra_get_family();
2288         soc_dev_attr->revision = tegra_get_revision();
2289 }
2290
2291 int __init tegra_soc_device_init(const char *machine)
2292 {
2293         struct soc_device *soc_dev;
2294         struct soc_device_attribute *soc_dev_attr;
2295
2296         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
2297         if (!soc_dev_attr)
2298                 return -ENOMEM;
2299
2300         tegra_soc_info_populate(soc_dev_attr, machine);
2301
2302         soc_dev = soc_device_register(soc_dev_attr);
2303         if (IS_ERR_OR_NULL(soc_dev)) {
2304                 kfree(soc_dev_attr);
2305                 return -1;
2306         }
2307
2308         return 0;
2309 }
2310
2311 void __init tegra_init_late(void)
2312 {
2313 #ifndef CONFIG_COMMON_CLK
2314         tegra_clk_debugfs_init();
2315 #endif
2316         tegra_powergate_debugfs_init();
2317 }
2318
2319 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2320 #define ASIM_SHUTDOWN_REG       0x538f0ffc
2321
2322 static void asim_power_off(void)
2323 {
2324         pr_err("ASIM Powering off the device\n");
2325         writel(1, IO_ADDRESS(ASIM_SHUTDOWN_REG));
2326         while (1)
2327                 ;
2328 }
2329
2330 static int __init asim_power_off_init(void)
2331 {
2332         if (tegra_cpu_is_asim())
2333                 pm_power_off = asim_power_off;
2334         return 0;
2335 }
2336
2337 arch_initcall(asim_power_off_init);
2338
2339 #if defined(CONFIG_SMC91X)
2340 static struct resource tegra_asim_smc91x_resources[] = {
2341         [0] = {
2342                 .start          = TEGRA_SIM_ETH_BASE,
2343                 .end            = TEGRA_SIM_ETH_BASE + TEGRA_SIM_ETH_SIZE - 1,
2344                 .flags          = IORESOURCE_MEM,
2345         },
2346         [1] = {
2347                 .start          = IRQ_ETH,
2348                 .end            = IRQ_ETH,
2349                 .flags          = IORESOURCE_IRQ,
2350         },
2351 };
2352
2353 static struct platform_device tegra_asim_smc91x_device = {
2354         .name           = "smc91x",
2355         .id             = 0,
2356         .num_resources  = ARRAY_SIZE(tegra_asim_smc91x_resources),
2357         .resource       = tegra_asim_smc91x_resources,
2358 };
2359
2360 static int __init asim_enet_smc91x_init(void)
2361 {
2362         if (tegra_cpu_is_asim() && !tegra_cpu_is_dsim())
2363                 platform_device_register(&tegra_asim_smc91x_device);
2364         return 0;
2365 }
2366
2367 rootfs_initcall(asim_enet_smc91x_init);
2368 #endif
2369 #endif
2370
2371 #if defined(CONFIG_SMSC911X)
2372 static struct resource tegra_smsc911x_resources[] = {
2373         [0] = {
2374                 .start          = 0x4E000000,
2375                 .end            = 0x4E000000 + SZ_64K - 1,
2376                 .flags          = IORESOURCE_MEM,
2377         },
2378         [1] = {
2379                 .start          = IRQ_ETH,
2380                 .end            = IRQ_ETH,
2381                 .flags          = IORESOURCE_IRQ,
2382         },
2383 };
2384
2385 static struct smsc911x_platform_config tegra_smsc911x_config = {
2386         .flags          = SMSC911X_USE_32BIT,
2387         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
2388         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
2389         .phy_interface  = PHY_INTERFACE_MODE_MII,
2390 };
2391
2392 static struct platform_device tegra_smsc911x_device = {
2393         .name              = "smsc911x",
2394         .id                = 0,
2395         .resource          = tegra_smsc911x_resources,
2396         .num_resources     = ARRAY_SIZE(tegra_smsc911x_resources),
2397         .dev.platform_data = &tegra_smsc911x_config,
2398 };
2399
2400 static int __init enet_smsc911x_init(void)
2401 {
2402         if (!tegra_cpu_is_dsim() && !tegra_platform_is_qt())
2403                 platform_device_register(&tegra_smsc911x_device);
2404         return 0;
2405 }
2406
2407 rootfs_initcall(enet_smsc911x_init);
2408 #endif
2409
2410 int tegra_split_mem_active(void)
2411 {
2412         return tegra_split_mem_set;
2413 }
2414
2415 static int __init set_tegra_split_mem(char *options)
2416 {
2417         tegra_split_mem_set = 1;
2418         return 0;
2419 }
2420 early_param("tegra_split_mem", set_tegra_split_mem);
2421
2422 #define FUSE_SKU_INFO       0x110
2423 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2424 #define STRAP_OPT 0x464
2425 #define RAM_ID_MASK (0xF << 4)
2426 #else
2427 #define STRAP_OPT 0x008
2428 #define RAM_ID_MASK (3 << 4)
2429 #endif
2430 #define RAM_CODE_SHIFT 4
2431
2432 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2433 static enum tegra_platform tegra_platform;
2434 static bool cpu_is_asim;
2435 static bool cpu_is_dsim;
2436 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
2437         [TEGRA_PLATFORM_SILICON] = "silicon",
2438         [TEGRA_PLATFORM_QT]      = "quickturn",
2439         [TEGRA_PLATFORM_LINSIM]  = "linsim",
2440         [TEGRA_PLATFORM_FPGA]    = "fpga",
2441 };
2442 #endif
2443
2444 static u32 tegra_chip_sku_id;
2445 static u32 tegra_chip_id;
2446 static u32 tegra_chip_bct_strapping;
2447 enum tegra_revision tegra_revision;
2448
2449 u32 tegra_read_pmc_reg(int offset)
2450 {
2451         return readl(IO_ADDRESS(TEGRA_PMC_BASE) + offset);
2452 }
2453
2454 u32 tegra_read_clk_ctrl_reg(int offset)
2455 {
2456         return readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + offset);
2457 }
2458
2459 u32 tegra_read_apb_misc_reg(int offset)
2460 {
2461         return readl(IO_ADDRESS(TEGRA_APB_MISC_BASE) + offset);
2462 }
2463
2464 u32 tegra_fuse_readl(unsigned long offset)
2465 {
2466         return readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2467 }
2468
2469 void tegra_fuse_writel(u32 val, unsigned long offset)
2470 {
2471         writel(val, IO_ADDRESS(TEGRA_FUSE_BASE + offset));
2472 }
2473
2474 u32 tegra_read_chipid(void)
2475 {
2476         return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE)
2477                         + 0x804);
2478 }
2479
2480 static void tegra_set_sku_id(void)
2481 {
2482         u32 reg;
2483
2484         reg = tegra_fuse_readl(FUSE_SKU_INFO);
2485         tegra_chip_sku_id = reg & 0xFF;
2486 }
2487
2488 static void tegra_set_chip_id(void)
2489 {
2490         u32 id;
2491
2492         id = tegra_read_chipid();
2493         tegra_chip_id = (id >> 8) & 0xff;
2494 }
2495
2496 static void tegra_set_bct_strapping(void)
2497 {
2498         u32 reg;
2499 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2500         reg = readl(IO_ADDRESS(TEGRA_PMC_BASE + STRAP_OPT));
2501 #else
2502         reg = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + STRAP_OPT));
2503 #endif
2504         tegra_chip_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
2505 }
2506
2507 u32 tegra_get_sku_id(void)
2508 {
2509         return tegra_chip_sku_id;
2510 }
2511
2512 u32 tegra_get_chip_id(void)
2513 {
2514         return tegra_chip_id;
2515 }
2516
2517 u32 tegra_get_bct_strapping(void)
2518 {
2519         return tegra_chip_bct_strapping;
2520 }
2521
2522 static void tegra_fuse_cfg_reg_visible(void)
2523 {
2524         /* Make all fuse registers visible */
2525         u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2526         reg |= BIT(28);
2527         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
2528 }
2529
2530 void tegra_init_fuse(void)
2531 {
2532         u32 sku_id;
2533
2534         tegra_fuse_cfg_reg_visible();
2535         tegra_set_sku_id();
2536         sku_id = tegra_get_sku_id();
2537         tegra_set_bct_strapping();
2538         tegra_set_chip_id();
2539         tegra_revision = tegra_chip_get_revision();
2540         tegra_init_speedo_data();
2541         pr_info("Tegra Revision: %s SKU: 0x%x CPU Process: %d Core Process: %d\n",
2542                 tegra_revision_name[tegra_revision],
2543                 sku_id, tegra_cpu_process_id(),
2544                 tegra_core_process_id());
2545 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
2546         if (!tegra_platform_is_silicon()) {
2547                 pr_info("Tegra Platform: %s%s%s\n",
2548                         tegra_cpu_is_asim() ? "ASIM+" : "",
2549                         tegra_cpu_is_dsim() ? "DSIM+" : "",
2550                         tegra_platform_name[tegra_platform]);
2551         }
2552 #endif
2553 }
2554
2555 void __init display_tegra_dt_info(void)
2556 {
2557         unsigned long dt_root;
2558         const char *dts_fname;
2559
2560
2561         dt_root = of_get_flat_dt_root();
2562
2563         dts_fname = of_get_flat_dt_prop(dt_root, "nvidia,dtsfilename", NULL);
2564         if (dts_fname)
2565                 pr_info("DTS File Name: %s\n", dts_fname);
2566         else
2567                 pr_info("DTS File Name: <unknown>\n");
2568 }
2569
2570 static int __init tegra_get_last_reset_reason(void)
2571 {
2572 #define PMC_RST_STATUS 0x1b4
2573 #define RESET_STR(REASON) "last reset is due to "#REASON"\n"
2574         char *reset_reason[] = {
2575                 RESET_STR(power on reset),
2576                 RESET_STR(watchdog timeout),
2577                 RESET_STR(sensor),
2578                 RESET_STR(software reset),
2579                 RESET_STR(deep sleep reset),
2580         };
2581
2582         u32 val = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_RST_STATUS) & 0x7;
2583         if (val >= ARRAY_SIZE(reset_reason))
2584                 pr_info("last reset value is invalid 0x%x\n", val);
2585         else
2586                 pr_info("%s\n", reset_reason[val]);
2587         return 0;
2588 }
2589 late_initcall(tegra_get_last_reset_reason);