ARM: tegra: power: Refactored kernel powergate code
[linux-3.10.git] / arch / arm / mach-tegra / common.c
1 /*
2  * arch/arm/mach-tegra/common.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  *
6  * Author:
7  *      Colin Cross <ccross@android.com>
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/platform_device.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/irqchip.h>
26 #include <linux/clk/tegra.h>
27 #include <linux/highmem.h>
28 #include <linux/memblock.h>
29 #include <linux/bitops.h>
30
31 #include <asm/hardware/cache-l2x0.h>
32 #include <asm/system_info.h>
33
34 #include <mach/powergate.h>
35
36 #include "board.h"
37 #include "common.h"
38 #include "dvfs.h"
39 #include "fuse.h"
40 #include "iomap.h"
41 #include "pm.h"
42 #include "pmc.h"
43 #include "apbio.h"
44 #include "sleep.h"
45 #include "reset.h"
46
47 #define MC_SECURITY_CFG2        0x7c
48
49 #define AHB_ARBITRATION_PRIORITY_CTRL           0x4
50 #define   AHB_PRIORITY_WEIGHT(x)        (((x) & 0x7) << 29)
51 #define   PRIORITY_SELECT_USB   BIT(6)
52 #define   PRIORITY_SELECT_USB2  BIT(18)
53 #define   PRIORITY_SELECT_USB3  BIT(17)
54
55 #define AHB_GIZMO_AHB_MEM               0xc
56 #define   ENB_FAST_REARBITRATE  BIT(2)
57 #define   DONT_SPLIT_AHB_WR     BIT(7)
58
59 #define AHB_GIZMO_USB           0x1c
60 #define AHB_GIZMO_USB2          0x78
61 #define AHB_GIZMO_USB3          0x7c
62 #define   IMMEDIATE     BIT(18)
63
64 #define AHB_MEM_PREFETCH_CFG3   0xe0
65 #define AHB_MEM_PREFETCH_CFG4   0xe4
66 #define AHB_MEM_PREFETCH_CFG1   0xec
67 #define AHB_MEM_PREFETCH_CFG2   0xf0
68 #define   PREFETCH_ENB  BIT(31)
69 #define   MST_ID(x)     (((x) & 0x1f) << 26)
70 #define   AHBDMA_MST_ID MST_ID(5)
71 #define   USB_MST_ID    MST_ID(6)
72 #define   USB2_MST_ID   MST_ID(18)
73 #define   USB3_MST_ID   MST_ID(17)
74 #define   ADDR_BNDRY(x) (((x) & 0xf) << 21)
75 #define   INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
76
77 unsigned long tegra_bootloader_fb_start;
78 unsigned long tegra_bootloader_fb_size;
79 unsigned long tegra_fb_start;
80 unsigned long tegra_fb_size;
81 unsigned long tegra_fb2_start;
82 unsigned long tegra_fb2_size;
83 unsigned long tegra_carveout_start;
84 unsigned long tegra_carveout_size;
85 unsigned long tegra_lp0_vec_start;
86 unsigned long tegra_lp0_vec_size;
87 unsigned long tegra_grhost_aperture = ~0ul;
88 static   bool is_tegra_debug_uart_hsport;
89 static struct board_info pmu_board_info;
90
91 static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
92 static int board_panel_type;
93
94 /*
95  * Storage for debug-macro.S's state.
96  *
97  * This must be in .data not .bss so that it gets initialized each time the
98  * kernel is loaded. The data is declared here rather than debug-macro.S so
99  * that multiple inclusions of debug-macro.S point at the same data.
100  */
101 u32 tegra_uart_config[4] = {
102         /* Debug UART initialization required */
103         1,
104         /* Debug UART physical address */
105         0,
106         /* Debug UART virtual address */
107         0,
108         /* Scratch space for debug macro */
109         0,
110 };
111
112 #ifdef CONFIG_OF
113 void __init tegra_dt_init_irq(void)
114 {
115         tegra_clocks_init();
116         tegra_pmc_init();
117         tegra_init_irq();
118         irqchip_init();
119 }
120 #endif
121
122 void tegra_assert_system_reset(char mode, const char *cmd)
123 {
124         void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
125         u32 reg;
126
127         reg = readl_relaxed(reset);
128         reg |= 0x10;
129         writel_relaxed(reg, reset);
130 }
131
132 void tegra_init_cache(u32 tag_latency, u32 data_latency)
133 {
134 #ifdef CONFIG_CACHE_L2X0
135         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
136         u32 aux_ctrl, cache_type;
137         u32 tag_latency, data_latency;
138
139 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
140         tag_latency = 0x331;
141         data_latency = 0x441;
142 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
143 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
144         if (is_lp_cluster()) {
145                 tag_latency = 0x221;
146                 data_latency = 0x221;
147         } else {
148                 tag_latency = 0x331;
149                 data_latency = 0x441;
150         }
151 #else
152         tag_latency = 0x770;
153         data_latency = 0x770;
154 #endif
155 #endif
156         writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
157         writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
158
159 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
160 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
161         writel(7, p + L2X0_PREFETCH_CTRL);
162         writel(2, p + L2X0_POWER_CTRL);
163 #endif  
164
165         /* Enable PL310 double line fill feature. */
166         writel(((1<<30) | 0), p + L2X0_PREFETCH_CTRL);
167 #endif
168
169         cache_type = readl(p + L2X0_CACHE_TYPE);
170         aux_ctrl = (cache_type & 0x700) << (17-8);
171         aux_ctrl |= 0x7C400001;
172
173         l2x0_init(p, aux_ctrl, 0x8200c3fe);
174 #endif
175 }
176
177 static void __init tegra_init_power(void)
178 {
179         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_MPE);
180         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_3D);
181 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
182         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_3D1);
183 #endif
184 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
185         /* for TEGRA_3x_SOC it will be handled seperately */
186         tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
187 #endif
188 }
189
190 static inline unsigned long gizmo_readl(unsigned long offset)
191 {
192         return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
193 }
194
195 static inline void gizmo_writel(unsigned long value, unsigned long offset)
196 {
197         writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
198 }
199
200 static void __init tegra_init_ahb_gizmo_settings(void)
201 {
202         unsigned long val;
203
204         val = gizmo_readl(AHB_GIZMO_AHB_MEM);
205         val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
206         gizmo_writel(val, AHB_GIZMO_AHB_MEM);
207
208         val = gizmo_readl(AHB_GIZMO_USB);
209         val |= IMMEDIATE;
210         gizmo_writel(val, AHB_GIZMO_USB);
211
212         val = gizmo_readl(AHB_GIZMO_USB2);
213         val |= IMMEDIATE;
214         gizmo_writel(val, AHB_GIZMO_USB2);
215
216         val = gizmo_readl(AHB_GIZMO_USB3);
217         val |= IMMEDIATE;
218         gizmo_writel(val, AHB_GIZMO_USB3);
219
220         val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
221         val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
222                                 | AHB_PRIORITY_WEIGHT(7);
223         gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
224
225         val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
226         val &= ~MST_ID(~0);
227         val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
228         gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
229
230         val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
231         val &= ~MST_ID(~0);
232         val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
233         gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
234
235         val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
236         val &= ~MST_ID(~0);
237         val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
238         gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
239
240         val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
241         val &= ~MST_ID(~0);
242         val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
243         gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
244 }
245
246 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
247 void __init tegra20_init_early(void)
248 {
249 #ifndef CONFIG_SMP
250         /* For SMP system, initializing the reset handler here is too
251            late. For non-SMP systems, the function that calls the reset
252            handler initializer is not called, so do it here for non-SMP. */
253         tegra_cpu_reset_handler_init();
254 #endif
255         tegra_apb_io_init();
256         tegra_init_fuse();
257         tegra_init_cache();
258         tegra_powergate_init();
259         tegra20_hotplug_init();
260         tegra_init_power();
261         tegra_init_ahb_gizmo_settings();
262 }
263 #endif
264 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
265 void __init tegra30_init_early(void)
266 {
267 #ifndef CONFIG_SMP
268         /* For SMP system, initializing the reset handler here is too
269            late. For non-SMP systems, the function that calls the reset
270            handler initializer is not called, so do it here for non-SMP. */
271         tegra_cpu_reset_handler_init();
272 #endif
273         tegra_apb_io_init();
274         tegra_init_fuse();
275         tegra_init_cache();
276         tegra_pmc_init();
277         tegra_powergate_init();
278         tegra30_hotplug_init();
279         tegra_init_power();
280         tegra_init_ahb_gizmo_settings();
281 }
282 #endif
283
284 static int __init tegra_lp0_vec_arg(char *options)
285 {
286         char *p = options;
287
288         tegra_lp0_vec_size = memparse(p, &p);
289         if (*p == '@')
290                 tegra_lp0_vec_start = memparse(p+1, &p);
291         if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
292                 tegra_lp0_vec_size = 0;
293                 tegra_lp0_vec_start = 0;
294         }
295
296         return 0;
297 }
298 early_param("lp0_vec", tegra_lp0_vec_arg);
299
300 static int __init tegra_bootloader_fb_arg(char *options)
301 {
302         char *p = options;
303         unsigned long start;
304         unsigned long size;
305
306         tegra_bootloader_fb_size = memparse(p, &p);
307         if (*p == '@')
308                 tegra_bootloader_fb_start = memparse(p+1, &p);
309
310         pr_info("Found tegra_fbmem: %08lx@%08lx\n",
311                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
312
313         return 0;
314 }
315 early_param("tegra_fbmem", tegra_bootloader_fb_arg);
316
317 enum panel_type get_panel_type(void)
318 {
319         return board_panel_type;
320 }
321 static int __init tegra_board_panel_type(char *options)
322 {
323         if (!strcmp(options, "lvds"))
324                 board_panel_type = panel_type_lvds;
325         else if (!strcmp(options, "dsi"))
326                 board_panel_type = panel_type_dsi;
327         else
328                 return 0;
329         return 1;
330 }
331 __setup("panel=", tegra_board_panel_type);
332
333 int get_core_edp(void)
334 {
335         return pmu_core_edp;
336 }
337 static int __init tegra_pmu_core_edp(char *options)
338 {
339         char *p = options;
340         int core_edp = memparse(p, &p);
341         if (core_edp != 0)
342                 pmu_core_edp = core_edp;
343         return 1;
344 }
345 __setup("core_edp_mv=", tegra_pmu_core_edp);
346
347 static int __init tegra_debug_uartport(char *info)
348 {
349         if (!strcmp(info, "hsport"))
350                 is_tegra_debug_uart_hsport = true;
351         else if (!strcmp(info, "lsport"))
352                 is_tegra_debug_uart_hsport = false;
353
354         return 1;
355 }
356
357 bool is_tegra_debug_uartport_hs(void)
358 {
359         return is_tegra_debug_uart_hsport;
360 }
361
362 __setup("debug_uartport=", tegra_debug_uartport);
363
364 void tegra_get_board_info(struct board_info *bi)
365 {
366         bi->board_id = (system_serial_high >> 16) & 0xFFFF;
367         bi->sku = (system_serial_high) & 0xFFFF;
368         bi->fab = (system_serial_low >> 24) & 0xFF;
369         bi->major_revision = (system_serial_low >> 16) & 0xFF;
370         bi->minor_revision = (system_serial_low >> 8) & 0xFF;
371 }
372
373 static int __init tegra_pmu_board_info(char *info)
374 {
375         char *p = info;
376         pmu_board_info.board_id = memparse(p, &p);
377         pmu_board_info.sku = memparse(p+1, &p);
378         pmu_board_info.fab = memparse(p+1, &p);
379         pmu_board_info.major_revision = memparse(p+1, &p);
380         pmu_board_info.minor_revision = memparse(p+1, &p);
381         return 1;
382 }
383
384 void tegra_get_pmu_board_info(struct board_info *bi)
385 {
386         memcpy(bi, &pmu_board_info, sizeof(struct board_info));
387 }
388
389 __setup("pmuboard=", tegra_pmu_board_info);
390
391
392 /*
393  * Tegra has a protected aperture that prevents access by most non-CPU
394  * memory masters to addresses above the aperture value.  Enabling it
395  * secures the CPU's memory from the GPU, except through the GART.
396  */
397 void __init tegra_protected_aperture_init(unsigned long aperture)
398 {
399 #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
400         void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
401         pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
402         writel(aperture, mc_base + MC_SECURITY_CFG2);
403 #else
404         pr_err("Tegra protected aperture disabled because nvmap is using "
405                 "system memory\n");
406 #endif
407 }
408
409 /*
410  * Due to conflicting restrictions on the placement of the framebuffer,
411  * the bootloader is likely to leave the framebuffer pointed at a location
412  * in memory that is outside the grhost aperture.  This function will move
413  * the framebuffer contents from a physical address that is anywher (lowmem,
414  * highmem, or outside the memory map) to a physical address that is outside
415  * the memory map.
416  */
417 void tegra_move_framebuffer(unsigned long to, unsigned long from,
418         unsigned long size)
419 {
420         struct page *page;
421         void __iomem *to_io;
422         void *from_virt;
423         unsigned long i;
424
425         BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
426         BUG_ON(PAGE_ALIGN(from) != from);
427         BUG_ON(PAGE_ALIGN(size) != size);
428
429         to_io = ioremap(to, size);
430         if (!to_io) {
431                 pr_err("%s: Failed to map target framebuffer\n", __func__);
432                 return;
433         }
434
435         if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
436                 for (i = 0 ; i < size; i += PAGE_SIZE) {
437                         page = phys_to_page(from + i);
438                         from_virt = kmap(page);
439                         memcpy_toio(to_io + i, from_virt, PAGE_SIZE);
440                         kunmap(page);
441                 }
442         } else {
443                 void __iomem *from_io = ioremap(from, size);
444                 if (!from_io) {
445                         pr_err("%s: Failed to map source framebuffer\n",
446                                 __func__);
447                         goto out;
448                 }
449
450                 for (i = 0; i < size; i+= 4)
451                         writel(readl(from_io + i), to_io + i);
452
453                 iounmap(from_io);
454         }
455 out:
456         iounmap(to_io);
457 }
458
459 #ifdef CONFIG_TEGRA_IOVMM_SMMU
460 /* Support for Tegra3 A01 chip mask that needs to have SMMU IOVA reside in
461  * the upper half of 4GB IOVA space. A02 and after use the bottom 1GB and
462  * do not need to reserve memory.
463  */
464 #define SUPPORT_TEGRA_3_IOVMM_SMMU_A01
465 #endif
466
467 void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
468         unsigned long fb2_size)
469 {
470 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
471         extern struct platform_device tegra_smmu_device;
472         int smmu_reserved = 0;
473         struct resource *smmu_window =
474                     platform_get_resource_byname(&tegra_smmu_device,
475                                                 IORESOURCE_MEM, "smmu");
476 #endif
477         if (tegra_lp0_vec_size)
478                 if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
479                         pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
480                                 tegra_lp0_vec_size, tegra_lp0_vec_start);
481                         tegra_lp0_vec_start = 0;
482                         tegra_lp0_vec_size = 0;
483                 }
484
485         if (carveout_size) {
486                 tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
487                 if (memblock_remove(tegra_carveout_start, carveout_size)) {
488                         pr_err("Failed to remove carveout %08lx@%08lx "
489                                 "from memory map\n",
490                                 carveout_size, tegra_carveout_start);
491                         tegra_carveout_start = 0;
492                         tegra_carveout_size = 0;
493                 }
494                 else
495                         tegra_carveout_size = carveout_size;
496         }
497
498         if (fb2_size) {
499                 tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
500                 if (memblock_remove(tegra_fb2_start, fb2_size)) {
501                         pr_err("Failed to remove second framebuffer %08lx@%08lx "
502                                 "from memory map\n",
503                                 fb2_size, tegra_fb2_start);
504                         tegra_fb2_start = 0;
505                         tegra_fb2_size = 0;
506                 } else
507                         tegra_fb2_size = fb2_size;
508         }
509
510         if (fb_size) {
511                 tegra_fb_start = memblock_end_of_DRAM() - fb_size;
512                 if (memblock_remove(tegra_fb_start, fb_size)) {
513                         pr_err("Failed to remove framebuffer %08lx@%08lx "
514                                 "from memory map\n",
515                                 fb_size, tegra_fb_start);
516                         tegra_fb_start = 0;
517                         tegra_fb_size = 0;
518                 } else
519                         tegra_fb_size = fb_size;
520         }
521
522         if (tegra_fb_size)
523                 tegra_grhost_aperture = tegra_fb_start;
524
525         if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
526                 tegra_grhost_aperture = tegra_fb2_start;
527
528         if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
529                 tegra_grhost_aperture = tegra_carveout_start;
530
531 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
532         if (!smmu_window) {
533                 pr_err("No SMMU resources\n");
534         } else {
535                 size_t smmu_window_size;
536
537                 if (tegra_revision == TEGRA_REVISION_A01) {
538                         smmu_window->start = TEGRA_SMMU_BASE_A01;
539                         smmu_window->end   = TEGRA_SMMU_BASE_A01 +
540                                                 TEGRA_SMMU_SIZE_A01 - 1;
541                 }
542                 smmu_window_size = smmu_window->end + 1 - smmu_window->start;
543                 if (smmu_window->start >= 0x80000000) {
544                         if (memblock_reserve(smmu_window->start,
545                                                 smmu_window_size))
546                                 pr_err(
547                         "Failed to reserve SMMU I/O VA window %08lx@%08lx\n",
548                                 (unsigned long)smmu_window_size,
549                                 (unsigned long)smmu_window->start);
550                         else
551                                 smmu_reserved = 1;
552                 }
553         }
554 #endif
555
556         /*
557          * TODO: We should copy the bootloader's framebuffer to the framebuffer
558          * allocated above, and then free this one.
559          */
560         if (tegra_bootloader_fb_size)
561                 if (memblock_reserve(tegra_bootloader_fb_start,
562                                 tegra_bootloader_fb_size)) {
563                         pr_err("Failed to reserve bootloader frame buffer %08lx@%08lx\n",
564                                 tegra_bootloader_fb_size, tegra_bootloader_fb_start);
565                         tegra_bootloader_fb_start = 0;
566                         tegra_bootloader_fb_size = 0;
567                 }
568
569         pr_info("Tegra reserved memory:\n"
570                 "LP0:                    %08lx - %08lx\n"
571                 "Bootloader framebuffer: %08lx - %08lx\n"
572                 "Framebuffer:            %08lx - %08lx\n"
573                 "2nd Framebuffer:        %08lx - %08lx\n"
574                 "Carveout:               %08lx - %08lx\n",
575                 tegra_lp0_vec_start,
576                 tegra_lp0_vec_size ?
577                         tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
578                 tegra_bootloader_fb_start,
579                 tegra_bootloader_fb_size ?
580                         tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
581                 tegra_fb_start,
582                 tegra_fb_size ?
583                         tegra_fb_start + tegra_fb_size - 1 : 0,
584                 tegra_fb2_start,
585                 tegra_fb2_size ?
586                         tegra_fb2_start + tegra_fb2_size - 1 : 0,
587                 tegra_carveout_start,
588                 tegra_carveout_size ?
589                         tegra_carveout_start + tegra_carveout_size - 1 : 0);
590
591 #ifdef SUPPORT_TEGRA_3_IOVMM_SMMU_A01
592         if (smmu_reserved)
593                 pr_info("SMMU:                   %08x - %08x\n",
594                         smmu_window->start, smmu_window->end);
595 #endif
596 }
597
598 void __init tegra_init_late(void)
599 {
600 #ifndef CONFIG_COMMON_CLK
601         tegra_clk_debugfs_init();
602 #endif
603         tegra_powergate_debugfs_init();
604 }